Method and apparatus for dynamically configuring overclocking frequency

Abstract

Methods, apparatus, and articles of manufacture for dynamically configuring overclocking frequencies have been disclosed. An example apparatus includes a clock rate regulator to cause a processor core to operate at a first overclocked clock rate; a comparator for comparing the sensed temperature corresponding to the processor core with a threshold value; and a clock rate regulator to reduce a clock rate of the processor core from a first overclocked clock rate by a user-defined amount when the sensed temperature satisfies a threshold, the reduced clock rate being higher than a normal operating clock rate of the processor core.

Description

This invention patent application is a divisional application of the invention patent application with international application number PCT / US2021 / 050882, international application date September 17, 2021, application number 202180067369.2 entering the Chinese national phase, and name “Method and device for dynamically configuring overclocking frequency”. Related applications

[0001] This patent claims the benefit of U.S. Patent Application No. 17 / 130,982, filed December 22, 2020, which claims priority to U.S. Provisional Application No. 63 / 108,074, filed October 30, 2020. U.S. Patent Application No. 17 / 130,982 and U.S. Provisional Application No. 63 / 108,074 are hereby incorporated by reference in their entireties. Priority is claimed to U.S. Patent Application No. 17 / 130,982 and U.S. Provisional Application No. 63 / 108,074. Technical Field

[0002] The present disclosure relates generally to processors, and more particularly to methods and apparatus for dynamically configuring turbo frequencies. Background Art

[0003] A processing unit (e.g., a central processing unit (CPU), a graphics processing unit (GPU)) operates according to a clock rate (also known as clock speed). The clock rate is a measure of how many clock cycles (e.g., pulses) a processing unit can execute per second. The clock cycles are used to synchronize the operation of the components of the processing unit. Therefore, in general, the faster the clock cycles, the faster operations and / or instructions can be executed by the processing unit. Although many devices that include processing units are configured to operate at a specific maximum speed (e.g., a clock rate), such devices can be configured to overclock the clock rate (e.g., increase the clock rate above its normal operating level). Overclocking refers to techniques for increasing the clock rate of a component (e.g., increasing a preset configuration of the device). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example implementation of a processing unit described in conjunction with the examples disclosed herein.

[0005] Figure 2 yes Figure 1 A block diagram of an example implementation of a power control unit.

[0006] Figure 3-Figure 8 The diagram shows that the representation can be performed to implement Figure 2A flow chart of example machine-readable instructions for a power control unit.

[0007] Figure 9 An example user interface for configuring an overclocking configuration is shown.

[0008] Figure 10 is constructed to execute Figure 3-Figure 8 Instructions to achieve Figure 2 A block diagram of an example processor platform with a power control unit.

[0009] Figure 11 is a block diagram of an example software distribution platform for distributing software (e.g., Figure 3-Figure 8 The software (e.g., software corresponding to example computer-readable instructions) is distributed to client devices such as consumers (e.g., for licensing, sale, and / or use), retailers (e.g., for sale, resale, licensing, and / or sublicensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and / or direct purchasing customers).

[0010] These drawings are not to scale. Generally speaking, the same reference numbers will be used to refer to the same or like parts throughout the drawings (one or more) and the accompanying written description.

[0011] Descriptors such as "first," "second," and "third" are used herein when identifying multiple elements or components that can be referenced separately. Unless otherwise specified or understood based on the context of their use, such descriptors are not intended to confer any meaning of priority or temporal order, but are merely labels that refer to multiple elements or components separately for ease of understanding the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while a different descriptor such as "second" or "third" may be used to refer to the same element in the claims. In such cases, it should be understood that such descriptors are merely used to facilitate reference to multiple elements or components. DETAILED DESCRIPTION

[0012] A processing unit (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.) is an electronic circuit that executes instructions that constitute a program or workload. The CPU / GPU may include one or more processor cores to execute instructions by accessing data from main memory. The speed at which the processor cores execute instructions corresponds to the clock speed of the processing unit. The faster the clock speed, the higher the temperature of the system. Most computing devices include a preset clock speed for the processing unit. The preset clock speed is a speed at which the risk of overheating and / or causing damage to the device is limited or does not exist. Although some devices include a preset clock speed or clock rate (e.g., a normal operating clock rate), a user can enable overclocking to increase the preset clock rate to a higher clock rate to achieve faster computing speeds. However, as described above, overclocking increases the temperature of the chip, which, if hot enough, can cause damage to the device.

[0013] Conventional overclocking techniques allow for preset overclocking configurations. For example, with conventional overclocking techniques, users can only select overclocked clock speeds. In this manner, if a user enables overclocking and the temperature reaches a predefined maximum temperature (e.g., 100 degrees Celsius), the device automatically reduces the clock speed significantly to a preset value (e.g., the normal operating clock rate or a clock rate lower than the normal operating clock rate) for a preset amount of time to cool and protect the device. However, such inflexible conventional methods only allow overclocking at a single clock speed and shut down when the temperature reaches the maximum value.

[0014] The examples disclosed herein provide a mechanism for allowing a user to customize overclocking for a dynamic overclocking protocol that can be adjusted based on user and / or manufacturer preferences. In this way, overclocking can occur at different speeds depending on the temperature of the system (e.g., when the temperature is lower, the overclocking speed / frequency is faster, and when the temperature is higher, the overclocking speed / frequency is slower to avoid reaching the maximum temperature and automatically disabling overclocking). In some examples, a user can customize the overclocking of a device so that the clock signal can switch between two overclocked clock signals to keep the temperature within a safe range during overclocking. In some examples disclosed herein, users and / or manufacturers can set overclocking preferences based on the number of active cores and / or based on individual cores. In some examples disclosed herein, the rate at which the temperature rises or falls (e.g., slope) can be used to determine how to adjust the clock speed (e.g., a faster temperature rise can cause a lowering of the clock signal before the temperature reaches a threshold).

[0015] Additionally, the examples disclosed herein allow a user to increase or decrease the supply voltage of the system based on the temperature corresponding to the processing unit. When silicon-based circuits operate at higher temperatures, the voltage supply must be at a specific supply voltage level to ensure proper operation. However, at lower temperatures, the system can operate properly at a lower supply voltage. Therefore, the examples disclosed herein provide a mechanism for allowing a user to reduce the voltage supply to save power when the measured / sensed temperature is below one or more thresholds. The examples disclosed herein allow users and / or manufacturers to customize clock preferences based on one or more clock speeds for overclocking, one or more temperature thresholds, one or more clock speeds, one or more clock speed decrement or increment values, one or more temperature slope thresholds, one or more supply voltage levels, and / or the number of active cores.

[0016] FIG. 1 is a block diagram of an example implementation of an example processing unit 100. As shown in FIG. Figure 1 The example processing unit 100 includes example core(s) 102 , example sensor(s) 104 , example application 103 , and example power control unit 106 . The example processing unit 100 receives user input from an example user interface 112 .

[0017] Figure 1 The example processing unit 100 is any type of processing unit (e.g., a CPU, a GPU, an accelerated processing unit (APU), a general purpose GPU (GPGPU), etc.). For example, the processing unit 100 can be an embedded system, a field programmable gate array, a shared memory controller, a network on a chip, a networked system, and / or any other circuit that includes a hardware (e.g., semiconductor-based) processor, memory, and / or cache. The example processing unit 100 utilizes processor resources (e.g., the logic circuitry of the example processor core(s) 102) to execute instructions to implement the example application 103.

[0018] Figure 1The example processor core(s) 102 execute instructions (e.g., a workload) from the example application 103 (e.g., by reading data or writing data). The processing unit 100 may enable one or more of the core(s) 102 to execute instructions. The example processor core(s) execute instructions at a rate corresponding to a clock rate. As described above, when overclocking is enabled, one or more of the core(s) 102 may operate at a rate higher than a standard rate defined by the processing unit 100. In some examples, the processing unit 100 includes a single clock, and all of the core(s) 102 operate according to the single clock. In some examples, the processing unit 100 includes multiple clocks (e.g., one clock for each core 102). In this manner, the example power control unit 106 may control the frequency of the clock signal for the individual core(s) 102.

[0019] Figure 1 The example application 103 may demonstrate one or more computational stages of performing one or more tasks. The example application 103 uses resources of the core(s) 102 to execute instructions to perform one or more tasks.

[0020] Figure 1 The example sensor(s) 104 are temperature sensor(s) for sensing the temperature near the example core(s) 102. The temperature sensor(s) 104 can be a single sensor for a chip implementing the core(s) 102 and / or can be multiple sensor(s) (e.g., one sensor for one or more of the core(s) 102). In some examples, where the core(s) 102 are implemented in different chips, there can be multiple sensor(s) 104 to measure the temperature(s) of the corresponding chips and / or the core(s) of the corresponding chips. The example sensor(s) 104 output the measured temperature(s) to the example power control unit 106.

[0021] Figure 1The example power control unit 106 dynamically adjusts the clock rate when overclocking is enabled and / or dynamically adjusts the supply voltage level based on at least one of: (a) one or more temperature readings, (b) the number of active core(s) 102, and (c) the rate at which the temperature is increasing or decreasing. The example power control unit 106 adjusts the clock rate based on overclocking preferences selected by a user and / or manufacturer (e.g., preset). In this manner, a user can define (a) an overclock rate, (b) one or more temperature and / or slope thresholds for adjusting the overclock rate, and (c) how much the overclock rate is adjusted when the temperature reaches one or more thresholds. Preferences can be applied on an individual core basis or based on the group and / or number of active cores (e.g., if one core is active, a first overclocking preference is applied; if two cores are active, a second overclocking preference is applied; and so on). The power control unit 106 ensures that the user and / or manufacturer overclocking preferences are applied as an overclocking configuration to the core(s) 102. Thus, the example power control unit 106 obtains temperature(s) from the sensor(s) 104 and / or determines how many of the example core(s) 102 are active and compares the obtained data with an overclocking configuration defined by a user and / or manufacturer preferences to determine how to dynamically adjust the clock frequency and / or supply voltage. The example power control unit 106 obtains the user preferences by displaying prompts to the user via the example user interface 112 and obtains user-entered data from the prompts to convert the clock preferences into a clock configuration that the power control unit 106 uses to dynamically adjust the clock frequency and / or supply voltage.

[0022] In some examples, Figure 1The power control unit 106 stores one or more previous temperature measurements to help adjust the clock based on historical data. For example, the power control unit 106 can store previous temperature measurements to determine a rate of change, which can also be used to dynamically adjust the clock signal frequency and / or supply voltage. In some examples, the power control unit 106 analyzes the effects of changes in the clock frequency and / or supply voltage to determine the amount of increments / decrements for subsequent clock rate adjustments. For example, if a user or manufacturer selects a 0.5 gigahertz (GHz) reduction for a core when the temperature corresponding to the core is above 50°C and a 0.1 GHz increase for the core when the temperature is below 46°C, the power control unit 106 can process the resulting temperature corresponding to the core 102 based on such overclocking characteristics. The power control unit 106 uses the results to determine that reducing the clock rate by 0.5 GHz reduced the temperature much more than expected, thereby causing the core to operate at the lower clock frequency for a duration longer than necessary. In such an example, the power control unit 106 may suggest (e.g., by transmitting a prompt via the example user interface 112) and / or may automatically reduce the 0.5 GHz reduction to a smaller amount so that the temperature reduction triggered by the adjustment learns, which causes the lower clock frequency to be applied for a shorter period of time. In some examples, the power control unit 106 may calculate the suggested amount by using statistical analysis of the core's operation and the corresponding clock frequency and / or the corresponding temperature. Figure 2 An example power control unit 106 is further described.

[0023] Figure 1 The example user interface 112 displays prompts generated by the example power control unit 106. Additionally, the user interface 112 obtains overclocking preferences from the user and provides the overclocking preferences to the power control unit 106. In some examples, the user interface 112 transmits prompts to suggest adjusting preferences (e.g., based on historical data) and / or to let the user know that the configuration has been adjusted based on historical data.

[0024] Figure 2 yes Figure 1 1 is a block diagram of an example implementation of a power control unit 106. The example power control unit 106 includes an example component interface 200, an example configuration storage 202, an example comparator(s) 204, and an example clock rate / voltage regulator 206.

[0025] Figure 2The example component interface 200 transmits and / or obtains data from other components. For example, the component interface 200 transmits prompts to the user interface 112 and / or obtains user preferences from the user interface 112. Additionally, the component interface 200 provides an interface to the sensor(s) 104 to obtain temperature measurements. Additionally, the component interface 200 provides an interface to the core(s) 102 to determine how many of the core(s) 102 are active at a given point in time. Additionally, the example interface 200 provides an interface to one or more clocks of the processing unit 100 and / or the core(s) 102 to instruct the clocks to increase and / or decrease clock rates according to an overclocking configuration. In some examples, the interface 200 provides an interface to the processing unit 100 and / or one or more of the core(s) 102 to instruct one or more cores 102 and / or other components of the processing unit 100 to adjust supply voltage levels based on the obtained temperature(s).

[0026] Figure 2 The example configuration storage device 202 stores overclocking configuration details. For example, the configuration storage device 202 stores pre-selected and / or user-selected temperature thresholds, slopes, incremental increases, incremental decreases, supply voltages, etc. based on user (e.g., via user interface 112) and / or manufacturer (e.g., preset) overclocking preferences. In this manner, the example comparator(s) 204 can compare the obtained temperature and / or the determined rate of temperature change to various threshold(s) based on the user and / or manufacturer overclocking preferences. In some examples, the user provides a supply voltage in conjunction with a specific temperature, a change in temperature, a clock rate / frequency, a change in clock rate frequency, and / or the number of active cores. In this manner, the power control unit 106 can adjust the supply voltage based on the temperature, clock rate, and / or the number of active cores. In some examples, the configuration storage device 202 stores previous temperature readings and stores these previous temperature readings in conjunction with core context information (e.g., a timestamp of the temperature measurement, the clock speed(s) at the time of the temperature measurement, the number of cores running at the time of the temperature measurement, etc.). In this manner, comparator(s) 204 may compare historical data to patterns for suggesting different overclocking configurations based on the historical data.

[0027] The example comparator(s) 204 compares the temperature measurements obtained from the example sensor(s) 104 to one or more thresholds defined by the overclocking configuration stored in the example configuration storage device 202. For example, if the overclocking configuration corresponds to reducing the overclocked clock speed of a particular core by 0.1 GHz when the temperature corresponding to the core is above 50°C, the comparator(s) 204 compares the temperature corresponding to the core from the sensor 104 and compares the temperature to the 50°C threshold to determine whether the temperature is above or below the threshold. In some examples, the threshold can be based on the temperature and the number of active cores. For example, the overclocking configuration can correspond to adjusting the overclocked frequency when three cores 102 are active and the temperatures corresponding to the three cores 102 are above 60°C or below 45°C. In such an example, the comparator(s) 204 identifies how many cores 102 are active and the temperatures corresponding to the active cores, and outputs a value indicating when three cores are active and the temperature is outside the range of 45°C to 60°C. The output of comparator(s) 204 (e.g., a value corresponding to whether the sensed temperature meets one or more thresholds) is transmitted to clock rate / voltage regulator 206 to adjust the clock rate and / or supply voltage of processing unit 100 based on the comparison.

[0028] Figure 2The example clock rate / voltage regulator 206 adjusts the overclocked clock rate to increase or decrease the block frequency based on the output of the comparator(s) 204. The example clock rate / voltage regulator 206 adjusts the clock frequency based on an amount defined by the overclocking configuration. For example, if the overclocking configuration corresponds to reducing the clock rate of a particular core by 0.2 GHz when the temperature corresponding to the particular core is above 50° C., and the comparator 204 outputs a signal indicating that the temperature corresponding to the particular core is above 50° C., the clock rate / voltage regulator 206 accesses the configuration storage 202 to determine that the clock frequency of the particular core should be adjusted by 0.2 GHz, and sends a signal to the processing unit 100 and / or the particular core to instruct the core to reduce the clock signal by 0.2 GHz. Additionally, when the measured temperature is below one or more thresholds (e.g., defined by a user and / or manufacturer and stored in the example configuration storage 202), and / or based on the clock rate and / or the number of active cores, the example clock rate / voltage regulator 206 can adjust the supply voltage used by the example processing unit 100 to save energy. When the temperature of the silicon components is low, the clock rate is slow, and / or the number of active cores is low, the processing unit 100 may operate at a lower supply voltage, and when the temperature of the silicon components is high, the clock rate is fast, and / or the number of active cores is high, the processing unit 100 requires a higher supply voltage to operate. Thus, a user and / or manufacturer can select one or more temperature thresholds, clock rate thresholds, and / or the number of active cores corresponding to one or more (or a group of) cores 102 to adjust the supply voltage to save energy. Thus, when the temperature is below one or more temperature thresholds, the clock rate is below a threshold, and / or the number of active cores is below a threshold, the example clock rate / voltage regulator 206 can transmit instructions to the example processing unit 100 and / or one or more cores 102 to reduce the supply voltage. The example clock rate / voltage regulator 206 can be a single component (e.g., a component that regulates both the clock rate and the supply voltage) or can be two components (e.g., a first component for regulating the clock rate and a second component for regulating the supply voltage).

[0029] Despite Figure 1 and / or Figure 2 An example manner of implementing an example power control unit 112 is illustrated in FIG. Figure 1 and / or Figure 2 One or more of the elements, processes and / or devices illustrated in the drawings may be combined, split, rearranged, omitted, removed and / or implemented in any other manner. Figure 2The example component interface 200, the example configuration storage 202, the example comparator(s) 204, the example clock rate / voltage regulator 206, and / or more generally, the example power control unit 106 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, any of the following can be implemented by one or more analog or digital circuits, logic circuits, programmable processor(s), programmable control(s), graphics processing unit(s) (GPUs), digital signal processor(s) (DSPs), application specific integrated circuit(s) (ASICs), programmable logic device(s) (PLDs), and / or field programmable logic device(s) (FPLDs): Figure 2 The example component interface 200, the example configuration storage device 202, the example comparator(s) 204, the example clock rate / voltage regulator 206, and / or more generally, the example power control unit 106. When reading any of the apparatus or system claims of this patent covering pure software and / or firmware implementations, Figure 2 The example component interface 200, the example configuration storage 202, the example comparator(s) 204, the example clock rate / voltage regulator 206, and / or more generally, at least one of the example power control unit 106 is thereby expressly defined as including a non-transitory computer-readable storage device or storage disk (such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc.) containing software and / or firmware. Further, the example power control unit 106 may include as Figure 1 and / or Figure 2 As used herein, the phrase "communicating" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-time events.

[0030] exist Figure 3-Figure 8 The diagram shows the method used to implement Figure 1 and / or Figure 2 Flowchart of example hardware logic, machine readable instructions, hardware implemented state machine and / or any combination thereof for an example power control unit 106. The machine readable instructions may be one or more executable programs or portions of executable programs for execution by a computer processor, such as described below in conjunction with Figure 10 The processor 1012 is shown in the example processor platform 1000 discussed. The program(s) may be embodied in software stored on a non-transitory computer-readable storage medium such as a CD-ROM, floppy disk, hard drive, DVD, Blu-ray disc, or memory associated with the processor 1012, but all and / or portions of the program(s) may alternatively be executed by a device other than the processor 1012 and / or embodied in firmware or dedicated hardware. Further, although reference is made to Figure 10 The flowcharts shown in FIG. 1 describe example procedures (one or more), but implementations Figure 1 and / or Figure 2 Many other methods of implementing the example power control unit 106 may be used alternatively. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, removed, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational-amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0031] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, an encapsulated format, and the like. The machine-readable instructions described herein may be stored as data (e.g., portions of instructions, code, code representations, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., a server). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, and the like so that they are directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and stored on separate computing devices, wherein the parts, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program such as the program described herein.

[0032] In another example, the machine-readable instructions may be stored in a state in which they are computer-readable, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the instructions on a particular computing device or other device. In another example, the machine-readable instructions and / or corresponding program(s) may need to be configured (e.g., stored settings, entered data, recorded network addresses, etc.) before the machine-readable instructions and / or corresponding program(s) can be executed in whole or in part. Thus, the disclosed machine-readable instructions and / or corresponding program(s) are intended to encompass such machine-readable instructions and / or program(s) regardless of the particular format or state of the machine-readable instructions and / or program(s) when stored or otherwise at rest or in transit.

[0033] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented by any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0034] As mentioned above, the present invention may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on a non-transitory computer and / or machine readable medium. Figure 3-Figure 8 In an example process of a non-transitory computer and / or machine readable medium, such as a hard drive, flash memory, read-only memory, compact disk, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, for a brief instance, for temporary buffering, and / or for caching information). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable storage device and / or storage disk and to exclude propagating signals and to exclude transmission media.

[0035] "Include" and "comprising" (and all their forms and tenses) are used herein as open-ended terms. Thus, whenever a claim uses any form of "include" and "comprising" (e.g., includes, comprises, including, containing, having, etc.) as a preamble or within any type of claim recitation, it is understood that additional elements, items, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transition term, such as in the preamble of a claim, it is open-ended in the same manner as the terms "include" and "comprising." When used, for example, in a form such as A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, and (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, actions, and / or steps, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of a process, instruction, action, action, and / or step, the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B.

[0036] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude the plural. As used herein, the term "a" or "an" entity refers to one or more of that entity. The terms "a" (or "an"), "one or more," and "at least one" may be used interchangeably herein. Furthermore, although listed separately, a plurality of devices, elements, or method actions may be implemented by, for example, a single unit or processor. Additionally, although individual features may be included in different examples or claims, these features may potentially be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0037] Figure 3 The diagram illustrates how operations may be performed to implement an example power control unit 106 ( Figure 1 and / or Figure 2 ) to adjust Figure 1 A flow chart of example machine readable instructions 300 for controlling the clock rate of processing unit 100. Figure 3 The flowchart of the example processing unit 100 is described in conjunction with the example power control unit 106, but other types of power control units (one or more) and / or other types of processing units (one or more) may be utilized instead. Additionally, although the example instructions 300 correspond to updating an overclocked clock rate based on temperature, the instructions 300 may be used in conjunction with any clock rate.

[0038] At block 302, the example component interface 200 determines whether a user has provided overclocking preferences via the example user interface 112. The component interface 200 may cause a prompt to be displayed to the user to allow the user to select overclocking preferences (e.g., when to increment or decrement the clock rate of one or more cores, how much to increment or decrement, etc.). If the example component interface 200 determines that the user has not provided overclocking preferences (block 302: No), control continues to block 306, and the power control unit 106 uses a preset or pre-stored configuration stored in the example configuration storage 202. If the example component interface 200 determines that the user has provided overclocking preferences (block 302: Yes), the example configuration storage 202 stores an overclocking configuration based on the provided overclocking preferences (e.g., obtained from the user interface 112) (block 304).

[0039] At block 306, the example comparator(s) 204 access the stored overclocking configuration stored in the example configuration storage 202 to determine whether the overclocking configuration corresponds to an individual core or to the number of active cores. As described above, the overclocking configuration can be based on an individual core, a group of cores, and / or the number of active cores. If the example comparator(s) 204 determines that the overclocking configuration (e.g., stored in the configuration storage 202) is based on an individual core (block 306: individual), the example power control unit 106 adjusts the clock rate of the processing unit 100 based on the data corresponding to the individual core 102 (block 308), as described below in conjunction with Figure 4 If the example comparator(s) 204 determine that the overclocking configuration (e.g., stored in the configuration storage device 202) is based on the number of active cores (block 306: number), the example power control unit 106 adjusts the clock rate of the processing unit 100 based on data corresponding to the number of active cores 102 (block 310), as described below in conjunction with Figure 5 Further description.

[0040] Figure 4 The figure shows a flowchart representative of example machine readable instructions 308 that may be executed to implement the power control unit 106 to adjust the clock rate of the processing unit 100 based on data corresponding to the individual cores 102. Figure 4 The flowchart of the example processing unit 100 is described in conjunction with the example power control unit 106, but other types of power control units (one or more) and / or other types of processing units (one or more) may be utilized instead. Additionally, although the example instructions 300 correspond to updating an overclocked clock rate based on temperature, the instructions 300 may be used in conjunction with any clock rate.

[0041] At block 402, the example clock rate / voltage regulator 206 causes the clock speed (e.g., clock rate) of one or more cores 102 to increase based on the overclocking configuration. For example, the clock rate / voltage regulator 206 will initiate overclocking by increasing the clock rate of one or more cores 102 in the core(s) 102 to an overclocked clock rate defined by the overclocking configuration. At block 404, the example component interface 200 receives a request from Figure 1 One or more of the sensor(s) 104 obtain(s) temperature measurements.

[0042] For each of the (one or more) individual cores 102 (blocks 406-416), the example comparator(s) 204 determine whether the temperature corresponding to the individual core is above (e.g., meets) a maximum threshold defined by the overclocking configuration (block 408). For example, the comparator(s) 204 accesses a first temperature threshold (e.g., a maximum temperature threshold) corresponding to the core and compares the obtained temperature of the core to the corresponding first temperature threshold. In some examples, the comparator(s) 204 may determine the slope / rate of change of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) may compare the rate / slope of temperature change to a user-defined slope threshold.

[0043] If the example comparator(s) 204 determine that the measured temperature corresponding to the individual core is not above the first threshold defined by the overclocking configuration (block 408: No), control continues to block 412. If the example comparator(s) 204 determine that the measured temperature corresponding to the individual core is above the first threshold defined by the overclocking configuration (block 408: Yes), the example clock rate / voltage regulator 206 reduces the clock rate of the individual core by an amount defined by the overclocking configuration (e.g., by sending a signal to the processing unit 100 and / or the individual core 102) (block 410). Reducing the clock rate of the individual core will reduce the temperature and / or reduce the rate at which the temperature increases.

[0044] At block 412, the example comparator(s) 204 determine whether the temperature corresponding to the individual core is below (e.g., meets) a minimum threshold defined by the overclocking configuration (block 408). For example, the comparator(s) 204 accesses a second temperature threshold (e.g., a minimum temperature threshold) corresponding to the core and compares the obtained temperature of the core to the corresponding second temperature threshold. In some examples, the comparator(s) 204 may determine the rate of change / slope of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) may compare the rate of change / slope of the temperature to a user-defined slope threshold.

[0045] If the example comparator(s) 204 determine that the measured temperature corresponding to the individual core is not below the second threshold value defined by the overclocking configuration (block 412: No), control continues to block 416. If the example comparator(s) 204 determine that the measured temperature corresponding to the individual core is below the second threshold value defined by the overclocking configuration (block 412: Yes), the example clock rate / voltage regulator 206 (e.g., sends a signal to the processing unit 100 and / or the individual core 102) increases the clock rate of the individual core by an amount defined by the overclocking configuration (block 414). Increasing the clock rate of the individual core will increase the temperature and / or reduce the rate at which the temperature decreases.

[0046] At block 418, the example configuration storage device 202 determines whether the user has provided new / updated overclocking preferences (e.g., the new overclocking preferences are obtained from the user interface 112 via the component interface 200). If the example configuration storage device 202 determines that the user has not provided new / updated overclocking preferences (block 418: No), control returns to block 404. If the example configuration storage device 202 determines that the user has provided new / updated overclocking preferences (block 418: Yes), control returns to Figure 3 304 of the box.

[0047] Figure 5 A flowchart representative of example machine readable instructions 310 that may be executed to implement the power control unit 106 to adjust the clock rate of the processing unit 100 based on data corresponding to the number of active cores is shown. Figure 5 The flowchart of the example processing unit 100 is described in conjunction with the example power control unit 106, but other types of power control units and / or other types of processing units may be utilized instead. Additionally, although the example instructions 300 correspond to updating an overclocked clock rate based on temperature, the instructions 300 may be used in conjunction with any clock rate.

[0048] At block 502, the example clock rate / voltage regulator 206 causes the clock speed (e.g., clock rate) of one or more of the core(s) 102 to increase based on the overclocking configuration. For example, the clock rate / voltage regulator 206 initiates overclocking by increasing the clock rate of one or more of the core(s) 102 to an overclocked clock rate defined by the overclocking configuration. At block 504, the example interface 200 provides an interface to the core 102 to determine the number of active cores. At block 506, the example component interface 200 receives a request from the core 102 to determine the number of active cores. Figure 1 One or more of the sensor(s) 104 obtain(s) temperature measurements.

[0049] At block 508, the example comparator(s) 204 determine whether the temperature corresponding to the active core is greater than (e.g., meets) a maximum threshold value corresponding to the number of active cores defined by the overclocking configuration. For example, the comparator(s) 204 accesses a first temperature threshold value (e.g., a maximum temperature threshold value) corresponding to the number of active cores and compares the obtained temperature for the active cores to the corresponding first temperature threshold value. In some examples, the comparator(s) 204 may determine the slope / rate of change of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) may compare the rate of change / slope of the temperature to a user-defined slope threshold value.

[0050] If the example comparator(s) 204 determine that the measured temperature corresponding to the active core is not above the first threshold value for the number of active cores defined by the overclocking configuration (block 508: No), control continues to block 512. If the example comparator(s) 204 determine that the measured temperature corresponding to the active core is above the first threshold value for the number of active cores defined by the overclocking configuration (block 508: Yes), the example clock rate / voltage regulator 206 (e.g., sends a signal to the processing unit 100 and / or the individual core 102) reduces the clock rate of the active core by an amount defined by the overclocking configuration (block 510). Reducing the clock rate of the individual core will reduce the temperature and / or reduce the rate at which the temperature increases.

[0051] At block 512, the example comparator(s) 204 determine whether the temperature corresponding to the active core is below (e.g., meets) a minimum threshold value corresponding to the number of active cores defined by the overclocking configuration. For example, the comparator(s) 204 accesses a second temperature threshold value (e.g., a minimum temperature threshold value) corresponding to the number of active cores and compares the obtained temperature for the active core to the corresponding second temperature threshold value. In some examples, the comparator(s) 204 may determine the slope / rate of change of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) may compare the rate of change / slope of the temperature to a user-defined slope threshold value.

[0052] If the example comparator(s) 204 determine that the measured temperature corresponding to the active core is not below the second threshold value for the number of active cores defined by the overclocking configuration (block 512: No), control continues to block 516. If the example comparator(s) 204 determine that the measured temperature corresponding to the active core is above the second threshold value for the number of active cores defined by the overclocking configuration (block 512: Yes), the example clock rate / voltage regulator 206 increases the clock rate of the active core by an amount defined by the overclocking configuration (e.g., by sending a signal to the processing unit 100 and / or the individual core 102) (block 514). Increasing the clock rate of the individual core will increase the temperature and / or reduce the rate at which the temperature decreases.

[0053] At block 516, the example configuration storage device 202 determines whether the user has provided new / updated overclocking preferences (e.g., the new overclocking preferences are obtained from the user interface 112 via the component interface 200). If the example configuration storage device 202 determines that the user has not provided new / updated overclocking preferences (block 516: No), control returns to block 504. If the example configuration storage device 202 determines that the user has provided new / updated overclocking preferences (block 516: Yes), control returns to Figure 3 304 of the box.

[0054] Figure 6 The diagram illustrates how operations may be performed to implement an example power control unit 106 ( Figure 1 and / or Figure 2 ) to adjust Figure 1 A flow chart of example machine readable instructions 600 for controlling one or more supply voltages for processing unit 100. Figure 6 The flowchart of the example embodiment of the present invention is described in conjunction with the example power control unit 106 of the example processing unit 100, but other types of power control units and / or other types of processing units may be utilized instead. Additionally, the example instructions 600 may correspond to updating the supply voltage during overclocking or normal operation of the processing unit 100.

[0055] At block 602, the example component interface 200 determines whether a user has provided a supply voltage preference via the example user interface 112. The component interface 200 may cause a prompt to be displayed to the user to allow the user to select a supply voltage preference (e.g., when to increment or decrement the supply voltage of one or more cores, how much to increment or decrement, etc.). If the example component interface 200 determines that the user has not provided a supply voltage preference (block 602: No), control continues to block 606, and the power control unit 106 uses a preset or pre-stored configuration stored in the example configuration storage 202. If the example component interface 200 determines that the user has provided a supply voltage preference (block 602: Yes), the example configuration storage 202 stores a supply voltage configuration based on the provided supply voltage preference (e.g., obtained from the user interface 112) (block 604).

[0056] At block 606, the example comparator(s) 204 accesses the stored supply voltage configuration stored in the example configuration storage 202 to determine whether the supply voltage configuration corresponds to an individual core or corresponds to the number of active cores. As described above, the supply voltage configuration can be based on individual cores, groups of cores, and / or the number of active cores. If the example comparator(s) 204 determines that the supply voltage configuration (e.g., stored in the configuration storage 202) is based on an individual core (block 606: individual), the example power control unit 106 adjusts the supply voltage of the processing unit 100 based on the data corresponding to the individual core 102 (block 608), as described below in conjunction with Figure 7 If the example comparator(s) 204 determine that the supply voltage configuration (e.g., stored in the configuration storage device 202) is based on the number of active cores (block 606: number), the example power control unit 106 adjusts the supply voltage of the processing unit 100 based on data corresponding to the number of active cores 102 (block 610), as described below in conjunction with Figure 8 Further description.

[0057] Figure 7 A flowchart representative of example machine-readable instructions 608 that may be executed to implement the power control unit 106 to adjust one or more supply voltages of the processing unit 100 based on data corresponding to the individual cores 102 is shown. Figure 7 Flowchart 600 is described in conjunction with example power control unit 106 of example processing unit 100, but other types of power control units and / or other types of processing units may be utilized instead. In some examples, instructions 600 may correspond to updating a supply voltage during overclocking or normal operation of processing unit 100.

[0058] At block 702, the example clock rate / voltage regulator 206 causes a voltage driver of one or more of the core(s) 102 to output a supply voltage at a first voltage based on a supply voltage configuration. For example, the clock rate / voltage regulator 206 initiates the supply voltage to a first voltage defined by the supply voltage configuration. At block 704, the example component interface 200 receives a signal from the core(s) 102. Figure 1 One or more of the sensor(s) 104 obtain temperature measurement(s) and / or may determine a clock frequency of one or more of the core(s) 102 .

[0059] For each of the (one or more) individual cores 102 (blocks 706-716), the example comparator(s) 204 determine whether the temperature and / or frequency corresponding to the individual core is above (e.g., meets) a corresponding maximum threshold (e.g., a maximum temperature threshold and / or a maximum frequency threshold) defined by the supply voltage configuration (block 708). For example, the comparator(s) 204 accesses a first temperature threshold (e.g., a maximum temperature threshold) and / or a first frequency threshold (e.g., a maximum frequency threshold) corresponding to the core and compares the obtained temperature and / or determined frequency for the core to the corresponding first corresponding threshold. In some examples, the comparator(s) 204 may determine the slope / rate of change of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) may compare the rate of change / slope of the temperature to a user-defined slope threshold.

[0060] If the example comparator(s) 204 determine that the measured temperature and / or the determined frequency corresponding to the individual core is not above the first corresponding threshold value defined by the supply voltage configuration (block 708: No), control continues to block 712. If the example comparator(s) 204 determine that the measured temperature and / or the determined frequency corresponding to the individual core is above the first corresponding threshold value defined by the supply voltage configuration (block 708: Yes), the example clock rate / voltage regulator 206 (e.g., by sending a signal to the processing unit 100 and / or the individual core 102) causes the driver to increase the supply voltage by an amount defined by the supply voltage configuration (block 710). Increasing the supply voltage of the individual core will ensure that the core is able to operate properly (e.g., the higher the temperature and / or clock rate, the higher the supply voltage required for error-free operation).

[0061] At block 712, the example comparator(s) 204 determine whether the temperature and / or clock frequency corresponding to the individual core is below (e.g., meets) a corresponding minimum threshold (e.g., a minimum temperature threshold and / or a minimum clock frequency threshold) defined by the supply voltage configuration (block 712). For example, the comparator(s) 204 accesses a second temperature threshold (e.g., a minimum temperature threshold) and / or a second clock rate threshold (e.g., a minimum clock rate threshold) corresponding to the core and compares the obtained temperature and / or clock rate for the core to the second corresponding threshold. In some examples, the comparator(s) 204 may determine the slope / rate of change of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) may compare the rate of change / slope of the temperature to a user-defined slope threshold.

[0062] If the example comparator(s) 204 determine that the measured temperature and / or the clock rate corresponding to the individual core is not below the second corresponding threshold value defined by the overclocking configuration (block 712: No), control continues to block 716. If the example comparator(s) 204 determine that the measured temperature and / or the determined clock rate corresponding to the individual core is below the second corresponding threshold value defined by the supply voltage configuration (block 712: Yes), the example clock rate / voltage regulator 206 causes the driver of the corresponding core(s) to reduce the supply voltage (block 714, for example, by sending a signal to the processing unit 100 and / or the individual core 102). Reducing the supply voltage of the individual core saves energy while ensuring that the core can operate properly because the silicon components can operate properly at the lower supply voltage when the temperature and / or clock frequency of the silicon components are lower.

[0063] At block 718, the example configuration storage device 202 determines whether the user has provided new / updated supply voltage preferences (e.g., the new supply voltage preferences are obtained from the user interface 112 via the component interface 200). If the example configuration storage device 202 determines that the user has not provided new / updated supply voltage preferences (block 718: No), control returns to block 704. If the example configuration storage device 202 determines that the user has provided new / updated supply voltage preferences (block 718: Yes), control returns to Figure 6 604 of the box.

[0064] Figure 8 A flowchart representative of example machine readable instructions 610 that may be executed to implement the power control unit 106 to adjust one or more supply voltages of the processing unit 100 based on data corresponding to the number of active cores is shown. Figure 8The flowchart of the example embodiment of the present invention is described in conjunction with the example power control unit 106 of the example processing unit 100, but other types of power control units and / or other types of processing units may be utilized instead. Additionally, the example instructions 600 may correspond to updating the supply voltage during overclocking or normal operation of the processing unit 100.

[0065] At block 802, the example clock rate / voltage regulator 206 causes a voltage driver of one or more cores 102 in the core(s) 102 to output a supply voltage at a first voltage based on a supply voltage configuration. For example, the clock rate / voltage regulator 206 initiates the supply voltage to a first voltage defined by the supply voltage configuration. At block 804, the example interface 200 provides an interface to the cores 102 to determine the number of active cores. At block 806, the example component interface 200 receives a request from the core 102 to determine the number of active cores. Figure 1 One or more of the sensor(s) 104 obtain(s) temperature measurements, and / or determine or obtain a clock rate from the core 102 .

[0066] At block 808, the example comparator(s) 204 determine whether the temperature corresponding to the active cores and / or the clock rate of the active cores is above (e.g., meets) a corresponding maximum threshold (e.g., a maximum temperature threshold or a maximum clock rate threshold) corresponding to the number of active cores defined by the supply voltage configuration. For example, the comparator(s) 204 accesses a first temperature threshold (e.g., a maximum temperature threshold) and / or a first clock rate threshold (e.g., a maximum clock rate threshold) corresponding to the number of active cores and compares the obtained temperature and / or clock rate for the active cores to the corresponding first corresponding threshold. In some examples, the comparator(s) 204 may determine the slope / rate of change of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) may compare the rate of change / slope of the temperature to a user-defined slope threshold.

[0067] If the example comparator(s) 204 determine that the measured temperature and / or clock rate corresponding to the active core(s) is not above the first corresponding threshold for the number of active cores defined by the supply voltage configuration (block 808: NO), control continues to block 812. In some examples, the comparator(s) 204 can determine the slope / rate of change of the temperature by comparing the temperature to a previous temperature taken at a previous point in time. In such examples, in addition to or in lieu of a single temperature comparison, the comparator(s) can compare the rate of change / slope of the temperature to a user-defined slope threshold.

[0068] If the example comparator(s) 204 determine that the measured temperature and / or clock rate corresponding to the active core(s) is above a first corresponding threshold value for the number of active cores defined by the supply voltage configuration (block 808: yes), the example clock rate / voltage regulator 206 increases the supply voltage of the active cores by an amount defined by the supply voltage configuration (e.g., by sending a signal to the processing unit 100 and / or the individual cores 102) (block 810). Reducing the clock rate of the individual cores will reduce the temperature and / or reduce the rate at which the temperature increases.

[0069] At block 812, the example comparator(s) 204 determine whether the temperature and / or clock rate corresponding to the active core is below (e.g., meets) a corresponding minimum threshold value corresponding to the number of active cores defined by the overclocking configuration. For example, the comparator(s) 204 accesses a second temperature threshold value (e.g., a minimum temperature threshold value) and / or a second clock rate threshold value (e.g., a minimum clock rate threshold value) corresponding to the number of active cores and compares the obtained temperature and / or clock rate for the active core to the corresponding second threshold value. If the example comparator(s) 204 determine that the measured temperature and / or clock rate corresponding to the active core is not below the second threshold value for the number of active cores defined by the overclocking configuration (block 812: No), control continues to block 816. If the example comparator(s) 204 determine that the measured temperature and / or clock rate corresponding to the active core is above a second threshold value for the number of active cores defined by the overclocking configuration (block 812: yes), the example clock rate / voltage regulator 206 (e.g., sends a signal to the processing unit 100 and / or the individual core 102) reduces the supply voltage of the active core by an amount defined by the supply voltage configuration (block 814). Increasing the clock rate of the individual core will increase the temperature and / or reduce the rate at which the temperature decreases.

[0070] At block 816, the example configuration storage device 202 determines whether the user has provided new / updated supply voltage preferences (e.g., the new supply voltage preferences are obtained from the user interface 112 via the component interface 200). If the example configuration storage device 202 determines that the user has not provided new / updated supply voltage preferences (block 816: No), control returns to block 804. If the example configuration storage device 202 determines that the user has provided new / updated supply voltage preferences (block 816: Yes), control returns to Figure 6 604 of the box.

[0071] Figure 9 An example graphical user interface 900 for customizing overclocking preferences is shown. The example graphical user interface 900 includes an example package option 902 , an example per-core option 904 , an example number of cores option 906 , an example initial overclock frequency option 908 , an example temperature threshold 910 , and an example decrement value 912 .

[0072] Figure 9 The example graphical user interface 900 can be customized to adjust the clock frequency (e.g., clock rate) based on the number of active cores (e.g., when package option 902 is selected) or on a per-core basis (e.g., when per-core option 904 is selected). Figure 9 In the example, package option 902 is enabled. Thus, the options are based on the number of active cores 906. The user can select an initial overclocked clock rate using the example initial overclock frequency option 908. Additionally, by setting a temperature threshold 910 based on the number of active cores, the user can select a temperature threshold to initiate a decrement of the clock rate. When the example per-core option 904 is enabled, the user can select a different temperature threshold on a per-core basis. The user can select how much to decrement the clock rate by setting the example decrement value 912. In some examples, the interface 900 may include other thresholds (e.g., a minimum threshold, one or more temperature slope thresholds, etc.) with other values for increasing and / or decrementing the clock rate.

[0073] While example interface 900 includes certain options, additional and / or alternative options corresponding to the examples disclosed herein may be included. For example, an option corresponding to a supply voltage level and a corresponding threshold value may be included in interface 900 .

[0074] Figure 10 is constructed to execute Figure 3-Figure 8 Instructions to achieve Figure 1 and / or Figure 2The processor platform 1000 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smartphone, an iPad, etc.). TM tablet) or any other type of computing device.

[0075] The processor platform 1000 of the illustrated example includes a processor 1012. The processor 1012 of the illustrated example is hardware. For example, the processor 1012 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor can be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements Figure 2 The example component interface 200 , the example comparator(s) 204 , and / or the example clock rate / voltage regulator 206 .

[0076] The processor 1012 of the illustrated example includes a local memory 1013 (e.g., cache). The processor 1012 of the illustrated example communicates with a main memory including a volatile memory 1014 and a non-volatile memory 1016 via a bus 1018. The volatile memory 1014 may be comprised of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory (DRAM) Dynamic Random Access Memory, ) and / or any other type of random access memory device. The non-volatile memory 1016 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 1014, 1016 is controlled by a memory controller. In some examples, the main memory 1014 implements the example memory and the example local memory 1013 implements Figure 2 An example configuration storage device 202 is provided.

[0077] The processor platform 1000 of the illustrated example further includes an interface circuit 1020. The interface circuit 1020 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), interface, near field communication (NFC) interface and / or PCI express interface. Figure 10 In the example, the interface circuit 1020 implements Figure 2 However, the interface 200 may be an interface with Figure 10 The interface circuit 1020 is a separate component.

[0078] In the illustrated example, one or more input devices 1022 are connected to the interface circuitry 1020. The input device(s) 1022 permit a user to enter data and / or commands into the processor 1012. The input device(s) may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an iso-mouse, and / or a voice recognition system.

[0079] One or more output devices 1024 are also connected to the interface circuit 1020 of the illustrated example. The output device 1024 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-place switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuit 1020 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics driver processor.

[0080] The interface circuitry 1020 of the illustrated example also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate exchanging data with external machines (e.g., any kind of computing device) via the network 1026. Communication can be via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a cellular telephone system, etc.

[0081] The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 for storing software and / or data. Examples of such mass storage devices 1028 include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and digital versatile disk (DVD) drives.

[0082] Figure 3-Figure 8 The machine-executable instructions 1032 may be stored in the mass storage device 1028, in the volatile memory 1014, in the non-volatile memory 1016, and / or on a removable non-transitory computer-readable storage medium such as a CD or DVD.

[0083] Figure 11 The diagram shows how to convert Figure 10 1032 to a third party. The example software distribution platform 1105 may be implemented by any computer server, data facility, cloud service, etc. that is capable of storing software and delivering it to other computing devices. The third party may be a customer of the entity that owns and / or operates the software distribution platform. For example, the entity that owns and / or operates the software distribution platform may be a software (such as Figure 10 The third party may be a consumer, user, retailer, OEM, etc. who purchases and / or licenses the software for use and / or resale and / or sublicensing. In the illustrated example, the software distribution platform 1105 includes one or more servers and one or more storage devices. The storage device stores the computer readable instructions 1032, which can be used with Figure 3-Figure 8 The example computer readable instructions 1032 of the example software distribution platform 1105 correspond to one or more of the example computer readable instructions 1032, as described above. One or more servers of the example software distribution platform 1105 communicate with a network 1110, which may correspond to any one or more of the Internet and / or any of the example networks 1026 described above. In some examples, as part of a business transaction, one or more servers transmit the software to the requestor in response to the request. Payment for the delivery, sale, and / or license of the software may be processed by one or more servers of the software distribution platform and / or via a third-party payment entity. The server enables a purchaser and / or licensor to download the computer readable instructions 1032 from the software distribution platform 1105. For example, the software (which may be Figure 10The example computer readable instructions 1032 corresponding to the example computer readable instructions 1032 may be downloaded to the example processor platform 1000, which will execute the computer readable instructions 1032 to implement Figure 1 and / or Figure 2 In some examples, one or more servers of the software distribution platform 1105 periodically provide, transmit, and / or enforce the software (e.g., Figure 10 Example computer readable instructions 1032) to ensure that improvements, patches, updates, etc. are distributed and applied to the software at the end user device.

[0084] Disclosed herein are example methods, apparatus, systems, and articles of manufacture for dynamically configuring overclocked frequencies. Further examples and combinations thereof include the following: Example 1 includes an apparatus for dynamically configuring overclocked frequencies, the apparatus comprising: a clock rate adjuster for operating a processor core at a first overclocked clock rate; a comparator for comparing a sensed temperature corresponding to the processor core to a threshold; and the clock rate adjuster for reducing the clock rate of the processor core from the first overclocked clock rate by a user-defined amount when the sensed temperature meets the threshold, the reduced clock rate being higher than a normal operating clock rate of the processor core.

[0085] Example 2 includes the apparatus of Example 1, wherein the sensed temperature is a first sensed temperature at a first time, the threshold is a first threshold, and the user-defined amount is a first user-defined amount; wherein the comparator is used to compare a second sensed temperature corresponding to the processor core at a second time different from the first time, and the clock rate adjuster is used to increase the clock rate of the processor core from the reduced clock rate by a second user-defined amount when the second sensed temperature corresponding to the processor core meets the second threshold.

[0086] Example 3 includes the apparatus of Example 2, wherein the second threshold is the first threshold, and the second user-defined amount is the first user-defined amount.

[0087] Example 4 includes the apparatus of Example 1, wherein the first overclocked clock rate is a user-defined overclocked clock rate.

[0088] Example 5 includes the apparatus of Example 1, wherein the clock rate adjuster is to cause a plurality of cores to operate at a first overclocked clock rate, the plurality of cores comprising a processor core, the comparator is to determine a threshold based on a number of the plurality of cores that are active and to compare one or more sensed temperatures corresponding to the plurality of active cores to the threshold, and the clock rate adjuster is to reduce the clock rate of the plurality of active cores from the first overclocked clock rate by a user-defined amount when the one or more sensed temperatures satisfy the threshold.

[0089] Example 6 includes the apparatus of Example 1, wherein the threshold is a first threshold and the comparator is used to compare the sensed temperature with a second threshold; the apparatus further includes a voltage regulator that is used to increase the supply voltage of the processor core when the sensed temperature meets the second threshold.

[0090] Example 7 includes the apparatus of Example 6, wherein the sensed temperature is a first sensed temperature at a first time, wherein the comparator is used to compare a second sensed temperature corresponding to the processor core at a second time different from the first time, and wherein the clock rate adjuster is used to reduce the supply voltage of the processor core when the second sensed temperature corresponding to the processor core satisfies a third threshold.

[0091] Example 8 includes the apparatus of Example 7, wherein the clock rate adjuster is to at least one of: increase the supply voltage by a user-defined amount, or decrease the supply voltage by a user-defined amount.

[0092] Example 9 includes a non-transitory computer-readable storage medium comprising instructions that, when executed, cause one or more processors to at least: operate a processor core at a first overclocked clock rate; compare a sensed temperature corresponding to the processor core to a threshold; and when the sensed temperature meets the threshold, reduce the clock rate of the processor core from the first overclocked clock rate by a user-defined amount, the reduced clock rate being higher than a normal operating clock rate of the processor core.

[0093] Example 10 includes the computer-readable storage medium of Example 9, wherein the sensed temperature is a first sensed temperature at a first time, the threshold is a first threshold, and the user-defined amount is a first user-defined amount; wherein the instructions cause the one or more processors to: compare a second sensed temperature corresponding to the processor core at a second time different from the first time; and increase a clock rate of the processor core from the reduced clock rate by a second user-defined amount when the second sensed temperature corresponding to the processor core satisfies the second threshold.

[0094] Example 11 includes the computer-readable storage medium of Example 10, wherein the second threshold is the first threshold, and the second user-defined amount is the first user-defined amount.

[0095] Example 12 includes the computer-readable storage medium of Example 9, wherein the first overclocked clock rate is a user-defined overclocked clock rate.

[0096] Example 13 includes the computer-readable storage medium of Example 9, wherein the instructions cause one or more processors to: operate a plurality of cores at a first overclocked clock rate, the plurality of cores comprising a processor core; determine a threshold based on the number of the plurality of cores that are active; compare one or more sensed temperatures corresponding to the plurality of active cores to the threshold; and when the one or more sensed temperatures meet the threshold, reduce the clock rate of the plurality of active cores from the first overclocked clock rate by a user-defined amount.

[0097] Example 14 includes the computer-readable storage medium of Example 9, wherein the threshold is a first threshold and the instructions cause the one or more processors to compare the sensed temperature to a second threshold, and increase a supply voltage to the processor core when the sensed temperature satisfies the second threshold.

[0098] Example 15 includes the computer-readable storage medium of Example 14, wherein the sensed temperature is a first sensed temperature at a first time, wherein the instructions cause the one or more processors to: compare a second sensed temperature corresponding to the processor core at a second time different from the first time, and reduce a supply voltage to the processor core when the second sensed temperature corresponding to the processor core satisfies a third threshold.

[0099] Example 16 includes the computer-readable storage medium of Example 15, wherein the instructions cause the one or more processors to at least one of: increase the supply voltage by a user-defined amount, or decrease the supply voltage by a user-defined amount.

[0100] Example 17 includes an apparatus for dynamically configuring an overclocked frequency, the apparatus comprising: a memory; and at least one processor for executing instructions to: cause a processor core to operate at a first overclocked clock rate; compare a sensed temperature corresponding to the processor core to a threshold; and when the sensed temperature meets the threshold, reduce the clock rate of the processor core from the first overclocked clock rate by a user-defined amount, the reduced clock rate being higher than a normal operating clock rate of the processor core.

[0101] Example 18 includes the apparatus of Example 17, wherein the sensed temperature is a first sensed temperature at a first time, the threshold is a first threshold, and the user-defined amount is a first user-defined amount; wherein at least one processor is to: compare a second sensed temperature corresponding to the processor core at a second time different from the first time, and increase a clock rate of the processor core from the reduced clock rate by a second user-defined amount when the second sensed temperature corresponding to the processor core satisfies the second threshold.

[0102] Example 19 includes the apparatus of Example 18, wherein the second threshold is the first threshold, and the second user-defined amount is the first user-defined amount.

[0103] Example 20 includes the apparatus of Example 17, wherein the first overclocked clock rate is a user-defined overclocked clock rate.

[0104] Example 21 includes the apparatus of Example 17, wherein at least one processor is to: operate a plurality of cores at a first overclocked clock rate, the plurality of cores comprising a processor core; determine a threshold based on the number of the plurality of cores that are active; compare one or more sensed temperatures corresponding to the plurality of active cores to the threshold; and reduce the clock rate of the plurality of active cores from the first overclocked clock rate by a user-defined amount when the one or more sensed temperatures meet the threshold.

[0105] Example 22 includes the apparatus of Example 17, wherein the threshold is a first threshold, and the at least one processor is to compare the sensed temperature to a second threshold, and increase a supply voltage of the processor core when the sensed temperature satisfies the second threshold.

[0106] Example 23 includes the apparatus of Example 22, wherein the sensed temperature is a first sensed temperature at a first time, wherein at least one processor is to perform: comparing a second sensed temperature corresponding to the processor core at a second time different from the first time, and reducing a supply voltage of the processor core when the second sensed temperature corresponding to the processor core satisfies a third threshold.

[0107] Example 24 includes the apparatus of Example 23, wherein the at least one processor is to at least one of: increase the supply voltage by a user-defined amount, or decrease the supply voltage by a user-defined amount.

[0108] Example 25 includes a method for dynamically configuring an overclocked frequency, the method comprising: operating a processor core at a first overclocked clock rate; comparing a sensed temperature corresponding to the processor core to a threshold by executing instructions using one or more processors; and when the sensed temperature meets the threshold, reducing the clock rate of the processor core from the first overclocked clock rate by a user-defined amount by executing instructions using one or more processors, the reduced clock rate being higher than a normal operating clock rate of the processor core.

[0109] Example 26 includes the method of Example 25, wherein the sensed temperature is a first sensed temperature at a first time, the threshold is a first threshold, and the user-defined amount is a first user-defined amount; the method further includes: comparing a second sensed temperature corresponding to the processor core at a second time different from the first time; and increasing the clock rate of the processor core from the reduced clock rate by a second user-defined amount when the second sensed temperature corresponding to the processor core satisfies the second threshold.

[0110] Example 27 includes the method of Example 26, wherein the second threshold is the first threshold, and the second user-defined amount is the first user-defined amount.

[0111] Example 28 includes the method of Example 25, wherein the first overclocked clock rate is a user-defined overclocked clock rate.

[0112] Example 29 includes the method of Example 25, further comprising: operating a plurality of cores at a first overclocked clock rate, the plurality of cores comprising a processor core; determining a threshold based on the number of the plurality of cores that are active; and comparing one or more sensed temperatures corresponding to the plurality of active cores to the threshold; and reducing the clock rate of the plurality of active cores from the first overclocked clock rate by a user-defined amount when the one or more sensed temperatures meet the threshold.

[0113] Example 30 includes the method of Example 25, wherein the threshold is a first threshold; and the method further comprises: comparing the sensed temperature to a second threshold; and increasing the supply voltage of the processor core when the sensed temperature satisfies the second threshold.

[0114] Example 31 includes the method of Example 30, wherein the sensed temperature is a first sensed temperature at a first time, and the method further includes: comparing a second sensed temperature corresponding to the processor core at a second time different from the first time; and reducing the supply voltage of the processor core when the second sensed temperature corresponding to the processor core meets a third threshold.

[0115] Example 32 includes the method of Example 31, further comprising at least one of increasing the supply voltage by a user-defined amount, or decreasing the supply voltage by a user-defined amount.

[0116] Example 33 includes an apparatus for dynamically configuring an overclocked frequency, the apparatus comprising: means for causing a processor core to operate at a first overclocked clock rate; means for comparing a sensed temperature corresponding to the processor core to a threshold; and means for causing the processor core to operate for: reducing the clock rate of the processor core from the first overclocked clock rate by a user-defined amount when the sensed temperature meets the threshold, the reduced clock rate being higher than a normal operating clock rate of the processor core.

[0117] Example 34 includes the apparatus of Example 33, wherein the sensed temperature is a first sensed temperature at a first time, the threshold is a first threshold, and the user-defined amount is a first user-defined amount; wherein the means for comparing is for comparing a second sensed temperature corresponding to the processor core at a second time different from the first time, and the means for causing the processor core to operate is for increasing the clock rate of the processor core from the reduced clock rate by a second user-defined amount when the second sensed temperature corresponding to the processor core satisfies the second threshold.

[0118] Example 35 includes the device of Example 34, wherein the second threshold is the first threshold, and the second user-defined amount is the first user-defined amount.

[0119] Example 36 includes the device of Example 33, wherein the first overclocked clock rate is a user-defined overclocked clock rate.

[0120] Example 37 includes the apparatus of Example 33, wherein the means for causing the processor core to operate is for causing a plurality of cores to operate at a first overclocked clock rate, the plurality of cores comprising the processor core; the means for comparing is for determining a threshold based on the number of the plurality of cores that are active and comparing one or more sensed temperatures corresponding to the plurality of active cores to the threshold; and the means for causing the processor core to operate is for reducing the clock rate of the plurality of active cores from the first overclocked clock rate by a user-defined amount when the one or more sensed temperatures satisfy the threshold.

[0121] Example 38 includes the apparatus of Example 33, wherein the threshold is a first threshold and the means for comparing is for comparing the sensed temperature to a second threshold, the apparatus further comprising means for increasing a supply voltage to the processor core when the sensed temperature satisfies the second threshold.

[0122] Example 39 includes the apparatus of Example 38, wherein the sensed temperature is a first sensed temperature at a first time, wherein the means for comparing is for comparing a second sensed temperature corresponding to the processor core at a second time different from the first time, and wherein the means for causing the processor core to operate is for reducing a supply voltage of the processor core when the second sensed temperature corresponding to the processor core satisfies a third threshold.

[0123] Example 40 includes the apparatus of Example 39, wherein the means for causing the processor core to operate is to at least one of increase the supply voltage by a user-defined amount or decrease the supply voltage by a user-defined amount.

[0124] As will be appreciated from the foregoing description, example methods, apparatus, and articles of manufacture for dynamically configuring overclocked frequencies have been disclosed herein. The disclosed methods, apparatus, and articles of manufacture improve the efficiency of a computer by enabling the computer to switch between overclocked clock rates to operate at increased speeds without risking reaching maximum temperatures. The disclosed methods, apparatus, and articles of manufacture accordingly relate to one or more improvements in the operation of a computer.

[0125] Although certain example methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent fairly covers all methods, apparatus, and articles of manufacture falling within the scope of the claims of this patent.

Claims

1. A processor, comprising: at least one core configured to be powered by a voltage, the at least one core configured to operate at a frequency associated with a clock; a sensor for sensing a temperature of the at least one core; as well as A circuit is provided for performing the following operations based on a sensed temperature being within a temperature range: reducing the voltage applied to the at least one core based on a voltage offset; as well as The frequency of the clock applied to the at least one core is increased, the temperature range is based on a first user input, and the voltage offset is based on a second user input.

2. The processor of claim 1, wherein: The circuit is configured to adjust the voltage applied to the at least one core based on the number of cores that are active.

3. The processor of claim 1, wherein: The temperature range is defined by a temperature threshold.

4. The processor of claim 1, wherein: The at least one core is configured to execute instructions based on a clock rate corresponding to the frequency.

5. The processor of claim 1, wherein: Based on the sensed temperature being outside the temperature range, the circuit is configured to: increasing the voltage applied to the at least one core based on the voltage offset; and The frequency of the clock applied to the at least one core is reduced.

6. A computer-readable medium comprising instructions for causing at least one programmable circuit to at least: Based on at least one core's sensed temperature being within the temperature range: reducing a voltage applied to the at least one core based on the voltage offset; and A frequency of a clock signal applied to the at least one core is increased, the temperature range is based on a first user input, and the voltage offset is based on a second user input.

7. The computer-readable medium of claim 6, wherein: The instructions cause one or more of the at least one programmable circuit to adjust the voltage applied to the at least one core based on a number of cores that are active.

8. The computer-readable medium of claim 6, wherein: The temperature range is defined by a temperature threshold.

9. The computer-readable medium of claim 6, wherein: The instruction is a first instruction, and one or more of the at least one core is to execute a second instruction based on a clock rate corresponding to the frequency.

10. The computer-readable medium of claim 6, wherein: Based on the sensed temperature being outside the temperature range, the instructions cause one or more of the at least one programmable circuit to: increasing the voltage applied to the at least one core based on the voltage offset; and The frequency of the clock signal is reduced.

11. A system comprising: Volatile memory; Non-volatile memory; Interface circuit; as well as Processor, including: at least one core to be powered by a voltage, the at least one core to operate at a frequency associated with a clock signal; a sensor for sensing a temperature of the at least one core; and A circuit is provided for performing the following operations based on a sensed temperature being within a temperature range: reducing the voltage provided to the at least one core based on the voltage offset; and The frequency of the clock signal is increased, the temperature range is based on a first user input, and the voltage offset is based on a second user input.

12. The system of claim 11, wherein: The circuit is configured to adjust the voltage provided to the at least one core based on the number of cores that are active.

13. The system of claim 11, wherein: The temperature range is defined by a temperature threshold.

14. The system of claim 11, wherein: The at least one core is configured to execute instructions based on a clock rate corresponding to the frequency.

15. The system of claim 11, wherein: Based on the sensed temperature being outside the temperature range, the circuit is configured to: increasing the voltage applied to the at least one core based on the voltage offset; and The frequency of the clock applied to the at least one core is reduced.

16. A processor comprising: One or more cores; at least one temperature sensor for sensing a temperature corresponding to at least one of the one or more cores; as well as A power control unit is configured to dynamically adjust at least one of an operating frequency or a supply voltage of at least one of the one or more cores based on a user-selected overclocking preference, wherein the adjustment of the power control unit is based on a plurality of temperature thresholds.

17. The processor of claim 16, wherein: The power control unit is configured to dynamically adjust the at least one of the operating frequency or the supply voltage of the at least one core among the one or more cores based on the number of active cores.

18. The processor of claim 16, wherein: The user selected overclocking preferences are used to obtain from the configuration storage device.

Images