Processor and processor operation control method

Abstract

To suppress current consumption of a processor from exceeding an upper limit when each of a plurality of cores variably controls a clock frequency and a power supply voltage.SOLUTION: In a processor comprising a plurality of cores including floating-point units, a frequency / voltage control unit provided corresponding to each core supplies the corresponding core with a clock having a variable frequency and a power-supply voltage having a variable voltage. An instruction issuance control unit provided in each core controls the issuance of floating-point operation instructions to the floating-point unit, and reduces the issuance frequency of floating-point operation instructions to the floating-point unit when the current frequency value is greater than a reference frequency value or when the current power-supply voltage value is greater than a reference power-supply voltage value. This makes it possible to prevent the current consumption of the processor from exceeding an upper limit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a processor and a method for controlling the operation of a processor. [Background technology]

[0002] A known processor has a pipeline including sequentially connected instruction units and execution units, and local clock buffers that generate clocks to be supplied to the instruction units and execution units from a common clock. When a stall bit is negated, each local clock buffer starts supplying clocks to the pipeline stages in order, starting from the upstream stage, thereby suppressing large current fluctuations and reducing noise (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2007 / 521538 Summary of the Invention [Problem to be solved by the invention]

[0004] Recently, some multi-core processors have a DVFS (Dynamic Voltage and Frequency Scaling) function that can dynamically control the clock frequency and power supply voltage for each core. For example, by using the DVFS function to increase the clock frequency and power supply voltage when a low-power program is executed, processing performance can be improved.

[0005] On the other hand, when the clock frequency and power supply voltage of a core of interest are high and another core is executing a program that consumes high power, the clock frequency and power supply voltage of the core of interest are lowered so that the processor's current consumption does not exceed the upper limit. However, under DVFS control, it takes a certain number of cycles for the clock frequency and power supply voltage to be lowered. Therefore, even when executing a program that consumes low power, the processor does not increase the clock frequency and power supply voltage sufficiently, preventing the processor's power consumption from exceeding the upper limit.

[0006] Increasing the number of power supply pins on a processor can increase the upper limit of the processor's current consumption. However, increasing the number of power supply pins increases the package size, which can lead to an increase in the size of the board on which the package is mounted. Therefore, even if the upper limit of current consumption can be increased, the cost of the processor and the system in which the processor is installed increases.

[0007] In one aspect, the present invention aims to prevent the current consumption of a processor from exceeding an upper limit when the clock frequency and power supply voltage are variably controlled in each of a plurality of cores. [Means for solving the problem]

[0008] According to one aspect, the processor has a plurality of cores each including a floating-point arithmetic unit, a frequency / voltage control unit provided corresponding to each of the plurality of cores and supplying a variable frequency clock and a variable voltage power supply voltage to the corresponding core, and an instruction issuance control unit provided in each of the plurality of cores and controlling the issuance of floating-point arithmetic instructions to the floating-point arithmetic unit, and reducing the frequency of issuance of floating-point arithmetic instructions to the floating-point arithmetic unit the greater the current frequency value of the clock is than a reference frequency value or the greater the current power supply voltage value is than the reference power supply voltage value. [Effects of the Invention]

[0009] When the clock frequency and power supply voltage are variably controlled for each of a plurality of cores, the current consumption of the processor can be prevented from exceeding the upper limit. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processor according to one embodiment. [Figure 2] 2 is an explanatory diagram showing an example of control of the frequency of issuing floating-point arithmetic instructions in each core of FIG. 1; [Figure 3] FIG. 10 is a block diagram illustrating an example of a processor according to another embodiment. [Figure 4] 4 is a flow chart showing an overview of the operation of each core of the processor of FIG. 3. [Figure 5] 4 is a block diagram showing an example of an issue frequency determination unit in FIG. 3. FIG. [Figure 6] 6 is a flowchart showing an example of the operation of the issue frequency determination unit of FIG. 5. [Figure 7] 6 is a diagram illustrating an example of the operation of a counter and an AND circuit in the issue frequency determination unit in FIG. 5. [Figure 8] 7 is a diagram illustrating another example of the operation of the counter and the AND circuit in the issue frequency determination unit in FIG. 5. [Figure 9] 4 is a flowchart showing an example of the operation of the instruction execution unit of FIG. 3. [Figure 10] FIG. 10 is a block diagram illustrating an example of a processor according to another embodiment. [Figure 11] 11A and 11B are diagrams illustrating an example of adjustment of a current frequency value and a current power supply voltage value by the frequency / voltage control unit of FIG. 10. [Figure 12] FIG. 10 is a block diagram illustrating an example of a processor according to another embodiment. [Figure 13] 13 is an explanatory diagram showing an example of the operation when the frequency of issuing floating-point arithmetic instructions is insufficient in each core of the processor of FIG. 12. FIG. [Figure 14] 13 is a flow chart showing an example of the operation of each core of the processor of FIG. 12. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, the same reference numerals as the signal names are used for signal lines through which signals are transmitted, and the same reference numerals as the voltage names are used for voltage lines through which voltages are supplied. Although not particularly limited, the processor described below is a superscalar processor that executes instructions in parallel through pipeline processing.

[0012] Fig. 1 shows an example of a processor according to an embodiment. The processor 100 shown in Fig. 1 has a plurality of cores 10 and a frequency / voltage control unit 20 provided for each of the cores 10. Each core 10 has a floating-point arithmetic unit 12 that executes a floating-point arithmetic instruction INS, and an instruction issuance control unit 11 that issues the floating-point arithmetic instruction INS to the floating-point arithmetic unit 12.

[0013] The frequency / voltage control unit 20 supplies a variable frequency clock CLK and a variable voltage power supply voltage VDD to the corresponding core 10. The frequency / voltage control unit 20 also outputs a frequency value F1 indicating the frequency of the clock CLK and a power supply voltage value V1 indicating the voltage value of the power supply voltage VDD to the instruction issuance control unit 11 of the corresponding core 10.

[0014] Each core 10 operates based on the clock CLK and power supply voltage VDD received from the frequency / voltage control unit 20. That is, the processor 100 has a DVFS function that dynamically controls the frequency of the clock CLK and the power supply voltage VDD for each core 10.

[0015] The instruction issuance control unit 11 reduces the frequency of issuing floating-point calculation instructions to the floating-point calculation unit 12 as the frequency of the current clock CLK becomes higher based on the frequency value F1, or as the current power supply voltage VDD becomes higher based on the power supply voltage value V1.

[0016] 2 shows an example of control of the frequency of issuing floating-point calculation instructions INS in each core 10 of FIG. 1. As explained in FIG. 1, the instruction issuance control unit 11 reduces the frequency of issuing floating-point calculation instructions to the floating-point calculation unit 12 as the frequency of the current clock CLK or the current power supply voltage VDD increases. Also, as shown by reversing the time axis in FIG. 2, the instruction issuance control unit 11 increases the frequency of issuing floating-point calculation instructions to the floating-point calculation unit 12 as the frequency of the current clock CLK or the current power supply voltage VDD decreases.

[0017] For example, when the frequency of the clock CLK supplied to the core 10 is increased, the frequency / voltage control unit 20 outputs a frequency value F1 indicating the increased frequency value to the instruction issuance control unit 11. The instruction issuance control unit 11 detects that the frequency of the clock CLK has increased based on the frequency value F1, and reduces the frequency of issuing floating-point operation instructions to the floating-point operation unit 12 in accordance with the increase in frequency.

[0018] Furthermore, when the frequency / voltage control unit 20 increases the power supply voltage VDD supplied to the core 10, it outputs a power supply voltage value V1 indicating the increased value of the power supply voltage VDD to the instruction issuance control unit 11. The instruction issuance control unit 11 detects that the power supply voltage VDD has increased based on the power supply voltage value V1, and reduces the frequency of issuing floating-point calculation instructions INS to the floating-point calculation unit 12 in accordance with the increase in the power supply voltage VDD.

[0019] Furthermore, when the frequency of the clock CLK and the power supply voltage VDD supplied to the core 10 are increased, the frequency / voltage control unit 20 outputs a frequency value F1 indicating the increased frequency value and a power supply voltage value V1 indicating the increased power supply voltage VDD value to the instruction issuance control unit 11. The instruction issuance control unit 11 detects that the frequency of the clock CLK and the power supply voltage VDD have increased based on the frequency value F1 and the power supply voltage value V1, and reduces the frequency of issuing floating-point calculation instructions INS to the floating-point calculation unit 12.

[0020] This makes it possible to suppress an increase in power consumption of processor 100 due to an increase in either or both of the frequency of clock CLK and the power supply voltage VDD. Therefore, even when either or both of the frequency of clock CLK and the power supply voltage VDD of core 10b are increased, it is not necessary to reduce the frequency of clock CLK and the power supply voltage VDD of core 10b. Therefore, it is possible to prevent the power consumption of processor 100 from exceeding the upper limit before the frequency of clock CLK and the power supply voltage VDD of core 10b decrease to a predetermined value.

[0021] By changing the frequency of issuing floating-point arithmetic instructions in conjunction with changes in the clock CLK frequency and power supply voltage VDD, it is possible to suppress fluctuations in the power consumption of core 10 due to changes in the clock CLK frequency and power supply voltage VDD. Therefore, even if the power consumption of other cores 10 increases, each core 10 can continue executing floating-point arithmetic instructions without lowering the clock CLK frequency and power supply voltage VDD of its own core 10. In other words, each core 10 can continue operating using an appropriate clock CLK frequency and power supply voltage VDD without being affected by the operation of other cores 10.

[0022] Since there is no need to control the frequency of the clock CLK and the power supply voltage VDD in a coordinated manner among the multiple cores 10, it is possible to simplify the control of the power control unit and the like that manages the frequency of the clock CLK and the power supply voltage VDD of the multiple cores 10. Furthermore, since each core 10 controls the amount of power consumption individually, it is possible to prevent the amount of power consumption of the processor 100 from exceeding the upper limit.

[0023] 1 and 2, when the frequency of the clock CLK and the power supply voltage VDD are variably controlled for each of the multiple cores 10, the frequency of issuing floating-point arithmetic instructions is changed in conjunction with changes in the frequency of the clock CLK and the power supply voltage VDD for each core 10. This makes it possible to prevent the current consumption of the processor 100 from exceeding the upper limit.

[0024] 3 shows an example of a processor according to another embodiment. The processor 100A shown in FIG. 3 includes multiple cores 200, a frequency / voltage control unit 300 provided for each of the cores 200, and a power control unit 400 provided in common to the multiple cores 200. Each core 200 includes an instruction decoder 210, an instruction execution unit 220, and a power monitoring unit 290. The instruction execution unit 220 includes a reservation station 230, an instruction issue control unit 240 including an issue instruction selection unit 250 and an issue frequency determination unit 260, a floating-point arithmetic unit 270, and a fixed-point arithmetic unit 280.

[0025] Each core 200 may have a primary cache, an instruction fetch unit, an instruction buffer, etc. in addition to the configuration shown in Fig. 3. Furthermore, the instruction execution unit 220 may have an operand address generator used when executing a load instruction or a store instruction in addition to the configuration shown in Fig. 3.

[0026] The power monitor unit 290 monitors the amount of power consumed within the core 200 and outputs power monitor information PM indicating the monitored amount of power consumption to the power control unit 400 at a predetermined frequency. The power control unit 400 calculates the total amount of power consumption of the multiple cores 200 based on the power monitor information PM received from each core 200, and determines the frequency of the clock CLK and the power supply voltage VDD to be supplied to each core 200 based on the calculation result and the amount of power consumption of each core 200. The power control unit 400 then outputs a frequency / voltage control signal VFCNT indicating the frequency of the clock CLK and the power supply voltage VDD to the frequency / voltage control unit 300 corresponding to each core 200 at a predetermined frequency. The power monitor information PM is an example of power information, and the frequency / voltage control signal VFCNT is an example of change information for changing the frequency of the clock CLK and the power supply voltage VDD.

[0027] The frequency / voltage control unit 300 may include a regulator (not shown) that generates a power supply voltage VDD and a PLL (Phase Locked Loop) (not shown) that generates a clock CLK. When the frequency / voltage control unit 300 receives a frequency / voltage control signal VFCNT, it changes the frequency of the clock CLK to the frequency indicated by the frequency / voltage control signal VFCNT and changes the power supply voltage VDD to the voltage indicated by the frequency / voltage control signal VFCNT. The frequency / voltage control unit 300 then outputs the changed frequency of the clock CLK and the power supply voltage VDD to the corresponding core 200.

[0028] Each time the frequency and power supply voltage VDD are changed, the frequency / voltage control unit 300 outputs a setting signal SET, a frequency value F1 indicating the changed frequency, and a power supply voltage value V1 indicating the changed power supply voltage VDD to the issue frequency determination unit 260 of the corresponding core 200. The frequency / voltage control unit 300 also outputs a reference frequency value F0 indicating a reference value of the frequency of the clock CLK and a reference power supply voltage value V0 indicating a reference value of the power supply voltage VDD to the issue frequency determination unit 260 of the corresponding core 200. For example, the reference frequency value F0 and the reference power supply voltage value V0 are not changed while the processor 100A is booted. Hereinafter, the frequency value F1 will also be referred to as the current frequency value F1, and the power supply voltage value V1 will also be referred to as the current power supply voltage value V1.

[0029] The instruction decoder 210, for example, decodes instructions output from an instruction buffer (not shown) and outputs the decoded instructions to the reservation station 230. For example, the instruction decoder 210 decodes floating-point arithmetic instructions, fixed-point arithmetic instructions, load instructions, store instructions, etc.

[0030] The reservation station 230 includes a queue that holds instructions output from the instruction decoder 210, and outputs the instructions held in the queue in the order in which they can be executed. That is, instructions are executed out of order. The reservation station 230 outputs floating-point arithmetic instructions to the issue instruction selection unit 250 of the instruction issuance control unit 240. The reservation station 230 outputs fixed-point arithmetic instructions to the fixed-point arithmetic unit 280 without going through the instruction issuance control unit 240. The reservation station 230 outputs load instructions and store instructions to an operand address generator (not shown) without going through the instruction issuance control unit 240.

[0031] The reservation station 230 deletes from the queue a floating-point arithmetic instruction that has been executed by the floating-point arithmetic unit 270, and deletes from the queue a fixed-point arithmetic instruction that has been executed by the fixed-point arithmetic unit 280. The instruction execution unit 220 may also have a commitment control unit (not shown) that completes the execution of instructions in order.

[0032] When the execution of a floating-point arithmetic instruction output to the instruction issuance control unit 240 is suppressed due to a decrease in the frequency of issuing floating-point arithmetic instructions by the instruction issuance control unit 240, the reservation station 230 holds the floating-point arithmetic instruction without deleting it from the queue. The reservation station 230 is an example of a scheduler.

[0033] If the enable signal EN from the issue frequency determination unit 260 indicates a valid state when the issue instruction selection unit 250 receives a floating-point calculation instruction from the reservation station 230, the issue instruction selection unit 250 issues the floating-point calculation instruction to the floating-point calculation unit 270. If the enable signal EN from the issue frequency determination unit 260 indicates an invalid state when the issue instruction selection unit 250 receives a floating-point calculation instruction from the reservation station 230, the issue instruction selection unit 250 inhibits the issuance of the floating-point calculation instruction to the floating-point calculation unit 270.

[0034] Note that when there are floating-point arithmetic instructions with high power consumption and floating-point arithmetic instructions with low power consumption, the issue instruction selection unit 250 may use the enable signal EN to control the issuance of floating-point arithmetic instructions whose power consumption when executed by the floating-point arithmetic unit 270 is equal to or greater than a reference value. For example, when the instruction decoder 210 decodes a floating-point arithmetic instruction whose power consumption is equal to or greater than the reference value, the instruction decoder 210 adds a high-frequency flag to the decoded floating-point arithmetic instruction, indicating that the power consumption is equal to or greater than the reference value, and stores the decoded floating-point arithmetic instruction in the reservation station 230. When the instruction decoder 210 decodes a floating-point arithmetic instruction whose power consumption is smaller than the reference value, the instruction decoder 210 stores the decoded floating-point arithmetic instruction in the reservation station 230 without adding a high-frequency flag.

[0035] When the issue instruction selection unit 250 receives a floating-point arithmetic instruction with a high-frequency flag attached from the reservation station 230, it controls the issue frequency of the received floating-point arithmetic instruction using the enable signal EN. When the issue instruction selection unit 250 receives a floating-point arithmetic instruction without a high-frequency flag attached from the reservation station 230, it immediately issues the received floating-point arithmetic instruction to the floating-point arithmetic unit 270.

[0036] For example, floating-point arithmetic instructions whose power consumption is equal to or greater than a reference value are SIMD (Single Instruction Multiple Data) arithmetic instructions, while floating-point arithmetic instructions whose power consumption is less than the reference value are SISD (Single Instruction Single Data) arithmetic instructions. SIMD arithmetic instructions, for example, when one element is 64-bit wide, execute operations on two, four, or eight elements in parallel, resulting in power consumption that is multiples of the number of elements compared to SISD arithmetic instructions that execute operations on one element.

[0037] The issue frequency determination unit 260 is initialized each time it receives the setting signal SET, and uses the reference frequency value F0, the reference power supply voltage value V0, the current frequency value F1, and the current power supply voltage value V1 to determine the output frequency of the enable signal EN, and outputs the enable signal EN at the determined frequency. The output of the enable signal EN indicates that the enable signal EN is set to an enabled state. For example, the issue frequency determination unit 260 decreases the issue frequency of the enable signal EN the higher the current frequency value F1 is the reference frequency value F0, or the higher the current power supply voltage value V1 is the higher the reference power supply voltage value V0. The issue frequency of the enable signal EN indicates the issue frequency of floating-point arithmetic instructions to the floating-point arithmetic unit 270.

[0038] The issue frequency of the enable signal EN may be calculated, for example, by equation (1). If the issue frequency calculated by equation (1) is equal to or greater than "1", the issue frequency is set to "1". By using equation (1), the issue frequency of the enable signal EN can be finely adjusted. In other embodiments, the issue frequency of the enable signal EN may also be calculated by using equation (1). Frequency of issuing the enable signal EN=(reference frequency value F0 / current frequency value F1)×(reference power supply voltage value V0 / current power supply voltage value V1) (1)

[0039] 4 shows an overview of the operation of each core 200 of the processor 100A of FIG. 3. The core 200 repeatedly executes the operation shown in FIG. 4. First, in step S10, the instruction fetch unit of the core 200 outputs an address indicated by a program counter or the like to a memory such as a primary cache, and fetches instructions stored in the memory. For example, the instruction fetch unit sequentially stores the fetched instructions in an instruction buffer.

[0040] Next, in step S11, the instruction decoder 210 of the core 200 reads an instruction from the instruction buffer, decodes it, and transfers the decoded instruction to the reservation station 230. Note that if a reservation station is provided for each type of arithmetic unit, the decoded instruction is transferred to the reservation station corresponding to the arithmetic unit that executes the instruction.

[0041] Next, in step S12, the reservation station 230 of the core 200 holds the instructions transferred from the instruction decoder 210 in a queue, and issues instructions that are ready for execution to an arithmetic unit such as the floating-point arithmetic unit 270, causing the arithmetic unit to execute the operation (out of order).

[0042] Next, in step S13, a completion control unit such as a commitment control unit of core 200 determines the completion of instructions whose execution has been completed in the order in which they are written in the program. Next, in step S14, core 200 updates programmable resources such as a program counter and registers used in the instructions whose completion has been determined by the completion control unit.

[0043] Fig. 5 shows an example of the issue frequency determination unit 260 of Fig. 3. The issue frequency determination unit 260 has a frequency counter 261, a power supply voltage counter 262, and an AND circuit 263. The counter 261 adds a reference frequency value F0 to the counter value, and, when the counter value becomes equal to or greater than the current frequency value F1, sets an enable signal ENf to be valid and subtracts the current frequency value F1 from the counter value.

[0044] The counter 262 performs the process of adding a reference power supply voltage value V0 to the counter value, and when the counter value becomes equal to or greater than the current power supply voltage value V1, sets the enable signal ENv to active and subtracts the current power supply voltage value V1 from the counter value.

[0045] The AND circuit 263 sets the enable signal EN to an enabled state when both the enable signals ENf and ENv are enabled, and sets the enable signal EN to an disabled state when one or both of the enable signals ENf and ENv are disabled. For example, each of the enable signals ENf and ENv is set to a high level when enabled, and to a low level when disabled. For example, the enabled state of the enable signal EN is a high level, and the disabled state of the enable signal EN is a low level.

[0046] FIG. 6 shows an example of the operation of the issue frequency determination unit of FIG. 5. The operation shown in FIG. 6 is executed, for example, for each cycle of the processor 100A. For example, the processor 100A can input an instruction to the arithmetic unit for each cycle. Steps S30 to S36 show the operation of the frequency counter 261. Steps S37 to S43 show the operation of the power supply voltage counter 262. Steps S44 to S46 show the operation of the AND circuit 263. Steps S30 to S36 and steps S37 to S43 are executed in parallel. The counter 261 counts a value indicating the frequency of the clock CLK, and the counter 262 counts a value indicating the power supply voltage VDD.

[0047] In step S30, the counter 261 reads out the counter value CNTf. Next, in step S31, the counter 261 adds the reference frequency value F0 to the read out counter value CNTf and holds the result as the counter value CNTf0.

[0048] Next, in step S32, if the counter value CNTf0 is equal to or greater than the current frequency value F1, the counter 261 sets the enable signal ENf to high level H in step S33 and executes step S34. On the other hand, if the counter value CNTf0 is smaller than the current frequency value F1, the counter 261 sets the enable signal ENf to low level L in step S35 and executes step S36.

[0049] In step S34, the counter 261 subtracts the current frequency value F1 from the counter value CNTf0 and stores the result as the counter value CNTf. In step S36, the counter 261 stores the counter value CNTf0 as the counter value CNTf.

[0050] In step S37, the counter 262 reads out the counter value CNTv. Next, in step S38, the counter 262 adds the reference power supply voltage value V0 to the read out counter value CNTv and holds the result as the counter value CNTv0.

[0051] Next, in step S39, if the counter value CNTv0 is equal to or greater than the current power supply voltage value V1, the counter 262 sets the enable signal ENv to high level H in step S40 and executes step S41. On the other hand, if the counter value CNTv0 is smaller than the current power supply voltage value V1, the counter 262 sets the enable signal ENv to low level L in step S42 and executes step S43.

[0052] In step S41, the counter 262 subtracts the current power supply voltage value V1 from the counter value CNTv0 and stores the result as the counter value CNTv. In step S43, the counter 262 stores the counter value CNTv0 as the counter value CNTv.

[0053] After one of steps S34 and S36 and one of steps S41 and S43 are executed, step S44 is performed. If the enable signals ENf and ENv are both high level H in step S44, the AND circuit 263 sets the enable signal EN to high level H in step S45, thereby permitting the issuance of a floating-point arithmetic instruction. If one or both of the enable signals ENf and ENv are low level L, the AND circuit 263 sets the enable signal EN to low level L in step S46, thereby inhibiting the issuance of a floating-point arithmetic instruction. Then, the operation shown in FIG. 6 ends.

[0054] Fig. 7 shows an example of the operation of the counters 261, 262 and the AND circuit 263 of the issue frequency determination unit 260 in Fig. 5. Fig. 7 shows the operation when the current frequency value F1 is 1.5 GHz and the current power supply voltage value V1 is 0.85 V. The reference frequency value F0 is set to 1.0 GHz, and the reference power supply voltage value V0 is set to 0.80 V.

[0055] 7 and 8, which will be described later, floating-point arithmetic instructions are transferred in each cycle from the reservation station 230 to the instruction issuance control unit 240. Alternatively, Fig. 7 and 8 show only cycles in which a floating-point arithmetic instruction is issued from the reservation station 230, or only cycles in which a floating-point arithmetic instruction, such as an SIMD arithmetic instruction, whose power consumption is equal to or exceeds a reference value, is issued.

[0056] The issue frequency determination unit 260 receives the setting signal SET in the cycle immediately before cycle 1, and in cycle 1 resets the counter value CNTf of the counter 261 to 0.0 and the counter value CNTv of the counter 262 to 0.00.

[0057] First, in cycle 1, the counter 261 adds the reference frequency value F0 (1.0) to the counter value CNTf (=0.0) and holds the result as the counter value CNTf0 (=1.0). Because the counter value CNTf0 (=1.0) is smaller than the current frequency value F1 (=1.5), the counter 261 sets the enable signal ENf to low level L and sets the counter value CNTf to the counter value CNTf0. The counter value CNTf is updated in the next cycle.

[0058] In cycle 1, the counter 262 adds the reference power supply voltage value V0 (0.80) to the counter value CNTv (=0.00) and holds the result as the counter value CNTv0 (=0.80). Because the counter value CNTv0 (=0.80) is smaller than the current power supply voltage value V1 (=0.85), the counter 262 sets the enable signal ENv to low level L and sets the counter value CNTv to the counter value CNTv0. The counter value CNTv is updated in the next cycle. Because the enable signals ENf and ENv are both low level L, the AND circuit 263 sets the enable signal EN to low level L.

[0059] Next, in cycle 2, the counter 261 adds the reference frequency value F0 (1.0) to the counter value CNTf (=1.0) and holds the result as the counter value CNTf0 (=2.0). The counter value CNTf0 (=2.0) of the counter 261 is equal to or greater than the current frequency value F1 (=1.5). Therefore, the counter 261 sets the enable signal ENf to high level H and sets the counter value CNTf to the value (=0.5) obtained by subtracting the current frequency value F1 (=1.5) from the counter value CNTf0 (=2.0).

[0060] In cycle 2, the counter 262 adds the reference power supply voltage value V0 (0.80) to the counter value CNTv (=0.80) and holds the result as the counter value CNTv0 (=1.60). The counter value CNTv0 (=1.60) of the counter 262 is equal to or greater than the current power supply voltage value V1 (=0.85). Therefore, the counter 262 sets the enable signal ENv to high level H and sets the counter value CNTv to the value (=0.75) obtained by subtracting the current power supply voltage value V1 (=0.85) from the counter value CNTv0 (=1.60). Because the enable signals ENf and ENv are both high level H, the AND circuit 263 sets the enable signal EN to high level H.

[0061] From cycle 3 onwards, counters 261, 262 and AND circuit 263 operate in the same way as in cycles 1 and 2, setting enable signal EN to low level L or high level H for each cycle. For example, issue frequency determination unit 260 sets enable signal EN to high level H in 13 cycles out of 22 cycles, and the issue rate of floating-point arithmetic instructions becomes 0.59. Here, the issue rate of floating-point arithmetic instructions indicates the proportion of floating-point arithmetic instructions issued to floating-point arithmetic unit 270 among the floating-point arithmetic instructions transferred from reservation station 230, and the higher the issue rate, the better the processing efficiency.

[0062] Fig. 8 shows another example of the operation of the counters 261, 262 and the AND circuit 263 of the issue frequency determination unit 260 in Fig. 5. Detailed description of the same operations as in Fig. 7 will be omitted. Fig. 8 shows the operation when the current frequency value F1 is 1.6 GHz and the current power supply voltage value V1 is 0.95 V.

[0063] In FIG. 8, the current frequency value F1 (=1.6 GHz) is higher than the current frequency value F1 (=1.5 GHz) in FIG. 7, so the frequency with which the enable signal ENf is set to high level H is lower than in FIG. 7. Also, the current power supply voltage value V1 (=0.95) is higher than the current power supply voltage value V1 (=0.85) in FIG. 7, so the frequency with which the enable signal ENv is set to high level H is lower than in FIG. 7. Therefore, the frequency with which the enable signal EN is set to high level H is lower than in FIG. 7.

[0064] For example, the issue frequency determination unit 260 sets the enable signal EN to high level H in 6 cycles out of 22 cycles, and the issue rate of floating-point arithmetic instructions becomes 0.27. That is, the higher either or both of the current frequency value F1 and the current power supply voltage value V1 are, the lower the issue frequency of floating-point arithmetic instructions and the lower the processing efficiency of floating-point arithmetic instructions.

[0065] Fig. 9 shows an example of the operation of the instruction execution unit 220 of Fig. 3. The operation shown in Fig. 9 is executed every time the reservation station 230 issues an instruction. For example, Fig. 9 shows the operation when the frequency of issuing floating-point arithmetic instructions that consume a large amount of power, such as SIMD arithmetic instructions, to the floating-point arithmetic unit 270 is adjusted.

[0066] Processor 100A may have reservation stations corresponding to floating-point arithmetic unit 270, fixed-point arithmetic unit 280, and operand address generator (not shown in FIG. 3), respectively. In this case, steps S20 and S24 are deleted from FIG. 9, and the operation shown in FIG. 9 is performed every time reservation station 230 for floating-point arithmetic instructions issues a floating-point arithmetic instruction.

[0067] First, in step S20, the instruction execution unit 220 determines whether the instruction received from the reservation station 230 is a floating-point arithmetic instruction. If the instruction is a floating-point arithmetic instruction, the instruction execution unit 220 executes step S21, and if the instruction is not a floating-point arithmetic instruction, the instruction execution unit 220 executes step S24. Instructions that are not floating-point arithmetic instructions include fixed-point arithmetic instructions, load instructions, store instructions, etc.

[0068] In step S21, the instruction execution unit 220 determines whether the floating-point arithmetic instruction has a high power consumption. If the floating-point arithmetic instruction has a high power consumption, the instruction execution unit 220 executes step S22. If the floating-point arithmetic instruction does not have a high power consumption, the instruction execution unit 220 executes step S23. Note that if the issuance frequencies of all of multiple types of floating-point arithmetic instructions with different power consumptions are adjusted, step S21 is omitted.

[0069] In step S22, the instruction execution unit 220 determines whether it is the timing to issue a floating-point arithmetic instruction (i.e., whether the enable signal EN is at high level) using the issue frequency determination unit 260. If it is the timing to issue a floating-point arithmetic instruction, the instruction execution unit 220 executes step S23, and if it is not the timing to issue a floating-point arithmetic instruction, the operation shown in FIG.

[0070] In step S23, the instruction issuance control unit 240 issues a floating-point arithmetic instruction to the floating-point arithmetic unit 270, and the operation shown in Fig. 9 is terminated. The instruction issuance control unit 240 controls the issuance frequency of instructions such as SIMD arithmetic instructions whose power consumption is equal to or greater than a reference value and which have a large effect on reducing power consumption. On the other hand, the instruction issuance control unit 240 does not control the issuance frequency of instructions whose power consumption is less than the reference value and whose suppression of issuance has a small effect on reducing power consumption, and immediately issues the instruction to the floating-point arithmetic unit 270.

[0071] In step S24, if the fixed-point arithmetic instruction is executable, the reservation station 230 issues the fixed-point arithmetic instruction to the fixed-point arithmetic unit 280, and ends the operation shown in Fig. 9. If the load instruction or store instruction is executable, the reservation station 230 issues the load instruction or store instruction to the operand address generator, and ends the operation shown in Fig. 9. That is, for instructions that consume less power than floating-point arithmetic instructions, the issuance frequency is not controlled, and the instruction is immediately issued to the arithmetic unit.

[0072] SIMD arithmetic instructions with high power consumption have a large impact on the current consumption of the processor 100A, while instructions with low power consumption have a small impact on the current consumption of the processor 100A. By controlling the issuance frequency of instructions with a large impact on the current consumption of the processor 100A, it is possible to appropriately control the current consumption of the processor 100A to be kept below the upper limit. On the other hand, if the issuance frequency of instructions with low power consumption is also controlled, the control becomes complex and the size of the control circuit also increases.

[0073] As described above, the embodiments shown in Figures 3 to 9 can also achieve the same effects as the embodiments shown in Figures 1 and 2. For example, in each core 200, even when one or both of the frequency of the clock CLK and the power supply voltage VDD increase due to DVFS control, the frequency of issuing floating-point arithmetic instructions can be reduced, thereby preventing the current consumption of the processor 100A from exceeding the upper limit.

[0074] 3 to 9, the issue frequency determination unit 260 determines the issue frequency of the enable signal EN from equation (1) using the current frequency value F1, the current power supply voltage value V1, the reference frequency value F0, and the reference power supply voltage value V0. Alternatively, the issue frequency determination unit 260 determines the issue frequency of the enable signal EN using a counter 261 that adds the reference frequency value F0 and subtracts the current frequency value F1, and a counter 262 that adds the reference power supply voltage value V0 and subtracts the current power supply voltage value V1. This allows the issue instruction selection unit 250 to adjust the issue frequency of floating-point arithmetic instructions in accordance with the enable signal EN from the issue frequency determination unit 260.

[0075] When the execution of a floating-point arithmetic instruction is suppressed due to a decrease in the issuance frequency of floating-point arithmetic instructions by the instruction issuance control unit 240, the floating-point arithmetic instruction is held without being deleted from the queue. This allows the reservation station 230 to re-output the floating-point arithmetic instruction, the execution of which has been suppressed due to a decrease in the issuance frequency, to the instruction issuance control unit 240. This prevents a problem in which a floating-point arithmetic instruction, the execution of which has been suppressed, is not executed, and prevents malfunction of the processor 100A.

[0076] By controlling the issuance frequency of instructions that have a large effect on the current consumption of the processor 100A and not controlling the issuance frequency of instructions that have a small effect on the current consumption of the processor 100A, it is possible to appropriately control the current consumption of the processor 100A to be below the upper limit value. For example, by controlling the issuance frequency of SIMD arithmetic instructions, which consume significantly more power than SISD arithmetic instructions, it is possible to obtain a greater effect.

[0077] 10 shows an example of a processor according to another embodiment. Elements similar to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The processor 100B shown in FIG. 10 includes a core 200B, a frequency / voltage control unit 300B, and a power control unit 400B, instead of the core 200, the frequency / voltage control unit 300, and the power control unit 400 of FIG. 3.

[0078] 3, except that core 200B has a function of outputting a sleep signal SLP to power control unit 400B when it is not operating and not executing instructions. For example, core 200B sets the sleep signal SLP to a high level during a sleep period when it is not executing instructions and power consumption is reduced, and sets the sleep signal SLP to a low level during an operating period when it is executing instructions and power consumption is increased. The sleep signal SLP is an example of state information that indicates the operating state of core 200B.

[0079] 3, except that the power control unit 400B has a function of calculating the number of active cores, which is the number of active cores 200B, based on the sleep signal SLP and outputting a core count signal CN indicating the number of active cores. If the number of active cores is less than the total number of cores installed in the processor 100B, the power control unit 400B determines that the total power consumption of the processor 100B has a margin relative to the upper limit of the power consumption of the processor 100B. The core count signal CN indicating that the number of active cores is less than the total number of cores is an example of margin information indicating that there is a margin in the total power consumption of the processor 100B or an example of information on the number of active cores of the cores 200B.

[0080] The frequency / voltage control unit 300B corresponding to the operating core 200B has a function of reducing one or both of the current frequency value F1 and the current power supply voltage value V1 when the number of operating cores indicated by the core number signal CN is less than the total number of cores. Other functions of the frequency / voltage control unit 300B are similar to those of the frequency / voltage control unit 300 in Fig. 3. For example, the frequency / voltage control unit 300B reduces one or both of the current frequency value F1 and the current power supply voltage value V1 as the number of operating cores indicated by the core number signal CN decreases.

[0081] 11 shows an example of adjustment of the current frequency value F1 and the current power supply voltage value V1 by the frequency / voltage control unit 300B of FIG. 10. For example, assume that the processor 100B has 16 cores 200B. The frequency / voltage control unit 300B detects the number of operating cores 200B based on the core count signal CN from the power control unit 400B.

[0082] When the number of operating cores 200B is 1-4, the frequency / voltage control unit 300B sets the current frequency value F1 to 300 MHz lower than the frequency of the actual clock CLK, and sets the current power supply voltage value V1 to 100 mV lower than the actual power supply voltage VDD.

[0083] When the number of operating cores 200B is 5-8, the frequency / voltage control unit 300B sets the current frequency value F1 to 200 MHz lower than the frequency of the actual clock CLK, and sets the current power supply voltage value V1 to 70 mV lower than the actual power supply voltage VDD.

[0084] When the number of operating cores 200B is 9-12, the frequency / voltage control unit 300B sets the current frequency value F1 to be 100 MHz lower than the frequency of the actual clock CLK, and sets the current power supply voltage value V1 to be 40 mV lower than the actual power supply voltage VDD.

[0085] When the number of operating cores 200B is 13-16, the frequency / voltage control unit 300B sets the current frequency value F1 to the frequency value of the actual clock CLK, and sets the current power supply voltage value V1 to the value of the actual power supply voltage VDD (no adjustment).

[0086] The frequency / voltage control unit 300B outputs the adjusted current frequency value F1 and current power supply voltage value V1 to the issue frequency determination unit 260 along with a setting signal SET that is output to update the frequency of the clock CLK and the power supply voltage VDD. Based on the setting signal SET, the issue frequency determination unit 260 initializes the counter values ​​CNTf and CNTv described in FIG. 6 to "0" and replaces the current frequency value F1 and the current power supply voltage value V1. The operation of the issue frequency determination unit 260 is the same as in FIGS. 6 to 8 except that the issue frequency of the enable signal EN is different.

[0087] The fewer the number of operating cores 200B, the lower the current frequency value F1 and the current power supply voltage value V1 can be set, thereby increasing the frequency with which the enable signal EN is output by the issue frequency determination unit 260. This improves the efficiency with which floating-point arithmetic instructions are executed by the operating cores 200B.

[0088] Depending on the operating status of the processor 100B, the number of operating cores 200B may be small, and the amount of current may be greater than the upper limit. In such a situation, the processing performance of the processor 100 can be improved by increasing the frequency of issuing floating-point arithmetic instructions that consume a large amount of power, without exceeding the upper limit of the amount of current. In this case, the frequency / voltage control unit 300B adjusts the current frequency value F1 and the current power supply voltage value V1, thereby increasing the frequency of issuing floating-point arithmetic instructions without changing the circuit configuration of the instruction issuance control unit 240.

[0089] The number of groups for adjusting the current frequency value F1 and the current power supply voltage value V1 is not limited to the four groups shown in FIG. 11. The number of cores 200B included in the processor 100B is not limited to 16. The power control unit 400B may output adjustment information for adjusting the current frequency value F1 and the current power supply voltage value V1 to the frequency / voltage control unit 300B based on the power consumption of all cores 200B determined from the power monitor information PM output by each core 200B. In this case, the power control unit 400B does not need to receive the sleep signal SLP.

[0090] As described above, the embodiments shown in Figures 10 and 11 can also achieve the same effects as the embodiments shown in Figures 1 to 9. For example, in each core 200B, even when one or both of the frequency of the clock CLK and the power supply voltage VDD become high due to DVFS control, the frequency of issuing floating-point arithmetic instructions can be reduced, thereby preventing the current consumption of the processor 100B from exceeding the upper limit.

[0091] 10 and 11, the fewer the number of operating cores 200B, the lower the current frequency value F1 and current power supply voltage value V1 can be set for each core 200B. This improves the efficiency with which the operating cores 200B execute floating-point arithmetic instructions, thereby improving the processing performance of the processor 100. In this case, by adjusting the current frequency value F1 and the current power supply voltage value V1 using the frequency / voltage control unit 300B, the frequency at which floating-point arithmetic instructions are issued can be increased without changing the circuit configuration of the instruction issuance control unit 240.

[0092] Figure 12 shows an example of a processor according to another embodiment. Elements similar to those in Figure 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The processor 100C shown in Figure 12 includes a core 200C, a frequency / voltage control unit 300C, and a power control unit 400C, instead of the core 200, frequency / voltage control unit 300, and power control unit 400 of Figure 3. The instruction issuance control unit 240 includes an issue instruction selection unit 250C and an issue frequency determination unit 260C, instead of the issue instruction selection unit 250 and the issue frequency determination unit 260 of Figure 3.

[0093] Hereinafter, the state in which the frequency / voltage control unit 300C outputs a current frequency value F1 indicating the actual frequency of the clock CLK and a current power supply voltage value V1 indicating the actual power supply voltage VDD will be referred to as the normal state. In the following, an example will be shown in which the control of the instruction issuance frequency is performed on floating-point arithmetic instructions. Note that, as described with reference to FIG. 9, the control of the issuance frequency of floating-point arithmetic instructions may also be performed on floating-point arithmetic instructions that consume a large amount of power, such as SIMD arithmetic instructions.

[0094] In a normal state, the issue instruction selection unit 250C monitors for a certain period the issue frequency of floating-point arithmetic instructions issued to the floating-point arithmetic unit 270 in response to floating-point arithmetic instructions received from the reservation station 230. When the issue frequency of floating-point arithmetic instructions falls below a preset reference frequency, the issue instruction selection unit 250C detects an insufficient issue frequency and outputs a request signal REQ to the power control unit 400C, requesting an increase in the issue frequency.

[0095] The issue command selection unit 250C has the same function as the issue command selection unit 250 in Fig. 3, except that it has a function to output a request signal REQ. The request signal REQ is an example of frequency deficiency information that indicates a deficiency in the frequency of issuing floating-point arithmetic instructions. The request signal REQ may be output to the power control unit 400C via the frequency / voltage control unit 300C.

[0096] When the power control unit 400C receives a request signal REQ when there is a margin in the total power consumption of the processor 100C, it outputs a frequency increase signal UP0 to the frequency / voltage control unit 300C connected to the core 200C that output the request signal REQ, instructing it to increase the issuance frequency. Here, if the total power consumption of the processor 100C is less than the upper limit of the power consumption of the processor 100C, the power control unit 400C determines that there is a margin in the total power consumption and outputs a frequency increase signal UP0 according to the margin in the total power consumption. For example, the value of the frequency increase signal UP0, which is represented by multiple bits, increases as the margin in the total power consumption increases. The value of the frequency increase signal UP0 is an example of frequency increase information.

[0097] Upon receiving the frequency improvement signal UP0, the frequency / voltage control unit 300C reduces one or both of the current frequency value F1 and the current power supply voltage value V1 in proportion to the degree of margin indicated by the frequency improvement signal UP0. The frequency / voltage control unit 300C then outputs the current frequency value F1 and the current power supply voltage value V1, which have been changed in one or both ways, and the improvement status signal UP, which indicates the improvement status of the issuance frequency, together with the setting signal SET, to the issuance frequency determination unit 260C.

[0098] When the issue frequency determination unit 260C receives the improvement status signal UP, the issue command selection unit 250C holds the issue frequency of floating-point arithmetic instructions received from the reservation station 230. After initializing the counters 261, 261 of Fig. 5, the issue frequency determination unit 260C generates an enable signal EN using the current frequency value F1 after the change and the current power supply voltage value V1 received from the frequency / voltage control unit 300C.

[0099] When an insufficient issuance frequency is detected, the frequency at which the issue frequency determination unit 260C outputs a high-level enable signal EN can be increased by reducing one or both of the current frequency value F1 and the current power supply voltage value V1. This can increase the frequency at which floating-point arithmetic instructions are issued. In other words, the core 200C that has requested an increase in the issue frequency can increase the frequency at which floating-point arithmetic instructions are issued to the floating-point arithmetic unit 270.

[0100] After the issue frequency determination unit 260C receives the improvement status signal UP, the issue instruction selection unit 250C monitors for a certain period the issue frequency of floating-point arithmetic instructions received from the reservation station 230. If the issue frequency by the reservation station 230 becomes lower than the issue frequency held when the improvement status signal UP was received, the issue instruction selection unit 250C determines that it is not necessary to improve the issue frequency of floating-point arithmetic instructions to the floating-point arithmetic unit 270.

[0101] Since the shortage in the frequency of issuing floating-point arithmetic instructions has been resolved, the issued instruction selection unit 250C outputs a return signal RTN to the frequency / voltage control unit 300C, which returns the current frequency value F1 and the current power supply voltage value V1 to their normal states. The return signal RTN is an example of a resolution signal indicating that the shortage in the frequency of issuing floating-point arithmetic instructions has been resolved.

[0102] Upon receiving the return signal RTN, the frequency / voltage control unit 300C returns the current frequency value F1 and the current power supply voltage value V1 output to the issue frequency determination unit 260C to their normal states. That is, the current frequency value F1 is set to a value indicating the actual frequency of the clock CLK, and the current power supply voltage value V1 is set to a value indicating the actual power supply voltage VDD.

[0103] When the current frequency value F1 and the current power supply voltage value V1 output to the issue frequency determination unit 260C are returned to the normal state, the frequency / voltage control unit 300C outputs the set signal SET and stops outputting the improved state signal UP. As a result, the issue frequency determination unit 260C initializes the counter values ​​CNTf and CNTv to "0" and outputs the enable signal EN at a predetermined frequency using the current frequency value F1 and the current power supply voltage value V1 in the normal state, as shown in Figures 6 to 8.

[0104] This allows the issue frequency determination unit 260C to generate the enable signal EN at a normal state frequency using the original current frequency value F1 and the original current power supply voltage value V1 before receiving the improved state signal UP.

[0105] 13 shows an example of the operation when the frequency of issuing floating-point arithmetic instructions is insufficient in each core 200C of the processor 100C of FIG. 12. Detailed description of the same operations as those in FIG. 2 will be omitted. FIG. 13 shows an example of the operation of the core 200C that has output the request signal REQ. The operation in which the frequency of issuing floating-point arithmetic instructions decreases based on an increase in either or both of the frequency of the clock CLK and the power supply voltage VDD is the same as that in FIG. 2 (FIGS. 13(a) and (b)).

[0106] 13, first, the frequency of issuing floating-point arithmetic instructions is controlled using the current frequency value F1 and the current power supply voltage value V1 in the normal state, which correspond to the actual frequency of the clock CLK and the power supply voltage VDD. After the frequency of issuing floating-point arithmetic instructions decreases, for example, due to a change in the program executed by the core 200C, the frequency of issuing floating-point arithmetic instructions from the reservation station 230 increases (FIG. 13(c)).

[0107] After that, in the normal state, the issued instruction selection unit 250C observes the issuance frequency of floating-point arithmetic instructions. Then, the issued instruction selection unit 250C detects that the issuance frequency of floating-point arithmetic instructions issued to the floating-point arithmetic unit 270 is low compared to the issuance frequency of floating-point arithmetic instructions from the reservation station 230. In other words, the issued instruction selection unit 250 detects an insufficient issuance frequency (FIG. 13(d)).

[0108] 12, the issue instruction selection unit 250 outputs a request signal REQ to the power control unit 400C, and the power control unit 400C outputs a frequency increase signal UP0 to the frequency / voltage control unit 300C. As a result, the current frequency value F1 and the current power supply voltage value V1 are set lower than in the normal state, and the core 200C that output the request signal REQ enters an issue frequency increase state in which the frequency of issuing floating-point arithmetic instructions to the floating-point arithmetic unit 270 increases (FIG. 13(e)).

[0109] After this, for example, due to a change in the program executed by core 200C, the issue frequency of floating-point arithmetic instructions from reservation station 230 decreases (FIG. 13(f)). In the issue frequency increased state, issue instruction selector 250C monitors the issue frequency of floating-point arithmetic instructions. When the issue frequency of floating-point arithmetic instructions becomes equal to or lower than the issue frequency in the normal state before receiving the improved state signal UP, issue instruction selector 250C detects that the insufficient issue frequency has been resolved (FIG. 13(g)).

[0110] Based on the detection by the issue instruction selection unit 250C that the insufficient issuance frequency has been resolved, the frequency / voltage control unit 300C returns the current frequency value F1 and the current power supply voltage value V1 output to the issue frequency determination unit 260C to their normal states. As a result, the issue frequency of floating-point arithmetic instructions returns to the original state before receiving the improvement status signal UP (FIG. 13(h)).

[0111] By performing the control shown in Figure 13, when the program to be executed is switched and the frequency of issuing floating-point arithmetic instructions that consume a large amount of power becomes insufficient, the frequency of issuing can be improved for each core 200C that is not issuing the instructions frequently enough.

[0112] Depending on the program being executed by the processor 100C, the frequency of issuing floating-point arithmetic instructions that consume a large amount of power may be insufficient. For example, highly parallel programs used in areas such as HPC (High Performance Computing) may frequently use floating-point arithmetic instructions.

[0113] At this time, depending on the operating frequency and voltage conditions, the frequency with which floating-point arithmetic instructions are issued to floating-point arithmetic unit 270 may be insufficient, resulting in a failure to achieve the expected performance. In such a situation, if processor 100C has a margin in its power consumption, control can be exercised to increase the frequency with which floating-point arithmetic instructions are issued to core 200C that is not issuing instructions frequently enough, thereby improving processing performance.

[0114] Fig. 14 shows an example of the operation of each core 200C of the processor 100C of Fig. 12. For example, the operation shown in Fig. 14 is started in a normal state when the processor 100C is started.

[0115] First, in step S50, the issued instruction selection unit 250C observes the frequency of issuing floating-point arithmetic instructions for a certain period of time. Next, in step S51, the issued instruction selection unit 250C detects whether the frequency of issuing floating-point arithmetic instructions is insufficient based on the observation result. If the frequency of issuing floating-point arithmetic instructions is insufficient, the operation of step S52 is performed. If the frequency of issuing floating-point arithmetic instructions is not insufficient, the operation returns to step S50.

[0116] In step S52, the power control unit 400C determines whether or not the issuance frequency of floating-point arithmetic instructions can be increased based on the margin of overall power consumption of the processor 100C. If the issuance frequency can be increased, the operation of step S53 is performed. If the issuance frequency cannot be increased, the operation returns to step S50.

[0117] In step S53, the power control unit 400C outputs a frequency increase signal UP0 to the frequency and voltage control unit 300C, causing the frequency and voltage control unit 300C to perform control to increase the issuance frequency of floating-point arithmetic instructions. The core 200C transitions from the normal state to the increased issuance frequency state, increasing the issuance frequency of floating-point arithmetic instructions.

[0118] After transitioning to the issue frequency increased state, in step S54, the issue instruction selection unit 250C monitors the issue frequency of floating-point arithmetic instructions for a certain period of time. Next, in step S55, the issue instruction selection unit 250C detects whether the issue frequency of floating-point arithmetic instructions is insufficient based on the observation result. If the issue frequency is insufficient, the operation of step S56 is performed. If the issue frequency is not insufficient, the operation of step S58 is performed.

[0119] In step S56, the power control unit 400C determines whether or not the issuance frequency of floating-point arithmetic instructions can be increased based on the margin of overall power consumption of the processor 100C. If the issuance frequency can be increased, the operation of step S57 is performed. If the issuance frequency cannot be increased, the operation returns to step S54.

[0120] In step S57, power control unit 400C outputs frequency increase signal UP0 to frequency / voltage control unit 300C, causing frequency / voltage control unit 300C to control the frequency of issuing floating-point arithmetic instructions to be increased. That is, core 200C can further increase the frequency of issuing floating-point arithmetic instructions if there is room for improvement in the overall power consumption of processor 100C in the issue frequency increased state. After step S57, operation returns to step S54.

[0121] If the shortage of the issuance frequency of floating-point arithmetic instructions is resolved, in step S58, the issued instruction selection unit 250C determines whether to return the issuance frequency to the normal state. If the issuance frequency is to be returned to the normal state, the issued instruction selection unit 250C outputs a return signal RTN to the frequency / voltage control unit 300C, and in step S59, the frequency / voltage control unit 300C performs control to return the issuance frequency to the normal state. If the increased issuance frequency state is to be maintained, the operation returns to step S54.

[0122] As described above, the embodiments shown in Figures 12 to 14 can also achieve the same effects as the embodiments shown in Figures 1 to 9. For example, in each core 200C, even when one or both of the frequency of the clock CLK and the power supply voltage VDD increase due to DVFS control, the frequency of issuing floating-point arithmetic instructions can be reduced, thereby preventing the current consumption of the processor 100C from exceeding the upper limit.

[0123] 12 to 14, one or both of the current frequency value F1 and the current power supply voltage value V1 output to a core 200C for which an insufficient issuance frequency of floating-point arithmetic instructions is detected is reduced. This makes it possible to increase the frequency of issuing floating-point arithmetic instructions for each core 200C for which an insufficient issuance frequency is detected. When the processor 100C has a margin for power consumption, control is performed to increase the issuance frequency for a core 200C for which an insufficient issuance frequency of floating-point arithmetic instructions, thereby improving processing performance.

[0124] When the shortage of the issuing frequency of floating-point arithmetic instructions is resolved during the increased issuing frequency state, the enable signal EN can be generated at the frequency before receiving the increased state signal UP by returning one or both of the current frequency value F1 and the current power supply voltage value V1 to the normal state.

[0125] 12 to 14 may be provided with the functions of Fig. 10 and Fig. 11. That is, a sleep signal SLP may be output from each core 200C to the power control unit 400C, and the fewer the number of operating cores 200C, the lower the current frequency value F1 and the current power supply voltage value V1 of each core 200C may be set.

[0126] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) a plurality of cores including a floating-point arithmetic unit; a frequency / voltage control unit provided corresponding to each of the plurality of cores, the frequency / voltage control unit supplying a variable frequency clock and a variable voltage power supply voltage to the corresponding core; an instruction issuance control unit provided in each of the plurality of cores, which controls the issuance of floating-point arithmetic instructions to the floating-point arithmetic unit, and reduces the frequency of issuing floating-point arithmetic instructions to the floating-point arithmetic unit as the current frequency value of the clock is higher than a reference frequency value or the current power supply voltage value is higher than a reference power supply voltage value; A processor having: (Appendix 2) The instruction issuance control unit issues floating-point arithmetic instructions to the floating-point arithmetic unit at an issue frequency (however, not more than "1") calculated by multiplying a ratio F0 / F1 of the reference frequency value F0 to the current frequency value F1 by a ratio V0 / V1 of the reference power supply voltage value V0 to the current power supply voltage value V1. 10. The processor of claim 1. (Appendix 3) the frequency / voltage control unit outputs the reference frequency value, the current frequency value, the reference power supply voltage value, and the current power supply voltage value to the command issuance control unit; The instruction issuance control unit a first counter that operates at a period that allows a floating-point arithmetic instruction to be issued to the floating-point arithmetic unit, and that sequentially increments the reference frequency value; and a second counter that sequentially increments the reference power supply voltage value, repeating an operation of subtracting the reference frequency value from the first counter value when a first counter value of the first counter is equal to or greater than the current frequency value, and subtracting the reference power supply voltage value from the second counter value when a second counter value of the second counter is equal to or greater than the current power supply voltage value; issuing a floating-point operation instruction to the floating-point operation unit in the period in which the first counter value is equal to or greater than the current frequency value and the second counter value is equal to or greater than the current power supply voltage value; In the period in which the first counter value is less than the current frequency value or the period in which the second counter value is less than the current power supply voltage value, issuance of a floating-point operation instruction to the floating-point operation unit is inhibited. 1. The processor of claim 1 or 2. (Appendix 4) Each of the plurality of cores an instruction decoder for decoding a floating-point operation instruction; a scheduler including a queue for holding the floating-point operation instructions decoded by the instruction decoder, outputting the floating-point operation instructions held in the queue to the instruction issue control unit in an order in which they can be executed, and suppressing deletion from the queue of a floating-point operation instruction whose issuance from the instruction issue control unit to the floating-point operation unit has been suppressed due to a decrease in the frequency of issuance of the floating-point operation instructions. 1. The processor of claim 1 or 2. (Appendix 5) the floating-point arithmetic instructions include a plurality of types of floating-point arithmetic instructions that have different amounts of power consumption when executed by the floating-point arithmetic unit; When the instruction decoder decodes a floating-point operation instruction whose power consumption amount when executed by the floating-point operation unit is equal to or greater than a reference value, it adds a high-frequency flag to the decoded floating-point operation instruction and stores the decoded floating-point operation instruction in the scheduler; The instruction issuance control unit controls the issuance frequency of the floating-point operation instruction to which the high-frequency flag is added, and issues the floating-point operation instruction to which the high-frequency flag is not added to the floating-point operation unit without controlling the issuance frequency of the floating-point operation instruction to which the high-frequency flag is not added. 5. The processor of claim 4. (Appendix 6) Floating-point instructions whose power consumption is equal to or exceeds the reference value are SIMD (Single Instruction Multiple Data) instructions. 6. The processor of claim 5. (Appendix 7) each of the plurality of cores has a fixed-point arithmetic unit; the instruction decoder decodes a floating-point arithmetic instruction and a fixed-point arithmetic instruction; The scheduler holds the floating-point arithmetic instructions and fixed-point arithmetic instructions decoded by the instruction decoder in the queue, and outputs the fixed-point arithmetic instructions held in the queue to the fixed-point arithmetic unit without going through the instruction issue control unit. 5. The processor of claim 4. (Appendix 8) a power control unit that calculates a total amount of power consumption of the plurality of cores from power information indicating power consumption received from each of the plurality of cores, and outputs change information to the frequency / voltage control unit corresponding to each of the plurality of cores to change the clock frequency and the power supply voltage based on the calculated total amount of power consumption; The frequency / voltage control unit changes the frequency and power supply voltage of the clock supplied to the corresponding core based on the change information, and outputs the current frequency value indicating the changed clock frequency and the current power supply voltage value indicating the changed power supply voltage to the instruction issuance control unit of the plurality of cores. 1. The processor of claim 1 or 2. (Appendix 9) When the total power consumption amount is smaller than the upper limit of the power consumption amount of the processor, the power control unit outputs margin information indicating that there is a margin in the total power consumption amount to the frequency / voltage control unit; When the frequency / voltage control unit receives the margin information, it reduces one or both of the current frequency value and the current power supply voltage value to be output to the instruction issuance control unit of the corresponding core. 9. The processor of claim 8. (Appendix 10) the power control unit determines the number of operating cores from state information indicating the operating states of the cores received from each of the plurality of cores, and outputs operating number information indicating the determined number of operating cores to the frequency / voltage control unit; The frequency / voltage control unit corresponding to the core in operation reduces one or both of the current frequency value and the current power supply voltage value output to the instruction issuance control unit of the core as the number of operating cores is smaller than the total number of cores. 9. The processor of claim 8. (Appendix 11) When each of the plurality of cores detects a shortage in the frequency of issuing the floating-point arithmetic instruction, the cores output information indicating the shortage in frequency to the power control unit; When the total power consumption amount is smaller than an upper limit of the power consumption amount of the processor, the power control unit outputs frequency improvement information according to a margin of the total power consumption amount to the frequency / voltage control unit corresponding to the core that output the frequency insufficiency information; The frequency / voltage control unit that has received the frequency improvement information reduces one or both of the current frequency value and the current power supply voltage value that are output to the corresponding core in accordance with the frequency improvement information. 9. The processor of claim 8. (Appendix 12) each of the plurality of cores outputs a resolution signal to the frequency / voltage control unit when the insufficiency in the issuance frequency of the floating-point arithmetic instructions is resolved; Upon receiving the cancellation signal, the frequency / voltage control unit outputs the original current frequency value and the original current power supply voltage value before receiving the frequency improvement information from the power control unit to the corresponding core. 12. The processor of claim 11. (Appendix 13) 1. A method for controlling the operation of a processor having a plurality of cores, each including a floating-point arithmetic unit, and a frequency / voltage control unit provided corresponding to each of the plurality of cores, the frequency / voltage control unit supplying a variable frequency clock and a variable voltage power supply voltage to the corresponding core, the method comprising: an instruction issuance control unit provided in each of the plurality of cores, Controlling the issuance of floating-point operation instructions to the floating-point operation unit; The higher the current frequency is than the reference frequency, or the higher the current power supply voltage is than the reference voltage, the lower the frequency of issuing floating-point operation instructions to the floating-point operation unit. A method for controlling the operation of a processor.

[0127] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0128] 10 cores 11. Instruction issue control unit 12 Floating-point arithmetic unit 20 Frequency and voltage control section 100, 100A, 100B, 100C processors 200, 200B, 200C Core 210 Instruction Decoder 220 Instruction Execution Unit 230 Reservation Station 240 Instruction issue control unit 250, 250C Issue command selection section 260, 260C Issue frequency determination unit 261, 262 Counters 263 AND Circuit 270 Floating-point arithmetic unit 280 Fixed-point arithmetic unit 290 Power monitor unit 300, 300B, 300C Frequency and voltage control section 400, 400B, 400C Power control section CLK Clock CN Core Number Signal CNTf, CNTf0 counter value CNTv, CNTv0 counter value EN, ENf, ENv enable signals F0 reference frequency value F1 Current frequency value INS floating point operation instruction PM Power Monitor Information REQ request signal RTN wake-up signal SET setting signal SLP Sleep signal UP improvement status signal UP0 Frequency improvement signal V0 Reference power supply voltage value V1 Current power supply voltage value VDD power supply voltage VFCNT Frequency voltage control signal

Claims

1. a plurality of cores including a floating-point arithmetic unit; a frequency / voltage control unit provided corresponding to each of the plurality of cores, the frequency / voltage control unit supplying a variable frequency clock and a variable voltage power supply voltage to the corresponding core; an instruction issuance control unit provided in each of the plurality of cores, which controls the issuance of floating-point arithmetic instructions to the floating-point arithmetic unit, and reduces the frequency of issuing floating-point arithmetic instructions to the floating-point arithmetic unit as the current frequency value of the clock is higher than a reference frequency value or the current power supply voltage value is higher than a reference power supply voltage value; A processor having:

2. The instruction issuance control unit issues floating-point arithmetic instructions to the floating-point arithmetic unit at an issue frequency (not more than "1") calculated by multiplying a ratio F0 / F1 of the reference frequency value F0 to the current frequency value F1 by a ratio V0 / V1 of the reference power supply voltage value V0 to the current power supply voltage value V1. The processor of claim 1 .

3. the frequency / voltage control unit outputs the reference frequency value, the current frequency value, the reference power supply voltage value, and the current power supply voltage value to the command issuance control unit; The instruction issuance control unit a first counter that operates at a period that allows a floating-point arithmetic instruction to be issued to the floating-point arithmetic unit, and that sequentially increments the reference frequency value; and a second counter that sequentially increments the reference power supply voltage value, repeating an operation of subtracting the reference frequency value from the first counter value when a first counter value of the first counter is equal to or greater than the current frequency value, and subtracting the reference power supply voltage value from the second counter value when a second counter value of the second counter is equal to or greater than the current power supply voltage value; issuing a floating-point operation instruction to the floating-point operation unit in the period in which the first counter value is equal to or greater than the current frequency value and the second counter value is equal to or greater than the current power supply voltage value; In the period in which the first counter value is less than the current frequency value or the period in which the second counter value is less than the current power supply voltage value, issuance of a floating-point operation instruction to the floating-point operation unit is inhibited. The processor of claim 1 or claim 2.

4. Each of the plurality of cores an instruction decoder for decoding a floating-point operation instruction; a scheduler including a queue for holding the floating-point operation instructions decoded by the instruction decoder, outputting the floating-point operation instructions held in the queue to the instruction issue control unit in an order in which they can be executed, and suppressing deletion from the queue of a floating-point operation instruction whose issuance from the instruction issue control unit to the floating-point operation unit has been suppressed due to a decrease in the frequency of issuance of the floating-point operation instructions. The processor of claim 1 or claim 2.

5. the floating-point arithmetic instructions include a plurality of types of floating-point arithmetic instructions that have different amounts of power consumption when executed by the floating-point arithmetic unit; When the instruction decoder decodes a floating-point operation instruction whose power consumption amount when executed by the floating-point operation unit is equal to or greater than a reference value, it adds a high-frequency flag to the decoded floating-point operation instruction and stores the decoded floating-point operation instruction in the scheduler; The instruction issuance control unit controls the issuance frequency of the floating-point operation instruction to which the high-frequency flag is added, and issues the floating-point operation instruction to which the high-frequency flag is not added to the floating-point operation unit without controlling the issuance frequency of the floating-point operation instruction to which the high-frequency flag is not added. The processor of claim 4 .

6. each of the plurality of cores has a fixed-point arithmetic unit; the instruction decoder decodes a floating-point arithmetic instruction and a fixed-point arithmetic instruction; The scheduler holds the floating-point arithmetic instructions and fixed-point arithmetic instructions decoded by the instruction decoder in the queue, and outputs the fixed-point arithmetic instructions held in the queue to the fixed-point arithmetic unit without going through the instruction issue control unit. The processor of claim 4 .

7. a power control unit that calculates a total amount of power consumption of the plurality of cores from power information indicating power consumption received from each of the plurality of cores, and outputs change information to the frequency / voltage control unit corresponding to each of the plurality of cores to change the clock frequency and the power supply voltage based on the calculated total amount of power consumption; The frequency / voltage control unit changes the frequency and power supply voltage of the clock supplied to the corresponding core based on the change information, and outputs the current frequency value indicating the changed clock frequency and the current power supply voltage value indicating the changed power supply voltage to the instruction issuance control unit of the plurality of cores. The processor of claim 1 or claim 2.

8. When the total power consumption amount is smaller than the upper limit of the power consumption amount of the processor, the power control unit outputs margin information indicating that there is a margin in the total power consumption amount to the frequency / voltage control unit; When the frequency / voltage control unit receives the margin information, it reduces one or both of the current frequency value and the current power supply voltage value to be output to the instruction issuance control unit of the corresponding core. The processor of claim 7.

9. the power control unit determines the number of operating cores from state information indicating the operating states of the cores received from each of the plurality of cores, and outputs operating number information indicating the determined number of operating cores to the frequency / voltage control unit; The frequency / voltage control unit corresponding to the core in operation reduces one or both of the current frequency value and the current power supply voltage value output to the instruction issuance control unit of the core as the number of operating cores is smaller than the total number of cores. The processor of claim 7.

10. When each of the plurality of cores detects a shortage in the frequency of issuing the floating-point arithmetic instruction, the cores output information indicating the shortage in frequency to the power control unit; When the total power consumption amount is smaller than an upper limit of the power consumption amount of the processor, the power control unit outputs frequency improvement information according to a margin of the total power consumption amount to the frequency / voltage control unit corresponding to the core that output the frequency insufficiency information; The frequency / voltage control unit that has received the frequency improvement information reduces one or both of the current frequency value and the current power supply voltage value that are output to the corresponding core in accordance with the frequency improvement information. The processor of claim 7.

11. each of the plurality of cores outputs a resolution signal to the frequency / voltage control unit when the insufficiency in the issuance frequency of the floating-point arithmetic instructions is resolved; Upon receiving the cancellation signal, the frequency / voltage control unit outputs the original current frequency value and the original current power supply voltage value before receiving the frequency improvement information from the power control unit to the corresponding core. The processor of claim 10.

12. 1. A method for controlling the operation of a processor having a plurality of cores, each including a floating-point arithmetic unit, and a frequency / voltage control unit provided corresponding to each of the plurality of cores, the frequency / voltage control unit supplying a variable frequency clock and a variable voltage power supply voltage to the corresponding core, the method comprising: an instruction issuance control unit provided in each of the plurality of cores, Controlling the issuance of floating-point operation instructions to the floating-point operation unit; The higher the current frequency is than the reference frequency, or the higher the current power supply voltage is than the reference voltage, the lower the frequency of issuing floating-point operation instructions to the floating-point operation unit. A method for controlling the operation of a processor.

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