Frequency adjusting system of chip device and chip device
By using a metal structure in the chip's metal layer to sense temperature changes and adjust the frequency, a direct adaptive mapping relationship between temperature and frequency is established, solving the problem of imprecise frequency adjustment in existing technologies and achieving efficient and real-time frequency adjustment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-01
AI Technical Summary
In existing technologies, frequency adjustment relies on the temperature-frequency correspondence stored in a lookup table, which makes it difficult to achieve fully adaptive dynamic adjustment, resulting in imprecise adjustment effects and delays.
By using the metal structure in the chip's metal layer as a temperature-sensitive element, the clock frequency is adjusted by sensing temperature changes in real time, thus establishing a direct, continuous, and adaptive mapping relationship between temperature and frequency, forming a closed-loop control, and avoiding reliance on preset discrete levels.
It achieves stepless, real-time, and fully adaptive frequency regulation, simplifies control logic, improves regulation response speed and energy efficiency, and enhances system stability and reliability.
Smart Images
Figure CN121957282A_ABST
Abstract
Description
A frequency adjustment system for a chip device and the chip device itself. Technical Field
[0001] This application relates to the field of electronic information technology, and more specifically, to a frequency adjustment system for a chip device and a chip device. Background Technology
[0002] In dynamic chip overclocking technology, controlling the chip core temperature threshold is a common method for achieving overclocking. The industry typically uses algorithms to adjust the chip's frequency and voltage, aiming to stabilize the core temperature near a target threshold and, without exceeding that threshold, maximize the chip's power consumption, thereby increasing the core frequency for higher performance. Existing solutions generally use temperature sensors to collect temperature signals, compare them with preset thresholds, and then determine the corresponding frequency adjustment level by consulting a pre-stored lookup table in memory. A clock generation circuit then executes the frequency adjustment to control the chip temperature within the threshold. However, this approach has the drawback that the frequency adjustment level needs to be preset for different temperatures, and the adjustment effect relies entirely on the temperature-frequency correspondence stored in the lookup table, making it difficult to achieve fully adaptive dynamic adjustment. Summary of the Invention
[0003] The purpose of this application is to provide a frequency adjustment system and a chip device for a chip device, so as to solve the problem that existing solutions rely on the temperature-frequency correspondence stored in a lookup table to adjust the frequency, which makes it difficult to achieve fully adaptive dynamic adjustment.
[0004] This application provides a frequency adjustment system for a chip device, comprising: a first temperature sensing unit and a clock generator; a first terminal of the first temperature sensing unit is connected to a power supply Vdd, and a second terminal of the first temperature sensing unit is connected to a reference voltage terminal of the clock generator; the first temperature sensing unit includes a metal structure in the metal layer of the chip, the metal structure being used to sense temperature changes in the chip to change the resistance value of the metal structure, thereby changing the voltage value output by the second terminal of the first temperature sensing unit; the clock generator outputs a corresponding clock frequency according to the voltage change at its reference voltage terminal.
[0005] The metal layers of the chip include back-end metal layers, redistribution layers, or bonding layers.
[0006] In the above technical solution, a metal structure integrated into the chip's back-end metal layer, redistribution layer, or bonding layer is used as a temperature-sensitive element, whose resistance value changes continuously and in real time with the chip temperature. This resistance change is directly converted into a voltage change applied to the reference voltage terminal of the clock generator, enabling the clock generator to respond instantly and output the corresponding clock frequency. The change in clock frequency further feeds back to affect the chip temperature, forming a closed-loop control. This embodiment, through pure hardware circuit design, constructs a direct, continuous, and adaptive mapping relationship between temperature and frequency, without relying on preset discrete temperature-frequency levels, thus avoiding adjustment delays or accuracy losses caused by insufficiently fine-grained level divisions. This solution achieves truly stepless, real-time, and fully adaptive dynamic frequency adjustment, which not only simplifies the control logic and reduces system complexity but also significantly improves adjustment response speed and overall energy efficiency.
[0007] In some alternative implementations, the metal structure includes: metal wire winding, or a series structure of metal wire winding and metal via array.
[0008] In the aforementioned technical solutions, the metal layer refers to the multi-layered metal interconnect structure built on top of the silicon wafer after transistors are fabricated on the wafer during the chip manufacturing process. The metal layer is responsible for connecting a large number of transistors according to circuit logic and distributing power and clock signals. The more layers there are, the higher the interconnect capability and complexity of the chip. Metal wires are conductive lines formed on a single metal layer, manufactured using photolithography and metal deposition processes. Metal wires interconnect transistors by transmitting electrical signals and power in the horizontal direction; their width and thickness directly determine their ability to carry current and signals at high speeds. Metal vias are vertical channels filled with conductive material, used to connect metal wires at different levels, allowing electrical signals to travel between adjacent metal layers, thus achieving complex three-dimensional wiring from local to global.
[0009] In some alternative implementations, the chip device includes multiple subsystems or modules; the first temperature sensing unit includes multiple metal structures, each metal structure being disposed close to a corresponding subsystem or module for sensing temperature changes in the corresponding subsystem or module.
[0010] In the above technical solution, the frequency decision is made by integrating the temperatures of multiple subsystems or modules within the chip, thereby achieving global thermal management and performance optimization of the entire chip and avoiding adjustment deviations that may be caused by a single local temperature reading.
[0011] In some alternative implementations, the chip device includes multiple chips; the first temperature sensing unit includes a metal structure in a metal layer of one or more chips.
[0012] In the above technical solution, the scope of frequency adjustment is extended from the inside of a single chip to complex devices containing multiple chips (such as multi-chip modules, chipsets, or system-in-packages). By using the metal structure in the metal layer of one or more chips as a temperature sensing unit, the frequency decision can be made by comprehensively considering the temperatures of multiple chips. This achieves global thermal management and performance optimization across chips, avoids adjustment deviations that may be caused by a single local temperature reading, and significantly improves the stability and energy efficiency of multi-chip systems under complex workloads.
[0013] In some alternative implementations, the system includes multiple temperature sensing units; the multiple temperature sensing units are connected in series; the multiple temperature sensing units include a first temperature sensing unit, which is connected in series with the other temperature sensing units and then connected to the reference voltage terminal of the clock generator.
[0014] In the above technical solution, by connecting multiple temperature sensing units distributed in different locations in series and superimposing their resistance values, the reference voltage received by the clock generator is determined by the temperature of multiple points. This makes the output frequency no longer dependent on a single, potentially unrepresentative, local hot or cold spot, but responds to an average value that better reflects the overall temperature level of the chip. This improves the comprehensiveness of temperature sampling and the ability to resist local interference, avoids frequency misadjustment caused by errors of a single sensor or local temperature fluctuations, and enhances the stability and reliability of the system under different workloads.
[0015] In some alternative implementations, each temperature sensing unit further includes a multiplexer connected in series with the metal structure; in the first temperature sensing unit, the first input terminal of the internal multiplexer is connected to the second terminal of the internal metal structure, and the first terminal of the internal metal structure is connected to the power supply Vdd; in the other temperature sensing units, the first input terminal of the internal multiplexer is connected to the second terminal of the internal metal structure, and the first terminal of the internal metal structure is connected to the second terminal of the internal multiplexer.
[0016] In the above technical solution, a multiplexer is configured for each temperature sensing unit. The second terminal of the multiplexer corresponding to the first temperature sensing unit can be disconnected from any power supply. When the multiplexer selects the output of the second terminal, the clock generator is turned off. The third terminal of the multiplexer corresponding to the first temperature sensing unit can be connected to a power supply with a voltage greater than Vdd. When the multiplexer selects the output of the third terminal, the clock generator outputs a higher clock frequency, achieving overclocking. The fourth terminal of the multiplexer corresponding to the first temperature sensing unit can be connected to a power supply with a voltage less than Vdd. When the multiplexer selects the output of the fourth terminal, the clock generator outputs a lower clock frequency, achieving frequency reduction.
[0017] Except for the first temperature sensing unit, the corresponding multiplexer for each of the remaining temperature sensing units can be used to: select to connect the metal structure of a specific temperature sensing unit to the circuit to sense the temperature at that location; or select to short-circuit the two ends of the metal structure of a specific temperature sensing unit to eliminate the temperature sensing effect at that location.
[0018] In some alternative implementations, the system further includes: a temperature-sensing control unit; different output ports of the temperature-sensing control unit are connected to different multiplexers, the temperature-sensing control unit is used to control the number of metal structures used in the system, and to control the clock generator to turn on or off.
[0019] In the above technical solution, the number of metal structures used in the temperature sensing control unit control system, i.e., the number of series-connected metal structures used to sense temperature, adjusts the total resistance and rate of change of the entire temperature sensing network. With more series-connected metal structures, the system is more sensitive to changes in chip temperature, resulting in better frequency reduction when the temperature rises. For example, in energy-efficient operating modes, frequency reduction can quickly lower the chip temperature. With fewer series-connected metal structures, the system is less sensitive to changes in chip temperature, resulting in less significant frequency reduction when the temperature rises. For example, in performance-oriented operating modes, this allows the system to tolerate higher chip temperatures while maintaining frequency stability, prioritizing peak performance.
[0020] In some alternative implementations, the higher the target temperature of the chip device, the fewer metal structures are used in the temperature sensing control unit control system; the higher the energy efficiency requirements of the chip device, the more metal structures are used in the temperature sensing control unit control system.
[0021] In some alternative implementations, the chip device includes one or more chips; each temperature sensing unit includes a metal structure in a metal layer of one or more chips.
[0022] In some alternative implementations, multiple chips are arranged side-by-side on a wafer, silicon interposer, substrate, or substrate.
[0023] In some alternative implementations, multiple chips are stacked and disposed on a silicon interposer, substrate, or substrate.
[0024] In some alternative implementations, the metal structure is used to sense changes in chip temperature to change the resistance value of the metal structure, thereby changing the voltage division value V' of the metal structure; the clock generator outputs the corresponding clock frequency according to the operating voltage Vref at its reference voltage terminal; where Vref = Vdd - V'.
[0025] In the above technical solution, the resistor in the metal structure is connected in series in the power supply path of the clock generation circuit. Changes in the resistance of the metal structure directly cause changes in the voltage division. The power supply voltage Vdd, after passing through the temperature sensing unit, generates the actual operating voltage Vref applied to the clock generation circuit. When the temperature rises, the resistance of the metal structure increases, causing the operating voltage Vref to decrease; when the temperature decreases, the resistance of the metal structure decreases, causing the operating voltage Vref to rise. The output frequency of the clock generator is positively correlated with its operating voltage Vref. A decrease in the operating voltage Vref leads to a decrease in the output clock frequency, which in turn reduces the power consumption of the core circuit of this clock chip, and the temperature drops accordingly; conversely, an increase in the operating voltage Vref increases the clock frequency, increases the core power consumption, and causes the temperature to rise again.
[0026] An embodiment of this application provides a chip device, comprising: a frequency adjustment system for a chip device as described in any of the preceding claims, and one or more chips. Attached Figure Description
[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 is a functional block diagram of a frequency adjustment system for a chip device provided in an embodiment of this application; Figure 2 is a schematic diagram of a metal structure composed of metal windings of a metal layer provided in an embodiment of this application; Figure 3 is a schematic diagram of a metal structure composed of metal windings of a metal layer and metal vias provided in an embodiment of this application; Figure 4 is a schematic diagram of a chip device provided in an embodiment of this application; Figure 5 is a schematic diagram of a chip device provided in another embodiment of this application; Figure 6 is a schematic diagram of the structure of a frequency adjustment system for a chip device provided in an embodiment of this application. Detailed Implementation
[0029] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0030] The abbreviations and key terms involved in one or more embodiments of this application are defined as follows: Temperature Fixed: refers to the chip stabilizing its temperature near a preset target value through a specific control mechanism during operation, so as to avoid the impact of temperature fluctuations on performance and stability.
[0031] Adaptive Clock system: A circuit system that can automatically adjust the output clock frequency according to the environment or operating conditions (such as temperature changes) to achieve a balance between performance and power consumption.
[0032] DVFS (Dynamic Voltage and Frequency Scaling): A technology that reduces power consumption while maintaining performance by dynamically adjusting the chip's operating voltage and clock frequency. It is commonly used in mobile devices and low-power chips.
[0033] Tsensor (temperature sensor): A device used to detect the temperature of a chip, which typically converts the temperature into an electrical signal for use by other circuits.
[0034] MUX (Multiple-Selector): A digital circuit that can select one output from multiple input signals, often used for signal routing or resource configuration.
[0035] BEOL (Back-to-End Metal): A metal layer located above transistors in chip manufacturing, used to connect different transistors and circuit modules, typically using conductive materials such as copper.
[0036] TSV (Through Silicon Via): A conductive channel that penetrates vertically through a silicon wafer, used for interlayer interconnection in three-dimensional chip stacking.
[0037] HB (Hybrid Bonding): An advanced chip packaging technology that achieves high-density interconnects by directly bonding metal and dielectric layers, improving performance and reducing size.
[0038] Turbo boost: a technology that enhances performance by temporarily increasing the chip's clock frequency, often used to dynamically accelerate processors under high load.
[0039] LUT (Lookup Table): A table that stores predefined data, often used for quick lookups or configurations, such as the implementation of logic functions in FPGAs.
[0040] BPV (Via in Hybrid Bonding): A conductive channel used for vertical connections in hybrid bonding structures, similar to TSV but used for finer interlayer interconnects.
[0041] BPM (Meta in hybrid bonding): The metal layer in a hybrid bonding structure used for signal transmission and power distribution, and is usually used in conjunction with BPV.
[0042] The purpose of this application is to provide a frequency adjustment system and chip device for a chip device. Through hardware circuit design, a temperature-based adaptive clock control mechanism is constructed. This mechanism directly adjusts the supply voltage of the clock generation circuit by utilizing temperature changes, thereby dynamically adjusting the output clock frequency. This allows the operating temperature of the chip circuit to automatically stabilize near a preset target temperature, achieving efficient and real-time temperature control. Frequency closed-loop control.
[0043] Please refer to Figure 1, which is a functional block diagram of a frequency adjustment system for a chip device provided in an embodiment of this application. The system includes: a first temperature sensing unit and a clock generator.
[0044] The first terminal of the first temperature sensing unit is connected to the power supply Vdd, and the second terminal of the first temperature sensing unit is connected to the reference voltage terminal of the clock generator. The first temperature sensing unit includes a metal structure in the metal layer of the chip. The metal structure is used to sense the temperature change of the chip to change the resistance value of the metal structure, thereby changing the voltage value output by the second terminal of the first temperature sensing unit. The clock generator outputs the corresponding clock frequency according to the voltage change of its reference voltage terminal.
[0045] The first temperature sensing unit uses the metal structure of the back-end metal layer, redistribution layer or bonding layer of the chip to sense the temperature and output a temperature sensing electrical signal. The metal structure of the back-end metal layer, redistribution layer or bonding layer is used as the temperature sensing unit, such as copper in the metal layer. The resistance of copper changes linearly with temperature. The higher the temperature, the higher the resistance of copper, and the lower the temperature, the lower the resistance of copper.
[0046] The output frequency of a clock generator needs to be adjustable according to changes in its supply voltage to achieve temperature-frequency adaptive closed-loop control. For example, a clock generator can be a PLL (Phase-Locked Loop), which generates a high-precision, low-jitter clock signal through feedback control. A clock generator can also be an FLL (Frequency-Locked Loop), which achieves frequency synchronization through frequency comparison and adjustment, suitable for scenarios requiring high frequency accuracy. A clock generator can also be a VCO (Voltage-Controlled Oscillator), whose output frequency changes linearly with the input voltage; it is the core component of a PLL and can also be used independently as a clock source. A clock generator can also be a RO (Ring Oscillator), composed of an odd number of inverters, with a simple structure and frequency adjustable via voltage or current. A clock generator can also be an RC oscillator, based on the resistor-capacitor charging and discharging principle, which is low-cost and suitable for low-frequency clock generation.
[0047] The metal layers of the chip include back-end metal layers, redistribution layers, or bonding layers.
[0048] In one or more embodiments of this application, a metal structure integrated in the back-to-the-edge (BEOL) metal layer is used as a temperature-sensitive element, whose resistance value changes continuously and in real time with the chip temperature. This resistance change is directly converted into a voltage change applied to the reference voltage terminal of the clock generator, enabling the clock generator to respond instantly and output a corresponding clock frequency. The change in clock frequency further feeds back to affect the chip temperature, forming a closed-loop control. This embodiment constructs a direct, continuous, and adaptive mapping relationship between temperature and frequency through pure hardware circuit design, without relying on preset discrete temperature-frequency levels, thus avoiding adjustment delays or accuracy losses caused by insufficiently fine-grained level division. This solution achieves truly stepless, real-time, and fully adaptive dynamic frequency adjustment, which not only simplifies the control logic and reduces system complexity, but also significantly improves the adjustment response speed and overall energy efficiency.
[0049] Back-end processes for chip manufacturing create multiple layers of conductive metal lines, with pillar-shaped metal sections connecting the different layers. Back-end processes, such as those used for packaging, include wiring and vias. Back-end metal structures typically include back-end metal formed during these processes. For example, a back-end metal structure might include back-end metal wire loops, pillar-shaped metal sections (Via) for coupling different layers of metal lines, and through-holes (Through-Silicon Through-Hole) connections. Silicon Through-silicon vias (TSVs), etc., are vertical interconnects created between chips and wafers. By filling with conductive materials such as copper and tungsten, vertical electrical interconnects are achieved through silicon vias, enabling interconnection between chips.
[0050] The frequency regulation system in this scheme is a closed-loop negative feedback system based on temperature-resistance-voltage-frequency. The specific process includes: the temperature sensing unit utilizes a metal structure within the chip's metal layer as a temperature-sensitive resistor. When the chip core temperature rises, the resistance of the metal structure increases linearly; when the temperature decreases, the resistance of the metal structure decreases linearly. Specifically, the resistor of the metal structure can be connected in series in the power supply path of the clock generation circuit, and changes in the resistance of the metal structure directly cause changes in the voltage division.
[0051] The power supply voltage Vdd, after passing through the temperature sensing unit, generates the actual operating voltage Vref applied to the clock generation circuit. When the temperature rises, the resistance of the metal structure increases, causing the operating voltage Vref to decrease; when the temperature decreases, the resistance of the metal structure decreases, causing the operating voltage Vref to rise.
[0052] The output frequency of a clock generator is positively correlated with its operating voltage Vref. A decrease in the operating voltage Vref leads to a decrease in the output clock frequency, which in turn reduces the power consumption of the core circuitry of the clock and lowers the temperature. Conversely, an increase in the operating voltage Vref increases the clock frequency, increases the core power consumption, and causes the temperature to rise.
[0053] By configuring the initial resistance value of the metal structure, different target temperature lock-in points can be set. Through the aforementioned closed-loop mechanism, the system automatically stabilizes the chip temperature near the target value, achieving fully hardware-based adaptive temperature control without software intervention.
[0054] In some alternative implementations, the metal structure includes: metal wire winding, or a series structure of metal wire winding and metal via array.
[0055] Please refer to Figure 2, which is a schematic diagram of a metal structure composed of metal windings with metal layers provided in an embodiment of this application. The temperature sensing unit includes a downstream metal winding formed in a subsequent process to sense temperature using conductive metal wires. Specifically, the metal winding can be made into a serpentine winding, with power input and power output at both ends of the winding.
[0056] Please refer to Figure 3, which is a schematic diagram of a metal structure composed of metal wires and metal vias provided in an embodiment of this application. The temperature sensing unit includes a back-end metal wire formed in a subsequent process and a back-end metal via array formed by columnar metals for coupling different layers of metal wires. Specifically, the metal via array can be mainly used as the resistor composition, and these metal via arrays are connected in series using metal wires. The metal vias described in this embodiment include TSVs and Vias.
[0057] The embodiments of this disclosure are based on the fact that the temperature sensing unit of the metal-type temperature sensor can be composed of any layer of back-end metal wires or metal via arrays, so as to realize temperature measurement at multiple physical layer locations within the chip, as well as temperature measurement in the 3D chip stack structure.
[0058] In this embodiment, a metal layer refers to a multi-layered metal interconnect structure built on top of a silicon wafer after transistors have been fabricated on the wafer during the chip manufacturing process. The metal layer is responsible for connecting a large number of transistors according to circuit logic and distributing power and clock signals. The more layers there are, the higher the interconnect capability and complexity of the chip. Metal wires are conductive lines formed on a single metal layer, manufactured using photolithography and metal deposition processes. Metal wires interconnect transistors by transmitting electrical signals and power in the horizontal direction; their width and thickness directly determine their ability to carry current and signals at high speeds. Metal vias are vertical channels filled with conductive material, used to connect metal wires at different levels, allowing electrical signals to travel between adjacent metal layers, thereby achieving complex three-dimensional wiring from local to global.
[0059] Please refer to Figure 4, which is a schematic diagram of a chip device provided in an embodiment of this application. In some optional embodiments, the chip device may contain only one chip, and a serpentine metal structure may be provided at one or more points on the chip to sense temperature changes.
[0060] Please refer to Figure 5, which is a schematic diagram of a chip device provided in another embodiment of this application. In some optional embodiments, the chip device includes multiple chips; the first temperature sensing unit includes a metal structure in the metal layer of one or more chips. A serpentine metal structure can be provided at one or more points on each chip to sense temperature changes, or a serpentine metal structure can be provided at one or more points in the metal layer of some of the multiple chips to sense temperature changes.
[0061] In this embodiment, the scope of frequency adjustment is extended from the inside of a single chip to complex devices containing multiple chips (such as multi-chip modules, chipsets, or system-in-packages). By using the metal structure in the metal layer of one or more chips as a temperature sensing unit, the frequency decision can be made by comprehensively considering the temperatures of multiple chips. This achieves global thermal management and performance optimization across chips, avoids adjustment deviations that may be caused by a single local temperature reading, and significantly improves the stability and energy efficiency of multi-chip systems under complex workloads.
[0062] Please refer to Figure 6, which is a schematic diagram of the frequency adjustment system structure of the chip device provided in the embodiment of this application.
[0063] In some alternative implementations, the system includes multiple temperature sensing units; the multiple temperature sensing units are connected in series; the multiple temperature sensing units include a first temperature sensing unit, which is connected in series with the other temperature sensing units and then connected to the reference voltage terminal of the clock generator.
[0064] In this embodiment, by connecting multiple temperature sensing units distributed at different locations in series and superimposing their resistance values, the reference voltage received by the clock generator is determined by the temperature of multiple points. This makes the output frequency no longer dependent on a single, potentially unrepresentative, local hot or cold spot, but responds to an average value that better reflects the overall temperature level of the chip. This improves the comprehensiveness of temperature sampling and the ability to resist local interference, avoids frequency misadjustment caused by errors of a single sensor or local temperature fluctuations, and enhances the stability and reliability of the system under different workloads.
[0065] In some alternative implementations, each temperature sensing unit also includes a multiplexer connected in series with the metal structure.
[0066] In the first temperature sensing unit, the first input terminal of the internal multiplexer is connected to the second terminal of the internal metal structure, and the first terminal of the internal metal structure is connected to the power supply Vdd.
[0067] In the remaining temperature sensing units, the first input terminal of the internal multiplexer is connected to the second terminal of the internal metal structure, and the first terminal of the internal metal structure is connected to the second terminal of the internal multiplexer.
[0068] In this embodiment, a multiplexer is configured for each temperature sensing unit. The second terminal of the multiplexer corresponding to the first temperature sensing unit can be disconnected from any power supply. When the multiplexer selects the output of the second terminal, the clock generator is turned off. The third terminal of the multiplexer corresponding to the first temperature sensing unit can be connected to a power supply with a voltage greater than Vdd. When the multiplexer selects the output of the third terminal, the clock generator outputs a higher clock frequency, achieving overclocking. The fourth terminal of the multiplexer corresponding to the first temperature sensing unit can be connected to a power supply with a voltage less than Vdd. When the multiplexer selects the output of the fourth terminal, the clock generator outputs a lower clock frequency, achieving frequency reduction.
[0069] Except for the first temperature sensing unit, the corresponding multiplexer for each of the remaining temperature sensing units can be used to: select to connect the metal structure of a specific temperature sensing unit to the circuit to sense the temperature at that location; or select to short-circuit the two ends of the metal structure of a specific temperature sensing unit to eliminate the temperature sensing effect at that location.
[0070] In some alternative implementations, the system further includes: a temperature-sensing control unit; different output ports of the temperature-sensing control unit are connected to different multiplexers, the temperature-sensing control unit is used to control the number of metal structures used in the system, and to control the clock generator to turn on or off.
[0071] As shown in Figure 6, port 1 of the temperature sensing control unit is connected to the controlled terminal of the first temperature sensing unit, port 2 of the temperature sensing control unit is connected to the controlled terminal of the second temperature sensing unit, and so on, with port n of the temperature sensing control unit connected to the controlled terminal of the nth temperature sensing control unit. The temperature sensing control unit controls each temperature sensing unit to select one of its two input ports for output. If the metal structure in the temperature sensing unit is to be used, the output of port 1 of the multiplexer of that temperature sensing unit is controlled; if the metal structure in the temperature sensing unit is not used, the output of port 2 of the multiplexer of that temperature sensing unit is controlled.
[0072] In this embodiment, the number of metal structures used in the temperature sensing control unit control system, i.e., the number of series-connected metal structures used for temperature sensing, adjusts the total resistance and rate of change of the entire temperature sensing network. With more series-connected metal structures, the system is more sensitive to changes in chip temperature, resulting in better frequency reduction when the temperature rises. For example, in energy-efficient operating modes, frequency reduction quickly lowers the chip temperature. With fewer series-connected metal structures, the system is less sensitive to changes in chip temperature, resulting in less significant frequency reduction when the temperature rises. For example, in performance-oriented operating modes, this allows the system to tolerate higher chip temperatures while maintaining frequency stability, prioritizing peak performance.
[0073] In some alternative implementations, the higher the target temperature of the chip device, the fewer metal structures are used in the temperature sensing control unit control system; the higher the energy efficiency requirements of the chip device, the more metal structures are used in the temperature sensing control unit control system.
[0074] In some alternative implementations, the chip device includes one or more chips; each temperature sensing unit includes a metal structure in a metal layer of one or more chips.
[0075] Similarly, the chip device may contain only one chip, and a serpentine metal structure may be set at one or more points on the chip to sense temperature changes.
[0076] The chip device may also include multiple chips; each temperature sensing unit may include a metal structure in the metal layer of one or more chips. A serpentine metal structure can be provided at one or more points on each chip to sense temperature changes, or a serpentine metal structure can be provided at one or more points in the metal layer of some of the multiple chips to sense temperature changes.
[0077] In some alternative implementations, multiple chips are arranged side-by-side on a wafer, silicon interposer, substrate, or substrate.
[0078] In some alternative implementations, multiple chips are stacked and disposed on a silicon interposer, substrate, or substrate.
[0079] Among them, the silicon interposer is a precision bridge in high-end chip packaging. Using silicon as the core material, it is essentially a thin silicon wafer with fine wiring. It mainly solves the problem of excessively high pin density of chips (especially chiplets and 3D packaged chips) and insufficient wiring capabilities of traditional substrates. One end is interconnected with the chip die through microbumps, and the other end is connected to the substrate. It can achieve low-loss transmission of high-density signals and also assist in heat dissipation. It is a key intermediate structure for improving chip integration and performance, and is commonly found in complex packaging scenarios such as high-end processors and AI chips.
[0080] The substrate serves as the signal and power distribution platform for chip packaging. Its core materials are mostly organic resins (such as BT resin and epoxy resin), but special materials like ceramics are also used. Located between the chip (or silicon interposer) and the external PCB board, it secures the chip above by soldering or bonding and connects to the PCB board below. Its main functions are transmitting electrical signals between the chip and the system, providing a stable power supply, and distributing chip heat to aid in heat dissipation. The substrate's wiring density and heat dissipation performance directly affect the chip's stability, making it an indispensable core support structure in all packaging forms.
[0081] The substrate is the fundamental carrier for chip manufacturing. The core material is mainly silicon (but also includes special semiconductor materials such as silicon carbide, sapphire, and gallium nitride), and its shape is usually a round semiconductor wafer. The core functional units of the chip (such as transistors, logic circuits, and memory cells) are directly fabricated on the surface of the substrate through processes such as photolithography and etching. It not only provides physical support for the circuit, but its semiconductor properties also directly affect the electrical performance of the chip. It is the foundation that carries the core functions of the chip. Without a substrate, the core manufacturing of the chip cannot be completed.
[0082] In some alternative implementations, the metal structure is used to sense changes in chip temperature to change the resistance value of the metal structure, thereby changing the voltage division value V' of the metal structure; the clock generator outputs the corresponding clock frequency according to the operating voltage Vref at its reference voltage terminal; where Vref = Vdd - V'.
[0083] In this embodiment, the resistor of the metal structure is connected in series in the power supply path of the clock generation circuit. Changes in the resistance of the metal structure directly cause changes in the voltage division. After the power supply voltage Vdd passes through the temperature sensing unit, it generates the actual operating voltage Vref applied to the clock generation circuit. When the temperature rises, the resistance of the metal structure increases, causing the operating voltage Vref to decrease; when the temperature decreases, the resistance of the metal structure decreases, causing the operating voltage Vref to rise. The output frequency of the clock generator is positively correlated with its operating voltage Vref. A decrease in the operating voltage Vref leads to a decrease in the output clock frequency, which in turn reduces the power consumption of the core circuit of this clock chip, and the temperature drops accordingly; conversely, an increase in the operating voltage Vref increases the clock frequency, increases the core power consumption, and causes the temperature to rise again.
[0084] This application provides a chip device, including: a frequency adjustment system for a chip device as described in any of the above claims, and one or more chips.
[0085] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.
[0086] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0087] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0088] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.
[0089] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A frequency adjustment system for a chip device, characterized in that, include: A first temperature sensing unit and a clock generator; a first end of the first temperature sensing unit is connected to a power supply Vdd, and a second end of the first temperature sensing unit is connected to a reference voltage terminal of the clock generator. The first temperature sensing unit includes a metal structure in the metal layer of the chip. The metal structure is used to sense the temperature change of the chip to change the resistance value of the metal structure, thereby changing the voltage value of BPV output at the second terminal of the first temperature sensing unit. The clock generator outputs a corresponding clock frequency based on the voltage change at its reference voltage terminal.
2. The system as described in claim 1, characterized in that, The metal structure includes: metal wire winding, or a series structure of metal wire winding and metal via array.
3. The system as described in claim 1, characterized in that, The chip device includes multiple subsystems or modules; the first temperature sensing unit includes multiple metal structures, each metal structure being disposed close to a corresponding subsystem or module for sensing temperature changes in the corresponding subsystem or module.
4. The system as described in claim 1, characterized in that, The chip device includes multiple chips; the first temperature sensing unit includes a metal structure in the metal layer of one or more chips.
5. The system as described in claim 1, characterized in that, The system includes multiple temperature sensing units; the multiple temperature sensing units are connected in series; the multiple temperature sensing units include a first temperature sensing unit, which is connected in series with the other temperature sensing units and then connected to the reference voltage terminal of the clock generator.
6. The system as described in claim 5, characterized in that, Each temperature sensing unit also includes a multiplexer connected in series with the metal structure; in the first temperature sensing unit, the first input terminal of the internal multiplexer is connected to the second terminal of the internal metal structure, and the first terminal of the internal metal structure is connected to the power supply Vdd; in the other temperature sensing units, the first input terminal of the internal multiplexer is connected to the second terminal of the internal metal structure, and the first terminal of the internal metal structure is connected to the second terminal of the internal multiplexer.
7. The system as described in claim 6, characterized in that, The system further includes a temperature sensing control unit; different output ports of the temperature sensing control unit are connected to different multiplexers, and the temperature sensing control unit is used to control the number of metal structures used in the system, and to control the clock generator to turn on or off.
8. The system as described in claim 7, characterized in that, The higher the target temperature of the chip device, the fewer metal structures the temperature sensing control unit controls in the system; the higher the energy efficiency requirements of the chip device, the more metal structures the temperature sensing control unit controls in the system.
9. The system as described in claim 5, characterized in that, The chip device includes one or more chips; each temperature sensing unit includes a metal structure in the metal layer of one or more chips.
10. The system as described in claim 9, characterized in that, Multiple chips are arranged side by side on a wafer, silicon interposer, substrate, or substrate.
11. The system as described in claim 9, characterized in that, Multiple chips are stacked and placed on a silicon interposer, substrate, or substrate.
12. The system as claimed in claim 1, characterized in that, The metal structure is used to sense changes in chip temperature to change the resistance value of the metal structure, thereby changing the voltage division value V' of the metal structure; the clock generator outputs a corresponding clock frequency based on the operating voltage Vref at its reference voltage terminal; where Vref = Vdd - V'.
13. A chip device, characterized in that, include: A frequency adjustment system for a chip device as described in any one of claims 1-11, and one or more chips.