A power management heat distribution optimization method and system in a multi-chip package scenario

Abstract

The application discloses a power management heat distribution optimization method and system in a multi-chip package scene, and belongs to the field of power management. The application obtains temperature data of each chip unit in a multi-chip package, timing margin data of a target timing path, and material thermal conductivity data. A dynamic thermal resistance network model is constructed based on the data and the physical structure of the package. When the timing margin is less than a preset threshold, the chip unit with the highest temperature on the target timing path is located as a target chip unit. According to the degree of insufficient timing margin and the thermal resistance network model, a first regulated voltage and a lower first regulated impedance for restoring performance are determined for the target chip unit, and a higher second regulated impedance for assisting heat dissipation is determined for the adjacent unit. Finally, the voltage and impedance values are applied to the corresponding chip through the respective power supply unit to realize the coordinated regulation of performance and heat distribution, and the heat distribution optimization can be effectively realized in the multi-chip package scene.

Description

Technical Field

[0001] The present application relates to the field of power management, and in particular to a method and system for optimizing thermal distribution of power management in a multi-chip package scenario. Background Art

[0002] With the rapid development of high-performance computing, artificial intelligence, and next-generation communications technologies, multi-chip packaging (MCP) systems have become a mainstream path to boosting computing power. Power management and thermal optimization within these systems are key technologies for ensuring stable and efficient operation. This technology, through precise control of chip power consumption and temperature, directly impacts the system's peak performance, timing stability, and long-term reliability, and therefore holds broad application prospects.

[0003] In existing technologies, dynamic voltage and frequency scaling (DVFS) or task migration strategies are used to manage the thermal performance of multi-chip systems. By monitoring the temperature of the multi-chip system, the operating frequency is reduced or tasks are migrated when the temperature is too high.

[0004] However, existing power management thermal distribution optimization methods generally adopt a strategy of reducing the operating frequency of the entire chip and core functional units. In a multi-chip package scenario, this global throttling measure sacrifices the performance of the entire functional unit or even the entire chip to solve the timing problem of a small area, resulting in unnecessary performance loss. It is unable to address the problem of timing performance degradation of key circuits caused by temperature rise in a local area within the package. Therefore, the existing power management thermal distribution optimization methods in a multi-chip package scenario are difficult to achieve efficient thermal distribution optimization while ensuring chip system performance, and cannot effectively achieve thermal distribution optimization. Summary of the Invention

[0005] The present application provides a method, system, device and computer storage medium for optimizing thermal distribution of power management in a multi-chip package scenario, which can effectively achieve thermal distribution optimization in a multi-chip package scenario.

[0006] In a first aspect, the present application provides a method for optimizing thermal distribution of power management in a multi-chip package scenario, the method comprising:

[0007] Acquiring temperature data of multiple chip units within the multi-chip package, timing margin data of a target timing path, and preset material thermal conductivity data of the multi-chip package, where the target timing path is a signal path with a maximum signal propagation delay within the multi-chip package, and the material thermal conductivity data includes a corresponding relationship between the thermal conductivity of the material within the multi-chip package and the temperature;

[0008] Based on temperature data, material thermal conductivity data, and package physical structure data of a multi-chip package, a thermal resistance network model is constructed by determining the thermal resistance values ​​of chip units and package material units in the package physical structure data. The thermal resistance network model includes network nodes representing chip units or package material units, edges representing heat transfer channels between network nodes, and multiple heat conduction paths including path thermal resistance values ​​formed by the network nodes and edges.

[0009] When the timing margin in the timing margin data is less than a preset margin threshold, determining a target chip unit among the chip units passed through in the target timing path by using the temperature data;

[0010] Determining a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, based on a difference between the timing margin and a preset margin threshold, and a path thermal resistance value of a heat conduction path associated with the target chip unit in a thermal resistance network model;

[0011] The supply voltage and output impedance of the power supply unit corresponding to the target chip unit are regulated by the first regulation voltage and the first regulation impedance, and the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit is regulated by the second regulation impedance.

[0012] In one possible implementation, after constructing a thermal resistance network model by determining thermal resistance values ​​of chip units and packaging material units in the packaging physical structure data based on temperature data, material thermal conductivity data, and packaging physical structure data of the multi-chip package, the method further includes:

[0013] Obtain real-time temperature data of multiple chip units in a multi-chip package;

[0014] The path thermal resistance value of the heat conduction path in the thermal resistance network model is updated using real-time temperature data and material thermal conductivity data.

[0015] In one practicable embodiment, based on temperature data, material thermal conductivity data, and package physical structure data of a multi-chip package, a thermal resistance network model is constructed by determining thermal resistance values ​​of chip units and package material units in the package physical structure data, including:

[0016] Multiple discrete physical regions representing chip units and packaging material units are extracted from the package physical structure data. Each discrete physical region is constructed as a network node. Based on the spatial adjacency relationship of the discrete physical regions in the package physical structure data, edges representing the existence of heat transfer channels between network nodes are constructed to obtain topological connection information.

[0017] Based on each network node, the temperature value of each chip unit corresponding to the network node is extracted from the temperature data, and the temperature value of each packaging material unit corresponding to the network node is calculated based on the topological connection information and the temperature value of each chip unit corresponding to the network node;

[0018] Based on the temperature value of each network node, the material thermal conductivity value of each network node is determined by using the corresponding relationship between the material thermal conductivity and temperature in the material thermal conductivity data;

[0019] The node thermal resistance value of each network node is calculated using the material thermal conductivity value and the geometric size information of the discrete physical area corresponding to the network node that encapsulates the physical structure data;

[0020] Based on the topological connection information, multiple heat conduction paths are determined, and according to the node thermal resistance values ​​of the network nodes in each heat conduction path, the path thermal resistance value of each heat conduction path is calculated to obtain a thermal resistance network model.

[0021] In one feasible embodiment, when the timing margin in the timing margin data is less than a preset margin threshold, determining a target chip unit among chip units passed through in a target timing path using temperature data includes:

[0022] Determining whether the timing margin in the timing margin data is less than a preset margin threshold;

[0023] When the timing margin in the timing margin data is less than a preset margin threshold, extracting identification information of each chip unit passed through in the target timing path to obtain a set of candidate chip units;

[0024] Determine the temperature value of each candidate chip unit in the candidate chip unit set based on the temperature values ​​of all chip units in the temperature data;

[0025] The candidate chip unit with the largest temperature value in the candidate chip unit set is determined as the target chip unit.

[0026] In one feasible implementation, the first regulating impedance is smaller than the second regulating impedance.

[0027] In one practicable embodiment, determining a first control voltage and a first control impedance of a target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, based on a difference between a timing margin and a preset margin threshold and a path thermal resistance value of a heat conduction path associated with the target chip unit in a thermal resistance network model, includes:

[0028] Calculating the difference between the timing margin and a preset margin threshold to obtain a target timing margin difference;

[0029] Determine a target voltage compensation value corresponding to a target timing margin difference according to a preset mapping relationship between the timing margin difference and the voltage compensation value, and obtain a first regulation voltage based on a reference voltage value of a target chip unit;

[0030] Among all heat conduction paths associated with the target chip unit, the heat conduction path with the smallest path thermal resistance is determined as the target heat conduction path, and according to the topological connection structure of the thermal resistance network model, the chip unit in the target heat conduction path whose path distance to the target chip unit is less than a preset path distance threshold is determined as the unit chip adjacent to the target chip unit;

[0031] The unit chip adjacent to the target chip unit with a preset first impedance value is used as the first control impedance, and the second control impedance of the unit chip adjacent to the target chip unit is determined in the preset second impedance value set, and the path thermal resistance value of the target heat conduction path is inversely correlated with the impedance value of the second control impedance.

[0032] In one feasible embodiment, regulating the supply voltage and output impedance of the power supply unit corresponding to the target chip unit by a first regulating voltage and a first regulating impedance, and regulating the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit by a second regulating impedance, includes:

[0033] Adjusting the supply voltage of a first power supply unit associated with the target chip unit according to the first regulation voltage, and reconstructing the power transistor array of the first power supply unit to match the first regulation impedance according to the first regulation impedance;

[0034] According to the second regulated impedance, the power supply transistor array of the second power supply unit associated with the unit chip adjacent to the target chip unit is reconstructed to match the second regulated impedance.

[0035] In a second aspect, the present application provides a power management thermal distribution optimization system in a multi-chip package scenario, the system comprising:

[0036] an acquisition module, configured to acquire temperature data of multiple chip units within a multi-chip package, timing margin data of a target timing path, and preset material thermal conductivity data of the multi-chip package, wherein the target timing path is a signal path with a maximum signal propagation delay within the multi-chip package, and the material thermal conductivity data includes a corresponding relationship between the thermal conductivity of the material within the multi-chip package and the temperature;

[0037] A construction module is used to construct a thermal resistance network model based on temperature data, material thermal conductivity data, and package physical structure data of a multi-chip package by determining the thermal resistance values ​​of chip units and package material units in the package physical structure data. The thermal resistance network model includes network nodes representing chip units or package material units, edges representing heat transfer channels between network nodes, and multiple heat conduction paths including path thermal resistance values ​​formed by the network nodes and edges;

[0038] a determination module, configured to determine a target chip unit among chip units passed through in a target timing path using temperature data when a timing margin in the timing margin data is less than a preset margin threshold;

[0039] The determination module is further configured to determine a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, based on a difference between the timing margin and a preset margin threshold and a path thermal resistance value of a heat conduction path associated with the target chip unit in a thermal resistance network model;

[0040] The control module is used to control the supply voltage and output impedance of the power supply unit corresponding to the target chip unit through the first control voltage and the first control impedance, and to control the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit through the second control impedance.

[0041] In a third aspect, the present application provides an electronic device comprising: a processor, and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement a power management thermal distribution optimization method in a multi-chip packaging scenario as in any embodiment of the first aspect.

[0042] In a fourth aspect, the present application provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, a power management thermal distribution optimization method in a multi-chip sealing scenario as in any embodiment of the first aspect is implemented.

[0043] This application implements a power management thermal distribution optimization method, system, device, and computer storage medium in a multi-chip package scenario. By dynamically constructing a thermal resistance network model, it accurately quantifies the non-uniform characteristics of thermal conductivity within the package as it changes with temperature. When the critical path timing margin is lower than the safety threshold, it combines thermal resistance path analysis with temperature data to lock the target chip unit to avoid energy efficiency loss caused by global voltage regulation. While fine-tuning the voltage to restore the timing margin, it utilizes the differentiation and fine-tuning of the digital LDO output impedance to cleverly change the leakage power consumption distribution of the local power domain, thereby actively guiding heat from the key hot spot area to the adjacent low-load area at the micro level. Under the premise of ensuring the performance and timing stability of the chip packaging system, it achieves the coordinated optimization of the power supply and heat distribution within the entire package, and achieves the precise optimization of the thermal distribution of the multi-chip package.

[0044] Furthermore, by collecting chip unit temperature data in real time and dynamically updating the thermal resistance network model, the weights of the heat conduction paths are continuously calibrated, the nodal thermal resistance values ​​of the packaging material units are corrected in real time, and the equivalent thermal resistance of the heat conduction paths is dynamically optimized based on temperature gradient changes. This allows for accurate identification of heat retention areas even in transient heat accumulation scenarios, avoiding misjudgment of heat dissipation paths due to model distortion. This effectively improves the real-time and reliability of the thermal guidance strategy, ensuring the accuracy and effectiveness of the coordinated optimization of power and heat distribution within the entire package while maintaining the performance and timing stability of the chip packaging system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 This is a flow chart of a method for optimizing thermal distribution of power management in a multi-chip package scenario provided by one embodiment of the present application;

[0047] Figure 2 This is a flow chart of a method for constructing a thermal resistance network model provided by one embodiment of the present application;

[0048] Figure 3 This is a flowchart of a power management and control method provided by an embodiment of the present application;

[0049] Figure 4 This is a structural diagram of a power management thermal distribution optimization system in a multi-chip package scenario provided by an embodiment of the present application;

[0050] Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0051] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0052] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0053] In existing technologies, dynamic voltage and frequency scaling (DVFS) technology or task migration strategies are used to thermally manage multi-chip systems. By monitoring the temperature of the multi-chip system, the operating frequency is reduced or tasks are migrated when the temperature is too high. However, existing power management thermal distribution optimization methods generally adopt a strategy of reducing the operating frequency of the entire chip and core functional units. In multi-chip co-packaging scenarios, especially in high-performance computing or communication baseband processing, chip performance is constrained by both timing closure and thermal effects. Refined management and optimization of thermal distribution within the package are required while ensuring performance. This global throttling measure sacrifices the performance of the entire functional unit or even the entire chip to solve a timing problem in a small area, resulting in unnecessary performance loss. It is unable to address the problem of timing performance degradation of critical circuits due to temperature increases in a local area within the package. Therefore, existing power management thermal distribution optimization methods in multi-chip co-packaging scenarios struggle to achieve efficient thermal distribution optimization while ensuring chip system performance, and are unable to achieve precise thermal distribution optimization.

[0054] To solve the prior art problems, the embodiment of the present application provides a power management heat distribution optimization method, system, device and computer storage medium in a multi-chip package scenario. First, the multi-chip package scenario power management heat distribution optimization method provided by the embodiment of the present application is introduced.

[0055] Figure 1 The flowchart of the multi-chip package scenario power management heat distribution optimization method provided by the embodiment of the present application is shown. As shown in Figure 1 , the method comprises steps S110 to S150.

[0056] S110: Obtain temperature data of multiple chip units in a multi-chip package and timing margin data of a target timing path, and preset material thermal conductivity data of the multi-chip package, the target timing path being a signal path with the maximum signal propagation delay in the multi-chip package, and the material thermal conductivity data including the correspondence between material thermal conductivity and temperature in the multi-chip package.

[0057] The multi-chip package scenario refers to a high-performance and high-density computing scenario in which multiple independent chip units are integrated in a single package to work cooperatively, such as communication baseband processing or data center computing. The multi-chip package is a physical entity in this scenario, which internally contains multiple functionally independent chip units. The chip unit is a basic functional module in the multi-chip package, such as a processor core or a memory controller. The target timing path refers to a specific signal path with the maximum signal propagation delay that plays a decisive role in the overall running speed of the multi-chip package determined by static timing analysis in the design stage. The timing margin data is quantitative data representing the stability of signal transmission on the target timing path, specifically the time difference between the specified time and the actual time of signal arrival. The material thermal conductivity data refers to a pre-established reference data set that records the thermal conductivity values of various physical materials, such as silicon and packaging substrates, at different temperatures, which constitute the multi-chip package.

[0058] First, load the preset material thermal conductivity data from the memory. The material thermal conductivity data is the correspondence between material thermal conductivity and temperature established by physical property testing of the materials used in the chip design and packaging stage. Then, through the on-chip sensor network, real-time data collection is performed, and temperature data reported by temperature sensors distributed in each chip unit is periodically polled or received, and the signal delay of the target timing path output by the key path monitor deployed in the key logic region of the chip, i.e. the timing margin data, is continuously monitored. Through the above process, the global temperature distribution data reflecting the current thermal condition, the timing margin data reflecting the current performance state, and the material thermal conductivity data including the correspondence between material thermal conductivity and temperature are synchronously obtained.

[0059] For example, a multi-chip package for high performance computing is taken as an example. In a package, a central input / output chip unit and four signal processing chip units are integrated, and a target timing path is a data communication path from a computing chip unit, through the central input / output chip unit, and to another computing chip unit. First, material thermal conductivity data is loaded from a memory, which records the thermal conductivity of silicon materials used by the central input / output chip unit and the signal processing chip units, the thermal conductivity of a package substrate on which the two are mounted, and the thermal conductivity of a thermal interface material between the chip units and a package cover plate corresponding to a temperature; for example, a record in the data can be that the thermal conductivity of the silicon material is 135 W / (m·K) at 55 °C. Then, the embedded management controller sends a polling request to a temperature sensor located at the geometric center of each chip unit every 10 ms to collect temperature readings of each chip unit, for example, five independent temperature readings can be obtained in one collection, the central input / output chip unit is 58 °C, and the four signal processing chip units are 65 °C, 52 °C, 49 °C, and 61 °C, respectively. At the same time, the controller receives signal delay time values output by a critical path monitor in the central input / output chip unit for monitoring the target timing path, that is, timing margin data, for example, the timing margin data is 50 ps.

[0060] S120: Based on the temperature data, the material thermal conductivity data, and the package physical structure data of the multi-chip package, a thermal resistance network model is constructed by determining the thermal resistance values of the chip units and the package material units in the package physical structure data, the thermal resistance network model including network nodes representing the chip units or the package material units, edges representing the heat transfer channels between the network nodes, and a plurality of heat conduction paths including path thermal resistance values composed of the network nodes and the edges.

[0061] The package physical structure data refers to a static data set describing the geometric layout and material composition of the multi-chip package, including the spatial coordinates, dimensions, and material categories of each chip unit and package material unit. The package material unit refers to a non-functional physical component that constitutes a heat conduction channel within the multi-chip package, such as a package substrate or a thermal interface material. The thermal resistance network model refers to a graph structure model used to abstractly represent the heat flow characteristics within the multi-chip package, where network nodes represent chip units or package material units, and edges represent heat transfer channels formed by physical contact between components. The heat conduction path refers to a specific path in the thermal resistance network model composed of a series of connected network nodes and edges, representing the transfer of heat from one point to another. The path thermal resistance value refers to the quantified value of the total resistance to heat flow along a specific heat conduction path.

[0062] First, a network topology is derived from the geometric layout and physical connections of physical components, such as chip units and packaging material units, within the package physical structure data. This structure converts the physical components and their spatial adjacencies into network nodes and the edges connecting them. Subsequently, for network nodes representing chip units, their corresponding temperature values ​​are determined directly using previously acquired temperature data; for network nodes representing packaging material units, their temperature values ​​are inferred based on the temperature data of adjacent chip units. After determining the temperature values ​​of all network nodes, the previously acquired material thermal conductivity data is used to query and assign the corresponding material thermal conductivity value at the current temperature to each network node. Finally, the independent thermal resistance of each network node is calculated by combining the geometric dimensions of each network node with the determined material thermal conductivity value. This is then accumulated along multiple pathways in the network topology to obtain the path thermal resistance value for each heat conduction path, thus completing the construction of a complete thermal resistance network model.

[0063] S130 : When the timing margin in the timing margin data is less than a preset margin threshold, determine a target chip unit among the chip units passed through in the target timing path using the temperature data.

[0064] The preset margin threshold is a performance benchmark value set to ensure stable operation of a multi-chip package under various workloads. It represents the minimum timing safety margin that must be maintained on the target timing path. The target chip unit is the specific chip unit on the target timing path where excessive temperature is most likely to cause overall timing performance degradation.

[0065] First, the timing margin of the real-time timing margin data is numerically compared with a preset margin threshold. If the timing margin data is detected to be below the preset margin threshold, all chip units along the target timing path are extracted to form a set of candidate chip units. Next, the acquired temperature data is used to extract the corresponding temperature value for each candidate chip unit in this set. Finally, by comparing the temperature values ​​of these candidate chip units, the candidate chip unit with the highest temperature value is identified as the target chip unit causing performance degradation.

[0066] S140: Determine a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit based on a difference between the timing margin and a preset margin threshold, and a path thermal resistance value of a heat conduction path associated with the target chip unit in a thermal resistance network model.

[0067] The first regulated voltage refers to a target supply voltage value calculated for a target chip unit to compensate for its timing performance loss due to temperature rise. The first regulated impedance refers to a lower target output impedance value set for the power supply unit corresponding to the target chip unit to enhance the power supply unit's transient response capability during voltage adjustment. The second regulated impedance refers to a higher target output impedance value set for the power supply unit corresponding to at least one adjacent unit of the target chip unit to reduce its static leakage power consumption, thereby forming a low-temperature area at the adjacent location to facilitate heat dissipation from the target chip unit.

[0068] First, the difference between the current timing margin and a preset margin threshold is calculated. The target voltage increment required to restore performance is determined based on a constructed lookup table that correlates timing margin loss with required voltage compensation, thereby obtaining a first control voltage. Furthermore, a constructed thermal resistance network model is queried to identify heat conduction paths with lower path thermal resistance values ​​from the target chip unit, and adjacent chip units along these paths are identified. Subsequently, a preset first control impedance is assigned to the target chip unit, and a second control impedance is assigned to selected adjacent chip units. The value of the second control impedance can be inversely correlated with the path thermal resistance value of the corresponding heat conduction path to guide heat flow.

[0069] S150: regulating the supply voltage and output impedance of the power supply unit corresponding to the target chip unit through the first regulation voltage and the first regulation impedance, and regulating the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit through the second regulation impedance.

[0070] A power supply unit (PSU) is an on-chip power module within a multi-chip package that provides independently adjustable power to individual chips. It is a digital low-dropout linear regulator. The supply voltage is the amplitude of the DC voltage output by the PSU to the chip it is responsible for. The output impedance is the internal equivalent resistance of the PSU, and its value determines the voltage drop in response to changes in load current and its own static power consumption.

[0071] The central power management controller sends parameters such as the first control voltage, the first control impedance, and the second control impedance to the power supply units corresponding to the target chip unit and its adjacent chip units. The power supply unit of the target chip unit adjusts its internal reference voltage to change the supply voltage based on the first control voltage instruction. It also restructures its internal power tube array based on the first control impedance instruction, such as by increasing the number of power tubes operating in parallel to reduce its output impedance. The power supply unit of the adjacent chip unit similarly restructures its power tube array based on the second control impedance instruction, such as by reducing the number of power tubes operating in parallel to increase its output impedance.

[0072] This embodiment dynamically constructs a thermal resistance network model to accurately quantify the non-uniform nature of thermal conductivity within the package as it changes with temperature. When the critical path timing margin falls below a safety threshold, it combines thermal resistance path analysis with temperature data to lock onto the target chip unit, avoiding energy efficiency losses caused by global voltage regulation. While fine-tuning the voltage to restore the timing margin, it utilizes differential and refined adjustments to the digital LDO output impedance to cleverly alter the leakage power distribution within the local power domain, thereby actively guiding heat flow from critical hotspots to adjacent low-load areas at a microscopic level. While ensuring the performance and timing stability of the chip packaging system, this achieves coordinated optimization of power and heat distribution within the entire package, achieving precise optimization of the thermal distribution of multi-chip packages.

[0073] In one possible implementation, after step S120: constructing a thermal resistance network model by determining thermal resistance values ​​of chip units and packaging material units in the packaging physical structure data based on the temperature data, the material thermal conductivity data, and the packaging physical structure data of the multi-chip package, the method further includes:

[0074] Acquire real-time temperature data of multiple chip units in a multi-chip package; use the real-time temperature data and material thermal conductivity data to update the path thermal resistance value of the heat conduction path in the thermal resistance network model.

[0075] After the thermal resistance network model is initially constructed, it is periodically updated. First, a set of the latest real-time temperature data for the chip units is obtained. Next, for each network node corresponding to the chip unit whose temperature has changed, the corresponding updated material thermal conductivity value is queried from the material thermal conductivity data using its latest temperature value. Subsequently, the thermal resistance of this network node is recalculated based on this updated material thermal conductivity value and the node's geometric dimensions. Finally, the path thermal resistance values ​​of all heat conduction paths containing this updated node are recalculated, completing the refresh of the thermal resistance network model.

[0076] Exemplarily, after the thermal resistance network model is constructed based on the initial temperature data, the system continues to monitor. For example, a new set of real-time temperature data is obtained every 100ms, in which the temperature of the target chip unit, which was previously 65°C, has risen to 67°C. For the network node representing this target chip unit, the system uses the new temperature of 67°C to query the material thermal conductivity data to obtain an updated thermal conductivity value, such as 128 W / (m·K). Based on this updated thermal conductivity value, the system recalculates the node's own thermal resistance as a new value, such as 0.154 K / W. Therefore, the path thermal resistance values ​​of all heat conduction paths passing through this network node will be updated synchronously; for example, a heat conduction path with a previous path thermal resistance value of 1.2K / W will have an updated path thermal resistance value of 1.204 K / W.

[0077] This embodiment collects chip unit temperature data in real time and dynamically updates the thermal resistance network model, continuously calibrating the weights of the heat conduction paths, correcting the node thermal resistance values ​​of the packaging material units in real time, and dynamically optimizing the equivalent thermal resistance of the heat conduction paths based on temperature gradient changes. This allows accurate identification of heat retention areas even in transient heat accumulation scenarios, avoiding misjudgment of heat dissipation paths due to model distortion. This effectively improves the real-time and reliability of the thermal guidance strategy, ensuring the accuracy and effectiveness of the coordinated optimization of power and heat distribution within the entire package while maintaining the performance and timing stability of the chip packaging system.

[0078] Figure 2 FIG. 1 shows a flow chart of a method for constructing a thermal resistance network model provided by an embodiment of the present application. Figure 2 As shown, the method includes steps S210 to S250.

[0079] In one possible implementation, step S120: constructing a thermal resistance network model by determining the thermal resistance values ​​of chip units and packaging material units in the packaging physical structure data based on the temperature data, the material thermal conductivity data, and the packaging physical structure data of the multi-chip package, includes:

[0080] S210: Extract multiple discrete physical areas representing chip units and packaging material units from the packaging physical structure data, construct each discrete physical area as a network node, and based on the spatial adjacency relationship of the discrete physical areas in the packaging physical structure data, construct edges that represent the existence of heat transfer channels between network nodes to obtain topological connection information.

[0081] Discrete physical regions are physical entities with clear boundaries and identical material properties, demarcated within the physical structure of a package, such as a complete chip unit or a portion of a package substrate. Spatial adjacency refers to the physical contact or close proximity of two discrete physical regions in three-dimensional space, which forms the basis for heat transfer channels. Topological connectivity information refers to an abstract connection diagram consisting of network nodes and edges, indicating whether connections exist between nodes.

[0082] All chip units and packaging material units defined in the package physical structure data are identified as discrete physical regions. A unique network node identifier is then created for each discrete physical region. Finally, all pairs of discrete physical regions are traversed, and based on their spatial coordinates and dimensions in the package physical structure data, a determination is made as to whether there is direct physical contact between them. If so, an edge is established between the corresponding network nodes of the two regions, ultimately obtaining complete topological connectivity information.

[0083] S220: Based on each network node, extract the temperature value of each chip unit corresponding to the network node from the temperature data, and calculate the temperature value of each packaging material unit corresponding to the network node based on the topological connection information and the temperature value of each chip unit corresponding to the network node.

[0084] The temperature value of a network node refers to the quantitative value assigned to each node in the thermal resistance network model, representing the current temperature of the corresponding discrete physical area. For network nodes representing chip units, the temperature reading that matches the chip unit identifier is directly extracted from the acquired temperature data as its temperature value. For network nodes representing packaging material units, since their temperature cannot be directly measured, the topological connection information is used to find all chip unit nodes directly connected to this packaging material unit node, and the temperature value of the packaging material unit node is calculated based on linear interpolation or weighted averaging of the temperature values ​​of these nodes, or based on the chip unit nodes directly connected to this packaging material unit node.

[0085] S230: Based on the temperature value of each network node, the material thermal conductivity value of each network node is determined using the corresponding relationship between the material thermal conductivity and the temperature in the material thermal conductivity data.

[0086] The material thermal conductivity value of a network node is a physical parameter that reflects its thermal conductivity, obtained by querying the material thermal conductivity data based on the current temperature of each network node. Each network node in the thermal resistance network model is traversed, and the temperature value of each network node is used as the query condition. The preset material thermal conductivity data is searched to determine the material thermal conductivity value of the material represented by the network node at this specific temperature, and this value is assigned to the network node.

[0087] S240: Calculate the node thermal resistance value of each network node using the material thermal conductivity value and the geometric dimension information of the discrete physical region corresponding to the network node in the package physical structure data.

[0088] The geometric dimension information refers to the parameter data describing the geometric shape of the length, width, and height of the discrete physical region. The node thermal resistance value refers to the degree of hindrance of the discrete physical region represented by a single network node to heat conduction. Traverse each network node in the thermal resistance network model, obtain the geometric dimension information of the discrete physical region corresponding to the network node from the package physical structure data, such as thickness and cross-sectional area. Finally, based on the existing material thermal conductivity value of each network node and the corresponding geometric dimension of the node corresponding material, the node thermal resistance value of each network node is calculated using the steady-state heat conduction formula as shown in formula (1).

[0089] R_th = L / (k ×A) (1)

[0090] Where R_th represents the node thermal resistance value, indicating the degree of hindrance of the discrete physical region to heat flow; L represents the thickness of the discrete physical region in the main heat conduction direction; k represents the material thermal conductivity value of the network node that has been determined, indicating the ability of the material to conduct heat; A represents the cross-sectional area of the discrete physical region perpendicular to the main heat conduction direction.

[0091] S250: Determine multiple heat conduction paths based on the topological connection information, and calculate the path thermal resistance value of each heat conduction path according to the node thermal resistance value of the network node in each heat conduction path, to obtain the thermal resistance network model.

[0092] First, use the topological connection information to identify all possible heat conduction paths from one chip unit to another chip unit or the heat dissipation boundary in the thermal resistance network model through depth-first search or breadth-first search. Then, for each identified heat conduction path, add up the node thermal resistance values of all network nodes on the path. Finally, by summarizing all heat conduction paths and their corresponding path thermal resistance values, a complete thermal resistance network model is obtained.

[0093] For example, a signal processing chip unit, the packaging substrate area directly below it, and the thermal interface material area directly above it are each identified as three discrete physical regions. Unique network node identifiers are created for each of them. Connecting edges are then established based on their physical contact relationships to form local topological connection information. If the temperature data for the signal processing chip unit is 65°C, and the heat sink boundary temperature above it is 40°C, a temperature value of 65°C is assigned to the network node representing the signal processing chip unit, and the temperature value of the thermal interface material node is calculated to be 52.5°C through linear interpolation. Next, using 65°C as a query condition, the material thermal conductivity value of silicon material at this temperature is searched in the material thermal conductivity data, for example, a thermal conductivity value of 130 W / (m·K); and using 52.5°C as a query condition, the material thermal conductivity value of the thermal interface material is determined, for example, a thermal conductivity value of 5 W / (m·K). Then, based on the geometric dimensions of the signal processing chip unit, which can be 0.5 mm thick and 25 mm² in area, its node thermal resistance is calculated to be 0.15 K / W. The thermal resistance values ​​of other network nodes are calculated using the same method. Finally, the topological connection information is used to identify a heat conduction path from the signal processing chip unit node through the thermal interface material node to the heat sink boundary. The node thermal resistance values ​​of the two network nodes on this path are cumulatively calculated to obtain a path thermal resistance of 0.95 K / W. Using this method, a complete thermal resistance network model is constructed, including all heat conduction paths and their corresponding path thermal resistance values.

[0094] For example, a signal processing chip unit (chip unit A) with a temperature of 65°C, another signal processing chip unit (chip unit B) directly adjacent to it on the package substrate with a temperature of 52°C, and the package substrate region between these two chip units are identified as three discrete physical regions. Unique network node identifiers are then created for these three discrete physical regions, and connecting edges are established based on their physical contact relationships to form local topological connectivity information. Next, the network nodes representing chip unit A and chip unit B are assigned temperature values ​​of 65°C and 52°C, respectively. Using this topological connectivity information, the package substrate region node is identified as being between the chip unit A node and the chip unit B node. The temperature value of this package substrate region node can then be calculated using linear interpolation, where the temperature value is 58.5°C.

[0095] Afterwards, 65°C is used as the query condition to find the material thermal conductivity value of silicon material at this temperature in the material thermal conductivity data, for example, the thermal conductivity value is 130 W / (m·K). Subsequently, based on the geometric dimension information of the signal processing chip unit, where the thickness can be 0.5mm and the area can be 25 mm², its node thermal resistance value is calculated to be 0.15 K / W; the thermal resistance values ​​of other network nodes are calculated in the same way. Finally, the topological connection information is used to identify a heat conduction path from the signal processing chip unit node through the thermal interface material node to the heat sink boundary, and the node thermal resistance values ​​of the two network nodes on this path are accumulated and calculated to obtain the path thermal resistance value of the heat conduction path to be 0.95K / W. Referring to the above method, a complete thermal resistance network model containing all heat conduction paths and their corresponding path thermal resistance values ​​is finally constructed.

[0096] In one feasible embodiment, step S130: when the timing margin in the timing margin data is less than a preset margin threshold, determining a target chip unit among the chip units passed through in the target timing path using the temperature data includes:

[0097] Determine whether the timing margin in the timing margin data is less than a preset margin threshold; if the timing margin in the timing margin data is less than the preset margin threshold, extract identification information of each chip unit passed through in the target timing path to obtain a set of candidate chip units.

[0098] The preset margin threshold refers to the minimum time safety margin that must be maintained in the pre-set timing path to ensure stable operation of the multi-chip package. The time value in the acquired timing margin data is compared with the preset margin threshold. If the time value in the timing margin data is less than the preset margin threshold, indicating insufficient performance margin, it is necessary to intervene and make optimization adjustments in advance to avoid affecting the normal operation of the multi-chip system. The unique identifiers of all chip units that constitute the target timing path are extracted from the target timing path to obtain a set of candidate chip units.

[0099] Based on the temperature values ​​of all chip units in the temperature data, the temperature value of each candidate chip unit in the candidate chip unit set is determined; and the candidate chip unit with the largest temperature value in the candidate chip unit set is determined as the target chip unit.

[0100] For each candidate chip unit in the candidate chip unit set, a temperature value corresponding to each candidate chip unit is extracted from the acquired temperature data of each chip unit. The temperature values ​​of each candidate chip unit in the candidate chip unit set are then compared to find a maximum value, and the candidate chip unit with the maximum temperature value is determined as the target chip unit.

[0101] For example, a determination is made as to whether the timing margin of 25 ps in the timing margin data is less than a preset margin threshold of 30 ps. If the timing margin in the timing margin data is less than the preset margin threshold, the identification information of each chip unit passed through in the target timing path is extracted, namely, computing chip unit A, central input / output chip unit, and computing chip unit B, to obtain a set of candidate chip units. For each candidate chip unit in the set of candidate chip units, the temperature values ​​corresponding to each candidate chip unit are extracted from the obtained temperature data of each chip unit, which are 65°C, 58°C, and 61°C, respectively. The temperature values ​​of each candidate chip unit in the set of candidate chip units are then compared to find the maximum value, and the candidate chip unit corresponding to the maximum value of 65°C, namely, computing chip unit A, is determined as the target chip unit.

[0102] In one feasible implementation, the first regulating impedance is smaller than the second regulating impedance.

[0103] Assigning a lower first control impedance to the target chip unit can ensure excellent transient response capabilities when the power supply unit of the target chip increases the voltage, thereby stably supporting high-performance operation. Assigning a higher second control impedance to the adjacent unit chip can reduce the static power consumption of the power supply unit, thereby actively creating a relatively low-temperature area near the target chip unit to facilitate heat dissipation from the high-temperature target chip unit.

[0104] In one feasible embodiment, step S140: determining a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, based on a difference between the timing margin and a preset margin threshold, and a path thermal resistance value of a heat conduction path associated with the target chip unit in a thermal resistance network model, includes:

[0105] The difference between the timing margin and the preset margin threshold is calculated to obtain the target timing margin difference; according to the mapping relationship between the preset timing margin difference and the voltage compensation value, the target voltage compensation value corresponding to the target timing margin difference is determined, and the first control voltage is obtained based on the reference voltage value of the target chip unit.

[0106] The target timing margin difference refers to the specific value by which the current timing margin falls below the preset margin threshold, quantifying the severity of performance degradation. The mapping between the timing margin difference and the voltage compensation value refers to a pre-established table that characterizes the relationship between the supply voltage compensation and timing margin loss. The reference voltage value refers to the standard supply voltage of the target chip unit under normal operating conditions.

[0107] First, the difference between the timing margin and a preset margin threshold is calculated to obtain a target timing margin difference. This difference is then used as input to query a preset mapping between timing margin differences and voltage compensation values ​​to obtain a target voltage compensation value. Finally, this target voltage compensation value is added to the reference voltage of the target chip unit to calculate the final first control voltage.

[0108] Among all heat conduction paths associated with the target chip unit, the heat conduction path with the smallest path thermal resistance value is determined to be the target heat conduction path, and based on the topological connection structure of the thermal resistance network model, the chip unit in the target heat conduction path whose path distance to the target chip unit is less than a preset path distance threshold is determined to be the unit chip adjacent to the target chip unit.

[0109] The target heat conduction path refers to one or more heat conduction paths starting from the target chip unit and having the smallest path thermal resistance value, through which heat can most easily flow out.

[0110] Path distance refers to the minimum number of edges required to travel from a node in a target chip unit to a node in another chip unit in the topological connection structure of the thermal resistance network model. The preset path distance threshold is an integer that defines the proximity range. For example, this value can be set to 2 or 3 to filter out chip units that are directly connected to the target chip unit or connected through one or two intermediate nodes in the topological structure.

[0111] First, all heat conduction paths from the target chip unit node in the constructed thermal resistance network model are traversed and the path thermal resistance values ​​of these paths are compared to determine one or more target heat conduction paths with the lowest path thermal resistance values. Then, along the determined target heat conduction path, starting from the target chip unit node, the path distance between other chip unit nodes on the path and the target chip unit node is calculated. Finally, those chip units whose path distance is less than a preset path distance threshold are determined to be unit chips adjacent to the target chip unit.

[0112] The unit chip adjacent to the target chip unit with a preset first impedance value is used as the first control impedance, and the second control impedance of the unit chip adjacent to the target chip unit is determined in the preset second impedance value set, and the path thermal resistance value of the target heat conduction path is inversely correlated with the impedance value of the second control impedance.

[0113] The preset first impedance value is a fixed low impedance value pre-set for the target chip unit to ensure a good transient response when the voltage is increased. The preset second impedance value set is a set of selectable high impedance values ​​used to control the power consumption of adjacent chip units.

[0114] First, a preset first impedance value is assigned to the target chip unit as its first control impedance. For each unit chip adjacent to the target chip unit, an appropriate second control impedance is selected from a preset set of second impedance values, based on the principle that the path thermal resistance of the target heat conduction path between the unit chip and the target chip unit is inversely correlated with the impedance value of the second control impedance. Specifically, a smaller path thermal resistance value indicates a better heat dissipation channel, and a larger second control impedance value can be selected to maximize power consumption reduction.

[0115] For example, the difference between the timing margin and the preset margin threshold of 25 ps is first calculated to obtain a target timing margin difference of 30 ps, ​​that is, 30 ps minus 25 ps equals 5 ps. Based on the mapping relationship between the timing margin difference and the voltage compensation value shown in Table 1, the target voltage compensation value corresponding to the target timing margin difference of 5 ps is determined to be 25 mV. Based on the reference voltage value of the target chip unit of 0.8 V, the first control voltage is calculated to be 0.825 V. Then, all heat conduction paths starting from the target chip unit node in the thermal resistance network model are traversed and the path thermal resistance values ​​of these paths are compared. A path associated with the target chip unit is determined to have a thermal resistance of 1.2 K / W, which is the target heat conduction path. At the same time, the path distance from unit chip A to the target chip unit in the target heat conduction path is determined in the thermal resistance network model to be 2, which is less than the preset path distance threshold of 3. Therefore, the adjacent unit chip A is determined to be the target of collaborative control.

[0116] Finally, a preset first impedance value of 0.5 mΩ is set as the first control impedance of the target chip unit. Based on the path thermal resistance of 1.2 K / W between the target chip unit and the adjacent unit chip A, a higher impedance value, such as 5 mΩ, is selected from a preset second impedance value set, which includes 2 mΩ, 5 mΩ, and 10 mΩ, as the second control impedance of the adjacent unit chip A. A set of control instructions is generated, including setting the voltage of the target chip unit to 0.825 V, the output impedance to 0.5 mΩ, and the output impedance of its adjacent unit chip A to 5 mΩ.

[0117] Table 1

[0118] Timing margin difference (ps) Voltage compensation value (mV) 0 - 2 12.5 3 - 5 25.0 6 - 10 37.5 11 - 20 50.0 >20 62.5

[0119] Figure 3 FIG1 shows a flow chart of a power management control method provided by an embodiment of the present application. Figure 3 As shown, the method includes steps S310 to S320.

[0120] In one feasible embodiment, regulating the supply voltage and output impedance of the power supply unit corresponding to the target chip unit by a first regulating voltage and a first regulating impedance, and regulating the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit by a second regulating impedance, includes:

[0121] S310: Adjusting the supply voltage of a first power supply unit associated with a target chip unit according to a first regulation voltage, and reconstructing the power transistor array of the first power supply unit according to a first regulation impedance to match the first regulation impedance.

[0122] A power supply unit (PSU) is an on-chip power module within a multi-chip package that provides independently adjustable power to individual chips. It is a digital low-dropout linear regulator. The power transistor array (PTA) is the core of the PSU, consisting of multiple parallel-connected power transistors. By controlling the number and type of transistors activated in this array, the PSU's output characteristics can be modified. Reconfiguring the PSU array involves dynamically adjusting the array's operating state to alter the PSU's output impedance.

[0123] Two sets of parallel digital control instructions are sent via the central power management controller to the power supply unit supplying the target chip unit. The first set of instructions adjusts the reference voltage or feedback network within the first power supply unit so that its output voltage precisely meets the first regulation voltage requirement. The second set of instructions reconfigures its power transistor array. Specifically, to match the lower first regulation impedance, the instructions activate more power transistors in parallel, thereby increasing the overall conductivity and reducing the equivalent output impedance.

[0124] S320: Reconstructing the power supply transistor array of the second power supply unit associated with the unit chip adjacent to the target chip unit according to the second control impedance to match the second control impedance.

[0125] A set of digital control instructions is sent through a central power management controller to the power supply unit that powers the unit chip adjacent to the target unit chip, which is used to reconfigure the power transistor array to match the higher second control impedance. Specifically, to achieve the higher second control impedance, the number of power transistors operating in parallel is reduced, or transistors with higher threshold voltages are switched to operate, thereby reducing the overall conductivity, reducing static leakage power consumption, and improving the equivalent output impedance.

[0126] Exemplarily, according to the generated control instruction, the first control voltage of the target chip unit is 0.825 V, the first control impedance is 0.5 mΩ, and the second control impedance of its adjacent unit chip A is 5 mΩ. The central power management controller sends two sets of parallel digital control instructions to the power supply unit that supplies power to the target chip unit. The first set of instructions is used to adjust the reference voltage inside the power supply unit so that its output power supply voltage is precisely adjusted from the reference 0.8V to the first regulation voltage of 0.825V. The second set of instructions is used to reconstruct its power supply tube array. To match the lower first regulation impedance of 0.5mΩ, more power transistors are activated to work in parallel, for example, the number of transistors working in parallel is increased from 100 to 120, thereby increasing the total conductivity and reducing the equivalent output impedance. At the same time, the central power management controller sends a set of digital control instructions to the power supply unit that supplies power to the unit chip A adjacent to the target chip unit. It is used to reconstruct its power supply tube array to match the higher second regulation impedance of 5mΩ and reduce the number of power transistors working in parallel, for example, reducing the number of transistors working in parallel from 80 to 20, thereby reducing the total conductivity, reducing static leakage power consumption while improving the equivalent output impedance. This embodiment can restore the timing performance of the target chip unit, and at the same time, the heat generated by it can be more easily transferred to the adjacent area with lower temperature after power consumption reduction treatment, thereby achieving coordinated optimization of performance and thermal management.

[0127] Based on the same concept, the embodiment of the present application provides a power management thermal distribution optimization system in a multi-chip package scenario. Figure 4 The power management thermal distribution optimization system in a multi-chip package scenario provided by an embodiment of the present application is described in detail.

[0128] Figure 4 This is a structural block diagram of a power management thermal distribution optimization system in a multi-chip packaging scenario shown in an embodiment of the present application.

[0129] like Figure 4 As shown, the power management thermal distribution optimization system in the multi-chip package scenario may include:

[0130] an acquisition module 410 configured to acquire temperature data of multiple chip units within a multi-chip package, timing margin data of a target timing path, and preset material thermal conductivity data of the multi-chip package, wherein the target timing path is a signal path with a maximum signal propagation delay within the multi-chip package, and the material thermal conductivity data includes a corresponding relationship between the thermal conductivity of the material within the multi-chip package and the temperature;

[0131] A construction module 420 is configured to construct a thermal resistance network model based on the temperature data, the material thermal conductivity data, and the package physical structure data of the multi-chip package by determining the thermal resistance values ​​of the chip units and the package material units in the package physical structure data. The thermal resistance network model includes network nodes representing the chip units or the package material units, edges representing the existence of heat transfer channels between the network nodes, and multiple heat conduction paths including path thermal resistance values ​​formed by the network nodes and edges.

[0132] a determination module 430 for determining a target chip unit from among the chip units passed through in the target timing path using the temperature data when the timing margin in the timing margin data is less than a preset margin threshold;

[0133] The determination module 430 is further configured to determine a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, based on a difference between the timing margin and a preset margin threshold and a path thermal resistance value of a heat conduction path associated with the target chip unit in the thermal resistance network model;

[0134] The control module 440 is used to control the power supply voltage and output impedance of the power supply unit corresponding to the target chip unit through the first control voltage and the first control impedance, and to control the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit through the second control impedance.

[0135] In one embodiment, the construction module 420 is also used to obtain real-time temperature data of multiple chip units in the multi-chip package after constructing a thermal resistance network model based on temperature data, material thermal conductivity data and packaging physical structure data of the multi-chip package by determining the thermal resistance values ​​of the chip units and packaging material units in the packaging physical structure data; and use the real-time temperature data and material thermal conductivity data to update the path thermal resistance value of the heat conduction path in the thermal resistance network model.

[0136] In one embodiment, the construction module 420 is specifically used to extract multiple discrete physical regions representing chip units and packaging material units from the packaging physical structure data, construct each discrete physical region as a network node, and construct edges representing the existence of heat transfer channels between network nodes based on the spatial adjacency relationship of the discrete physical regions in the packaging physical structure data to obtain topological connection information; based on each network node, extract the temperature value of the network node corresponding to each chip unit from the temperature data, and calculate the temperature value of the network node corresponding to each packaging material unit based on the topological connection information and the temperature value of the network node corresponding to each chip unit; based on the temperature value of each network node, use the corresponding relationship between material thermal conductivity and temperature in the material thermal conductivity data to determine the material thermal conductivity value of each network node; use the material thermal conductivity value and the geometric size information of the discrete physical region corresponding to the network node of the packaging physical structure data to calculate the node thermal resistance value of each network node; determine multiple heat conduction paths based on the topological connection information, and calculate the path thermal resistance value of each heat conduction path based on the node thermal resistance value of the network node in each heat conduction path to obtain a thermal resistance network model.

[0137] In one embodiment, the determination module 430 is specifically used to determine whether the timing margin in the timing margin data is less than a preset margin threshold; when the timing margin in the timing margin data is less than the preset margin threshold, the identification information of each chip unit passed through in the target timing path is extracted to obtain a set of candidate chip units; based on the temperature values ​​of all chip units in the temperature data, the temperature value of each candidate chip unit in the candidate chip unit set is determined; and the candidate chip unit with the largest temperature value in the candidate chip unit set is determined as the target chip unit.

[0138] In one embodiment, the first regulation impedance is smaller than the second regulation impedance.

[0139] In one embodiment, the determination module 430 is specifically used to calculate the difference between the timing margin and the preset margin threshold to obtain a target timing margin difference; determine the target voltage compensation value corresponding to the target timing margin difference based on the mapping relationship between the preset timing margin difference and the voltage compensation value, and obtain a first control voltage based on the reference voltage value of the target chip unit; among all heat conduction paths associated with the target chip unit, determine the heat conduction path with the smallest path thermal resistance as the target heat conduction path, and according to the topological connection structure of the thermal resistance network model, determine the chip unit in the target heat conduction path whose path distance with the target chip unit is less than the preset path distance threshold as the unit chip adjacent to the target chip unit; use the preset first impedance value and the unit chip adjacent to the target chip unit as the first control impedance, and determine the second control impedance of the unit chip adjacent to the target chip unit in the preset second impedance value set, and the path thermal resistance value of the target heat conduction path is inversely correlated with the impedance value of the second control impedance.

[0140] In one embodiment, the regulation module 440 is specifically configured to adjust the power supply voltage of the first power supply unit associated with the target chip unit according to the first regulation voltage, and reconstruct the power supply tube array of the first power supply unit to match the first regulation impedance according to the first regulation impedance; and reconstruct the power supply tube array of the second power supply unit associated with the unit chip adjacent to the target chip unit to match the second regulation impedance according to the second regulation impedance.

[0141] Figure 4 Each module in the system shown has the function of implementing each step in the method and can achieve its corresponding technical effects. For brevity, the description will not be repeated here. Figures 1 to 3 Each step in the method has the function of implementing each step in the method and can achieve its corresponding technical effects. For brevity, the description will not be repeated here.

[0142] Figure 5 A hardware structure schematic diagram of an electronic device provided by an embodiment of the present application is shown.

[0143] The electronic device can include a processor 510 and a memory 520 having computer program instructions stored therein.

[0144] Specifically, the processor 510 described above can include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or can be configured to implement one or more integrated circuits of the embodiments of the present application.

[0145] The memory 520 can include a mass storage for data or instructions. By way of example and not limitation, the memory 520 can include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. Where appropriate, the memory 520 can include removable or non-removable (or fixed) media. Where appropriate, the memory 520 can be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, the memory 520 is a non-volatile solid-state memory.

[0146] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical / tangible memory storage devices. Thus, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to the first aspect of the present disclosure.

[0147] The processor 510 reads and executes computer program instructions stored in the memory 520 to implement any one of the power management thermal distribution optimization methods in the multi-chip package scenario described in the above embodiments.

[0148] In one example, the electronic device may further include a communication interface 530 and a bus 540. Figure 5 As shown, the processor 510 , the memory 520 , and the communication interface 530 are connected via a bus 540 and communicate with each other.

[0149] The communication interface 530 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0150] Bus 540 includes hardware, software, or both, and couples the components of the online data traffic metering device to each other. By way of example, and not limitation, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industrial Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industrial Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Area Network (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 540 may include one or more buses. Although the embodiments of the present application describe and illustrate specific buses, the present application contemplates any suitable bus or interconnect.

[0151] The electronic device can execute the power management thermal distribution optimization method in the multi-chip package scenario in the embodiment of the present application, thereby realizing the combination Figures 1 to 3 Describes the power management thermal distribution optimization method in the multi-chip package scenario.

[0152] In addition, in conjunction with the power management thermal distribution optimization method in a multi-chip package scenario described in the above embodiments, embodiments of the present application may provide a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; when executed by a processor, the computer program instructions implement any of the power management thermal distribution optimization methods in a multi-chip package scenario described in the above embodiments.

[0153] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0154] The functional blocks shown in the block diagrams described above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they may be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, and the like. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments may be stored in a machine-readable medium or transmitted via a data signal carried in a carrier wave over a transmission medium or communication link. "Machine-readable medium" may include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memory, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, and the like. Code segments may be downloaded via a computer network such as the Internet or an intranet.

[0155] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0156] Those skilled in the art will appreciate that the functions of the various steps in the foregoing method, apparatus (system) and computer program product embodiments can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer program instructions can also be stored in a computer-usable or computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer- usable or computer-readable memory produce an article of manufacture including instructions which implement the functions / acts specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0157] The above description merely provides the preferred embodiments of the present application, and the skilled in the art can clearly understand the specific working process of the above-mentioned system, modules and units in the description, which can refer to the corresponding process in the foregoing method embodiments, and will not be described here. It should be understood that the protection scope of the present application is not limited to this, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed in the present application, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. A method for optimizing thermal distribution of power management in a multi-chip package scenario, characterized in that: include: Acquiring temperature data of multiple chip units within a multi-chip package, timing margin data of a target timing path, and preset material thermal conductivity data of the multi-chip package, wherein the target timing path is a signal path with a maximum signal propagation delay within the multi-chip package, and the material thermal conductivity data includes a corresponding relationship between the thermal conductivity of the material within the multi-chip package and the temperature; Based on the temperature data, the material thermal conductivity data, and the package physical structure data of the multi-chip package, a thermal resistance network model is constructed by determining the thermal resistance values ​​of the chip units and the packaging material units in the package physical structure data, wherein the thermal resistance network model includes network nodes representing the chip units or the packaging material units, edges representing the existence of heat transfer channels between the network nodes, and multiple heat conduction paths formed by the network nodes and the edges, including path thermal resistance values; When the timing margin in the timing margin data is less than a preset margin threshold, determining a target chip unit among the chip units passed through in the target timing path by using the temperature data; Determining a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, based on a difference between the timing margin and the preset margin threshold, and a path thermal resistance value of a heat conduction path associated with the target chip unit in the thermal resistance network model; Regulating the supply voltage and output impedance of the power supply unit corresponding to the target chip unit by using the first regulation voltage and the first regulation impedance, and regulating the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit by using the second regulation impedance; The step of constructing a thermal resistance network model based on the temperature data, the material thermal conductivity data, and the package physical structure data of the multi-chip package by determining the thermal resistance values ​​of the chip unit and the package material unit in the package physical structure data includes: Extracting multiple discrete physical regions representing chip units and packaging material units from the package physical structure data, constructing each of the discrete physical regions as a network node, and constructing edges representing heat transfer channels between the network nodes based on spatial adjacency relationships between the discrete physical regions in the package physical structure data to obtain topological connection information; Based on each of the network nodes, extracting the temperature value of the network node corresponding to each chip unit from the temperature data, and calculating the temperature value of the network node corresponding to each packaging material unit according to the topological connection information and the temperature value of the network node corresponding to each chip unit; Based on the temperature value of each network node, the material thermal conductivity value of each network node is determined using the corresponding relationship between the material thermal conductivity and the temperature in the material thermal conductivity data; Calculating a node thermal resistance value of each network node by using the material thermal conductivity value and the geometric size information of the discrete physical area corresponding to the network node of the encapsulated physical structure data; A plurality of heat conduction paths are determined based on the topological connection information, and a path thermal resistance value of each heat conduction path is calculated according to a node thermal resistance value of a network node in each heat conduction path to obtain the thermal resistance network model.

2. The method according to claim 1, characterized in that After constructing the thermal resistance network model based on the temperature data, the material thermal conductivity data, and the package physical structure data of the multi-chip package by determining the thermal resistance values ​​of the chip units and the package material units in the package physical structure data, the method further includes: Acquiring real-time temperature data of multiple chip units in the multi-chip package; The path thermal resistance value of the heat conduction path in the thermal resistance network model is updated using the real-time temperature data and the material thermal conductivity data.

3. The method according to claim 1, characterized in that When the timing margin in the timing margin data is less than a preset margin threshold, determining a target chip unit from the chip units passed through in the target timing path by using the temperature data includes: Determining whether the timing margin in the timing margin data is less than a preset margin threshold; When the timing margin in the timing margin data is less than a preset margin threshold, extracting identification information of each chip unit passed through in the target timing path to obtain a set of candidate chip units; Determining a temperature value of each candidate chip unit in the candidate chip unit set based on the temperature values ​​of all chip units in the temperature data; The candidate chip unit with the largest temperature value in the candidate chip unit set is determined as the target chip unit.

4. The method according to claim 1, wherein The first regulating impedance is smaller than the second regulating impedance.

5. The method according to claim 4, characterized in that The determining, based on the difference between the timing margin and the preset margin threshold and the path thermal resistance value of the heat conduction path associated with the target chip unit in the thermal resistance network model, a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, includes: Calculating a difference between the timing margin and the preset margin threshold to obtain a target timing margin difference; Determine a target voltage compensation value corresponding to the target timing margin difference according to a preset mapping relationship between the timing margin difference and the voltage compensation value, and obtain the first regulation voltage based on the reference voltage value of the target chip unit; Among all heat conduction paths associated with the target chip unit, determining the heat conduction path with the smallest path thermal resistance as the target heat conduction path, and determining, based on the topological connection structure of the thermal resistance network model, the chip units in the target heat conduction path whose path distance to the target chip unit is less than a preset path distance threshold as unit chips adjacent to the target chip unit; The unit chip adjacent to the target chip unit with a preset first impedance value is used as the first control impedance, and the second control impedance of the unit chip adjacent to the target chip unit is determined in a preset second impedance value set, and the path thermal resistance value of the target heat conduction path is inversely correlated with the impedance value of the second control impedance.

6. The method according to claim 1, characterized in that The step of regulating the supply voltage and output impedance of the power supply unit corresponding to the target chip unit by using the first regulating voltage and the first regulating impedance, and regulating the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit by using the second regulating impedance, includes: Adjusting the supply voltage of a first power supply unit associated with the target chip unit according to the first regulation voltage, and reconstructing the power transistor array of the first power supply unit to match the first regulation impedance according to the first regulation impedance; According to the second regulated impedance, the power supply transistor array of the second power supply unit associated with the unit chip adjacent to the target chip unit is reconstructed to match the second regulated impedance.

7. A power management thermal distribution optimization system in a multi-chip package scenario, characterized in that: The system comprises: an acquisition module, configured to acquire temperature data of a plurality of chip units within a multi-chip package, timing margin data of a target timing path, and preset material thermal conductivity data of the multi-chip package, wherein the target timing path is a signal path having a maximum signal propagation delay within the multi-chip package, and the material thermal conductivity data includes a corresponding relationship between the thermal conductivity of the material within the multi-chip package and the temperature; a construction module, configured to construct a thermal resistance network model based on the temperature data, the material thermal conductivity data, and the package physical structure data of the multi-chip package by determining the thermal resistance values ​​of the chip units and the packaging material units in the package physical structure data, wherein the thermal resistance network model includes network nodes representing the chip units or the packaging material units, edges representing the existence of heat transfer channels between the network nodes, and multiple heat conduction paths formed by the network nodes and the edges, including path thermal resistance values; A construction module is specifically used to extract multiple discrete physical regions representing chip units and packaging material units from the packaging physical structure data, construct each of the discrete physical regions into a network node, and construct edges representing the existence of heat transfer channels between the network nodes based on the spatial adjacency relationship of the discrete physical regions in the packaging physical structure data, thereby obtaining topological connection information; based on each of the network nodes, extract the temperature value of the network node corresponding to each chip unit from the temperature data, and calculate the temperature value of the network node corresponding to each packaging material unit based on the topological connection information and the temperature value of the network node corresponding to each chip unit; based on the temperature value of each network node, determine the material thermal conductivity value of each network node using the corresponding relationship between the material thermal conductivity and temperature in the material thermal conductivity data; calculate the node thermal resistance value of each network node using the material thermal conductivity value and the geometric size information of the discrete physical region corresponding to the network node of the packaging physical structure data; determine multiple heat conduction paths based on the topological connection information, and calculate the path thermal resistance value of each heat conduction path based on the node thermal resistance value of the network node in each heat conduction path, thereby obtaining the thermal resistance network model; a determining module, configured to determine a target chip unit among the chip units passed through in the target timing path using the temperature data when the timing margin in the timing margin data is less than a preset margin threshold; The determination module is further configured to determine a first control voltage and a first control impedance of the target chip unit, and a second control impedance of a unit chip adjacent to the target chip unit, based on a difference between the timing margin and the preset margin threshold, and a path thermal resistance value of a heat conduction path associated with the target chip unit in the thermal resistance network model; A control module is used to control the supply voltage and output impedance of the power supply unit corresponding to the target chip unit through the first control voltage and the first control impedance, and to control the output impedance of the power supply unit corresponding to the unit chip adjacent to the target chip unit through the second control impedance.

8. An electronic device, characterized in that: The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the power management thermal distribution optimization method in the multi-chip packaging scenario according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the power management thermal distribution optimization method in a multi-chip package scenario according to any one of claims 1 to 6.

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