Memory controller, memory device including same, and method of operating same

Abstract

A memory controller, a method of operating the memory controller, and a memory device are disclosed. The memory controller replaces a bad block of a given super block with a reserved block, and updates a bad block bitmap. The memory controller includes a superblock classifier configured to determine the given superblock as a free block or a reserved block according to a number of bad blocks of the given superblock. When the given super block is determined to be a free block, the memory controller inserts an identifier of the given super block into the free block list.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0019173 filed on February 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Embodiments relate to a memory device and a method of operating the memory device. Background Art

[0004] Flash memory, as a non-volatile memory, can retain stored data even when power is interrupted. Storage devices including flash memory, such as solid-state drives (SSDs), and memory cards are becoming widely used. Furthermore, due to recent rapid technological developments, the amount of data to be processed is increasing. Consequently, demand for high-performance and high-reliability storage devices is increasing.

[0005] In a storage device, a reserved area refers to an area allocated for replacing bad blocks. In order to improve the performance of the storage device, a technology for efficiently managing the reserved area is required. Summary of the Invention

[0006] Embodiments provide for efficient management of reserved areas of storage devices.

[0007] A storage device is provided herein, comprising: a non-volatile memory comprising a first plurality of super blocks each comprising a plurality of memory blocks; and a memory controller configured to determine that a first super block, one of the first plurality of super blocks, comprises at least one initial bad block, replace the at least one initial bad block with at least one reserved block, and update a bad block bitmap based on the at least one initial bad block, wherein the memory controller comprises a super block classifier configured to determine whether the first super block is a free block or a reserved block based on the number of at least one initial bad blocks of the first super block based on the bad block bitmap, and insert the first super block into a free block list based on the determination that the first super block is a free block, wherein the free block list identifies a second plurality of super blocks, and the first plurality of super blocks comprises the second plurality of super blocks.

[0008] Also provided herein is a method for operating a memory controller, the method comprising: determining that a first super block includes at least one initial bad block, the first super block being one of a first plurality of super blocks each including a plurality of memory blocks; replacing the at least one initial bad block with at least one reserved block; updating a bad block bitmap based on the at least one initial bad block; determining whether the first super block is a free block or a reserved block based on a number of the at least one initial bad blocks of the first super block based on the bad block bitmap; and inserting an identifier of the first super block into a free block list based on the determination that the first super block is a free block, wherein the free block list identifies a second plurality of super blocks, and the first plurality of super blocks includes the second plurality of super blocks.

[0009] Also provided herein is a storage device comprising: a non-volatile memory comprising a first plurality of super blocks each comprising a plurality of memory blocks; and a memory controller configured to determine whether a first super block, one of the first plurality of super blocks, comprises at least one initial bad block, and replace the at least one initial bad block with at least one reserved block, wherein the memory controller comprises: a super block classifier configured to determine the first super block as a free block and insert the first super block into a free block list based on the number of at least one initial bad blocks of the first super block being less than or equal to a preset K, K being an integer greater than or equal to 1, wherein the free block list identifies a second plurality of super blocks, and the first plurality of super blocks comprises the second plurality of super blocks, and the super block allocator is configured to allocate the first super block for writing in response to a write command. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a storage system according to an embodiment;

[0012] Figure 2 is a block diagram illustrating a memory controller according to an embodiment;

[0013] Figure 3 is a block diagram illustrating a memory controller according to an embodiment;

[0014] Figure 4 is a diagram illustrating that a memory controller according to an embodiment increases an over-provisioning (OP) area by using a reserved area;

[0015] Figures 5A to 5C is a diagram illustrating the operation of a memory controller for classifying super blocks;

[0016] Figure 5D It is shown for Figure 5B and Figure 5CSchematic diagram of the BBB of the super block;

[0017] Figure 6 is a diagram showing a structure of an NVM according to an embodiment;

[0018] Figure 7 is a diagram illustrating a free block list used by a memory controller according to an embodiment;

[0019] Figure 8 is a diagram illustrating a method of operating a storage device according to an embodiment;

[0020] Figure 9 is a diagram illustrating a method of operating a storage device according to an embodiment;

[0021] Figure 10 is a diagram illustrating a method of operating a storage device according to an embodiment;

[0022] Figure 11A and Figure 11B is a diagram illustrating a method of operating a storage device according to an embodiment;

[0023] Figure 12 is a diagram illustrating a method of operating a memory controller according to an embodiment;

[0024] Figure 13 is a block diagram showing an example in which a storage device according to an embodiment is applied to an SSD system; and

[0025] Figure 14 is a diagram illustrating a computing system according to an embodiment. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram illustrating a storage system 10 according to an embodiment.

[0027] Reference Figure 1 , the storage system 10 may include a storage device 100 and a host 200, and the storage device 100 may include a memory controller 110 and a non-volatile memory (NVM)

[0028] 120. The memory controller 110 may include a super block classifier (SBC) and a super block allocator (SBA). Hereinafter, for convenience, the memory controller 110 may also be referred to as a "controller." Each of the SBC and the SBA may be implemented by custom hardware, a processor that executes instructions from memory, or a combination of hardware and software.

[0029] The host 200 can communicate with the storage device 100 through various interfaces. For example, the host 200 can be implemented as an application processor (AP) or a system on a chip (SoC). In addition, for example, the host 200 can be implemented as an integrated circuit, a motherboard, or a database server, but is not limited thereto. The host 200 can send a write request or a read request to the storage device 100, and the storage device 100 can write data to the NVM 120 or read data from the NVM 120 in response to the write request or the read request.

[0030] NVM 120 may include multiple memory groups 121. Multiple memory groups 121 may each include multiple super memory blocks (hereinafter referred to as "super blocks"). Multiple super blocks may each include multiple memory blocks (hereinafter referred to as "blocks"), multiple blocks may each include multiple pages, and multiple pages may each include multiple memory cells. For example, super blocks and / or blocks may be erase units, and pages may be write / read units. According to some embodiments, multiple memory groups 121 may include multiple memory chips, multiple dies, or multiple planes. According to embodiments, NVM 120 may include a flash memory device, for example, a NAND flash memory device. However, embodiments are not limited thereto, and NVM 120 may include a resistive memory device such as resistive RAM (ReRAM), phase change RAM (PRAM), and magnetic RAM (MRAM).

[0031] although Figure 1 The bad block bitmap (BBB) is shown to be included in the memory controller 110, but the embodiment is not limited thereto, and according to some embodiments, the BBB may be loaded into a memory chip (e.g., a dynamic random access memory (DRAM) chip (e.g., Figure 3 130)).

[0032] The storage system 10 may be implemented as, for example, a personal computer (PC), a data server, a network attached storage, an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device may be a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book device, a wearable device, etc.

[0033] According to some embodiments, the storage device 100 may be an internal memory embedded in an electronic device. For example, the storage device 100 may be a solid-state drive (SSD), an embedded universal flash storage (UFS) memory device, or an embedded multimedia card (eMMC). According to some embodiments, the storage device 100 may be an external memory that can be attached to and detached from the electronic device. For example, the storage device 100 may be a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, or a memory stick.

[0034] According to an embodiment, a storage device 100 includes: an NVM 120 including a plurality of Super Blocks (also referred to as a first plurality of Super Blocks) having a plurality of memory blocks; and a memory controller 110 configured to determine whether a first Super Block, one of the plurality of Super Blocks, includes at least one initial bad block, replace the at least one initial bad block with at least one reserved block, and update a back-buffered block (BBB) based on the at least one initial bad block. Memory controller 110 may include a storage controller (SBC) configured to determine, based on the BBB, whether the first Super Block is a free block or a reserved block according to the number of at least one initial bad blocks in the first Super Block, and insert the first Super Block into a free block list when the first Super Block is determined to be a free block. For example, inserting the first Super Block may include inserting an identifier of the first Super Block into a free block list, where the free block list contains identifiers of a second plurality of Super Blocks. In an example, the second plurality of Super Blocks is a subset of the first plurality of Super Blocks (the first plurality of Super Blocks being all Super Blocks in NVM 120). When the number of initial bad blocks in the first Super Block is greater than N (N is an integer greater than or equal to 0), the SBC may determine the first Super Block as a reserved block. When the number of initial bad blocks in a first Super Block is equal to or less than a preset N (N is an integer greater than or equal to 0), the SBC may determine the first Super Block as a free block. Memory controller 110 may further include an SBA configured to allocate a Super Block for writing in response to a write command. The SBA may be configured to select a first Super Block from the Super Blocks included in the Free Block List, determine whether the selected first Super Block is a normal Super Block based on the BBB, and allocate the first Super Block for writing if the first Super Block is a normal Super Block. The SBA may select a first Super Block as a Partial Super Block from the Super Blocks included in the Free Block List. The SBA may be configured to allocate the selected first Super Block for writing when the write command has a second type from among a first type and a second type. The first type may correspond to a host command received from a host, and the second type may correspond to an internal command based on an internal operation of the memory controller. The internal operation may include garbage collection. When writing, memory controller 110 may exclude at least one initial bad block of the allocated first Super Block (partial Super Block) from data partitioning. The SBA may be configured to allocate a first Super Block for writing when a write command has a first type from among the first type and the second type and the number of free blocks included in the free block list is less than M (M is a positive integer). When the write command has the first type and the number of free blocks included in the free block list is greater than or equal to M, the SBA may reselect a Super Block from among the Super Blocks included in the free block list for writing. For example, the number M of free blocks for allocation in the free block list may be the sum of a critical number of free blocks for garbage collection triggering and the number of partial Super Blocks included in the free block list.

[0035] A storage device 100 according to an embodiment includes an NVM 120 including a plurality of Super Blocks having a plurality of memory blocks, and a memory controller 110 configured to check initial bad blocks of a first Super Block, one of the plurality of Super Blocks, and replace at least one of the initial bad blocks with at least one reserved block. Memory controller 110 may include an SBC configured to, when the number of at least one initial bad blocks of the first Super Block is equal to or less than a preset K (K is an integer greater than or equal to 1), determine the first Super Block as a free block and insert the first Super Block into a free block list; and an SBA configured to allocate the first Super Block for writing in response to a write command. The SBA may be configured to, in response to the write command, select a second Super Block, one of the Super Blocks in the free block list, determine whether at least one of the conditions for allocating the second Super Block is satisfied, and allocate the second Super Block for writing if the at least one condition is satisfied. The conditions may include a first condition that the second Super Block is a Normal Super Block, a second condition that the write command has the second type from among the first type and the second type, and a third condition that the number of Super Blocks included in the Free Block List is less than M. When none of the above-stated conditions is met, the SBA may select a third Super Block that is any one of the Super Blocks in the Free Block List in response to the write command. The third Super Block may be different from the second Super Block.

[0036] The storage device 100 according to an embodiment may use a reserved area for a storage space.

[0037] The memory device 100 according to the embodiment may use a portion of the reserved area as an over-provisioning (OP) area.

[0038] The memory device 100 according to the embodiment may improve random write performance by using a reserved area.

[0039] Figure 2 FIG. 1 is a block diagram showing a memory controller according to an embodiment. Figure 1 describe Figure 2 , and the same description as that given above may be omitted.

[0040] Refer to it together Figure 1 and Figure 2 , the memory controller 110 may include a processor 111, a memory 112, a host interface 113, and an NVM interface 114 that may communicate with each other through a bus 115. The processor 111 may include a central processing unit or a microprocessor and may control the overall operation of the memory controller 110. According to an embodiment, the processor 111 may be implemented as a multi-core processor, for example, a dual-core processor or a quad-core processor.

[0041] The memory 112 operates under the control of the processor 111 and can be used as an operating memory, a buffer memory, a cache memory, etc. For example, the memory 112 can be implemented with a volatile memory such as DRAM and SRAM or a non-volatile memory such as PRAM and flash memory. For example, the memory 112 can store a flash translation layer (FTL) code that can be executed by the processor 111. For example, when the storage device 100 is started, the FTL code can be loaded from the NVM 120 to the memory 112.

[0042] The SBC, SBA, and BBB may be loaded into the memory 112. The SBC and SBA may be implemented in firmware or software and may be loaded into the memory 112. However, the embodiment is not limited thereto, and according to some embodiments, the SBC and SBA may be implemented in hardware and may be arranged outside the memory 112.

[0043] The host interface 113 may provide an interface between the host 200 and the memory controller 110. For example, the host interface 113 may provide an interface based on a universal serial bus (USB), MMC, PCI Express (PCI-E), AT attachment (ATA), serial AT attachment (SATA), parallel AT attachment (PATA), small computer system interface (SCSI), serial attached SCSI (SAS), enhanced small disk interface (ESDI), and integrated drive electronics (IDE).

[0044] The NVM interface 114 may provide an interface between the memory controller 110 and the NVM 120. For example, metadata (such as a BBB and a mapping table), write data, and read data may be transmitted and received between the memory controller 110 and the NVM 120 through the NVM interface 114. In an embodiment, the number of NVM interfaces 114 may correspond to the number of NVM chips included in the memory device 100 or the number of channels between the memory controller 110 and the NVM 120.

[0045] Figure 3 is a block diagram illustrating a memory controller 110 ′ according to an embodiment.

[0046] Reference Figure 3 , the memory controller 110′ may include a processor 111, a memory 112a, a host interface 113, an NVM interface 114, and a DRAM interface 116 that can communicate with each other through a bus 115. Figure 2The present invention corresponds to a modified example of the memory controller 110 of FIG. 1 , and thus, descriptions identical to those already described above will be omitted. According to this embodiment, the BBB can be loaded into the DRAM 130. The DRAM interface 116 can provide an interface between the memory controller 110′ and the DRAM 130. For example, some data included in the BBB can be transmitted and received between the memory controller 110′ and the DRAM 130 via the DRAM interface 116.

[0047] Figure 4 is a diagram illustrating that a memory controller according to an embodiment increases an OP area by using a reserved area.

[0048] You can refer to Figure 1 describe Figure 4 . Reference Figure 4 , metadata is generated by the storage system 10 to manage user data or data of the NVM 120. The metadata may include mapping information for converting a logical address into a physical address to access data stored in the NVM 120.

[0049] The free block area may refer to an area including free blocks. Free blocks may be included in a free block list and may refer to blocks that do not store valid user data. For example, a free block may be a block that has completed an erase operation and a block that can be used again for a programming operation. Valid user data may be stored in a free block. In addition, a free block may be used to perform garbage collection to store valid user data. User space may refer to an area of free blocks that store valid user data. The OP area may refer to a temporary working space of the memory controller 110 for writing valid data. For example, the OP area may include free blocks for performing garbage collection. In other words, when a free block is used for garbage collection, the corresponding free block may be classified as a free block of the OP area. In another example, when a free block temporarily stores data to be written to a DRAM, the corresponding free block may be classified as a free block of the OP area.

[0050] The reserved area may refer to an area used for block replacement of a bad block. The reserved block is a block of the reserved area and may refer to a block predefined for block replacement of a bad block.

[0051] The memory controller 110 according to an embodiment may use blocks that meet specific conditions among blocks in the reserved area for garbage collection. Therefore, the reserved area may be reduced and the OP area may be increased.

[0052] Figures 5A to 5C is a diagram illustrating the operation of a memory controller for classifying super blocks. Figure 5D It is shown for Figure 5B and Figure 5C Schematic diagram of the BBB of the super block.

[0053] You can refer to Figure 1 describe 5A to 5D .although Figures 5A to 5C A super block for four planes is shown for ease of explanation, but embodiments are not limited thereto and a super block may include blocks of various numbers of planes, dies, and chips. 5A to 5D The metadata area is omitted in the , but the super block may be included in the metadata area.

[0054] Reference Figure 5A , Super Blocks 1 to 109 each include blocks included in four planes (i.e., Plane 0 to Plane 3). In detail, Super Block 1 is a set of blocks located in the first row among the blocks included in Plane 0 to Plane 3, and Super Block 109 is a set of blocks located in the 109th row among the blocks included in Plane 0 to Plane 3. Super Blocks 104 to 109 are Super Blocks defined as blocks in the Reserved Area.

[0055] Figure 5A The following illustrates a case where a block in plane 2 among the blocks in super block 101 is a bad block. For example, among the blocks in super block 101, a block in plane 2 may be an initial bad block. An initial bad block may refer to a bad block formed during the manufacturing process of NVM 120. Memory controller 110 may detect an initial bad block during the formatting process. Memory controller 110 may replace the initial bad block with a block in a reserved area. For example, memory controller 110 may modify the mapping relationship between the logical page number (LPN) and the physical page number (PPN). Memory controller 110 may replace the initial bad block with a block in plane 2 among the blocks in super block 109.

[0056] The memory controller 110 may replace the initial bad blocks with blocks in the reserved area. Figure 5B 1 is a diagram showing that the initial bad blocks are replaced with blocks in the reserved area. The bad blocks in the free block area are replaced with some blocks in the super blocks 104 to 109. Figure 5B , the replaced blocks are marked as bad. A Super Block that includes bad blocks (such as Super Blocks 104 to 109) can be called a partial Super Block. A Super Block that does not include bad blocks (such as Super Block 1) can be called a normal Super Block.

[0057] Reference Figure 5C When certain conditions are met, the memory controller 110 may use some Super Blocks in the Reserved Area as Free Blocks for writing valid user data. In other words, the memory controller 110 may insert the Partial Super Blocks in the Reserved Area that meet certain conditions into the Free Block List. The Partial Super Blocks inserted into the Free Block List may be referred to as Special Partial Super Blocks.

[0058] For example, the memory controller 110 can use a Super Block (Super Blocks 104 to 108) with two or fewer bad blocks as a free block for writing valid user data. The memory controller 110 can use the Super Block (Super Blocks 104 to 108) for garbage collection for writing valid user data. For ease of explanation, an example of using a Super Block (Super Blocks 104 to 108) with two or fewer bad blocks as a free block has been described. However, the embodiment is not limited thereto, and the number of bad blocks used to switch a portion of the Super Block of the reserved area to a free block can vary.

[0059] Figure 5D It is shown for Figure 5B and Figure 5C 1. The BBB may have a meta structure with Super Blocks as units. Meta area 400 may include a Super Block Number (SBN). Super Block 104 has a SBN of 104, and the SBNs of Super Blocks 105 to 109 may also be determined based on this. Figure 5D Show Figure 5B and Figure 5C The memory controller 110 may use the BBB to determine whether a particular Super Block is a normal Super Block or a partial Super Block. For example, the memory controller 110 may determine that the BBB for Super Block 104 is not 0 and determine that Super Block 104 is a partial Super Block.

[0060] Figure 6 is a diagram illustrating a structure of an NVM according to an embodiment.

[0061] You can refer to Figure 1 describe Figure 6 . Reference Figure 6 NVM 120 may include multiple chips Chip 1 to Chip k. k is a positive integer. Each of the multiple chips Chip 1 to Chip k may include multiple blocks. Chip 1 may include blocks Blk_11 to Blk_1N, chip Chip 2 may include blocks Blk_21 to Blk_2N, and chip Chip k may include blocks Blk_K1 to Blk_KN. N is a positive integer.

[0062] Super block 1 is a set of blocks Blk_11 to Blk_K1 of multiple chips Chip 1 to Chip k. Super block 2 is a set of blocks Blk_12 to Blk_K2 of multiple chips Chip 1 to Chip k. Super block N is a set of blocks Blk_1N to Blk_KN of multiple chips Chip 1 to Chip k. The flash translation layer (FTL) of the memory controller 110 can perform parallel processing (interleaving) based on super blocks (i.e., super blocks 1 to N) to write data to multiple chips Chip 1 to Chip k at the same time. Blocks with the same plane offset classified for each channel and each storage body can become a super block. When a data write request is received, the FTL can request data write to all chips at the same time in units of super blocks.

[0063] Figure 7 is a diagram illustrating a free block list used by a memory controller according to an embodiment.

[0064] You can refer to Figure 1 describe Figure 7 . A free block may be included in a free block list and may refer to a block that does not store valid user data. The free block list may include normal super blocks without bad blocks, and may include partial super blocks that each include at least one bad block. The partial super blocks included in the free block list may be referred to as special partial super blocks.

[0065] Figure 8 is a diagram illustrating a method of operating a memory device according to an embodiment.

[0066] You can refer to Figure 1 describe Figure 8 . Reference Figure 8 In operation S101, the memory controller 110 may replace an initial bad block with a reserved block. For example, after performing FTL formatting, the memory controller 110 may determine an initial bad block and replace the initial bad block with a reserved block.

[0067] In operation S103, the memory controller 110 may update the BBB. The memory controller 110 may mark the reserved block replacing the initial bad block as bad in the BBB of the super block of the reserved area.

[0068] In operation S105, the memory controller 110 may determine the number of replaced blocks (initial bad blocks) among the blocks included in the Super Block of the reserved area. The memory controller 110 may determine whether the number of replaced blocks among the blocks included in the Super Block is equal to or less than N. N is a positive integer. For example, the memory controller 110 may determine whether the number of replaced blocks among the blocks included in the Super Block is equal to or less than N based on the BBB.

[0069] In operation S107 , when the number of replaced blocks is equal to or less than N, the memory controller 110 may insert the super block of the reserved area into the free block list.

[0070] In operation S109, when the number of blocks to be replaced is greater than N, the memory controller 110 may maintain the area of the super block as a reserved area. The number N of bad blocks included in the super block (which serves as a criterion for inserting the super block of the reserved area into the free block list) may be predetermined. For example, the value of N may be determined based on the addressing overhead of reading a replacement block of a given plane from the reserved area to replace a bad block in the given plane in the free area.

[0071] Figure 9 is a diagram illustrating a method of operating a memory device according to an embodiment.

[0072] You can refer to Figure 1 and Figure 8 describe Figure 9 . Can be omitted and have been referred to above Figure 8 The same description as given. Figure 9 In operation S201, the memory controller 110 may replace the initial bad block with a reserved block. In operation S203, the memory controller 110 may update the BBB. In operation S205, the memory controller 110 may determine the number of replaced blocks (initial bad blocks) among the blocks included in the super block of the reserved area. In operation S207, when the number of replaced blocks is equal to or less than N, the memory controller 110 may insert the super block of the reserved area into the free block list. In operation S209, when the number of replaced blocks is greater than N, the memory controller 110 may determine the corresponding area of the super block as a reserved area. The proportion X% of bad blocks included in the super block (which serves as a criterion for inserting the super block of the reserved area into the free block list) may be predetermined. For example, X% may be predetermined to be within the range of 12.5% to 15%.

[0073] Figure 10 is a diagram illustrating a method of operating a memory device according to an embodiment.

[0074] You can refer to Figure 1 describe Figure 10 . Reference Figure 10 In operation S301, the memory controller 110 may select a super block from among super blocks in a free block list in response to a write command.

[0075] In operation S303, the memory controller 110 may determine whether at least one of the conditions for allocating the selected Super Block for writing is satisfied. The conditions for allocating the selected Super Block for writing may include when the selected Super Block is a Normal Super Block, when the type of the write command is the second type, and when the number of free blocks included in the free block list is less than M.

[0076] In operation S305, if at least one of the conditions for allocating the selected Super Block is satisfied, the memory controller 110 may allocate the selected Super Block for writing. When none of the conditions for allocating the selected Super Block is satisfied, the memory controller 110 may reselect a Super Block from the Super Blocks in the Free Block List in response to the write command. The memory controller 110 may then repeat the above-stated process to allocate a Super Block for writing.

[0077] Figure 11A and Figure 11B is a diagram illustrating a method of operating a memory device according to an embodiment.

[0078] You can refer to Figure 1 describe Figure 11A and Figure 11B . Reference Figure 11A In operation S401, the memory controller 110 may select a super block from among super blocks in a free block list in response to a write command.

[0079] In operation S403, memory controller 110 may determine whether the selected Super Block is a Normal Super Block. For example, memory controller 110 may determine whether the selected Super Block is a Normal Super Block based on the BBB of the selected Super Block. In other words, when the value of the BBB of the selected Super Block is 0, memory controller 110 may determine that the selected Super Block is a Normal Super Block. When the value of the BBB of the selected Super Block is not 0, memory controller 110 may determine that the selected Super Block is a Partial Super Block. In operation S405, when the selected Super Block is a Normal Super Block, memory controller 110 may allocate the selected Super Block (Normal Super Block) for writing.

[0080] In operation S407, when the selected Super Block is not a normal Super Block (i.e., a Partial Super Block), the memory controller 110 may determine the type of the write command. The memory controller 110 may determine whether the write command is of the first type or the second type. The first type may correspond to a host command received from the host. The second type may correspond to an internal command based on an internal operation of the memory controller. In operation S409, when the write command is of the second type, the memory controller 110 may allocate the selected Super Block (Partial Super Block) for writing.

[0081] In operation S411, when the write command is of the first type, the memory controller 110 may determine whether the number of free blocks included in the free block list is less than M. M is a positive integer. When the number of free blocks included in the free block list is greater than or equal to M, the memory controller 110 may reselect one of the super blocks included in the free block list for writing. In other words, the memory controller 110 may restart the operation from operation S401. When the number of free blocks included in the free block list is less than M (M is a positive integer), in operation S409, the memory controller 110 may allocate the selected super block (partial super block) for writing. According to an embodiment, the number M of free blocks in the free block list (which is the criterion for allocating the selected super block for writing) may be the sum of the "critical number of free blocks for garbage collection triggering" and the "number of partial super blocks included in the free block list."

[0082] Reference Figure 11B In operation S409, the memory controller 110 may allocate the selected Super Block (Partial Super Block) for writing. In operation S411, the memory controller 110 may exclude bad blocks when writing. Specifically, the memory controller 110 may exclude at least one initial bad block of the allocated Partial Super Block from the data partition and perform writing in response to the write command.

[0083] Figure 12 is a diagram illustrating a method of operating a memory controller according to an embodiment.

[0084] You can refer to Figure 1 describe Figure 12 In operation S501, the memory controller 110 may check whether a first super block, which is one of a plurality of super blocks each including a plurality of memory blocks, includes at least one initial bad block. In operation S503, the memory controller 110 may replace the at least one initial bad block with at least one reserved block. In operation S505, the memory controller 110 may update a BBB based on the at least one initial bad block.

[0085] In operation S507, the memory controller 110 may determine the first Super Block as a free block or a reserved block based on the number of at least one initial bad blocks in the first Super Block. For example, the memory controller 110 may determine the first Super Block as a free block or a reserved block based on the number of at least one initial bad blocks in the first Super Block based on the BBB. When the number of initial bad blocks in the first Super Block is greater than N (N is an integer greater than or equal to 0), the memory controller 110 may determine the first Super Block as a reserved block. When the number of initial bad blocks in the first Super Block is equal to or less than a preset N (N is an integer greater than or equal to 0), the memory controller 110 may determine the first Super Block as a free block. In operation S509, when the memory controller 110 determines that the first Super Block is a free block, the memory controller 110 may insert the first Super Block into a free block list.

[0086] When the first Super Block includes an initial bad block, it can be considered that the Reserved Area is switched to the OP Area. The memory controller 110 can allocate a Super Block for writing based on the switched OP Area. In other words, the memory controller 110 can allocate a Super Block for writing in response to a write command. The operation of the memory controller 110 allocating a Super Block will be described below.

[0087] Memory controller 110 may select a first Super Block from the Super Blocks included in the Free Block List. Memory controller 110 may also determine whether the selected first Super Block is a Normal Super Block based on the BBB. For example, if the first Super Block is a Normal Super Block, memory controller 110 may allocate the first Super Block for writing without considering other conditions.

[0088] In addition, when the write command has the second type from among the first type and the second type, the memory controller 110 may allocate the selected first Super Block for writing. The first type may correspond to a host command received from the host 200, and the second type may correspond to an internal command based on an internal operation of the memory controller 110. For example, the memory controller 110 may determine whether the selected first Super Block is a partial Super Block. When the first Super Block is a partial Super Block, the memory controller 110 may determine whether the write command has the first type or the second type. When the write command has the second type, the memory controller 110 may allocate the first Super Block for writing. In this case, the first Super Block may be allocated for garbage collection in response to the internal command. However, at least one initial bad block of the first Super Block may be excluded from the data partition. In other words, the memory controller 110 may exclude at least one initial bad block of the first Super Block from the data partition and perform the write.

[0089] When a write command is of the first type from among the first type and the second type and the number of free blocks included in the free block list is less than M (M is a positive integer), memory controller 110 may allocate the first Super Block for writing. For example, memory controller 110 may determine whether the selected first Super Block is a partial Super Block. When the first Super Block is a partial Super Block, memory controller 110 may determine whether the write command is of the first type or the second type. When the write command is of the first type, memory controller 110 may determine the number of free blocks included in the free block list. When the number of free blocks included in the free block list is less than M (M is a positive integer), memory controller 110 may allocate the selected first Super Block for writing. However, at least one initial bad block of the first Super Block may be excluded from the data partition. In other words, memory controller 110 may exclude at least one initial bad block of the first Super Block from the data partition and perform the write. The reference number M of free blocks included in the free block list for allocation may be a preset value. For example, the reference number M of free blocks for allocation in the free block list may be the sum of the critical number of free blocks for garbage collection triggering and the number of partial super blocks included in the free block list.

[0090] When the write command is of the first type and the number of free blocks included in the free block list is greater than or equal to M, the memory controller 110 may reselect a Super Block from the Super Blocks included in the free block list. For example, the memory controller 110 may determine whether the selected first Super Block is a partial Super Block. When the first Super Block is a partial Super Block, the memory controller 110 may determine whether the write command is of the first type or the second type. When the number of free blocks included in the free block list is greater than or equal to M (M is a positive integer), the memory controller 110 may reselect a Super Block from the Super Blocks included in the free block list.

[0091] Figure 13 is a block diagram illustrating an example in which a storage device according to an embodiment is applied to an SSD system.

[0092] Reference Figure 13 , the SSD system 300 may include a host 310 and an SSD 320. The SSD 320 exchanges signals with the host 310 through a signal connector and receives power through a power connector. The SSD 320 may include an SSD controller 321, an auxiliary power supply device 322, and memory devices 323_1 to 323_n. The memory devices 323_1 to 323_n may be vertically stacked NAND flash memory devices. Here, the SSD 320 may be configured as described above with reference to FIG. Figures 1 to 12In other words, the memory devices 323_1 to 323_n provided in the SSD 320 may each include a plurality of super blocks. Among the plurality of super blocks in each of the memory devices 323_1 to 323_n, the super blocks may be selected according to the Figures 1 to 12 The method shown in manages super blocks in the reserved area.

[0093] Figure 14 is a diagram illustrating a computing system 1000 according to an embodiment.

[0094] Reference Figure 14 , the computing system 1000 may include a memory system 1100, a processor 1200, a RAM 1300, an input / output device 1400, and a power supply unit 1500. Meanwhile, although Figure 14 Although not shown in the figure, the computing system 1000 may also include ports capable of communicating with a video card, a sound card, a memory card, a USB device, or other electronic devices. The computing system 1000 may be implemented as a personal computer, or may be implemented as a portable electronic device such as a laptop computer, a mobile phone, a personal digital assistant (PDA), and a camera.

[0095] The processor 1200 may perform a specific calculation or task. According to an embodiment, the processor 1200 may be a microprocessor or a central processing unit (CPU). The processor 1200 may communicate with the RAM 1300, the input / output device 1400, and the memory system 1100 through a bus 1600 such as an address bus, a control bus, and a data bus. At this time, the memory system 1100 may communicate with the RAM 1300, the input / output device 1400, and the memory system 1100. Figures 1 to 12 According to an embodiment, the processor 1200 may also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0096] The RAM 1300 can store data required for the operation of the computing system 1000. For example, the RAM 1300 can be implemented using DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and / or MRAM. The input / output device 1400 can include input units such as a keyboard, a keypad, and a mouse, and output units such as a printer and a display. The power supply unit 1500 can supply the operating voltage required for the operation of the computing system 1000.

[0097] Various changes in form and details may be made in the embodiments without departing from the spirit and scope of the appended claims.

Claims

1. A storage device comprising: a non-volatile memory comprising a first plurality of super blocks each comprising a plurality of memory blocks; as well as a memory controller configured to determine that a first super block, one of the first plurality of super blocks, includes at least one initial bad block, replace the at least one initial bad block with at least one reserved block, and update a bad block bitmap based on the at least one initial bad block, wherein the memory controller includes a super block classifier configured to determine whether the first super block is a free block or a reserved block based on the bad block bitmap according to the number of the at least one initial bad blocks of the first super block, and insert the first super block into a free block list based on the first super block being determined as the free block, wherein the free block list identifies a second plurality of super blocks, and the first plurality of super blocks includes the second plurality of super blocks.

2. The storage device according to claim 1, wherein The super block classifier is further configured to determine the first super block as the reserved block based on the number of initial bad blocks of the first super block being greater than N, where N is an integer greater than 0.

3. The storage device according to claim 1, wherein The super block classifier is further configured to determine the first super block as the free block based on the number of initial bad blocks of the first super block being less than or equal to a preset N, where N is an integer greater than 0. The storage device according to claim 1 , wherein: The memory controller includes a Super Block allocator configured to allocate the first Super Block for writing in response to a write command, and Wherein, the super block allocator is further configured to select the first super block from the second plurality of super blocks identified in the free block list, determine whether the first super block is a normal super block based on the bad block bitmap, and allocate the first super block for the write based on the first super block being the normal super block. The storage device according to claim 1 , wherein: The memory controller includes a Super Block allocator configured to allocate the first Super Block for writing in response to a write command, Wherein, the super block allocator is further configured to: selecting said first Super Block as a partial Super Block from among said second plurality of Super Blocks identified in said Free Block List, and allocating the first Super Block for writing based on the write command being of the second type from among the first type and the second type, wherein the first type corresponds to a host command received from a host, and The second type corresponds to an internal command based on an internal operation of the memory controller. The storage device according to claim 5 , wherein: The memory controller is further configured to exclude the at least one initial bad block of the first super block from data partitioning during the writing.

7. The storage device according to claim 5, wherein: The internal operations include garbage collection.

8. The storage device according to claim 1, wherein The memory controller further includes a Super Block allocator configured to allocate the first Super Block for writing in response to a write command, Wherein, the super block allocator is further configured to: selecting the first Super Block as a partial Super Block from among the second plurality of Super Blocks identified in the Free Block List; allocating the first Super Block for writing based on the write command being of the first type from among a first type and a second type and the number of free blocks identified in the free block list being less than M, M being a positive integer; and Based on the write command having the first type and the number of free blocks identified in the free block list being greater than or equal to M, reselect one from the second plurality of super blocks identified in the free block list for the write, wherein the first type corresponds to a host command received from a host, and wherein the second type corresponds to an internal command based on an internal operation of the memory controller.

9. The storage device according to claim 8, wherein: The memory controller is further configured to exclude the at least one initial bad block of the first super block from data partitioning during the writing.

10. The storage device according to claim 8, wherein M is the sum of the critical number of free blocks for garbage collection triggering and the number of partial super blocks identified in the free block list.

11. A method of operating a memory controller, the method comprising: determining that a first Super Block includes at least one initial bad block, the first Super Block being one of a first plurality of Super Blocks each including a plurality of memory blocks; replacing the at least one initial bad block with at least one reserved block; updating a bad block bitmap based on the at least one initial bad block; determining whether the first super block is a free block or a reserved block based on the number of the at least one initial bad block of the first super block based on the bad block bitmap; as well as Based on the first Super Block being determined to be the Free Block, an identifier of the first Super Block is inserted into a Free Block List, wherein the Free Block List identifies a second plurality of Super Blocks, and wherein the first plurality of Super Blocks includes the second plurality of Super Blocks.

12. The method according to claim 11, further comprising: Based on the number of initial bad blocks of the first super block being greater than N, the first super block is determined as the reserved block, where N is an integer greater than 0.

13. The method according to claim 11, further comprising: Based on the fact that the number of initial bad blocks of the first super block is less than or equal to a preset N, the first super block is determined as the free block, where N is an integer greater than 0.

14. The method according to claim 11, further comprising: In response to a write command, allocating the first Super Block for writing, wherein allocating the first Super Block comprises: selecting the first super block from among the second plurality of super blocks identified in the free block list; determining whether the first super block is a normal super block based on the bad block bitmap; and The first Super Block is allocated for the write based on the first Super Block being the normal Super Block.

15. The method according to claim 11, further comprising: allocating the first super block for writing in response to a write command, Wherein, allocating the super block includes: selecting said first Super Block as a Partial Super Block from among said second plurality of Super Blocks identified in said Free Block List; and allocating the first Super Block for writing based on the write command being of the second type from among the first type and the second type, wherein the first type corresponds to a host command received from a host, and The second type corresponds to an internal command based on an internal operation of the memory controller.

16. The method according to claim 15, further comprising: The at least one initial bad block of the first super block is excluded from data partitioning and the writing is performed.

17. The method according to claim 15, wherein: The internal operations include garbage collection.

18. A storage device comprising: a non-volatile memory comprising a first plurality of super blocks each comprising a plurality of memory blocks; as well as a memory controller configured to determine whether a first Super Block, one of the first plurality of Super Blocks, includes at least one initial bad block and replace the at least one initial bad block with at least one reserved block, Wherein, the memory controller includes: a Super Block classifier configured to determine the first Super Block as a free block and insert the first Super Block into a free block list based on the number of the at least one initial bad blocks of the first Super Block being less than or equal to a preset K, K being an integer greater than or equal to 1, wherein the free block list identifies a second plurality of Super Blocks and the first plurality of Super Blocks includes the second plurality of Super Blocks, and A Super Block Allocator is configured to allocate the first Super Block for writing in response to a write command.

19. The storage device according to claim 18, wherein The Super Block allocator is further configured to: select a second Super Block from among the second plurality of Super Blocks identified in the Free Block List, determine whether at least one condition from among the conditions for allocating the second Super Block is satisfied, and allocate the second Super Block for the write based on satisfying the at least one condition, and The conditions include a first condition, a second condition and a third condition, wherein the first condition is that the second super block is a normal super block, the second condition is that the write command has the second type from the first type and the second type, and the third condition is that the number of super blocks identified in the free block list is less than M.

20. The storage device according to claim 19, wherein The Super Block allocator is further configured to, in response to the write command, select a third Super Block that is any one of the second plurality of Super Blocks identified in the Free Block List based on none of the conditions being satisfied, and The third super block is different from the second super block.

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