Remote processing method and remote processing system of accelerator card and accelerator card

Abstract

The invention provides a remote processing method and a remote processing system of an accelerator card and the accelerator card, and relates to the technical field of communication. The accelerator card comprises a main logic processing chip and a control management chip. The method comprises the steps that an operating system PS of the control management chip obtains a target data packet transmitted by debugging equipment; the PS of the control management chip processes the target data packet to realize a first operation; the first operation comprises at least one of the following items: remote upgrading of the main logic processing chip; remote online debugging of the main logic processing chip is carried out; remote upgrading of a programmable logic unit PL of the control management chip; remote online debugging of the PL of the control management chip; the remote upgrading and remote online debugging functions of the acceleration card facilitate program maintenance, problem analysis and troubleshooting of the acceleration card among multiple stations, and the test verification efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a remote processing method, a remote processing system, and an accelerator card. Background Art

[0002] The accelerator card is a key component of the baseband unit (BBU). Its main functions include accelerating data processing and providing high-performance real-time protocol data processing. It serves as a bridge between the past and the future. On the one hand, it can leverage the parallel processing and multitasking advantages of the field programmable gate array (FPGA), reducing the burden on the central processing unit (CPU) and achieving system acceleration. On the other hand, it has fronthaul capabilities, conducting baseband data communications through optical ports and active antenna units (AAUs).

[0003] Currently, most accelerator cards are customized products that require adaptation to the solutions recommended by different chip manufacturers. They only process some of the physical layer data of the baseband protocol and have limited data processing capabilities. Therefore, the overall BBU implementation has certain limitations. Current accelerator card upgrades primarily utilize PCIe (PCIe Express) links. The host transfers the accelerator card version image to be upgraded via the PCIe link to the accelerator card's upgrade device. The accelerator card then performs the firmware upgrade according to the existing upgrade solution.

[0004] In summary, existing accelerator card upgrade solutions mainly rely on the PCIe transmission link on the host side and do not support remote upgrades and remote online debugging based on the Internet. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a remote processing method, a remote processing system and an accelerator card to solve the problem that existing solutions do not support remote upgrade and remote online debugging of accelerator cards based on the Internet.

[0006] To solve the above problems, an embodiment of the present application provides a remote processing method for an accelerator card, wherein the accelerator card includes a main logic processing chip and a control management chip. The method includes: The operating system PS of the control management chip obtains the target data packet transmitted by the debugging device; The PS of the control management chip processes the target data packet to implement a first operation, wherein the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

[0007] In some embodiments of the present application, the target data packet includes at least one of the following: The bit package file of the main logic processing chip that needs to be remotely upgraded; The debugging data packet of the main logic processing chip; The PL bit package file of the control management chip that needs to be remotely upgraded; The debug data packet of the PL of the control management chip.

[0008] In some embodiments of the present application, the operating system PS of the control management chip obtains the target data packet transmitted by the debugging device, including: The PS of the control management chip obtains the target data packet transmitted by the debugging device through the public Internet; wherein, the debugging device is connected to the public Internet through Ethernet, and the public Internet is connected to the PS of the control management chip.

[0009] In some embodiments of the present application, the PS of the control management chip includes: a data protocol parsing module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridging conversion module; The PS of the control management chip processes the target data packet to implement a first operation, including: The data protocol parsing module parses the target data packet and transmits the parsed target data packet to the encryption and decryption module; The encryption and decryption module decrypts the data packets transmitted by the data protocol analysis module; The remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement the first operation.

[0010] In some embodiments of the present application, the remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement remote upgrade of the main logic processing chip, including: The remote upgrade debugging module stores the decrypted data in a cache, and converts the data in the cache into a serial peripheral interface SPI signal through the data bridge conversion module; The SPI signal is transmitted to the main logic processing chip through the configuration interface of the main logic processing chip to upgrade the configuration of the main logic processing chip.

[0011] In some embodiments of the present application, the remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement remote online debugging of the main logic processing chip, including: The remote upgrade debugging module connects the decrypted data to the Joint Test Working Group JTAG interface of the main logic processing chip through the data bridge conversion module, and the debugging device performs remote online debugging on the main logic processing chip through the JTAG interface in the software interface.

[0012] In some embodiments of the present application, the remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement the remote upgrade of the PL, including: The remote upgrade and debugging module stores the decrypted data in a flash memory and upgrades the PL configuration according to the data in the flash memory.

[0013] In some embodiments of the present application, the remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement remote online debugging of the PL, including: The remote upgrade debugging module connects the decrypted data to the monitoring interface of the PL through the data bridge conversion module, and the debugging device performs remote online debugging on the PL through the monitoring interface in the software interface.

[0014] In some embodiments of the present application, the method further comprises: In the event of an upgrade problem or error, the remote upgrade debugging module obtains error information and transmits the error information to the encryption and decryption module; After the encryption and decryption module encrypts the error information, the encrypted information is transmitted to the data protocol analysis module; The data protocol parsing module transmits the encrypted information to the debugging device via the public Internet.

[0015] In some embodiments of the present application, the method further comprises: In the event of a problem or error during the upgrade, the remote upgrade debugging module restores the main logic processing chip and / or the PL to the version before the upgrade.

[0016] In some embodiments of the present application, the data bridge conversion module further includes: a PL local online debugging data bridge module, and the PL local online debugging data bridge module is used to implement local online debugging of the PL.

[0017] The embodiment of the present application further provides a remote processing system, the remote processing system comprising: a debugging device and a baseband processing unit (BBU); the BBU comprising: an accelerator card, and a central processing unit (CPU) connected to the accelerator card via a PCIe interface; The debugging device is connected to the acceleration card via the public Internet; the acceleration card includes a main logic processing chip and a control management chip; The operating system PS of the control management chip can obtain a target data packet transmitted by the debugging device to implement a first operation; the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

[0018] In some embodiments of the present application, the debugging device is connected to the public Internet via Ethernet, and the public Internet is connected to the PS of the control management chip.

[0019] In some embodiments of the present application, the PS of the control management chip includes: a data protocol parsing module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridging conversion module; The data protocol parsing module is used to parse data packets transmitted on the public Internet and transmit the parsed data to the encryption and decryption module; and / or is used to receive data processed by the encryption and decryption module, package it, and transmit it to the public Internet; The encryption and decryption module is used to perform encryption and decryption processing on received data packets; The remote upgrade debugging module and the data bridging conversion module are used to process the data transmitted by the encryption and decryption module to implement the first operation.

[0020] An embodiment of the present application further provides an accelerator card, the accelerator card including a main logic processing chip and a control management chip, the operating system PS of the control management chip including a processor and a transceiver, the transceiver receiving and sending data under the control of the processor, and the processor being configured to perform the following operations: Get the target data packet transmitted by the debugging device; Process the target data packet to implement a first operation, wherein the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

[0021] In some embodiments of the present application, the target data packet includes at least one of the following: The bit package file of the main logic processing chip that needs to be remotely upgraded; The debugging data packet of the main logic processing chip; The PL bit package file of the control management chip that needs to be remotely upgraded; The debug data packet of the PL of the control management chip.

[0022] In some embodiments of the present application, the processor is further configured to perform the following operations: Obtain the target data packet transmitted by the debugging device through the public Internet; wherein, the debugging device is connected to the public Internet through Ethernet, and the public Internet is connected to the PS of the control management chip.

[0023] In some embodiments of the present application, the PS of the control management chip includes: a data protocol parsing module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridging conversion module; The data protocol parsing module is used to parse the target data packet and transmit the parsed target data packet to the encryption and decryption module; The encryption and decryption module is used to decrypt the data packets transmitted by the data protocol analysis module; The remote upgrade debugging module and the data bridging conversion module are used to process the decrypted data packet to implement the first operation.

[0024] In some embodiments of the present application, the processor is further configured to perform the following operations: Get error information if there are any problems or errors during the upgrade; After encrypting the error information, the encrypted information is transmitted to the data protocol parsing module; The encrypted information is transmitted to the debugging device via the public Internet.

[0025] In some embodiments of the present application, the processor is further configured to perform the following operations: In case of problems or errors during the upgrade, the main logic processing chip and / or the PL are restored to the version before the upgrade.

[0026] An embodiment of the present application also provides an accelerator card, comprising a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, the remote processing method of the accelerator card as described above is implemented.

[0027] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the remote processing method of the accelerator card as described above.

[0028] An embodiment of the present application further provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the steps of the remote processing method of the accelerator card as described above.

[0029] The above technical solution of the present application has at least the following beneficial effects: In the remote processing method, remote processing system and accelerator card of the embodiment of the present application, the accelerator card includes a main logic processing chip and a control management chip. According to the test verification requirements of the accelerator card, the PS of the control management chip runs the data module application required for the remote upgrade and remote online debugging of the main logic processing chip and PL, and realizes data transmission and protocol conversion between each module, and is connected to the chip through a dedicated interface to realize the following functions: remote upgrade of the main logic processing chip; remote online debugging of the main logic processing chip; remote upgrade of the programmable logic unit PL of the control management chip; remote online debugging of the PL of the control management chip. The remote upgrade and remote online debugging functions of the accelerator card facilitate program maintenance, problem analysis and troubleshooting of the accelerator card between multiple stations, and improve the efficiency of test verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 One of the structural diagrams of the remote processing system provided in an embodiment of the present application is shown; Figure 2 A schematic diagram showing the structure of a BBU provided in an embodiment of the present application; Figure 3 A second structural diagram of the remote processing system provided in an embodiment of the present application is shown; Figure 4 A flowchart showing the steps of a remote processing method of an accelerator card provided in an embodiment of the present application; Figure 5 An example diagram of the remote processing flow of the accelerator card provided in an embodiment of the present application; Figure 6 An example diagram showing the remote upgrade of the main logic processing chip provided in an embodiment of the present application; Figure 7 An example diagram showing remote online debugging of the main logic processing chip provided by an embodiment of the present application; Figure 8 An example diagram showing remote upgrade of the programmable logic unit PL of the control management chip provided in an embodiment of the present application; Figure 9An example diagram showing remote online debugging of the PL of the control management chip provided in an embodiment of the present application; Figure 10 A schematic diagram showing the structure of an accelerator card provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0031] In order to make the technical problems, technical solutions and advantages to be solved by this application clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0032] like Figure 1 As shown, an embodiment of the present application provides a remote processing system, which includes: a debugging device 1 and one or more baseband processing units (Building Baseband Units, BBUs) (such as BBU1, BBUn); the BBU (such as BBU1) includes: an accelerator card 7, and a central processing unit CPU 9 connected to the accelerator card 7 via a PCIe interface; The debugging device 1 is connected to the accelerator card 7 via the public Internet 2. The accelerator card 7 includes a main logic processing chip 6 (such as a field programmable gate array (FPGA)) and a control management chip 3 (such as a system on chip (SOC)). The operating system PS of the control management chip can obtain a target data packet transmitted by the debugging device to implement a first operation; the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

[0033] Optionally, the debugging device is connected to the public Internet via Ethernet, and the public Internet is connected to the PS of the control management chip.

[0034] Optionally, a debugging device (also known as a PC debugging machine) is responsible for overall system upgrade and debugging. Connected via Gigabit Ethernet and the public internet, it distributes upgrade programs for all accelerator cards, as well as transmits and displays debugging-related data.

[0035] Optionally, the public Internet connects BBU base station units in different areas mainly according to the destination IP, and bridges the data channel between the debugging device and the BBU base station unit.

[0036] Optionally, the BBU adopts a general server architecture, including a CPU (X86) and an acceleration card of a PCIe architecture. The server CPU 9 processes part of the High-PHY data, and the acceleration card 7 processes part of the baseband data of the Low-PHY. The CPU 9 and the acceleration card 7 exchange data through a high-speed PCIe interface. The acceleration card provides high-performance real-time protocol data processing, plays a role in connecting the past and the future, and adopts a heterogeneous architecture of SOC+FPGA. In order to facilitate the remote upgrade and remote online debugging of the acceleration card, the SOC implements the control and management functions, receives control instructions for remote upgrades and remote online debugging on the public Internet, performs TCP / IP network port protocol conversion, and after passing through the encryption and decryption module, such as Figure 2 As shown, the data corresponding to remote upgrade and remote online debugging are transmitted to the remote debugging module, the debugging bridge module and the FPGA configuration program respectively, and finally the remote upgrade and remote online debugging functions of the accelerator card are realized, including the remote upgrade and remote online debugging of FPGA 6 and the remote upgrade and remote online debugging of SOC PL 5.

[0037] In at least one embodiment of the present application, Figure 3 As shown, the PS of the control management chip includes: a data protocol parsing module, an encryption and decryption module, a remote upgrade and debugging module (also known as a remote upgrade and remote online debugging module), and a data bridge conversion module; The data protocol parsing module is used to parse data packets transmitted on the public Internet and transmit the parsed data to the encryption and decryption module; and / or is used to receive data processed by the encryption and decryption module, package it, and transmit it to the public Internet; The encryption and decryption module is used to perform encryption and decryption processing on received data packets; The remote upgrade debugging module and the data bridging conversion module are used to process the data transmitted by the encryption and decryption module to implement the first operation.

[0038] In some embodiments, as Figure 3 As shown, the debugging device runs the data packaging and unpacking module. After receiving the remote upgrade or remote online debugging requirements of the SOC PL and FPGA, it performs data processing in two directions: the data packaging and unpacking module packages the data packets to be transmitted according to the TCP / IP protocol and transmits them to the public Internet after packaging is completed; or the data packaging and unpacking module receives the data packets transmitted by the public Internet, performs unpacking processing, and displays the corresponding data on the debugging device.

[0039] In some embodiments, as Figure 3As shown, the data packet transmission module of the public Internet transmits the data packets required by the data packaging and depacketization module according to the destination IP of the accelerator card for remote upgrade or remote online debugging, thereby realizing the network intercommunication function between the debugging device and accelerator cards in different regions.

[0040] In some embodiments, as Figure 3 As shown, the SOC PS of the accelerator card runs a data protocol parsing module, which implements two functions: parsing data packets transmitted on the public Internet and transmitting the parsed data to the encryption and decryption module for subsequent processing; or receiving data processed by the encryption and decryption module, and assembling it into packets according to the TCP / IP protocol for transmission to the public Internet.

[0041] In some embodiments, as Figure 3 As shown in the figure, the accelerator card's SOC PS runs the encryption and decryption module, ensuring reliable and secure transmission of BBU base station unit data. This module encrypts and decrypts data packets related to remote upgrades and remote online debugging, ensuring the correctness of remote upgrade versions and the accuracy of remote debugging data.

[0042] In some embodiments, as Figure 3 As shown in the figure, the SOC PS of the accelerator card runs the remote upgrade and remote online debugging module, which contains four applications: SOC PL remote online debugging module (XVC Server2), SOC PL remote upgrade module (FPGA manager), FPGA remote online debugging module (XVC Server1), and FPGA remote upgrade module (FPGA configuration program).

[0043] The SOC PL remote debugging module implements protocol conversion between debugging data packets and debugging interfaces. It can convert real-time monitoring and control data streams into debugging data packets and transmit them to the encryption and decryption module, ultimately realizing the function of remote online debugging of the PC debugging machine. The FPGA remote online debugging module implements protocol conversion between debugging data packets and debugging interfaces. It can convert real-time monitoring and control data streams into debugging data packets and transmit them to the encryption and decryption module, ultimately realizing the function of remote online debugging on a PC debugger. At the same time, the module can also provide the function of online downloading of FPGA program versions. The SOC PL remote upgrade module receives and stores SOC PL upgrade data packets and performs remote online upgrades. If any problems or errors occur during the upgrade, the remote upgrade module collects relevant error information and transmits it to the PC debugger, while restoring the last correct version to ensure the normal operation of the accelerator card. Among them, the FPGA remote upgrade module receives and stores the FPGA upgrade data packets and performs remote online upgrades. If any problems or errors occur during the upgrade, the remote upgrade module summarizes the relevant error information and transmits it to the PC debugger, while restoring the last correct version to ensure the normal operation of the accelerator card.

[0044] In some embodiments, as Figure 3 As shown in the figure, the SOC PL of the accelerator card runs a data bridge conversion module, which contains four applications: FPGA remote online debugging data bridge module (Debug Bridge1), SOC PL remote online debugging data bridge module (Debug Bridge2), SOC PL local online debugging data bridge module (Debug Bridge3), and FPGA remote upgrade data bridge module.

[0045] Among them, the FPGA remote online debugging data bridge module realizes the signal bridge between debugging data and JTAG signals. The JTAG signals are connected to the dedicated pins of the FPGA, realizing online debugging of the FPGA and online version loading; the SOC PL remote online debugging data bridge module realizes the signal bridge between debugging data and PL internal monitoring signals, realizing online debugging of PL monitoring signals; the SOC PL local online debugging data bridge module realizes the coexistence of remote debugging and local debugging signals, ensuring that the local JTAG debugging signal can be connected normally; the FPGA remote upgrade data bridge module realizes the signal bridge conversion between debugging data and SPI configuration signals, realizing the function of remote upgrade and solidification of debugging data through the dedicated SPI configuration interface of the FPGA.

[0046] In summary, the accelerator card hardware circuit in this embodiment uses an FPGA + SOC heterogeneous architecture solution. The SOC's PS is connected to the Internet via a Gigabit Ethernet interface and exchanges data with the debugging PC. The accelerator card's FPGA implements Low-PHY data processing and exchanges data with the x86 server's CPU via a PCIe interface, completing all data processing for the BBU base station.

[0047] like Figure 4 As shown, an embodiment of the present application provides a remote processing method for an accelerator card, wherein the accelerator card includes a main logic processing chip (such as a field programmable gate array (FPGA)) and a control management chip (such as a system on chip (SOC)). The method includes: Step 101: The operating system (Processing System, PS) of the control management chip obtains a target data packet transmitted by a debugging device; Step 102: The PS of the control management chip processes the target data packet to implement a first operation; the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit (PL) of the control management chip; The control manages remote online debugging of the PL of the chip.

[0048] For example, Figure 5 As shown, the accelerator card includes a main logic processing chip (FPGA) and a control management chip (SOC). Based on the accelerator card's test and verification requirements, the SOC (PS) runs the data module applications required for remote upgrades and online debugging of the FPGA and program logic (PL). Each module implements data transmission and protocol conversion between them and connects to the chip via a dedicated interface, enabling the following functions: remote upgrades of the main logic processing chip (FPGA); remote online debugging of the main logic processing chip (FPGA); remote upgrades of the control management chip (SOC) and online debugging of the control management chip (SOC). The accelerator card's remote upgrade and online debugging capabilities facilitate program maintenance, problem analysis, and troubleshooting of the accelerator card across multiple sites, improving test and verification efficiency.

[0049] In at least one embodiment of the present application, the target data packet includes at least one of the following: The bit package file of the main logic processing chip that needs to be remotely upgraded; The debugging data packet of the main logic processing chip; The PL bit package file of the control management chip that needs to be remotely upgraded; The debug data packet of the PL of the control management chip.

[0050] In at least one embodiment of the present application, the operating system PS of the control management chip obtains the target data packet transmitted by the debugging device, including: The PS of the control management chip obtains the target data packet transmitted by the debugging device through the public Internet; wherein, the debugging device is connected to the public Internet through Ethernet, and the public Internet is connected to the PS of the control management chip.

[0051] In at least one embodiment of the present application, the PS of the control management chip includes: a data protocol parsing module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridging conversion module; The PS of the control management chip processes the target data packet to implement a first operation, including: The data protocol parsing module parses the target data packet and transmits the parsed target data packet to the encryption and decryption module; The encryption and decryption module decrypts the data packets transmitted by the data protocol analysis module; The remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement the first operation.

[0052] In other words, after the upgrade data packets and debug data packets are converted through multiple modules and protocols, they are transmitted between the PC debugger and the accelerator card upgrade and debug module.

[0053] In one implementation of the present application, the remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement remote upgrade of the main logic processing chip, including: The remote upgrade debugging module stores the decrypted data in a cache, and converts the data in the cache into a serial peripheral interface SPI signal through the data bridge conversion module; The SPI signal is transmitted to the main logic processing chip through the configuration interface of the main logic processing chip to upgrade the configuration of the main logic processing chip.

[0054] Optionally, in the event of a problem or error during the upgrade, the remote upgrade debugging module obtains error information and transmits the error information to the encryption and decryption module; After the encryption and decryption module encrypts the error information, the encrypted information is transmitted to the data protocol analysis module; The data protocol parsing module transmits the encrypted information to the debugging device via the public Internet.

[0055] Optionally, the method further includes: In the event of a problem or error during the upgrade, the remote upgrade debugging module restores the main logic processing chip to the version before the upgrade.

[0056] For example, the FPGA dedicated interface includes two parts: the JTAG interface and the configuration interface. The JTAG interface is used for online debugging of the FPGA, and the configuration interface is used to configure the bit program after the FPGA is powered on. Figure 6The figure shows the flowchart of FPGA remote upgrade. The PC's data packaging and unpacking module transmits the FPGA bit file that needs to be remotely upgraded to the BBU accelerator card unit via the public Internet data packet transmission module. After receiving the corresponding bit package file, the PS data protocol parsing module of the SOC performs protocol parsing of the network message. After passing through the encryption and decryption module, the FPGA remote upgrade module temporarily stores the bit file in the cache and converts the temporarily stored bit file into SPI interface data through the FPGA remote upgrade data bridge module. The FPGA is upgraded and configured using the SPI configuration signal. After the configuration is complete, the FPGA is tested for successful configuration. If the configuration is successful, the remote upgrade ends. If the configuration fails, the error information is summarized and fed back to the PC, and the FPGA configuration process is repeated.

[0057] In another implementation of the present application, the remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement remote online debugging of the main logic processing chip, including: The remote upgrade debugging module connects the decrypted data to the Joint Test Working Group JTAG interface of the main logic processing chip through the data bridge conversion module, and the debugging device performs remote online debugging on the main logic processing chip through the JTAG interface in the software interface.

[0058] For example, the FPGA-specific interface consists of a JTAG interface and a configuration interface. The JTAG interface is used for online debugging of the FPGA, while the configuration interface is used to configure the bit program after the FPGA is powered on. The FPGA remote online debugging module and the FPGA remote online debugging data bridge module implement protocol conversion between Gigabit Ethernet and JTAG. The SoC PL connects to the FPGA's JTAG interface via EMIO, enabling online debugging of the FPGA. Figure 7 The figure shows the FPGA online debugging flow chart. Open the remote debugging software on the PC. The data assembly and decompression module prepares the debug data packet and connects to the FPGA of the target accelerator card by entering the IP address and port number. The debug data packet is transmitted to the accelerator card's PS data protocol parsing module via the data packet transmission module. The parsed data is then transmitted to the FPGA remote online debugging module via the encryption and decryption module. This data is then connected to the FPGA's dedicated JTAG pins through the FPGA remote online debugging data bridge module. After the debugging interface appears on the PC, download the FPGA test program and add the debug monitoring program. Use the software interface to perform online debugging, analyze data, and troubleshoot the FPGA. After debugging is complete, restart the accelerator card to resume normal operation.

[0059] In another implementation of the present application, the remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement the remote upgrade of the PL, including: The remote upgrade and debugging module stores the decrypted data in a flash memory and upgrades the PL configuration according to the data in the flash memory.

[0060] Optionally, the method further includes: In the event of an upgrade problem or error, the remote upgrade debugging module obtains error information and transmits the error information to the encryption and decryption module; After the encryption and decryption module encrypts the error information, the encrypted information is transmitted to the data protocol analysis module; The data protocol parsing module transmits the encrypted information to the debugging device via the public Internet.

[0061] Optionally, the method further includes: In the event of an upgrade problem or error, the remote upgrade debugging module restores the PL to the version before the upgrade.

[0062] For example, Figure 8 The figure shows a flowchart for a remote SOC PL upgrade. The PC's data assembly and decompression module transmits the SOC PL bit file to be remotely upgraded to the BBU accelerator card via the public internet data packet transmission module. After receiving the corresponding bit package file, the SOC's power supply (PS) uses the data protocol parsing module to parse the network message protocol. After passing through the encryption and decryption module, the bit file is stored in the eMMC. The PS runs the SOC PL remote upgrade module and uses the stored bit file to upgrade the PL configuration. After configuration is complete, the PS checks whether the SOC PL configuration is successful. If so, the remote upgrade is complete. If configuration fails, error information is collected and fed back to the PC, and the PL configuration process is repeated.

[0063] In another implementation of the present application, the remote upgrade debugging module and the data bridge conversion module process the decrypted data packet to implement remote online debugging of the PL, including: The remote upgrade debugging module connects the decrypted data to the monitoring interface of the PL through the data bridge conversion module, and the debugging device performs remote online debugging on the PL through the monitoring interface in the software interface.

[0064] For example, Figure 9The following diagram shows the SOC PL online debugging flow. The remote debugging software is opened on the PC. The data assembly and decompression module prepares the debug data packet. The target accelerator card's PL is connected by entering the IP address and port number. The debug data packet is then transmitted to the accelerator card's PS data protocol parsing module via the data packet transmission module. The parsed data is then transmitted to the PL remote online debugging module via the encryption and decryption module. This data is then connected to the PL's real-time monitoring and control data stream via the PL remote online debugging data bridge module. Once the debugging interface appears on the PC, the PL can be debugged online, data analyzed, and issues identified. After debugging is complete, the accelerator card is restarted to resume normal operation.

[0065] In at least one embodiment of the present application, the data bridge conversion module further includes: a PL local online debugging data bridge module, and the PL local online debugging data bridge module is used to implement local online debugging of the PL.

[0066] In summary, the embodiments of the present application propose to support remote upgrades and remote online debugging and hardware devices and methods based on TCP / IP networks, and at the same time support remote upgrades and remote online debugging of both SOC PL and FPGA chips, solving the problem that existing technical solutions cannot realize the function of online debugging, improving the efficiency of accelerator card testing and verification in the preliminary verification stage of the test network, and ensuring the normal and stable operation of the test network after it is put into operation.

[0067] like Figure 10 As shown, an embodiment of the present application further provides an accelerator card, which includes a main logic processing chip and a control management chip. The operating system PS of the control management chip includes a processor 300 and a transceiver 310. The transceiver 310 receives and sends data under the control of the processor 300. The processor 300 is used to perform the following operations: Get the target data packet transmitted by the debugging device; Process the target data packet to implement a first operation, wherein the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

[0068] In some embodiments of the present application, the target data packet includes at least one of the following: The bit package file of the main logic processing chip that needs to be remotely upgraded; The debugging data packet of the main logic processing chip; The PL bit package file of the control management chip that needs to be remotely upgraded; The debug data packet of the PL of the control management chip.

[0069] In some embodiments of the present application, the processor is further configured to perform the following operations: Obtain the target data packet transmitted by the debugging device through the public Internet; wherein, the debugging device is connected to the public Internet through Ethernet, and the public Internet is connected to the PS of the control management chip.

[0070] In some embodiments of the present application, the PS of the control management chip includes: a data protocol parsing module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridging conversion module; The data protocol parsing module is used to parse the target data packet and transmit the parsed target data packet to the encryption and decryption module; The encryption and decryption module is used to decrypt the data packets transmitted by the data protocol analysis module; The remote upgrade debugging module and the data bridging conversion module are used to process the decrypted data packet to implement the first operation.

[0071] In some embodiments of the present application, the processor is further configured to perform the following operations: Get error information if there are any problems or errors during the upgrade; After encrypting the error information, the encrypted information is transmitted to the data protocol parsing module; The encrypted information is transmitted to the debugging device via the public Internet.

[0072] In some embodiments of the present application, the processor is further configured to perform the following operations: In case of problems or errors during the upgrade, the main logic processing chip and / or the PL are restored to the version before the upgrade.

[0073] In the embodiment of the present application, the accelerator card includes a main logic processing chip and a control management chip. According to the test verification requirements of the accelerator card, the PS of the control management chip runs the data module application required for the remote upgrade and remote online debugging of the main logic processing chip and PL, and realizes data transmission and protocol conversion between each module, and is connected to the chip through a dedicated interface to realize the following functions: remote upgrade of the main logic processing chip; remote online debugging of the main logic processing chip; remote upgrade of the programmable logic unit PL of the control management chip; remote online debugging of the PL of the control management chip. The remote upgrade and remote online debugging functions of the accelerator card facilitate program maintenance, problem analysis and troubleshooting of the accelerator card between multiple stations, thereby improving the efficiency of test verification.

[0074] It should be noted that the accelerator card provided in the embodiment of the present application is an accelerator card that can execute the remote processing method of the above-mentioned accelerator card. All embodiments of the remote processing method of the above-mentioned accelerator card are applicable to the accelerator card and can achieve the same or similar beneficial effects, which will not be repeated here.

[0075] An embodiment of the present application also provides an accelerator card, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, each process in the embodiment of the remote processing method for the accelerator card as described above is implemented, and the same technical effect can be achieved. To avoid repetition, these processes will not be described here.

[0076] The present application also provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the program implements the various processes in the embodiment of the remote processing method for the accelerator card described above and achieves the same technical effect. To avoid repetition, the details are not described here. The computer-readable storage medium may be, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0077] An embodiment of the present application also provides a computer program product, including computer instructions. When the computer instructions are executed by a processor, the various processes of the embodiment of the remote processing method of the acceleration card described above are implemented, and the same technical effects can be achieved. To avoid repetition, they are not described here.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage and optical storage) containing computer-usable program code.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1means for performing functions specified in one or more processes and / or one or more blocks.

[0080] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable storage medium produce a paper product including an instruction device that implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing device to cause the computer or other programmable device to execute a series of operating steps to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0082] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A remote processing method for an accelerator card, characterized in that: The accelerator card includes a main logic processing chip and a control management chip, and the method includes: The operating system PS of the control management chip obtains the target data packet transmitted by the debugging device; The PS of the control management chip processes the target data packet to implement a first operation, wherein the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

2. The method according to claim 1, characterized in that The target data packet includes at least one of the following: The bit package file of the main logic processing chip that needs to be remotely upgraded; The debugging data packet of the main logic processing chip; The PL bit package file of the control management chip that needs to be remotely upgraded; The debug data packet of the PL of the control management chip.

3. The method according to claim 1 or 2, characterized in that The operating system PS of the control management chip obtains the target data packet transmitted by the debugging device, including: The PS of the control management chip obtains the target data packet transmitted by the debugging device through the public Internet; wherein, the debugging device is connected to the public Internet through Ethernet, and the public Internet is connected to the PS of the control management chip.

4. The method according to claim 1 or 2, characterized in that The PS of the control management chip includes: a data protocol analysis module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridge conversion module; The PS of the control management chip processes the target data packet to implement a first operation, including: The data protocol parsing module parses the target data packet and transmits the parsed target data packet to the encryption and decryption module; The encryption and decryption module decrypts the data packets transmitted by the data protocol analysis module; The remote upgrade debugging module and the data bridging conversion module process the decrypted data packet to implement the first operation.

5. The method according to claim 4, characterized in that The remote upgrade debugging module and the data bridging conversion module process the decrypted data packets to implement remote upgrade of the main logic processing chip, including: The remote upgrade debugging module stores the decrypted data in a cache, and converts the data in the cache into a serial peripheral interface SPI signal through the data bridge conversion module; The SPI signal is transmitted to the main logic processing chip through the configuration interface of the main logic processing chip to upgrade the configuration of the main logic processing chip.

6. The method according to claim 4, characterized in that The remote upgrade debugging module and the data bridging conversion module process the decrypted data packets to implement remote online debugging of the main logic processing chip, including: The remote upgrade debugging module connects the decrypted data to the Joint Test Working Group JTAG interface of the main logic processing chip through the data bridge conversion module, and the debugging device performs remote online debugging on the main logic processing chip through the JTAG interface in the software interface.

7. The method according to claim 4, characterized in that The remote upgrade debugging module and the data bridging conversion module process the decrypted data packets to implement the remote upgrade of the PL, including: The remote upgrade and debugging module stores the decrypted data in a flash memory and upgrades the PL configuration according to the data in the flash memory.

8. The method according to claim 4, characterized in that The remote upgrade debugging module and the data bridge conversion module process the decrypted data packets to implement remote online debugging of the PL, including: The remote upgrade debugging module connects the decrypted data to the monitoring interface of the PL through the data bridge conversion module, and the debugging device performs remote online debugging on the PL through the monitoring interface in the software interface.

9. The method according to claim 5 or 7, characterized in that The method further comprises: In the event of an upgrade problem or error, the remote upgrade debugging module obtains error information and transmits the error information to the encryption and decryption module; After the encryption and decryption module encrypts the error information, the encrypted information is transmitted to the data protocol analysis module; The data protocol parsing module transmits the encrypted information to the debugging device via the public Internet.

10. The method according to claim 9, characterized in that The method further comprises: In the event of a problem or error during the upgrade, the remote upgrade debugging module restores the main logic processing chip and / or the PL to the version before the upgrade.

11. The method according to claim 4, characterized in that The data bridge conversion module further includes: a PL local online debugging data bridge module, and the PL local online debugging data bridge module is used to implement local online debugging of the PL.

12. A remote processing system, characterized in that: The remote processing system includes: a debugging device and a baseband processing unit BBU; the BBU includes: an accelerator card, and a central processing unit CPU connected to the accelerator card via a PCIe interface; The debugging device is connected to the acceleration card via a public Internet of Things; the acceleration card includes a main logic processing chip and a control management chip; The operating system PS of the control management chip can obtain a target data packet transmitted by the debugging device to implement a first operation; the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

13. The system according to claim 12, wherein: The debugging device is connected to the public Internet via Ethernet, and the public Internet is connected to the PS of the control management chip.

14. The system according to claim 12, wherein: The PS of the control management chip includes: a data protocol analysis module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridge conversion module; The data protocol parsing module is used to parse data packets transmitted on the public Internet and transmit the parsed data to the encryption and decryption module; and / or is used to receive data processed by the encryption and decryption module, package it, and transmit it to the public Internet; The encryption and decryption module is used to perform encryption and decryption processing on received data packets; The remote upgrade debugging module and the data bridging conversion module are used to process the data transmitted by the encryption and decryption module to implement the first operation.

15. An accelerator card, comprising a main logic processing chip and a control management chip, wherein the operating system PS of the control management chip comprises a processor and a transceiver, wherein the transceiver receives and sends data under the control of the processor, characterized in that: The processor is configured to perform the following operations: Get the target data packet transmitted by the debugging device; Process the target data packet to implement a first operation, wherein the first operation includes at least one of the following: Remote upgrade of the main logic processing chip; Remote online debugging of the main logic processing chip; Remote upgrade of the programmable logic unit PL of the control management chip; The control manages remote online debugging of the PL of the chip.

16. The accelerator card according to claim 15, wherein: The target data packet includes at least one of the following: The bit package file of the main logic processing chip that needs to be remotely upgraded; The debugging data packet of the main logic processing chip; The PL bit package file of the control management chip that needs to be remotely upgraded; The debug data packet of the PL of the control management chip.

17. The accelerator card according to claim 15 or 16, characterized in that: The processor is further configured to perform the following operations: Obtain the target data packet transmitted by the debugging device through the public Internet; wherein, the debugging device is connected to the public Internet through Ethernet, and the public Internet is connected to the PS of the control management chip.

18. The accelerator card according to claim 15 or 16, characterized in that: The PS of the control management chip includes: a data protocol analysis module, an encryption and decryption module, a remote upgrade and debugging module, and a data bridge conversion module; The data protocol parsing module is used to parse the target data packet and transmit the parsed target data packet to the encryption and decryption module; The encryption and decryption module is used to decrypt the data packets transmitted by the data protocol analysis module; The remote upgrade debugging module and the data bridging conversion module are used to process the decrypted data packet to implement the first operation.

19. The accelerator card according to claim 18, wherein: The processor is further configured to perform the following operations: Get error information if there are any problems or errors during the upgrade; After encrypting the error information, the encrypted information is transmitted to the data protocol parsing module; The encrypted information is transmitted to the debugging device via the public Internet.

20. The accelerator card according to claim 19, wherein: The processor is further configured to perform the following operations: In case of problems or errors during the upgrade, the main logic processing chip and / or the PL are restored to the version before the upgrade.

21. An accelerator card comprising a memory, a processor, and a program stored in the memory and executable on the processor; characterized in that: When the processor executes the program, the remote processing method of the acceleration card according to any one of claims 1 to 11 is implemented.

22. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the remote processing method of the accelerator card are implemented.

23. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the steps of the remote processing method of the acceleration card according to any one of claims 1 to 11.

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