Chip testing method and system

Abstract

The invention discloses a chip testing method and system. The method comprises the steps that S100, a USB connection channel and an instruction control channel between a testing host and a chip to be tested are established; s200, the test host supplies power to the to-be-tested chip through the USB connection channel and identifies the to-be-tested chip; s300, the test host enumerates the hgic device name of the chip to be tested through the USB connection channel, if the hgic device name succeeds, the step S410 is executed, and otherwise, the step S420 is executed; s410, the test host sends test firmware to the to-be-tested chip through the USB connection channel and enters the step S500; s420, the test host controls the chip to be tested to enter a USB starting mode through the instruction control channel and returns to the step S300; and S500, testing the chip to be tested through the test firmware. According to the invention, the performance of the chip can be normally tested no matter whether the chip is empty or has application firmware, so that the test efficiency is greatly improved; and moreover, various USB starting modes are supported, the method is suitable for various chip states, and the flexibility and compatibility of chip testing are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a chip testing method and system. Background Art

[0002] Chip testing refers to the process of verifying the proper function of a chip after production, using a test host computer and pre-set test items. For example, in the case of RF chips, chip testing primarily involves testing and calibrating RF performance.

[0003] In the prior art, when performing chip testing, a test host (also called a test mainboard) is connected to the chip to be tested via a USB communication interface, the test firmware is transferred to the RAM of the chip to be tested via the USB interface, and then the test firmware is run and tested.

[0004] The existing technology has an obvious defect, which is mainly manifested in the following: during testing, the chip to be tested must be a blank chip, that is, there is no application firmware code in the flash memory, so that testing can be carried out; if the chip to be tested has already burned the application firmware, the USB will not be recognized and the test firmware cannot be transmitted, resulting in test failure.

[0005] Currently, when testing a chip that has already been programmed with application firmware, the flash code must be erased before testing. Clearly, existing chip testing methods suffer from poor compatibility and operational lockout, severely impacting test efficiency. Summary of the Invention

[0006] The present invention provides a chip testing method and system, aiming to improve chip testing efficiency. The technical solution for implementing the present invention is as follows:

[0007] In a first aspect, the present invention provides a chip testing method, comprising:

[0008] S100, establishing a USB connection channel and a command control channel between the test host and the chip under test;

[0009] S200: The test host supplies power to the chip under test through the USB connection channel and identifies the chip under test;

[0010] S300, the test host enumerates the hgic device name of the chip under test through the USB connection channel. If successful, it goes to step S410, otherwise it goes to step S420;

[0011] S410: The test host sends the test firmware to the chip under test through the USB connection channel and proceeds to step S500;

[0012] S420, the test host controls the chip under test to enter the USB boot mode through the command control channel and returns to step S300;

[0013] S500: Testing the chip to be tested using the test firmware.

[0014] As a preferred technical solution, before step S100, the USB startup mode and test parameter thresholds of the chip to be tested are configured on the test host by the host computer.

[0015] As a preferred technical solution, the configured USB startup mode of the chip to be tested includes at least two optional and mutually switchable USB startup modes.

[0016] As a preferred technical solution, the at least two USB startup modes include: a USB startup mode triggered by a serial port instruction and a USB startup mode triggered by an SPI instruction.

[0017] As a preferred technical solution, controlling the chip under test to enter USB boot mode in S420 specifically includes:

[0018] a. Receive the USB boot mode selection signal;

[0019] b. Generate a trigger command signal corresponding to the mode;

[0020] c. Sending the trigger command signal to the chip under test;

[0021] d. The chip under test enters the corresponding USB boot mode and returns to step S300.

[0022] As a preferred technical solution, controlling the chip under test to enter USB boot mode in S420 specifically includes:

[0023] A. Arrange at least two USB boot modes by priority.

[0024] B. Automatically generate the trigger command signal corresponding to the USB boot mode with the highest priority and send it to the chip under test;

[0025] C. Detect whether the chip under test enters the USB boot mode within a predetermined time. If yes, return to step S300; otherwise, go to step D.

[0026] D. Automatically generate a trigger command signal corresponding to the USB boot mode with a relatively lower priority and send it to the chip under test;

[0027] E. Detect whether the chip under test enters the USB boot mode within the predetermined time. If yes, return to step S300; otherwise, return to step D.

[0028] As a preferred technical solution, step S500 specifically includes: the test host sends firmware verification and firmware running commands to the chip under test through the USB connection channel, and the chip under test executes the test firmware after the verification is successful.

[0029] As a preferred technical solution, the chip to be tested is a radio frequency chip. When the test firmware is executed in step S500, the radio frequency performance of the radio frequency chip is first tested, and then the radio frequency parameters of the radio frequency chip are calibrated.

[0030] In a second aspect, the present invention provides a chip testing system, comprising a testing host and a chip to be tested; the testing host and the chip to be tested are connected via a USB connection channel and an instruction control channel; the testing host and the chip to be tested cooperate to execute the chip testing method described above.

[0031] As a preferred technical solution, the download pin of the test host is switchably connected to the debug serial port pin and SPI pin of the chip under test; or, the download pin of the test host is simultaneously connected to the debug serial port pin and SPI pin of the chip under test.

[0032] The chip testing method and system provided by the present invention can normally test the performance of the chip regardless of whether the chip is blank or has applied firmware, greatly improving the testing efficiency; and supports multiple USB boot modes, is applicable to various chip states, and improves the flexibility and compatibility of chip testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is an implementation block diagram of the chip testing system provided by an embodiment of the present invention.

[0035] Figure 2 This is another implementation block diagram of the chip testing system provided by an embodiment of the present invention.

[0036] Figure 3 This is the main flow chart of the chip testing method provided by an embodiment of the present invention.

[0037] Figure 4 This is a flowchart of a specific implementation method of controlling the chip under test to enter USB startup mode in the chip testing method provided by an embodiment of the present invention.

[0038] Figure 5This is a flowchart of another specific implementation method of controlling the chip under test to enter the USB startup mode in the chip testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] To make the technical solution of the present invention clearer and the technical advantages more apparent, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of the present invention.

[0040] For ease of explanation, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Furthermore, in the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "connect", "send", "receive", "transmit" and so on should be understood in a broad sense. For example, it can be directly connected or indirectly connected through an intermediate medium; it can be directly transmitted or indirectly transmitted through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0042] Combine Figure 1 As shown, the test system based on the chip testing method provided by the present invention is generally implemented by the cooperation of a host computer, a test host and a chip to be tested; wherein, the host computer and the test host are communicatively connected, and the mode and parameter configuration of the test host are performed in advance; the test host and the chip to be tested are connected through a line to realize the interaction of test data.

[0043] Combine Figure 2 As shown, in certain application scenarios, the test system on which the chip testing method provided by the present invention is based can also be implemented by the cooperation of a host computer, a test host, a test socket and a chip to be tested; wherein the configured test socket serves as an intermediate connecting device, which carries and positions the chip to be tested while facilitating the rapid connection of related circuits between the test host and the chip to be tested.

[0044] Combine Figure 3 As shown, as a basic implementation method, the chip testing method provided in this embodiment includes:

[0045] S100, establishing a USB connection channel and a command control channel between the test host and the chip under test;

[0046] S200: The test host supplies power to the chip under test through the USB connection channel and identifies the chip under test;

[0047] S300, the test host enumerates the hgic device name of the chip under test through the USB connection channel. If successful, it goes to step S410, otherwise it goes to step S420;

[0048] S410: The test host sends the test firmware to the chip under test through the USB connection channel and proceeds to step S500;

[0049] S420, the test host controls the chip under test to enter the USB boot mode through the command control channel and returns to step S300;

[0050] S500: Testing the chip to be tested using the test firmware.

[0051] Before step S100, the USB boot mode and test parameter thresholds of the chip under test are configured on the test host through the host computer. Specifically, the host computer is connected to the test host via a serial port. Taking the chip under test as an RF chip as an example, the configured parameters include RF performance parameter thresholds, frequency deviation power calibration thresholds, and other parameters. In addition, the configured USB boot mode of the chip under test includes at least two optional USB boot modes, and the at least two optional USB boot modes can be switched between each other.

[0052] In step S100, the test host and the chip under test are connected via a USB interface, establishing a USB connection channel. Simultaneously, the test host's download pins (dat / clk) are connected to the chip under test's serial port pins (tx / rx) and / or input / output pins (e.g., fixed pins PA8 / PA9) via DuPont cables to establish a command control channel for USB boot mode command control. The command control method is determined based on the actual application scenario.

[0053] In this embodiment, at least two USB boot modes include: a USB boot mode triggered by a serial port command and a USB boot mode triggered by an SPI command. In the serial port command trigger mode, USB boot is triggered by sending the command AT+USB_BOOT=1 through the serial port of the chip under test; in the SPI command trigger mode, USB boot is triggered by sending an SPI timing instruction code through a fixed pin. If configured for the serial port command mode, the test host's download pins dat / clk are connected to the debug serial port pins TX / RX of the chip under test. SDK development for this application solution requires adding a default serial port command AT+USB_BOOT=1 to enable the chip to enter USB boot mode. If configured for the SPI command mode, the test host's download pins dat / clk are connected to the preset fixed pins PA8 / PA9 of the chip under test.

[0054] In step S300, the test host successfully enumerates the hgic device name of the chip under test through the USB connection channel to determine whether the current state of the chip under test is an empty chip state. If it is an empty chip state, the test host directly sends the test firmware segments to the RAM of the chip under test through the USB connection channel (i.e., step S410) and tests the chip under test (i.e., step S500). If it is not an empty chip (there is already application firmware in the chip under test), the test host controls the chip under test to enter USB boot mode through the command control channel (i.e., step S420). After enumerating the hgic device name of the chip under test, the test firmware is transferred to the chip under test through USB and tested (i.e., step S500). The USB sends firmware verification and firmware run commands to the chip under test. After the chip under test successfully verifies, the test firmware is executed.

[0055] See also Figure 4 As shown, as a feasible implementation method, controlling the chip under test to enter the USB boot mode in step S420 specifically includes:

[0056] a. Receive the USB boot mode selection signal;

[0057] b. Generate a trigger command signal corresponding to the mode;

[0058] c. Sending the trigger command signal to the chip under test;

[0059] d. The chip under test enters the corresponding USB boot mode and returns to step S300.

[0060] See also Figure 5 As shown, as another feasible implementation, controlling the chip under test to enter the USB boot mode in step S420 specifically includes:

[0061] A. Arrange at least two USB boot modes by priority.

[0062] B. Automatically generate the trigger command signal corresponding to the USB boot mode with the highest priority and send it to the chip under test;

[0063] C. Detect whether the chip under test enters the USB boot mode within a predetermined time. If yes, return to step S300; otherwise, go to step D.

[0064] D. Automatically generate a trigger command signal corresponding to the USB boot mode with a relatively lower priority and send it to the chip under test;

[0065] E. Detect whether the chip under test enters the USB boot mode within the predetermined time. If yes, return to step S300; otherwise, return to step D.

[0066] Furthermore, step S500 specifically includes: the test host sends a firmware verification and firmware execution command to the chip under test via the USB connection channel, and the chip under test executes the test firmware after the verification is successful. Specifically, when the chip under test is a RF chip, when executing the test firmware in step S500, the RF performance of the RF chip is first tested, and then the RF parameters of the RF chip are calibrated.

[0067] Combine Figure 1 and Figure 2 As shown, the chip testing system provided in this embodiment includes a test host and a chip under test; the test host and the chip under test are connected via a USB connection channel and a command control channel; the test host and the chip under test cooperate to perform the chip testing method described above. The download pin of the test host is switchably connected to the debug serial port pin and SPI pin of the chip under test; or the download pin of the test host is simultaneously connected to the debug serial port pin and SPI pin of the chip under test.

[0068] The chip testing method and system provided in the above embodiment can normally test the performance of the chip regardless of whether the chip is blank or has applied firmware, thereby improving test efficiency; and supports multiple USB boot modes, is applicable to various chip states, and improves the flexibility and compatibility of chip testing.

[0069] The above disclosure is merely a preferred embodiment of the present invention and certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A chip testing method, characterized in that: include: S100, establishing a USB connection channel and a command control channel between the test host and the chip under test; S200: The test host supplies power to the chip under test through the USB connection channel and identifies the chip under test; S300, the test host enumerates the hgic device name of the chip under test through the USB connection channel. If successful, it goes to step S410, otherwise it goes to step S420; S410: The test host sends the test firmware to the chip under test through the USB connection channel and proceeds to step S500; S420, the test host controls the chip under test to enter the USB boot mode through the command control channel and returns to step S300; S500: Testing the chip to be tested using the test firmware.

2. The chip testing method according to claim 1, characterized in that: Before step S100, the USB startup mode and test parameter thresholds of the chip to be tested are configured on the test host by the host computer.

3. The chip testing method according to claim 1, wherein: The configured USB startup mode of the chip to be tested includes at least two optional and mutually switchable USB startup modes.

4. The chip testing method according to claim 3, characterized in that: The at least two USB startup modes include: a USB startup mode triggered by a serial port instruction and a USB startup mode triggered by an SPI instruction.

5. The chip testing method according to claim 3 or 4, characterized in that: In step S420, the chip under test is controlled to enter the USB boot mode, which specifically includes: a. Receive the USB boot mode selection signal; b. Generate a trigger command signal corresponding to the mode; c. Sending the trigger command signal to the chip under test; d. The chip under test enters the corresponding USB boot mode and returns to step S300.

6. The chip testing method according to claim 3 or 4, characterized in that: In step S420, the chip under test is controlled to enter the USB boot mode, which specifically includes: A. Arrange at least two USB boot modes by priority. B. Automatically generate the trigger command signal corresponding to the USB boot mode with the highest priority and send it to the chip under test; C. Detect whether the chip under test enters the USB boot mode within a predetermined time. If yes, return to step S300; otherwise, go to step D. D. Automatically generate a trigger command signal corresponding to the USB boot mode with a relatively lower priority and send it to the chip under test; E. Check whether the chip under test enters the USB boot mode within the predetermined time. If yes, return to step S300; otherwise, return to step D.

7. The chip testing method according to claim 1, wherein: Step S500 specifically includes: the test host sends firmware verification and firmware running commands to the chip under test through the USB connection channel, and the chip under test executes the test firmware after the verification is successful.

8. The chip testing method according to claim 7, characterized in that: The chip to be tested is a radio frequency chip. When the test firmware is executed in step S500, the radio frequency performance of the radio frequency chip is first tested, and then the radio frequency parameters of the radio frequency chip are calibrated.

9. A chip testing system, comprising a testing host and a chip to be tested; the testing host and the chip to be tested are connected via a USB connection channel and an instruction control channel; the testing host and the chip to be tested cooperate to execute the chip testing method according to any one of claims 1 to 8.

10. The chip testing system according to claim 9, characterized in that: The download pin of the test host is switchedly connected to the debug serial port pin and the SPI pin of the chip to be tested; or, the download pin of the test host is simultaneously connected to the debug serial port pin and the SPI pin of the chip to be tested.

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