Integrated circuit, control method and control system of integrated circuit

Abstract

The invention discloses an integrated circuit and a control method and system of the integrated circuit, and relates to the technical field of electronic circuits. The integrated circuit includes an enable circuit and a digital circuit module. The enabling circuit comprises a first input end, a second input end, a third input end and an output end, the first input end is used for receiving a serial data input signal, the second input end is used for receiving a chip selection signal, the third input end is used for receiving a holding signal, and the output end is used for outputting an internal enabling signal for controlling the integrated circuit to be powered on or powered off. And the digital circuit module is used for outputting a holding signal and configuring the holding signal to enable the output end to keep outputting the internal enabling signal for controlling the power-on of the integrated circuit after the enabling branch outputs the internal enabling signal for controlling the power-on of the integrated circuit based on the serial data input signal and the chip selection signal. Through the mode, the cost can be reduced, and the size of an integrated circuit can be reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to an integrated circuit, an integrated circuit control method, and a control system. Background Art

[0002] The Serial Peripheral Interface (SPI) bus was created in the 1980s for communication between microcontrollers and the various integrated circuits coupled to them. Most integrated circuits have an enable port that is used to control the power-up and power-down of the integrated circuit. Figure 1 FIG. 1 illustrates an integrated circuit with an enable port. Figure 1 As shown, the integrated circuit 100 includes a power management module 101 , a digital circuit module 102 and an analog circuit module 103 .

[0003] Integrated circuit 100 also includes at least eight input / output ports, namely, a power bus port VBB, an output voltage port Vo, a ground port GND, an enable port EN, a serial data input port SDI, a serial data output port SDO, a serial clock port SCK, and a chip select port nCS. The serial data input port SDI, the serial data output port SDO, the serial clock port SCK, and the chip select port nCS are used to communicate with a microcontroller using SPI signals. The serial data input port SDI is configured to receive serial data generated by the microcontroller, while the serial data output port SDO is configured to transmit serial signals to the microcontroller. The serial clock port SCK is configured to receive a clock signal generated by the microcontroller. The chip select port nCS is configured to receive a chip select signal that determines whether the integrated circuit is communicating with the microcontroller at a given time. The enable port EN is configured to receive an enable signal generated by the microcontroller. The enable signal is used to control the power-up and power-down of the integrated circuit.

[0004] Figure 2 The schematic diagram of the structure of a control system including a microcontroller and a plurality of integrated circuits with enable ports EN is shown as an example. The control system includes a microcontroller 200 and a plurality of integrated circuits 100. A serial communication protocol (such as SPI) is used to provide a communication channel between various elements of the control system. Figure 2 As shown, the microcontroller 200 includes three serial peripheral interface ports, namely, a master output slave input port MOSI, a master input slave output port MISO, and a serial clock port SCK. The master output slave input port MOSI, the master input slave output port MISO, and the serial clock port SCK of the microcontroller 200 are respectively connected to the serial data input port SDI, the serial data output port SDO, and the serial clock port SCK of each integrated circuit.

[0005] Microcontroller 200 also includes multiple chip select ports, namely, port SS1, port SS2, ..., and port SSn. Each chip select port of microcontroller 200 is connected to a chip select port of integrated circuit 100. In practical applications, the chip select port of microcontroller 200 is configured to generate a chip select signal that specifies which integrated circuit the microcontroller 200 communicates with at a given time. When the chip select signal is low, communication with the integrated circuit corresponding to the chip select signal is active.

[0006] Microcontroller 200 also includes multiple enable ports, namely, enable port EN1, enable port EN2, ..., and enable port ENn. One enable port of microcontroller 200 is connected to enable port EN of an integrated circuit 100. A dedicated enable port of the integrated circuit is required to control the power-up and power-down of the integrated circuit 100. Once the integrated circuit 100 is powered on, SPI communication is established, allowing microcontroller 200 to communicate with the integrated circuit 100 via the SPI interface.

[0007] exist Figure 2 In the control system shown in FIG, there may be many integrated circuits 100, each of which requires a dedicated enable port and a connection line between the enable port and the microcontroller 200. The enable port of the integrated circuit 100 and the connection line between the enable port and the microcontroller 200 increase the cost and size of the control system. Summary of the Invention

[0008] The present application aims to provide an integrated circuit, an integrated circuit control method and a control system, which can reduce the cost and size of the integrated circuit.

[0009] To achieve the above objectives, in a first aspect, the present application provides an integrated circuit, comprising:

[0010] an enabling circuit, comprising a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output an internal enabling signal for controlling power on or off of the integrated circuit;

[0011] A digital circuit module is used to output the hold signal and to configure the hold signal so that the output end keeps outputting the internal enable signal for controlling the power-on of the integrated circuit after the enable branch outputs the internal enable signal for controlling the power-on of the integrated circuit based on the serial data input signal and the chip select signal.

[0012] In an optional manner, the enabling circuit is further configured to configure the internal enabling signal to be in the first enabling logic state when the chip select signal is in the first chip select logic state and the serial data input signal is in the first data logic state, so as to power on the integrated circuit;

[0013] The digital circuit module is further configured to configure the hold signal to be in a first hold logic state when the internal enable signal is in the first enable logic state;

[0014] The enabling circuit is further configured to configure the internal enabling signal to be in the first enabling logic state when the holding signal is in the first holding logic state, so as to keep the integrated circuit powered on;

[0015] The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

[0016] In an optional manner, the first chip select logic state is a low level, and the first data logic state, the first enable logic state, and the first hold logic state are all high levels.

[0017] In an optional manner, when the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal so that the chip select signal and the serial data input signal cannot act on the integrated circuit through the enable circuit.

[0018] In an optional manner, the digital circuit module is further used to receive a power-off instruction output by the controller, and configure the hold signal based on the power-off instruction so that the output end of the enable circuit outputs an internal enable signal for controlling power-off of the integrated circuit.

[0019] In an optional manner, the digital circuit module is further configured to configure the hold signal to a second hold logic state based on the power-off instruction, so as to configure the internal enable signal to a second enable logic state, so as to power off the integrated circuit;

[0020] The second enable logic state and the second hold logic state both include a high level or a low level.

[0021] In an optional manner, the second enable logic state and the second hold logic state are both low levels.

[0022] In an optional manner, the enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor and a Zener diode;

[0023] The first P-type transistor, the second N-type transistor and the second resistor are connected in series between a power bus and ground;

[0024] The gate of the third N-type transistor receives the holding signal, and the third N-type transistor is connected between the first P-type transistor and the ground;

[0025] The third resistor is connected in parallel with the Zener diode;

[0026] The gate of the second N-type transistor receives the serial data input signal through the first resistor;

[0027] The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground;

[0028] The second P-type transistor and the Zener diode are connected in series between the power bus and the ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor respectively;

[0029] The internal enable signal is generated at a common node of the second P-type transistor and the Zener diode.

[0030] In an optional manner, the enabling circuit further includes a fourth N-type transistor;

[0031] A gate of the fourth N-type transistor receives the holding signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

[0032] In a second aspect, the present application provides a control method for an integrated circuit, wherein the integrated circuit inputs a serial data input signal and a chip select signal, the method comprising:

[0033] configuring the chip select signal to a first chip select logic state to allow an external device to control the integrated circuit;

[0034] When the serial data input signal is in a first data logic state, configuring an internal enable signal to be in a first enable logic state, wherein the integrated circuit is powered on when the internal enable signal is in the first enable logic state;

[0035] When the internal enable signal is in the first enable logic state, configuring the hold signal to be in a first hold logic state, wherein when the hold signal is in the first hold logic state, the internal enable signal is maintained in the first enable logic state;

[0036] The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

[0037] In an optional manner, the first chip select logic state is a low level, and the first data logic state, the first enable logic state, and the first hold logic state are all high levels.

[0038] In an optional manner, the method further includes:

[0039] If a power-off instruction output by the controller is received, the holding signal is configured to switch from a first holding logic state to a second holding logic state, wherein the second holding logic state includes a high level or a low level, and the second holding logic state is different from the first holding logic state;

[0040] When the hold signal is in the second hold logic state, configuring the internal enable signal to be in a second enable logic state, wherein the second enable logic state includes a high level or a low level, and the second enable logic state is different from the first enable logic state;

[0041] Wherein, when the internal enable signal is in the second enable logic state, the integrated circuit is powered off.

[0042] In an optional manner, the second hold logic state and the second enable logic state are both low levels.

[0043] In an optional manner, the method further includes:

[0044] After receiving the power-off instruction, and when the hold signal switches from the first hold logic state to the second hold logic state, configuring the chip select signal to a second chip select logic state and / or configuring the serial data input signal to a second data logic state;

[0045] The second chip select logic state and the second data logic state include a high level or a low level.

[0046] In an optional manner, the second chip select logic state and the second data logic state are both low levels.

[0047] In an optional manner, the method further includes:

[0048] Configuring an enabling circuit to generate the internal enabling signal, and configuring a digital circuit module to generate the holding signal;

[0049] Among them, the enabling circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is used to receive the serial data input signal, the second input terminal is used to receive the chip select signal, the third input terminal is used to receive the hold signal, and the output terminal is used to output the internal enable signal.

[0050] In an optional manner, the method further includes:

[0051] When the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot affect the internal enable signal through the enable circuit.

[0052] In an optional manner, the enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor and a Zener diode;

[0053] The first P-type transistor, the second N-type transistor and the second resistor are connected in series between a power bus and ground;

[0054] The gate of the third N-type transistor receives the holding signal, and the third N-type transistor is connected between the first P-type transistor and the ground;

[0055] The third resistor is connected in parallel with the Zener diode;

[0056] The gate of the second N-type transistor receives the serial data input signal through the first resistor;

[0057] The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground;

[0058] The second P-type transistor and the Zener diode are connected in series between the power bus and the ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor respectively;

[0059] The internal enable signal is generated at a common node of the second P-type transistor and the Zener diode.

[0060] In an optional manner, the enabling circuit further includes a fourth N-type transistor;

[0061] A gate of the fourth N-type transistor receives the holding signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

[0062] In a third aspect, the present application provides a control system, which includes a controller and the integrated circuit as described above, wherein the controller is connected to the integrated circuit.

[0063] The beneficial effects of the present application are as follows: the integrated circuit provided by the present application includes an enable circuit and a digital circuit module. The enable circuit includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output an internal enable signal that controls the integrated circuit to power on or off. The digital circuit module is used to output the hold signal. The digital circuit module is also used to configure a hold signal so that the output terminal continues to output the internal enable signal that controls the integrated circuit to power on after the enable branch outputs the internal enable signal that controls the integrated circuit to power on based on the serial data input signal and the chip select signal. As a result, the integrated circuit no longer requires an enable port, no longer requires a connection line between the controller, and does not occupy an output port of the controller. Compared to the related art solution that requires a dedicated enable port and a connection line connecting the enable port to the microcontroller, the present application can reduce the cost and size of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0065] Figure 1 A schematic diagram of the structure of an integrated circuit in the related art;

[0066] Figure 2 A schematic diagram of the structure of an integrated circuit in the related art;

[0067] Figure 3 A schematic diagram of the structure of the control system provided in Example 1 of the present application;

[0068] Figure 4 A schematic diagram of the structure of an integrated circuit provided in Example 1 of the present application;

[0069] Figure 5 A schematic diagram of the circuit structure of the integrated circuit provided in Example 1 of the present application;

[0070] Figure 6 A schematic diagram of various signals in the integrated circuit provided in Example 1 of the present application;

[0071] Figure 7 A schematic diagram of various signals in an integrated circuit provided in Example 2 of the present application;

[0072] Figure 8 This is a flowchart of the integrated circuit control method provided in Example 1 of the present application. DETAILED DESCRIPTION

[0073] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0074] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the control system 1000 provided in the embodiment of the present application. Figure 3 As shown, the control system 1000 includes a controller 400 and at least one integrated circuit 300. The controller 400 is connected to each integrated circuit 300. The controller 400 communicates with each integrated circuit 300 via a serial communication protocol.

[0075] The controller 400 includes three serial peripheral interface ports: a master output slave input port MOSI, a master input slave output port MISO, and a serial clock port SCK. Each integrated circuit 300 also includes a serial data input port SDI, a serial data output port SDO, and a serial clock port SCK. The master output slave input port MOSI, the master input slave output port MISO, and the serial clock port SCK of the controller 400 are respectively connected to the serial data input port SDI, the serial data output port SDO, and the serial clock port SCK of each integrated circuit 300. Each integrated circuit 300 receives serial data through the serial data input port SDI and transmits serial data through the serial data output port SDO. The serial clock port SCK is a clock signal used to synchronize data transmission between devices. The clock signal ensures that the sending and receiving devices are synchronized in time, enabling them to correctly interpret the transmitted data.

[0076] The controller 400 also includes a plurality of chip select ports, namely, chip select port SS1, chip select port SS2, ..., chip select port SSn. Each integrated circuit 300 also includes a chip select port nCS. A chip select port of the controller 400 is connected to the chip select port of an integrated circuit 300. The chip select port of the controller 400 is configured to generate a chip select signal, which specifies which integrated circuit the controller 400 communicates with at a given time. In actual applications, the controller 400 pulls down the chip select port of the integrated circuit 300 to be communicated with (or the integrated circuit 300 to be controlled). The controller 400 then sends and receives data according to the clock signal. After the data transmission is completed, the controller 400 pulls up the chip select port of the integrated circuit 300 to release the data transmission line. The change in the state of the chip select port indicates that communication with a specific integrated circuit 300 is about to begin or has been completed. The chip select port and associated chip select signals allow multiple integrated circuits 300 to share the same SPI bus without interfering with each other because only the selected integrated circuit 300 responds to the data (ie, SDO transmits data and SDI receives data) and clock SCK signals.

[0077] and Figure 2 Compared with the control system in the related art shown in Figure 3 The control system provided by the embodiment of the present application shown in Figure 2 eliminates the need for enable ports on each integrated circuit, saving many input / output ports and thus reducing overall system costs. Furthermore, reducing the total number of ports simplifies wiring in large integrated circuit systems, helping to reduce printed circuit board (PCB) area and costs. This achieves the goal of reducing costs and the size of integrated circuits.

[0078] In practical applications, the control system 1000 provided in the embodiment of the present application relies on a specific combination of chip select signals and serial data input signals to control the power-up and power-down of each integrated circuit 300. The detailed working principle of the power-up and power-down process of the integrated circuit 300 will be described in detail below.

[0079] Please refer to Figure 4 , Figure 4 Schematic diagram of the structure of the integrated circuit 300 provided in the embodiment of the present application. Figure 4 As shown, the integrated circuit 300 includes an enabling circuit 301 and a digital circuit module 302 .

[0080] The enable circuit 301 includes a first input terminal for receiving a serial data input signal S_SDI, a second input terminal for receiving a chip select signal S_nCS, a third input terminal for receiving a hold signal HLD, and an output terminal for outputting an internal enable signal INT_EN for controlling the power-up or power-down of the integrated circuit 300.

[0081] The digital circuit module 302 is used to output a hold signal HLD, and is used to configure the hold signal HLD so that the output end of the enable circuit 301 keeps outputting the internal enable signal INT_EN that controls the power-on of the integrated circuit 300 after the enable branch 301 outputs the internal enable signal INT_EN that controls the power-on of the integrated circuit 300 based on the serial data input signal S_SDI and the chip select signal S_nCS.

[0082] Specifically, during the power-up process of the integrated circuit 300, the chip select logic state (including a high level and a low level) of the chip select signal S_nCS input to the integrated circuit 300 is configured to change to allow the controller 400 to control the integrated circuit 300. For example, in one embodiment, the chip select signal S_nCS is configured to the first chip select logic state to allow the controller 400 to control the integrated circuit 300. At the same time, in response to the serial data input signal S_SDI being the first data logic state (including a high level and a low level), the internal enable signal INT_EN is configured to the first enable logic state (including a high level and a low level) to enable the integrated circuit 300 to begin powering up. In summary, the enable circuit 301 can configure the internal enable signal INT_EN to the first enable logic state when the chip select signal S_nCS is the first chip select logic state and the serial data input signal S_SDI is the first data logic state to enable the integrated circuit 300 to power up. Next, in response to the internal enable signal INT_EN being in the first enable logic state, the digital circuit module 302 configures the hold signal HLD to be in the first hold logic state (including a high level and a low level). When the hold signal HLD is in the first hold logic state, the internal enable signal remains in the first enable logic state. In other words, the enable circuit 301 can also configure the internal enable signal INT_EN to be in the first enable logic state when the hold signal HLD is in the first hold logic state, so as to keep the integrated circuit 300 powered on.

[0083] In one embodiment, the first chip select logic state is a low level, and the first data logic state, the first enable logic state, and the first hold logic state are all high levels.

[0084] In one embodiment, when the hold signal HLD is in the first hold logic state, the hold signal HLD overrides the chip select signal S_nCS and the serial data input signal S_SDI, so that the internal enable signal INT_EN is not affected by the chip select signal S_nCS and the serial data input signal S_SDI. In other words, when the hold signal HLD is in the first hold logic state, the chip select signal S_nCS and the serial data input signal S_SDI cannot act on the integrated circuit 300 through the enable circuit 301. As a result, the integrated circuit 300 can remain in a powered-on state.

[0085] During the power-off process of the integrated circuit 300, the digital circuit module 302 is further configured to receive a power-off command output by the controller 400 via the SPI bus, and, based on the power-off command, configure the hold signal HLD so that the output terminal of the enable circuit 301 outputs the internal enable signal INT_EN for controlling the power-off of the integrated circuit 300. Specifically, in one embodiment, in response to the power-off command from the controller 400, the digital circuit module 302 configures the hold signal HLD to a second hold logic state (including a high level or a low level, and the second hold logic state is different from the first hold logic state). The chip select signal S_nCS of the corresponding integrated circuit 300 is configured to a first chip select logic state, and the power-off command output by the controller 400 is transmitted to the digital circuit module 302 of the integrated circuit via the serial data input signal S_SDI. When the hold signal HLD is in the second hold logic state, the internal enable signal INT_EN switches from the first enable logic state to a second enable logic state (including a high level or a low level, and the second enable logic state is different from the first enable logic state). Once the internal enable signal INT_EN is in the second enable logic state, the integrated circuit 300 is powered off.

[0086] In one embodiment, the second enable logic state and the second hold logic state are both low.

[0087] Please refer to Figure 5 , Figure 5 Schematically shows a circuit structure of an integrated circuit 300. Figure 5 As shown, the enabling circuit 301 includes a first N-type transistor M1, a second N-type transistor M2, a third N-type transistor M3, a first P-type transistor MP1, a second P-type transistor MP2, a first resistor R1, a second resistor R2, a third resistor R3 and a Zener diode Z1.

[0088] The first P-type transistor MP1, the second N-type transistor M2, and the second resistor R2 are connected in series between the power bus L_VBB and ground. The gate of the third N-type transistor M3 receives a hold signal HLD, and the third N-type transistor M3 is connected between the first P-type transistor MP1 and ground. The third resistor R3 is connected in parallel with the Zener diode Z1. The gate of the second N-type transistor M2 receives a serial data input signal S_SDI through the first resistor R1. The gate of the first N-type transistor M1 receives a chip select signal S_nCS, and the first N-type transistor M1 is connected between the gate of the second N-type transistor M2 and ground. The second P-type transistor MP1 and the Zener diode Z1 are connected in series between the power bus L_VBB and ground, and the gate of the second P-type transistor MP2 is connected to the gate and drain of the first P-type transistor MP1, respectively. An internal enable signal INT_EN is generated at the common node between the second P-type transistor MP2 and the Zener diode Z1. A gate of the fourth N-type transistor M4 receives the hold signal HLD, and the fourth N-type transistor M4 is connected between the gate of the second N-type transistor M2 and ground.

[0089] Specifically, the power bus L_VBB is connected to the positive electrode of the battery (not shown). The drain of the third N-type transistor M3 is connected to the drain of the first P-type transistor MP1. The source of the third N-type transistor M3 is connected to the source of the second N-type transistor M2. In this embodiment, the source of the third N-type transistor M3 is grounded via the second resistor R2. In other embodiments, a separate resistor may be provided between the source of the third N-type transistor M3 and ground. In this configuration, the source of the third N-type transistor M3 is not directly connected to the source of the second N-type transistor M2 or ground. The serial data input signal S_SDI is fed to the gate of the second N-type transistor M2 via the first resistor R1, while the chip select signal S_nCS is applied to the gate of the first N-type transistor M1. The gate of the third N-type transistor M3 is configured to receive the hold signal HLD generated by the digital circuit module 302. The gates of the first P-type transistor MP1 and the second P-type transistor MP2 are connected together and further connected to the drain of the first P-type transistor MP1. The first P-type transistor MP1 and the second P-type transistor MP2 form a current mirror structure. The drain of the first N-type transistor M1 is connected to the gate of the second N-type transistor M2. The source of the first N-type transistor M1 is connected to ground. The drain of the fourth N-type transistor M4 is connected to the drain of the first N-type transistor M1. The source of the fourth N-type transistor M4 is connected to the source of the first N-type transistor M1. The gate of the fourth N-type transistor M4 is configured to receive a hold signal HLD.

[0090] In this embodiment, the integrated circuit 300 further includes a low-voltage dropout linear regulator 303 and a main circuit 304. The internal enable signal INT_EN is input to the low-voltage dropout linear regulator 303. When the internal enable signal INT_EN is in the first enable logic state, the low-voltage dropout linear regulator 303 provides a bias voltage VDD to the digital circuit module 302 and the main circuit 304 based on the power supply on the power bus L_VBB, so that the digital circuit module 302 and the main circuit 304 operate. The main circuit 304 is configured to perform the main functions of the integrated circuit 300. In one embodiment, the main circuit 304 corresponds to Figure 1 The analog circuit module 103 shown is used to process analog signals; the low voltage drop linear regulator 303 corresponds to Figure 1 The power management module 101 shown in FIG; the digital circuit module 302 is Figure 1 Improvements made on the digital circuit module 102 are shown.

[0091] In actual applications, before integrated circuit 300 is powered on, when the serial data input signal S_SDI is high and the chip select signal S_nCS is low, the first N-type transistor M1 is turned off. The serial data input signal S_SDI drives the gate of the second N-type transistor M2 high, turning it on. The current flowing through the second N-type transistor M2 is mirrored to the right circuit formed by the second P-type transistor MP2 and the Zener diode Z1. The current flowing through the second P-type transistor MP2 provides the initial power supply for the low-dropout linear regulator 303. The Zener diode Z1 stabilizes the voltage of this power supply. The voltage at the common node between the second P-type transistor MP2 and the Zener diode Z1 can be considered the internal enable signal INT_EN. The internal enable signal INT_EN is used to enable the low-dropout linear regulator 303. After the low-dropout linear regulator 303 is started, the voltage on the power bus L_VBB is converted to the bias voltage VDD for the digital circuit module 302 and the main circuit 303. After the digital circuit module 302 is powered on, it configures its output hold signal HLD to be high. The hold signal HLD (currently high) then turns on the third N-type transistor M3 to maintain current flowing through the first P-type transistor MP1, thereby maintaining the internal enable signal INT_EN at a high level.

[0092] In an optional embodiment, the fourth N-type transistor M4 can be configured to be turned on by a hold signal HLD. The conduction of the fourth N-type transistor M4 turns off the second N-type transistor M2. As can be seen, the hold signal HLD turns on the fourth N-type transistor M4 to override the serial data input signal S_SDI and the chip select signal S_nCS, thereby preventing the serial data input signal S_SDI and the chip select signal S_nCS from affecting the internal enable signal INT_EN through the enable circuit 301 after the integrated circuit 300 is powered on. Specifically, when the hold signal HLD is high, the conduction of the fourth N-type transistor M4 pulls down the gate of the second N-type transistor M2, thereby preventing the combination of the serial data input signal S_SDI and the chip select signal S_nCS from changing the operating state of the second N-type transistor M2, thereby affecting the enable state of the integrated circuit 300.

[0093] The power-off process is entirely carried out through SPI communication between the controller 400 and the integrated circuit 300. The controller 400 sends a power-off instruction to the digital circuit module 302 of the integrated circuit 300 via the SPI bus, so that the digital circuit module 302 configures the hold signal HLD it outputs to a low level. In response to the hold signal HLD being at a low level, the power-off process of the integrated circuit 300 begins. Once the hold signal HLD is at a logic low level, the third N-type transistor M3 is turned off. The turning off of the third N-type transistor M3 causes the current flowing through the first P-type transistor MP1 to stop, thereby turning off the second P-type transistor MP2. Once the second P-type transistor MP2 is turned off, the third resistor R3 pulls the internal enable signal INT_EN down to a low level, and the low-voltage dropout linear regulator 303 is turned off to complete the power-off process of the integrated circuit 300.

[0094] It should be noted that the first N-type transistor M1, the second N-type transistor M2, the third N-type transistor M3, the first P-type transistor MP1, the second P-type transistor MP2, the second resistor R2, the third resistor R3, and the Zener diode Z1 form an initial bias circuit 3011. The initial bias circuit 3011 functions similarly to an OR gate. Specifically, when the serial data input signal S_SDI and the inverted signal of the chip select signal S_nCS are both at a logic high level, or when the hold signal HLD is at a logic high level, the initial bias circuit 3011 can configure the internal enable signal INT_EN to be at a logic high level.

[0095] In addition, the fourth N-type transistor M4 forms an optional module 3012. The optional module 3012 is used to further reduce the power consumption of the enable circuit 301. Once the controller 400 sends an instruction to set the enable signal HLD to a low level (e.g., a power-down instruction PD) via the SPI interface, the chip select signal S_nCS can be set to a logic high level to prevent the second N-type transistor M2 from being mistakenly turned on during the power-down process, or the serial data input signal S_SDI can be set to a logic low level to prevent the second N-type transistor M2 from being mistakenly turned on during the power-down process.

[0096] The enabling circuit 301 is used in the following scenario: Before being enabled, the disabled integrated circuit 300 has no internal power supply. In this case, although the integrated circuit 300 is connected to the power bus L_VBB, the digital circuit module 302 is not powered before being enabled because the bias voltage VDD is not available. As described above, by using the enabling circuit 301, the integrated circuit 300 can be enabled via an SPI signal, and the enabling circuit 301 can power up the integrated circuit 300. Once powered up, the integrated circuit 300 can communicate with the controller 400 via the SPI bus.

[0097] Please refer to Figure 6 , Figure 6 An example is shown Figure 5 The first schematic diagram of the various signals in the circuit shown. Figure 6 As shown, Figure 6 The horizontal axis represents time. Figure 6 The vertical axis of FIG has five rows. The first row represents the chip select signal S_nCS; the second row represents the serial data input signal S_SDI; the third row represents the internal enable signal INT_EN; the fourth row represents the hold signal HLD; and the fifth row represents the output Vo of the integrated circuit 300 (in this embodiment, a high level at the output Vo indicates that the integrated circuit 300 has completed power-up). The "X" in the serial data input signal S_SDI indicates that it can be any data, "1" indicates a high level, and "PD" indicates a power-down instruction.

[0098] Please refer to Figure 5 and Figure 6Before time t1, integrated circuit 300 is in a power-off state. Output Vo is low, and chip select signal S_nCS is high. At time t1, chip select signal S_nCS changes from a logic high to a logic low. In response to chip select signal S_nCS being low, first N-type transistor M1 turns off, allowing controller 400 to configure the gate voltage of second N-type transistor M2 via serial data input signal S_SDI. Furthermore, at time t1, to power on integrated circuit 300, serial data input signal S_SDI is configured high. The logic high of serial data input signal S_SDI causes internal enable signal INT_ENT to go high. Specifically, when serial data input signal S_SDI is high, second N-type transistor M2 turns on. The current flowing through second N-type transistor M2 is mirrored by the current mirror formed by first P-type transistor MP1 and second P-type transistor MP2 to the right circuit formed by the series connection of second P-type transistor MP2 and Zener diode Z1. At this time, the current flowing through the second P-type transistor MP2 establishes the internal enable signal INT_EN having a logic high level.

[0099] In response to the internal enable signal INT_EN being high, the digital circuit module 302 configures the hold signal HLD to transition from a logic low to a logic high at time t2. After a predetermined delay, the output voltage Vo is established at time t3. At time t4, SPI communication between the controller 400 and the integrated circuit 300 proceeds normally. The serial data input signal S_SDI can have any value depending on the function and / or instruction sent by the controller 400.

[0100] After time t4, to prevent the internal enable signal INT_EN from being altered when the integrated circuit 300 stops communicating with the controller 400 (e.g., when the chip select signal S_nCS goes high between times t5 and t6), the hold signal HLD can be used to override the serial data input signal S_SDI, the chip select signal S_nCS, and the combination of the serial data input signal S_SDI and the chip select signal S_nCS. This prevents the serial data input signal S_SDI, the chip select signal S_nCS, and the combination of the serial data input signal S_SDI and the chip select signal S_nCS from potentially affecting the internal enable signal INT_EN through the enable circuit 301, thereby maintaining the internal enable signal INT_EN at a logic high state. Once the hold signal HLD is high, the third N-type transistor M3 is turned on. This conduction of the third N-type transistor M3 replaces the second N-type transistor M2, maintaining the internal enable signal INT_EN at a logic high state. Furthermore, once the hold signal HLD is high, the fourth N-type transistor M4 is turned on. The conduction of the fourth N-type transistor M4 pulls down the gate of the second N-type transistor M2, so that the second N-type transistor M2 remains off, thereby preventing at least one of the serial data input signal S_SDI and the chip select signal S_nCS from affecting the enable state of the integrated circuit 300 through the enable circuit 301.

[0101] At time t7, controller 400 uses the SPI bus to send a power-down command PD to integrated circuit 300 via serial data input signal S_SDI. After communication regarding power-down command PD is completed, chip select signal S_nCS is pulled high at time t8, terminating communication with integrated circuit 300. In response to the power-down command from controller 400, after a certain delay, at time t9, digital circuit module 302 configures hold signal HLD to switch from a logic high level to a logic low level.

[0102] It should be noted that, depending on different applications and design requirements, the delay time in the above embodiment may also be zero.

[0103] In this embodiment, the internal enable signal INT_EN changes from a logic high level to a logic low level immediately after the holding signal HLD switches to a low level at time t9. After a predetermined delay (e.g., the power-off time of the integrated circuit 300), at time t10, the output voltage Vo of the integrated circuit 300 also returns to a low level after the internal enable signal INT_EN is at a logic low level, thus completing the power-off of the integrated circuit 300.

[0104] In this embodiment, the Figure 6An advantageous feature of the control method shown is that it utilizes the existing SPI interface to power up and power down the integrated circuit 300 without relying on a dedicated enable terminal. Removing the dedicated enable terminal from the integrated circuit 300 and the controller 400 can save many input / output terminals, thereby reducing the complexity and cost of the entire control system.

[0105] Please refer to Figure 7 , Figure 6 An example is shown Figure 5 The second schematic diagram of the various signals in the circuit shown. Figure 7 The implementation shown is similar to Figure 6 The implementation shown in is similar, the only difference is that the chip select signal S_nCS changes from logic low to logic high after the power-down process is completed. Figure 7 As shown, from time t13 to time t15, the serial data input signal S_SDI remains at a logic low level after the power-down signal PD is transmitted (where "0" in the serial data input signal S_SDI represents a low level). As can be seen, as long as the serial data input signal S_SDI remains at a low level after the power-down command PD is transmitted, it is not necessary to pull the chip select signal S_nCS high immediately after the power-down command PD is transmitted. After the hold signal HLD is pulled low, the integrated circuit 300 is powered off.

[0106] In short, when the hold signal HLD is pulled low, at least one of the following conditions ensures that the integrated circuit can be powered off: the first condition is to pull the chip select signal S_nCS high; the second condition is to keep the serial data input signal S_SDI at a low level.

[0107] It should be noted that after the hold signal HLD is pulled low, if the chip select signal S_nCS and the serial data input signal S_SDI appear as follows Figure 6 In the state between time t1 and time t4 shown in FIG, the hold signal HLD is configured to be high again. In this case, since the hold signal HLD is in the logic high state, the integrated circuit 300 cannot be powered off.

[0108] Please refer to Figure 8 , Figure 8 This is a flow chart of the control method of the integrated circuit provided in the embodiment of the present application. The integrated circuit inputs a serial data input signal and a chip select signal. Figure 8 As shown, the control method of the integrated circuit includes the following steps:

[0109] Step 801: Configure a chip select signal to a first chip select logic state to allow an external device to control an integrated circuit.

[0110] Step 802 : When the serial data input signal is in a first data logic state, configure the internal enable signal to be in a first enable logic state, wherein the integrated circuit is powered on when the internal enable signal is in the first enable logic state.

[0111] Step 803 : When the internal enable signal is in the first enable logic state, configure the hold signal to be in the first hold logic state, wherein when the hold signal is in the first hold logic state, the internal enable signal remains in the first enable logic state.

[0112] The first chip select logic state, the first data logic state, the first enable logic state and the first hold logic state all include a high level or a low level.

[0113] In one embodiment, the first chip select logic state is a low level, and the first data logic state, the first enable logic state, and the first hold logic state are all high levels.

[0114] In one embodiment, the control method of the integrated circuit further includes the following steps: when the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal so that the chip select signal and the serial data input signal cannot affect the internal enable signal through the enable circuit.

[0115] In one embodiment, the control method of the integrated circuit further includes the following steps: if a power-off instruction output by the controller is received, configuring the hold signal to switch from a first hold logic state to a second hold logic state, wherein the second hold logic state includes a high level or a low level, and the second hold logic state is different from the level of the first hold logic state; when the hold signal is in the second hold logic state, configuring the internal enable signal to be in a second enable logic state, wherein the second enable logic state includes a high level or a low level, and the second enable logic state is different from the level of the first enable logic state; wherein, when the internal enable signal is in the second enable logic state, the integrated circuit is powered off.

[0116] In one embodiment, the second hold logic state and the second enable logic state are both low level.

[0117] In one embodiment, the control method of the integrated circuit further includes the following steps: after receiving a power-off instruction, and when the hold signal switches from the first hold logic state to the second hold logic state, configuring the chip select signal to the second chip select logic state and / or configuring the serial data input signal to the second data logic state; wherein the second chip select logic state and the second data logic state include a high level or a low level.

[0118] In one embodiment, the second chip select logic state and the second data logic state are both low level.

[0119] In one embodiment, the control method of the integrated circuit further includes the following steps: configuring an enable circuit to generate an internal enable signal, and configuring a digital circuit module to generate a hold signal; wherein the enable circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output the internal enable signal.

[0120] In one embodiment, the enable circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor and a Zener diode; the first P-type transistor, the second N-type transistor and the second resistor are connected in series between a power bus and a ground; the gate of the third N-type transistor receives a hold signal, and the third N-type transistor is connected between the first P-type transistor and the ground; the third resistor is connected in parallel with the Zener diode; the gate of the second N-type transistor receives a serial data input signal through the first resistor; the gate of the first N-type transistor receives a chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and the ground; the second P-type transistor and the Zener diode are connected in series between the power bus and the ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor, respectively; and an internal enable signal is generated at a common node of the second P-type transistor and the Zener diode.

[0121] In one embodiment, the enabling circuit further includes a fourth N-type transistor; a gate of the fourth N-type transistor receives the holding signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

[0122] It should be understood that the specific control of the integrated circuit and the beneficial effects produced in the method embodiment can refer to the corresponding description in the above-mentioned integrated circuit embodiment, and for the sake of brevity, it will not be repeated here.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above. For the sake of simplicity, they are not provided in detail. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An integrated circuit, characterized in that: include: an enabling circuit, comprising a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal is used to receive a serial data input signal, the second input terminal is used to receive a chip select signal, the third input terminal is used to receive a hold signal, and the output terminal is used to output an internal enabling signal for controlling power on or off of the integrated circuit; A digital circuit module is used to output the hold signal and to configure the hold signal so that the output end keeps outputting the internal enable signal for controlling the power-on of the integrated circuit after the enable branch outputs the internal enable signal for controlling the power-on of the integrated circuit based on the serial data input signal and the chip select signal.

2. The integrated circuit according to claim 1, wherein: The enabling circuit is further configured to configure the internal enabling signal to be in the first enabling logic state when the chip select signal is in the first chip select logic state and the serial data input signal is in the first data logic state, so as to power on the integrated circuit; The digital circuit module is further configured to configure the hold signal to be in a first hold logic state when the internal enable signal is in the first enable logic state; The enabling circuit is further configured to configure the internal enabling signal to be in the first enabling logic state when the holding signal is in the first holding logic state, so as to keep the integrated circuit powered on; The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

3. The integrated circuit according to claim 2, wherein: The first chip select logic state is a low level, and the first data logic state, the first enable logic state, and the first hold logic state are all high levels.

4. The integrated circuit according to claim 2, wherein: When the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot act on the integrated circuit through the enable circuit.

5. The integrated circuit according to claim 2, wherein: The digital circuit module is further configured to receive a power-off instruction output by the controller, and configure the hold signal based on the power-off instruction so that the output end of the enable circuit outputs an internal enable signal for controlling power-off of the integrated circuit.

6. The integrated circuit according to claim 5, characterized in that The digital circuit module is further configured to configure the hold signal to a second hold logic state based on the power-off instruction, so as to configure the internal enable signal to a second enable logic state, so as to power off the integrated circuit; The second enable logic state and the second hold logic state both include a high level or a low level.

7. The integrated circuit according to claim 6, wherein: The second enable logic state and the second hold logic state are both low levels.

8. The integrated circuit according to any one of claims 1 to 7, wherein: The enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor and a Zener diode; The first P-type transistor, the second N-type transistor and the second resistor are connected in series between a power bus and ground; The gate of the third N-type transistor receives the holding signal, and the third N-type transistor is connected between the first P-type transistor and the ground; The third resistor is connected in parallel with the Zener diode; The gate of the second N-type transistor receives the serial data input signal through the first resistor; The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground; The second P-type transistor and the Zener diode are connected in series between the power bus and the ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor respectively; The internal enable signal is generated at a common node of the second P-type transistor and the Zener diode.

9. The integrated circuit according to claim 8, wherein: The enabling circuit further includes a fourth N-type transistor; A gate of the fourth N-type transistor receives the holding signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

10. A control method for an integrated circuit, characterized in that: The integrated circuit inputs a serial data input signal and a chip select signal, and the method includes: configuring the chip select signal to a first chip select logic state to allow an external device to control the integrated circuit; When the serial data input signal is in a first data logic state, configuring an internal enable signal to be in a first enable logic state, wherein the integrated circuit is powered on when the internal enable signal is in the first enable logic state; When the internal enable signal is in the first enable logic state, configuring the hold signal to be in a first hold logic state, wherein when the hold signal is in the first hold logic state, the internal enable signal is maintained in the first enable logic state; The first chip select logic state, the first data logic state, the first enable logic state, and the first hold logic state all include a high level or a low level.

11. The method according to claim 10, characterized in that The first chip select logic state is a low level, and the first data logic state, the first enable logic state, and the first hold logic state are all high levels.

12. The method according to claim 10, characterized in that The method further comprises: If a power-off instruction output by the controller is received, the holding signal is configured to switch from a first holding logic state to a second holding logic state, wherein the second holding logic state includes a high level or a low level, and the second holding logic state is different from the first holding logic state; When the hold signal is in the second hold logic state, configuring the internal enable signal to be in a second enable logic state, wherein the second enable logic state includes a high level or a low level, and the second enable logic state is different from the first enable logic state; When the internal enable signal is in the second enable logic state, the integrated circuit is powered off.

13. The method according to claim 12, characterized in that The second hold logic state and the second enable logic state are both low levels.

14. The method according to claim 12, characterized in that The method further comprises: After receiving the power-off instruction, and when the hold signal switches from the first hold logic state to the second hold logic state, configuring the chip select signal to a second chip select logic state and / or configuring the serial data input signal to a second data logic state; The second chip select logic state and the second data logic state include a high level or a low level.

15. The method according to claim 14, characterized in that The second chip select logic state and the second data logic state are both low level.

16. The method according to claim 10, characterized in that The method further comprises: Configuring an enabling circuit to generate the internal enabling signal, and configuring a digital circuit module to generate the holding signal; Among them, the enabling circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal is used to receive the serial data input signal, the second input terminal is used to receive the chip select signal, the third input terminal is used to receive the hold signal, and the output terminal is used to output the internal enable signal.

17. The method according to claim 16, characterized in that The method further comprises: When the hold signal is in the first hold logic state, the hold signal covers the chip select signal and the serial data input signal, so that the chip select signal and the serial data input signal cannot affect the internal enable signal through the enable circuit.

18. The method according to claim 16, characterized in that The enabling circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a first resistor, a second resistor, a third resistor and a Zener diode; The first P-type transistor, the second N-type transistor and the second resistor are connected in series between a power bus and ground; The gate of the third N-type transistor receives the holding signal, and the third N-type transistor is connected between the first P-type transistor and the ground; The third resistor is connected in parallel with the Zener diode; The gate of the second N-type transistor receives the serial data input signal through the first resistor; The gate of the first N-type transistor receives the chip select signal, and the first N-type transistor is connected between the gate of the second N-type transistor and ground; The second P-type transistor and the Zener diode are connected in series between the power bus and the ground, and the gate of the second P-type transistor is connected to the gate and drain of the first P-type transistor respectively; The internal enable signal is generated at a common node of the second P-type transistor and the Zener diode.

19. The method according to claim 18, characterized in that The enabling circuit further includes a fourth N-type transistor; A gate of the fourth N-type transistor receives the holding signal, and the fourth N-type transistor is connected between the gate of the second N-type transistor and ground.

20. A control system, characterized in that: The method comprises a controller and at least one integrated circuit according to any one of claims 1 to 9, wherein the controller is connected to the integrated circuit.

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