Parallel daisy chain FPGA configuration method and device

Abstract

The invention provides a parallel daisy chain FPGA configuration method and device. The parallel daisy chain FPGA configuration method comprises the steps that FPGA chips in a board card are connected according to a parallel daisy chain structure, and the FPGA chip serving as a master chip and the FPGA chip serving as a slave chip are determined; the master chip and the slave chips control the configuration process through state machines of the master chip and the slave chips and parallel daisy chain starting signals in received code streams, so that an FPGA chip of the master chip serves as a master control end, and code streams with different configurations can be accurately configured to the master chip or sent to the corresponding slave chips in a parallel daisy chain. And the configuration function sending of the FPGA chip in the parallel daisy chain is realized.

Description

Technical Field

[0001] One or more embodiments of this specification relate to the field of computer technology, and more particularly, to a parallel daisy-chain FPGA configuration method and apparatus. Background Art

[0002] When multiple FPGA chips are deployed on a board, the FPGA chips on the board can be connected in a daisy-chain structure. A single control source can be used to configure the FPGA chips in the daisy-chain through a single interface. However, this method can only configure the same configuration information for all FPGA chips in the daisy-chain and cannot configure different configuration information for the FPGA chips on the board. Summary of the Invention

[0003] This application describes a parallel daisy-chain FPGA configuration method and device, which can solve the above technical problems.

[0004] According to a first aspect, a parallel daisy-chain FPGA configuration method is provided. An FPGA chip serving as a master chip and at least one FPGA chip serving as a slave chip are connected in a parallel daisy-chain structure. The master chip includes a first state machine configured to control a configuration process of the master chip. The slave chip includes a second state machine configured to control a configuration process of the slave chip. The method includes:

[0005] The master chip reads a first code stream and / or a second code stream from an external memory, wherein the first code stream includes a parallel daisy chain start signal and a configuration code stream of the master chip, and the second code stream includes a parallel daisy chain start signal and a configuration code stream of the slave chip;

[0006] The master chip configures and sends itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal;

[0007] The master chip executes sending the second code stream to a slave chip connected in a parallel daisy-chain structure; the slave chip receives the second code stream and, according to the second state machine and the parallel daisy-chain start signal, configures itself using a configuration code stream in the second code stream, or sends the second code stream to the next slave chip connected in the parallel daisy-chain structure;

[0008] Repeat the above steps until all FPGA chips in the parallel daisy chain structure are configured.

[0009] Based on the above embodiment, an address space is allocated in the external memory for storing the code stream of each FPGA chip, wherein the code stream includes a bit width mode code, a command frame and a configuration code stream. The bit width mode code is used for the chip to automatically detect the bit width of the current configuration interface data; the command code includes the code stream length, a parallel daisy chain start signal and a starting address flag of the next code stream.

[0010] Based on the above embodiment, the first state machine includes an initial state, a data receiving state, a command frame detection state and a bypass state;

[0011] The master chip configures and sends itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal, including:

[0012] When the first state machine is in the initial state or the data receiving state, the master chip configures and sends itself using the configuration code stream in the first code stream.

[0013] Based on the above further embodiment, when the first state machine is in the initial state or the data receiving state, the master chip configures itself using the configuration code stream in the first code stream, specifically including:

[0014] When the first state machine is in the initial state, the main chip reads the first code stream and switches the first state machine to the data receiving state;

[0015] The master chip reads the configuration code stream according to the data length field in the first code stream, and uses the configuration code stream to complete its own configuration;

[0016] The main chip determines whether the parallel daisy chain start signal is true;

[0017] If true, pull down the chip select output port of the master chip;

[0018] The main chip reads the second code stream from the external memory according to the next code stream start address mark in the first code stream, and switches the first state machine to the command frame detection state.

[0019] Otherwise, switching the first state machine to the initial state;

[0020] The master chip executes sending the second code stream to the slave chips connected in the parallel daisy chain structure, specifically including:

[0021] When the parallel daisy chain start signal is true and the first state machine is in the command frame detection state, switching the first state machine to the bypass state;

[0022] Sending the second code stream to the slave chips connected in the parallel daisy chain structure, and switching the first state machine to a command frame detection state;

[0023] or,

[0024] When the parallel daisy chain start signal is true and the first state machine is in the bypass state, the second code stream is sent to the slave chip connected in the parallel daisy chain structure, and the first state machine is switched to the command frame detection state.

[0025] Based on the above embodiment, the second state machine includes an initial state, a data receiving state, a command frame detection state, and a data discarding state;

[0026] The slave chip receives the second code stream and configures itself using the configuration code stream in the second code stream according to the second state machine and the parallel daisy chain start signal, or sends the second code stream to the next slave chip connected in the parallel daisy chain structure, specifically including:

[0027] When the second state machine is in the initial state or the data receiving state, the slave chip configures itself using the configuration code stream in the second code stream;

[0028] When the parallel daisy chain start signal is true and the second state machine is in the command frame detection state or the data discarding state, the slave chip sends the second code stream to the slave chips connected in the parallel daisy chain structure.

[0029] Based on the above further embodiment, when the second state machine is in the initial state or the data receiving state, the slave chip configures itself using the configuration code stream in the second code stream, specifically including:

[0030] When the second state machine is in the initial state, the slave chip reads the second code stream and switches the second state machine to the data receiving state;

[0031] The slave chip reads the configuration code stream according to the data length field in the second code stream, and uses the configuration code stream to complete its own configuration;

[0032] The slave chip determines whether the parallel daisy chain start signal is true;

[0033] If true, pull down the chip select output port of the slave chip;

[0034] The slave chip switches the second state machine to a command frame detection state.

[0035] Otherwise, switch the second state machine to the initial state.

[0036] Based on the above further embodiment, when the parallel daisy chain start signal is true and the second state machine is in the command frame detection state or the data discarding state, the slave chip sends the second code stream to the slave chips connected in the parallel daisy chain structure, specifically including:

[0037] When the parallel daisy chain start signal is true and the second state machine is in the command frame detection state, switching the second state machine to the data discarding state;

[0038] Sending the second code stream to the slave chips connected in the parallel daisy chain structure, and switching the second state machine to a command frame detection state;

[0039] or,

[0040] When the parallel daisy chain start signal is true and the second state machine is in the data discarding state, the second code stream is sent to the slave chip connected in the parallel daisy chain structure, and the second state machine is switched to the command frame detecting state.

[0041] According to a second aspect, a parallel daisy-chain FPGA configuration device is provided. The parallel daisy-chain FPGA configuration device is applied to a parallel daisy-chain structure. The parallel daisy-chain structure includes an FPGA chip serving as a master chip and at least one FPGA chip serving as a slave chip. The master chip includes a first state machine configured to control a configuration process of the master chip. The slave chip includes a second state machine configured to control a configuration process of the slave chip.

[0042] The master chip is configured to read a first code stream from an external memory, wherein the first code stream includes a parallel daisy chain start signal and a configuration code stream of the master chip, and the second code stream includes a parallel daisy chain start signal and a configuration code stream of the slave chip;

[0043] The master chip is configured to configure itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal;

[0044] The master chip is configured to read a second code stream from an external memory, where the second code stream includes a parallel daisy chain start signal and a configuration code stream of the slave chip;

[0045] The slave chip is configured to send the second code stream to a slave chip connected in a parallel daisy-chain structure. The slave chip receives the second code stream and, based on the second state machine and the parallel daisy-chain start signal, configures itself using a configuration code stream in the second code stream, or sends the second code stream to the next slave chip connected in the parallel daisy-chain structure.

[0046] Based on the above embodiment, an address space is allocated in the external memory for storing the code stream of each FPGA chip, wherein the code stream includes a bit width mode code, a command frame and a configuration code stream. The bit width mode code is used for the chip to automatically detect the bit width of the current configuration interface data; the command code includes the code stream length, a parallel daisy chain start signal and a starting address flag of the next code stream.

[0047] Based on the above embodiment, the first state machine includes an initial state, a data receiving state, a command frame detection state and a bypass state;

[0048] When the first state machine is in the initial state or the data receiving state, the main chip is configured to configure itself using the configuration code stream in the first code stream.

[0049] Based on the above embodiment, when the first state machine is in the initial state, the main chip is used to read the first code stream and switch the first state machine to the data receiving state;

[0050] The master chip reads the configuration code stream according to the data length field in the first code stream, and uses the configuration code stream to complete its own configuration;

[0051] The main chip determines whether the parallel daisy chain start signal is true;

[0052] If true, pull down the chip select output port of the master chip;

[0053] The main chip reads the second code stream from the external memory according to the next code stream start address mark in the first code stream, and switches the first state machine to the command frame detection state.

[0054] Otherwise, switch the first state machine to the initial state.

[0055] Based on the above embodiment, when the parallel daisy chain start signal is true and the first state machine is in the command frame detection state, the main chip is used to switch the first state machine to the bypass state;

[0056] The master chip is configured to send the first code stream to the slave chips connected in the parallel daisy chain structure, and switch the first state machine to a command frame detection state;

[0057] or,

[0058] When the parallel daisy chain start signal is true and the first state machine is in the bypass state, the master chip is used to send the second code stream to the slave chip connected in the parallel daisy chain structure, and switch the first state machine to the command frame detection state.

[0059] Based on the above embodiment, the second state machine includes an initial state, a data receiving state, a command frame detection state, and a data discarding state;

[0060] When the second state machine is in the initial state or the data receiving state, the slave chip is configured to configure itself using the configuration code stream in the second code stream;

[0061] When the parallel daisy chain start signal is true and the second state machine is in the command frame detection state or the data discarding state, the slave chip is used to send the second code stream to the slave chips connected in the parallel daisy chain structure.

[0062] Based on the above embodiment, when the second state machine is in the initial state, the slave chip is used to read the second code stream and switch the second state machine to the data receiving state;

[0063] The slave chip reads the configuration code stream according to the data length field in the second code stream, and uses the configuration code stream to complete its own configuration;

[0064] The slave chip determines whether the parallel daisy chain start signal is true;

[0065] If true, pull down the chip select output port of the slave chip;

[0066] The slave chip switches the second state machine to a command frame detection state.

[0067] Otherwise, switch the second state machine to the initial state.

[0068] Based on the above embodiment, when the parallel daisy chain start signal is true and the second state machine is in the command frame detection state, the slave chip is used to switch the second state machine to the data discarding state;

[0069] Sending the second code stream to the slave chip connected in the parallel daisy chain structure, wherein the slave chip is used to switch the second state machine to the command frame detection state;

[0070] or,

[0071] When the parallel daisy chain start signal is true and the second state machine is in the data discarding state, the slave chip is used to send the second code stream to the slave chips connected in the parallel daisy chain structure, and switch the second state machine to the command frame detection state.

[0072] According to a third aspect, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the program, the parallel daisy chain FPGA configuration method as described in the above technical solution is implemented.

[0073] According to a fourth aspect, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the program, the parallel daisy chain FPGA configuration method as described in the above technical solution is implemented.

[0074] In the above method provided in the embodiment of this specification, the FPGA chips in the board are connected according to a parallel daisy chain structure, and the FPGA chip serving as the master chip and the FPGA chip serving as the slave chip are determined. The master chip and the slave chip control the configuration process through the state machine and the parallel daisy chain start signal in the code stream, so that the FPGA chip of the master chip serves as the main control end. Different configuration code streams can be accurately sent to the corresponding slave chip in the parallel daisy chain, thereby sending different configuration code streams to the slave chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0076] Figure 1 This is a schematic diagram of the connection structure of the parallel daisy chain provided by the present invention;

[0077] Figure 2 It is a storage schematic diagram of the external memory provided by the present invention;

[0078] Figure 3 This is a flow chart of a parallel daisy-chain FPGA configuration method provided by the present invention;

[0079] Figure 4 This is a state switching diagram of the first state machine provided by the present invention;

[0080] Figure 5 is a state switching diagram of the second state machine provided by the present invention;

[0081] Figure 6 The present invention provides a schematic diagram of a parallel daisy chain configuration process;

[0082] Figure 7 This is a schematic diagram of the parallel daisy chain configuration process provided by the present invention;

[0083] Figure 8 This is a schematic diagram of the configuration flow of the main chip provided by the present invention;

[0084] Figure 9It is a schematic diagram of the configuration flow of the slave chip provided by the present invention. DETAILED DESCRIPTION

[0085] The solution provided in this specification is described below in conjunction with the accompanying drawings.

[0086] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0087] In the description of the embodiments of the present application, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of the present application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0088] In the description of the embodiments of this application, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "plurality" means two or more.

[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0090] Multiple FPGA chips are deployed on a single board, and each needs to be configured. To facilitate FPGA chip configuration, the FPGA chips on the board are connected in a daisy-chain configuration. Specifically, multiple FPGA chips are connected in series, with each FPGA chip's output port connected to the input port of the next FPGA chip, and so on, forming a daisy-chain structure. The FPGA chip at the head of the daisy-chain is connected to an external controller, through which the FPGA chips on the board can be configured. The FPGA chips in the daisy-chain passively receive the configuration code stream sent by the external controller in sequence via a passive serial port (PS). This allows configuration information for multiple FPGA chips to be burned in a single pass through a single external controller, improving configuration efficiency and facilitating configuration. However, on its way to the FPGA chip to be configured, the configuration code stream must pass through already configured FPGA chips in the daisy-chain before finally reaching the FPGA chip to be configured. The configuration information of the configured FPGA chip will be overwritten by the configuration code stream of the FPGA chip to be configured, resulting in the same configuration information for all FPGA chips in the daisy chain. It is impossible to configure different configuration information for the FPGA chips in the daisy chain structure.

[0091] To address the issue of FPGA chips in a daisy-chain structure being able to only configure the same configuration information, this application document proposes a parallel daisy-chain FPGA configuration method. Based on the parallel daisy-chain FPGA configuration method proposed in this application document, a master chip and slave chips are set up in the parallel daisy-chain structure. The FPGA chip serving as the master chip serves as the master control terminal. The master control terminal can accurately send different configuration code streams to the corresponding slave chips in the parallel daisy chain, thereby sending different configuration code streams to the slave chips.

[0092] Figure 1 This is a schematic diagram of the connection structure of a parallel daisy chain. Figure 1As shown, the parallel daisy chain in the embodiment of the present application includes an FPGA chip configured in BPI mode as the master chip, and multiple FPGA chips configured in PS mode as slave chips. The master chip uses a BPI port to connect to the BPI port of the external memory. The PS port includes a DIN port, a CSI_N port, and a CCLK port. The chip select output port CSO_N of the master chip is connected to the chip select input port CSI_N of the first connected slave chip, and the chip select output port CSO_N of the first slave chip is connected to the chip select input port CSI_N of the second slave chip, and so on, to complete the connection of the data channel of the FPGA chip in the parallel daisy chain. In the initial state, all chip select output ports CSO_N are in an invalid state, and all chip select input ports CSI_N are also in an invalid state. Among them, the FPGA chips in the parallel daisy chain share a data port and have the same bit width, and all slave chips share the clock signal output by the master chip.

[0093] Figure 2 This is a schematic diagram of the storage of external memory. Figure 2 As shown, in an embodiment of the present application, an address space is allocated to the configuration code stream of each FPGA chip in the external memory for storing the corresponding code stream. The code stream includes a bit width mode code, a command frame, and a configuration code stream. The bit width mode code is used by the FPGA chip to automatically detect the bit width of the current configuration port data. The command frame includes basic code stream information, such as code stream length, whether to compress, whether to start a parallel daisy chain, and the starting address of the next code stream. The configuration code stream is the configuration information of the corresponding FPGA chip.

[0094] Figure 3 This is a flow chart of a parallel daisy chain FPGA configuration method. Figure 3 As shown, the parallel daisy-chain FPGA configuration method includes the following steps:

[0095] 110: The main chip reads a first code stream from the external memory, where the first code stream includes a parallel daisy chain start signal and a configuration code stream;

[0096] 120: The master chip configures itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal.

[0097] In the embodiment of the present application, an FPGA chip serving as a master chip and at least one FPGA chip serving as a slave chip are connected in a parallel daisy chain structure.

[0098] The master chip includes a first state machine for controlling the configuration process of the master chip, and the slave chip includes a second state machine for controlling the configuration process of the slave chip.

[0099] Figure 4This is a state switching diagram of the first state machine. Figure 4 As shown, the first state machine includes an initial state, a data receiving state, a command frame detecting state and a bypass state.

[0100] When the first state machine is in the initial state or the data receiving state, the main chip configures itself using the configuration code stream in the first code stream.

[0101] Specifically, when the first state machine is in the initial state, the main chip reads the first code stream and switches the first state machine to the data receiving state;

[0102] The main chip reads the configuration code stream according to the data length field in the first code stream and uses the configuration code stream to complete its own configuration;

[0103] The main chip determines whether the parallel daisy chain start signal is true;

[0104] If true, pull down the chip select output port of the main chip;

[0105] The main chip reads the second code stream from the external memory according to the starting address mark of the next code stream in the first code stream, and switches the first state machine to the command frame detection state.

[0106] Otherwise, switch the first state machine to the initial state.

[0107] , when the parallel daisy chain start signal is true and the first state machine is in the command frame detection state, switching the first state machine to the bypass state;

[0108] Sending the second code stream to the slave chips connected in the parallel daisy-chain structure, switching the first state machine to the command frame detection state;

[0109] or,

[0110] When the parallel daisy chain start signal is true and the first state machine is in the bypass state, the first code stream is sent to the slave chips connected in the parallel daisy chain structure, and the first state machine is switched to the command frame detection state.

[0111] 130: The master chip reads a second code stream from the external memory, where the second code stream includes a parallel daisy chain start signal and a configuration code stream of the slave chip;

[0112] 140: The slave chip receives the second code stream, and configures itself using the configuration code stream in the second code stream according to the second state machine and the parallel daisy chain start signal, or sends the second code stream to the next slave chip connected in the parallel daisy chain structure.

[0113] Figure 5 This is a state switching diagram of the second state machine. Figure 5As shown, the second state machine includes an initial state, a data receiving state, a command frame detecting state and a data discarding state.

[0114] When the second state machine is in the initial state or the data receiving state, the slave chip configures itself using the configuration code stream in the second code stream.

[0115] Furthermore, when the second state machine is in the initial state, the second code stream is read from the chip, and the second state machine is switched from the chip to the data receiving state;

[0116] The slave chip reads the configuration code stream according to the data length field in the second code stream, and uses the configuration code stream to complete its own configuration;

[0117] The slave chip determines whether the parallel daisy chain start signal is true;

[0118] If true, pull down the chip select output port of the slave chip;

[0119] The second state machine of the slave chip is switched to the command frame detection state.

[0120] Otherwise, switch the second state machine to the initial state.

[0121] Specifically, when the parallel daisy chain start signal is true and the second state machine is in the command frame detection state or the discard data state, the slave chip sends the second code stream to the slave chips connected in the parallel daisy chain structure.

[0122] More specifically, when the parallel daisy chain start signal is true and the second state machine is in the command frame detection state, switching the second state machine to the discard data state;

[0123] Sending the second code stream to the slave chips connected in the parallel daisy chain structure, and switching the second state machine to the command frame detection state;

[0124] or,

[0125] When the parallel daisy chain start signal is true and the second state machine is in the data discarding state, the second code stream is sent to the slave chips connected in the parallel daisy chain structure, and the second state machine is switched to the command frame detecting state.

[0126] 150: Repeat 130 to 140 until all FPGA chips in the parallel daisy chain structure are configured.

[0127] In the embodiment of the present application, the master chip and the slave chip control the configuration process through the state machine and the parallel daisy chain start signal in the code stream, so that the FPGA chip of the master chip serves as the main control end, and different configuration code streams can be accurately sent to the corresponding slave chip in the parallel daisy chain, thereby sending different configuration code streams to the slave chip.

[0128] The following is an explanation of a specific embodiment.

[0129] Figure 6 Figure 2 is a diagram of the parallel daisy chain configuration process. Figure 7 It is also a schematic diagram of the parallel daisy chain configuration process. Figure 6 and Figure 7 As shown in the figure, the configuration process of the FPGA chip in the parallel daisy chain structure is as follows:

[0130] Step 1: The main chip reads the code stream from the starting address of the external memory, parses the command frame in the code stream, obtains the start parallel daisy chain signal and the starting address of the next code stream, and the internal state machine of the main chip enters the data receiving state.

[0131] Step 2: The master chip reads the configuration code stream from the external memory based on the code stream length in the command frame. It then configures itself using the configuration code stream. It then determines whether the parallel daisy chain start signal is valid. If so, it proceeds to Step 3. Otherwise, the master chip completes its configuration.

[0132] Step 3: Pull down the chip select output port CSO_N.

[0133] Step 4: The main chip reads the next code stream from the starting address of the next code stream in the external memory, and at the same time, the internal state machine of the main chip changes to the command frame detection state.

[0134] Step 5: The master chip parses the command frame in the next bit stream, obtains the start parallel daisy chain signal and the starting address of the next bit stream, updates the start parallel daisy chain signal and the starting address of the next bit stream, adjusts the internal state machine to enter bypass mode, reads the bit stream in the external memory according to the bit stream length in the command frame, and sends the bit stream to the first slave chip.

[0135] Step 6: The first slave chip receives the code stream, detects the code stream and parses the command frame in the code stream, obtains the start parallel daisy chain signal in the command frame, and the state machine of the first slave chip switches to the receive data state.

[0136] Step 7: The first slave chip reads the code stream according to the code stream length in the command frame, configures according to the code stream, and determines whether the parallel daisy chain start signal is valid. If valid, it executes step 8. Otherwise, the configuration is completed.

[0137] Step 8: First, pull down the chip select output port CSO_N from the chip;

[0138] Step 9: First, the internal state machine of the slave chip switches to the command frame detection state.

[0139] Step 10: The first slave chip receives the bit stream, detects it, and determines whether the device's start parallel daisy chain signal is valid. If so, it parses the command frame in the bit stream and switches the internal state machine to the non-detection state. It reads the data based on the bit stream length in the command frame and sends it to the next slave chip.

[0140] Step 11: Execute steps 6 to 10 for the next slave chip until all slave chips are configured. Pull the chip select output port CSO_N high.

[0141] Through the embodiments of the present application, the configuration code stream of each FPGA chip can be accurately sent to the corresponding FPGA chip, thereby configuring different configuration information for the FPGA chips in the daisy chain structure.

[0142] Figure 8 This is a schematic diagram of the configuration flow of the main chip. Figure 8 As shown in the figure, the configuration process of the master chip in the parallel daisy chain structure is as follows:

[0143] 510: The master chip reads the data stream from the beginning, detects and parses the command frame in the data stream, obtains the start signal of the parallel daisy chain and the starting address of the next data stream, and switches the master chip's internal state machine to the data receiving state.

[0144] 520: Read data according to the data length field in the command frame to complete the configuration.

[0145] 530: Determine whether the parallel daisy chain start signal PDC is valid.

[0146] If valid, execute step 540. If invalid, switch the internal state machine to the initial state.

[0147] 540: Pull down the chip select output port.

[0148] 550: The main chip continues to read the code stream from the starting address of the next code stream and switches the internal state machine to the command frame detection state.

[0149] 560: A new command frame is detected, and the current parallel daisy chain start signal (PDC) is valid. The new command frame is parsed, and the PDC start signal and the start address of the next bitstream are updated. The internal state machine is switched to the bypass state. In this state, the master chip discards the received data. Data of the corresponding length is read according to the data length field in the command frame and transmitted to the slave chip.

[0150] 570: Determine whether the current parallel daisy chain startup signal PDC is valid.

[0151] If valid, return to step 550. Otherwise, pull the chip select output port high and switch the internal state machine to the initial state.

[0152] The above is the configuration process of the master chip in the parallel daisy chain structure. The following is the configuration process of the slave chip in the parallel daisy chain structure.

[0153] Figure 9 This is a schematic diagram of the chip configuration process. Figure 9 As shown in the figure, the configuration process of the slave chip in the parallel daisy chain structure is as follows:

[0154] 610: The nth slave chip reads the data stream from the beginning, detects and parses the command frame in the data stream, obtains the start signal for the parallel daisy chain and the starting address of the next data stream segment, and switches the internal state machine of the slave chip to the data receiving state.

[0155] 620: Read data according to the data length field in the command frame to complete the configuration.

[0156] 630: Determine whether the parallel daisy chain start signal PDC is valid.

[0157] If valid, execute step 640. If invalid, switch the internal state machine to the initial state.

[0158] 640: Pull down the chip select output port.

[0159] 650: Switch the internal state machine of the chip to the command frame detection state.

[0160] 660: A new command frame is detected, and the current parallel daisy chain start signal (PDC) is valid. The new command frame is parsed, and the PDC start signal and the start address of the next bitstream are updated. The internal state machine is switched to the UNDETECT state. In this state, the slave chip discards the received data. Data of the corresponding length is read according to the data length field in the command frame and transmitted to the slave chip.

[0161] 670: Determine whether the current parallel daisy chain startup signal PDC is valid.

[0162] If valid, return to step 650. Otherwise, pull the chip select output port high and switch the internal state machine to the initial state.

[0163] Through the above embodiment, the master chip and the slave chip control the configuration process through the state machine and the parallel daisy chain start signal in the code stream, so that the FPGA chip of the master chip can be used as the master control end, and different configuration code streams can be accurately sent to the corresponding slave chip in the parallel daisy chain, so as to realize the sending of different configuration code streams to the slave chip.

[0164] In addition, an embodiment of the present application also provides a parallel daisy-chain FPGA configuration device, which is applied to a parallel daisy-chain structure. The parallel daisy-chain structure includes an FPGA chip as a master chip and at least one FPGA chip as a slave chip. The master chip includes a first state machine, which is used to control the configuration process of the master chip. The slave chip includes a second state machine, which is used to control the configuration process of the slave chip.

[0165] A master chip is configured to read a first code stream from an external memory, wherein the first code stream includes a parallel daisy chain start signal and a configuration code stream of the master chip;

[0166] The main chip is configured to configure itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal;

[0167] A master chip is configured to read a second code stream from an external memory, wherein the second code stream includes a parallel daisy chain start signal and a configuration code stream of the slave chip;

[0168] The slave chip is used to receive the second code stream and configure itself using the configuration code stream in the second code stream or send the second code stream to the next slave chip connected in the parallel daisy chain structure according to the second state machine and the parallel daisy chain start signal.

[0169] Based on the above embodiment, the first state machine includes an initial state, a data receiving state, a command frame detection state, and a bypass state;

[0170] When the first state machine is in the initial state or the data receiving state, the main chip is configured to configure itself using the configuration code stream in the first code stream;

[0171] When the parallel daisy chain start signal is true and the first state machine is in the command frame detection state or the bypass state, the master chip is configured to send the first code stream to the slave chips connected in the parallel daisy chain structure.

[0172] Based on the above embodiment, when the first state machine is in the initial state, the main chip is used to read the first code stream and switch the first state machine to the data receiving state;

[0173] The main chip reads the configuration code stream according to the data length field in the first code stream and uses the configuration code stream to complete its own configuration;

[0174] The main chip determines whether the parallel daisy chain start signal is true;

[0175] If true, pull down the chip select output port of the main chip;

[0176] The main chip reads the second code stream from the external memory according to the starting address mark of the next code stream in the first code stream, and switches the first state machine to the command frame detection state.

[0177] Otherwise, switch the first state machine to the initial state.

[0178] Based on the above embodiments,

[0179] The master chip is used to send the second code stream to the slave chips connected in the parallel daisy chain structure, and switch the first state machine to the command frame detection state.

[0180] Based on the above embodiment, the second state machine includes an initial state, a data receiving state, a command frame detecting state, and a data discarding state;

[0181] When the second state machine is in the initial state or the data receiving state, the slave chip is configured to configure itself using the configuration code stream in the second code stream;

[0182] When the parallel daisy chain start signal is true and the second state machine is in the command frame detection state or the data discarding state, the slave chip is used to send the first code stream to the slave chips connected in the parallel daisy chain structure.

[0183] Based on the above embodiment, when the second state machine is in the initial state, the slave chip is used to read the second code stream and switch the second state machine to the data receiving state;

[0184] The slave chip reads the configuration code stream according to the data length field in the second code stream and uses the configuration code stream to complete its own configuration;

[0185] The slave chip determines whether the parallel daisy chain start signal is true;

[0186] If true, pull down the chip select output port of the slave chip;

[0187] The second state machine of the slave chip is switched to the command frame detection state.

[0188] Otherwise, switch the second state machine to the initial state.

[0189] Based on the above embodiment, when the parallel daisy chain start signal is true and the second state machine is in the command frame detection state, the slave chip is used to switch the second state machine to the discard data state;

[0190] sending the second code stream to the slave chips connected in the parallel daisy-chain structure, the slave chips being used to switch the second state machine to the command frame detection state;

[0191] or,

[0192] When the parallel daisy chain start signal is true and the second state machine is in the data discarding state, the slave chip, which is used to send the second code stream to the slave chips connected in the parallel daisy chain structure, switches the second state machine to the command frame detecting state.

[0193] According to another embodiment, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the program, the octree-based computing node load balancing method in the above technical solution is implemented.

[0194] According to another embodiment, a computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed in a computer, the computer is caused to execute a method for load balancing computing nodes based on an octree.

[0195] Those skilled in the art will appreciate that, in one or more of the above examples, the functions described herein may be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions may be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium.

[0196] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above description is only the specific implementation methods of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of this application should be included in the scope of protection of this application.

Claims

1. A parallel daisy-chain FPGA configuration method, characterized in that: An FPGA chip serving as a master chip and at least one FPGA chip serving as a slave chip are connected in a parallel daisy-chain structure, the master chip including a first state machine configured to control a configuration process of the master chip, the slave chip including a second state machine configured to control a configuration process of the slave chip, and the method comprising: The master chip reads a first code stream from an external memory, where the first code stream includes a parallel daisy chain start signal and a configuration code stream of the master chip; The master chip configures and sends itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal; The master chip reads a second code stream from an external memory, where the second code stream includes a parallel daisy chain start signal and a configuration code stream of the slave chip; The master chip executes sending the second code stream to a slave chip connected in a parallel daisy-chain structure; the slave chip receives the second code stream and, according to the second state machine and the parallel daisy-chain start signal, configures itself using a configuration code stream in the second code stream, or sends the second code stream to the next slave chip connected in the parallel daisy-chain structure; Repeat the above steps until all FPGA chips in the parallel daisy chain structure are configured.

2. The method according to claim 1, characterized in that In the external memory, an address space is allocated for storing the code stream of each FPGA chip, wherein the code stream includes a bit width mode code, a command frame and a configuration code stream. The bit width mode code is used for the chip to automatically detect the bit width of the current configuration interface data; the command frame includes the code stream length, a parallel daisy chain start signal and a starting address mark of the next code stream.

3. The method according to claim 1, characterized in that The first state machine includes an initial state, a data receiving state, a command frame detection state and a bypass state; The master chip configures and sends itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal, including: When the first state machine is in the initial state or the data receiving state, the master chip configures and sends itself using the configuration code stream in the first code stream.

4. The method according to claim 3, characterized in that When the first state machine is in the initial state or the data receiving state, the master chip configures itself using the configuration code stream in the first code stream, specifically including: When the first state machine is in the initial state, the main chip reads the first code stream and switches the first state machine to the data receiving state; The master chip reads the configuration code stream according to the data length field in the first code stream, and uses the configuration code stream to complete its own configuration; The main chip determines whether the parallel daisy chain start signal is true; If true, pull down the chip select output port of the master chip; The main chip reads the second code stream from the external memory according to the next code stream start address mark in the first code stream, and switches the first state machine to the command frame detection state. Otherwise, switching the first state machine to the initial state; The master chip executes sending the second code stream to the slave chips connected in the parallel daisy chain structure, specifically including: When the parallel daisy chain start signal is true and the first state machine is in the command frame detection state, switching the first state machine to the bypass state; Sending the second code stream to the slave chips connected in the parallel daisy chain structure, and switching the first state machine to a command frame detection state; or, When the parallel daisy chain start signal is true and the first state machine is in the bypass state, the second code stream is sent to the slave chip connected in the parallel daisy chain structure, and the first state machine is switched to the command frame detection state.

5. The method according to claim 3, characterized in that The second state machine includes an initial state, a data receiving state, a command frame detection state and a data discarding state; The slave chip receives the second code stream and configures itself using the configuration code stream in the second code stream according to the second state machine and the parallel daisy chain start signal, or sends the second code stream to the next slave chip connected in the parallel daisy chain structure, specifically including: When the second state machine is in the initial state or the data receiving state, the slave chip configures itself using the configuration code stream in the second code stream; When the parallel daisy chain start signal is true and the second state machine is in the command frame detection state or the data discarding state, the slave chip sends the second code stream to the slave chips connected in the parallel daisy chain structure.

6. The method according to claim 5, characterized in that When the second state machine is in the initial state or the data receiving state, the slave chip configures itself using the configuration code stream in the second code stream, specifically including: When the second state machine is in the initial state, the slave chip reads the second code stream and switches the second state machine to the data receiving state; The slave chip reads the configuration code stream according to the data length field in the second code stream, and uses the configuration code stream to complete its own configuration; The slave chip determines whether the parallel daisy chain start signal is true; If true, pull down the chip select output port of the slave chip; The slave chip switches the first state machine to a command frame detection state. Otherwise, switch the first state machine to the initial state.

7. The method according to claim 5, characterized in that When the parallel daisy chain start signal is true and the second state machine is in the command frame detection state or the data discarding state, the slave chip sends the second code stream to the slave chips connected in the parallel daisy chain structure, specifically including: When the parallel daisy chain start signal is true and the second state machine is in the command frame detection state, switching the second state machine to the data discarding state; Sending the second code stream to the slave chips connected in the parallel daisy chain structure, and switching the second state machine to a command frame detection state; or, When the parallel daisy chain start signal is true and the second state machine is in the data discarding state, the second code stream is sent to the slave chip connected in the parallel daisy chain structure, and the second state machine is switched to the command frame detecting state.

8. A parallel daisy-chain FPGA configuration device, characterized in that: The parallel daisy chain FPGA configuration device is applied to a parallel daisy chain structure, wherein the parallel daisy chain structure includes an FPGA chip as a master chip and at least one FPGA chip as a slave chip, wherein the master chip includes a first state machine, which is used to control the configuration process of the master chip, and the slave chip includes a second state machine, which is used to control the configuration process of the slave chip; The master chip is configured to read a first code stream from an external memory, wherein the first code stream includes a parallel daisy chain start signal and a configuration code stream of the master chip; The master chip is configured to configure itself using the configuration code stream in the first code stream according to the state of the first state machine and the parallel daisy chain start signal; The master chip is configured to read a second code stream from an external memory, where the second code stream includes a parallel daisy chain start signal and a configuration code stream of the slave chip; the slave chip is configured to receive the second code stream and, based on the second state machine and the parallel daisy chain start signal, configure itself using the configuration code stream in the second code stream or send the second code stream to the next slave chip connected in the parallel daisy chain structure.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the parallel daisy chain FPGA configuration method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, causes the processor to perform the parallel daisy-chain FPGA configuration method according to any one of claims 1 to 7.

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