System on chip and method thereof

Abstract

Disclosed are a system on chip (SoC) and a method thereof, where the SoC includes a host configured to generate a job boot, a buffer memory, a producer configured to generate data in response to the job boot and store the generated data in the buffer memory, a consumer configured to read and process the data from the buffer memory in response to job initiation, and a HiveSync monitor configured to exchange with the producer and consumer at least one ready bit indicating a ready state of the data in the buffer memory, where the ready bit indicates a ready state of the data divided into specific cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0019075 filed on February 7, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In general, in some aspects, the present disclosure relates to a system-on-chip and a memory synchronization method thereof for synchronizing buffer data between heterogeneous processors. Background Art

[0004] Artificial intelligence (AI) capabilities have recently been adopted in a variety of fields. For example, AI functions are used in various electronic devices, such as personal computers, laptops, tablets, smartphones, and digital cameras, for various functions such as voice recognition and image classification. Furthermore, with the advancement of AI technology, the development of applications utilizing AI is expanding.

[0005] To apply artificial intelligence (AI) technologies, there's a growing demand for diverse utilization of the computing resources of application processors (APs). In heterogeneous APs, data sharing between different processors is primarily synchronized in buffers. Consequently, this reduces the performance and power efficiency of APs.

[0006] As application functionality becomes more diverse, data generation and consumption patterns between processors are also becoming more diverse. One of these data generation and consumption patterns is one in which data generated by one producer is consumed by two or more consumers. However, this data generation and consumption pattern presupposes certain patterns for data writing and reading between producers and consumers, as well as 1:1 connections between buffers. This premise places restrictions on free connectivity and data sharing between computing resources. Summary of the Invention

[0007] According to some embodiments, the present disclosure relates to a system on chip (SoC) including: a host configured to generate a job launch, a buffer memory, a producer configured to generate data in response to the job launch and store the generated data in the buffer memory, a consumer configured to read and process the data from the buffer memory in response to the job launch, and a HiveSync monitor configured to exchange at least one ready bit indicating a ready state of data in the buffer memory with the producer and the consumer, wherein the ready bit indicates a ready state of data divided into specific units.

[0008] According to some embodiments, the present disclosure relates to a method for synchronizing a buffer memory of a system on chip (SoC), comprising: writing data into the buffer memory by a producer, issuing a request by the producer to write a ready bit of the data to a HiveSync monitor, issuing a read request for the ready bit by a consumer to the HiveSync monitor, and wherein when the ready bit indicates a ready state, the consumer issues a read request for the data to the buffer memory.

[0009] According to some embodiments, the present disclosure relates to a system on chip (SoC) including: a host that generates a job launch, a buffer memory, a first processor configured to generate data in response to the job launch and store the generated data in the buffer memory, a second processor configured to read and process the data from the buffer memory in response to the job launch, a third processor configured to read and process the data from the buffer memory in response to the job launch, a HiveSync monitor configured to exchange a ready bit indicating a ready state of data in the buffer memory with the first to third processors, and a system interconnect configured to provide a communication channel for each of the host, the buffer memory, the first to third processors, and the HiveSync monitor, wherein the ready bit is allocated as 1 bit per specific size unit of data stored in the buffer memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating an example of a system-on-chip (SoC) according to some embodiments.

[0012] Figure 2 is a diagram showing that according to some embodiments Figure 1 A block diagram of an example configuration of the HiveSync monitor.

[0013] Figure 3 is a diagram illustrating example field values for a physical address applied to a system interconnect according to some embodiments.

[0014] Figure 4 is a block diagram illustrating an example of a ready bit write operation of a HiveSync monitor in accordance with some implementations.

[0015] Figure 5 is a block diagram illustrating an example of a ready bit write operation of a HiveSync monitor in accordance with some implementations.

[0016] Figure 6 is a block diagram illustrating an example of a ready bit read operation of a HiveSync monitor in accordance with some implementations.

[0017] Figure 7 is a flow diagram illustrating an example of a request to write to a producer's HiveSync monitor in accordance with some implementations.

[0018] Figure 8 is a flow chart illustrating an example of a process for reading attribute bits and reading data by a consumer according to some embodiments.

[0019] Figure 9 is a table showing an example of the structure of multiple ready bits according to some embodiments.

[0020] Figure 10 A state machine is shown that illustrates the state of the Figure 9 Examples of the operational characteristics of multiple ready bit states are shown in the table.

[0021] Figure 11 is a block diagram illustrating an example of a system on a chip according to some embodiments.

[0022] Figure 12 is a schematic diagram illustrating the use of some embodiments Figure 11 A block diagram of an example of the buffer synchronization method of the HiveSync monitor described in .

[0023] Figure 13 is a timing diagram illustrating an example of a general process when the HiveSync monitor does not support synchronization of the buffer store according to some embodiments.

[0024] Figure 14 is a timing diagram illustrating an example of a task initiation process for a host when using a HiveSync monitor according to some embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings. It should be understood that both the foregoing general description and the following detailed description are exemplary and should be considered to provide additional description of the claimed invention. Reference numerals are specifically indicated in the preferred embodiments of the invention, examples of which are indicated in the accompanying drawings. Wherever possible, the same reference numerals are used in the description and drawings to refer to the same or similar parts.

[0026] Hereinafter, the term "producer" will be used to encompass processors, functional blocks, proprietary assets, and logic blocks that generate data within a system-on-chip (SoC) and store it in a buffer memory. Furthermore, the term "consumer" refers to processors, functional blocks, proprietary assets, and logic blocks that perform subsequent processing using the data generated by the producer. Throughout this disclosure, the terms "producer" and "consumer" will be used to refer to producers and consumers of data shared in a buffer memory.

[0027] Figure 1 is a block diagram illustrating an example of a system on a chip (SoC) according to some embodiments. Figure 1 In the embodiment, the system on chip 1000 may include a host 1100, a producer 1200, a consumer 1300, a HiveSync monitor 1400, a buffer memory 1500, and a system interconnector 1600. Here, the consumer 1300 may include a plurality of processors, functional blocks, or proprietary assets.

[0028] Host 1100 performs overall functions for controlling system-on-chip 1000. Host 1100 can drive system-on-chip 1000 by executing programs and / or commands stored in buffer memory 1500 or a separate operating memory. Host 1100 can be implemented using at least one of a central processing unit (CPU), a graphics processing unit (GPU), functional blocks, or proprietary assets provided in system-on-chip 1000, but is not limited thereto. In some embodiments, host 1100 can be a processor or software itself that assigns tasks to components, such as producer 1200 or consumer 1300, based on software operations.

[0029] The producer 1200 generates data according to a request from the host 1100 within the system-on-chip 1000 and stores the data in the buffer memory 1500. Based on a schedule or command from the host 1100, the producer 1200 generates data and makes a write request to the buffer memory 1500 via the system interconnect 1600. For example, the producer 1200 may be an image signal processor (ISP) that samples an image and stores the sampled image in the buffer memory 1500, or a functional block or dedicated asset dedicated to image processing.

[0030] After writing data to the buffer memory 1500, the producer 1200 writes a ready bit for the address of the buffer memory 1500 to which the data is written into the ready table 1420 of the HiveSync monitor 1400. In some embodiments, when data is written to the buffer memory 1500, the ready bit of the corresponding address can be updated by the HiveSync monitor 1400. In this manner, the ready table 1420 that can manage the ready bits of all addresses of the buffer memory 1500 can be operated.

[0031] Consumer 1300 uses the data stored in buffer memory 1500 by producer 1200 to perform the operation requested by host 1100. Consumer 1300 must read and process the data stored in buffer memory 1500. To do this, consumer 1300 reads the ready bit of the address from ready table 1420 of HiveSync monitor 1400. When the ready bit is logic '1', consumer 1300 can read the corresponding memory area of buffer memory 1500. On the other hand, when the ready bit is logic '0', consumer 1300 must wait until the ready bit switches to logic '1'. When the ready bit that consumer 1300 requested to read switches to logic '1', HiveSync monitor 1400 can send an interrupt to consumer 1300. In response to the interrupt, consumer 1300 can read the ready bit of HiveSync monitor 1400 again.

[0032] Here, at least one of the host 1100, the producer 1200, and the consumer 1300 includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a visual processing unit (VPU), an image signal processor (ISP), and a digital signal processor (DSP) to perform specialized operations. The host 1100, the producer 1200, and the consumer 1300 may be implemented as hardware, software (or firmware), or a combination of hardware and software.

[0033] The HiveSync monitor 1400 can subdivide all memory areas of the buffer memory 1500 into fine units and manage each of the subdivided fine units using a ready bit. For example, the HiveSync monitor 1400 can map the memory areas of the buffer memory 1500 to a ready bit of 1 bit per fine unit of 32 bytes or 64 bytes. In other words, the HiveSync monitor 1400 divides all storage areas of the buffer memory 1500 into 64-byte units and can map the status of each 64-byte unit to a 1-bit ready bit. This mapping of the buffer memory 1500 and the ready bit can be managed by the ready table 1420.

[0034] When the producer 1200 makes a request to write data to the buffer memory 1500, the producer 1200 will also receive a request to write the ready bit to the ready table 1420 of the HiveSync monitor 1400. And before a read request to the buffer memory 1500 occurs, the consumer 1300 first reads the status of the ready bit from the HiveSync monitor 1400. The consumer 1300 can access the buffer memory 1500 or wait until the data is ready in the buffer memory 1500 according to the status of the ready bit of the HiveSync monitor 1400.

[0035] The ready bit values of all data areas of the buffer memory 1500 can be written and updated in the ready table 1420. The HiveSync monitor 1400 can write or output the ready bit of the requested address in response to a write request or a read request from the producer 1200 or the consumer 1300. In addition, when the ready bit of the address requested to be read is logic '0', the HiveSync monitor 1400 can place the consumer 1300 in a standby state. Furthermore, when the ready bit of the address requested to be read transitions to logic '1', an interrupt can be delivered to the consumer 1300 requesting the corresponding ready bit. In response to the interrupt, the consumer 1300 can retry reading the ready bit and read data from the address area of the corresponding buffer memory 1500. The HiveSync monitor 1400 may include an SRAM for generating and updating the ready table 1420 in the form of cache lines. The ready table 1420 can be managed by load / store operations in the buffer memory 1500, which serves as system memory.

[0036] Software or data for controlling various components of the host 1100 can be loaded into the buffer memory 1500. The software or data loaded into the buffer memory 1500 is executed or processed by the host 1100, the producer 1200, and the consumer 1300. Various applications, including an operating system (OS) to be run by the host 1100, can be loaded into the buffer memory 1500. In particular, data to be shared by the producer 1200 and the consumer 1300 is loaded into the buffer memory 1500. In the present invention, the status of the shared data area or all data areas of the buffer memory 1500 can be managed in the ready table 1420 of the HiveSync monitor 1400. In other words, the ready status of the memory area of the buffer memory 1500 can be monitored and managed using a ready bit in a fine unit (e.g., a 64-byte unit). Even when multiple consumers 1300 use data, they can access the data by referring to the ready bit of the ready table 1420. Therefore, pipeline processing is possible in tasks where multiple consumers 1300 share data.

[0037] The buffer memory 1500 may include, for example, a dynamic random access memory (DRAM). However, the buffer memory 1500 is not limited thereto and may include volatile memories such as SRAM (static random access memory), flash memory, PRAM (phase change RAM), MRAM (magnetic RAM), and ReRAM (resistive RAM), as well as nonvolatile memories such as FRAM (ferroelectric RAM).

[0038] System interconnect 1600 connects the components within system-on-chip 1000, namely, host 1100, producer 1200, consumer 1300, HiveSync monitor 1400, and buffer memory 1500. System interconnect 1600 can be implemented as a network-on-chip (NoC) circuit. NoC is a scheme for connecting functional blocks by applying general network technology within a semiconductor chip. System interconnect 1600 may include router circuits and switch circuits to provide a transmission path for data or signals between multiple processors. In some embodiments, system interconnect 1600 may be implemented as a bus that applies a protocol having a predetermined standard bus standard. For example, the Advanced Microcontroller Bus Architecture (AMBA) protocol of ARM (Advanced RISC Machine) may be applied as a standard bus standard. Bus types of the AMBA protocol may include the Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4, and AXI Coherence Extensions (ACE). Among these bus types, AXI is an interface protocol between functional blocks and provides multiple prominent address functions and data interleaving functions. In addition, other types of protocols such as SONIC's uNetwork, IBM's CoreConnect, or OCP-IP's Open Core protocol may be applied to the system interconnect 1600 .

[0039] System-on-chip 1000 can be installed in an electronic device, such as a smartphone, tablet personal computer, mobile phone, personal digital assistant (PDA), laptop computer, wearable device, GPS device, e-book terminal, digital broadcast terminal, MP3 player, digital camera, wearable computer, etc. For example, the electronic device may be an Internet of Things (IoT) device or an electric vehicle. System-on-chip 1000 may be a controller or processor that controls the operation of the electronic device. System-on-chip 1000 may also be referred to as an application processor (AP), mobile AP, or control chip.

[0040] As described above, the system-on-chip 1000 of the present disclosure includes a HiveSync monitor 1400 that monitors the status of the memory area of the buffer memory 1500 in fine units. The sharing of the buffer memory 1500 between the producer 1200 and the consumer 1300 can be managed in fine units by the HiveSync monitor 1400. In particular, when a plurality of consumers 1300 consume data from the buffer memory 1500, it can be processed in a pipeline manner, enabling high processing performance. The producer 1200 and the plurality of consumers 1300 are connected to the system interconnect 1600 and are operated by the HiveSync monitor 1400 of the present disclosure. Therefore, without changing the internal structure of the host 1100, the producer 1200 and the consumer 1300 or other computing resources, efficient data sharing of the buffer memory 1500 is possible.

[0041] Figure 2 is a diagram showing that according to some embodiments Figure 1 A block diagram of an example configuration for the HiveSync monitor. Figure 2 In the embodiment of the present invention, the HiveSync monitor 1400 divides the entire physical address PA area of the buffer memory 1500 into fine units and generates and updates a ready bit for each fine unit. To this end, the HiveSync monitor 1400 may include a ready table 1420 and a table manager 1440.

[0042] The ready table 1420 can store the ready bits in the form of cache lines according to the physical address PA of the buffer memory 1500 to be written. Figure 1 ) When data is written to the area corresponding to the physical address PA of the buffer memory 1500, the data is written to the ready list 1420 from the producer 1200 or the system interconnector 1600. At this time, the physical address PA where the data is written to the buffer memory 1500 may be sent through the slave interface 1410 of the HiveSync monitor 1400.

[0043] When data is written to the memory area of buffer memory 1500 corresponding to physical address PA with index '3' and tag '50', a request to write the ready bit corresponding to physical address PA is sent from producer 1200 or system interconnect 1600 via slave interface 1410. In response, table manager 1440 writes the ready bit with index '3' and tag '50' provided in physical address PA. Here, all the ready bits included in one cache line of ready table 1420 are shown as 64 bits. That is, one cache line can be allocated to include the ready bits in a 4K (64B×64) byte area of buffer memory 1500.

[0044] On the other hand, before reading data into the memory area of buffer memory 1500 corresponding to physical address PA with index '3' and tag '50', the HiveSync monitor 1400 checks the ready bit of the corresponding area. If consumer 1300 receives a request to read the ready bit of physical address PA with index '3' and tag '50', table manager 1440 compares the cache lines with input index '3' and tag '50'. Since a tag matching the requested read tag exists at the selected index, table manager 1440 determines this as a cache hit. Furthermore, the valid bit of the cache line at index '3' is '1'. In other words, there are no invalid lines in the cache line at index '3'. Accordingly, table manager 1440 can immediately output the ready bit requested by consumer 1300. If a cache miss occurs, table manager 1440 reads the data from buffer memory 1500 and sends it to consumer 1300.

[0045] Table manager 1440 manages the cache line-based ready table 1420 using a validity checker 1441, read control logic 1443, a ready value controller 1445, and a table load / store controller 1447. Validity checker 1441 checks the validity of the cache line by referencing the input physical address PA. Read control logic 1443 can output the value of the ready bit or send an interrupt in response to a read request for the ready bit. If the requested read ready bit is still '0', read control logic 1443 instructs the consumer 1300 that issued the read request to wait. When the requested read ready bit is updated to '1', read control logic 1443 sends an interrupt to the consumer 1300 that issued the read request. Ready value controller 1445 detects the value of the ready bit requested to be written by producer 1200 from physical address PA. Ready value controller 1445 can then write at least one of the ready bits in ready table 1420 to the corresponding location as the requested write value. In addition, when consumer 1300 completes reading the ready bit, ready value controller 1445 may initialize the ready bit, which was in an invalid state, to logic '0'. Table load / store controller 1447 may update ready table 1420, which is managed in the form of cache lines in buffer memory 1500. Furthermore, in situations such as cache misses, table load / store controller 1447 may read the ready bit of buffer memory 1500 and refill the corresponding cache line. Furthermore, table load / store controller 1447 may back up or write back ready table 1420 to buffer memory 1500.

[0046] The configuration and functions of the HiveSync monitor 1400 according to some embodiments are briefly described above. However, the management technique for the ready bit of shared data using the buffer memory 1500 is not limited to the configuration of the HiveSync monitor 1400 shown. Various ready bit management methods can be implemented by making modifications or adjustments based on the above-mentioned techniques.

[0047] Figure 3 is a diagram illustrating an example of field values for a physical address applied to a system interconnect according to some embodiments. Figure 3 , the structure of the HiveSync physical address HS_PA used for a read or write request to the HiveSync monitor 1400 is shown.

[0048] A request by the producer 1200 or the consumer 1300 to the HiveSync monitor 1400 to write or read the ready bit is sent to the HiveSync attribute HS_ATT bit in the physical address B_PA of the buffer memory 1500. For example, the HiveSync physical address HS_PA may have the HiveSync attribute HS_ATT bit including the ready bit, which is added to the MSB of the physical address B_PA.

[0049] When the HiveSync attribute HS_ATT bit is '0', the corresponding physical address PA indicates a physical address that is not a monitoring target of the HiveSync monitor 1400. When a physical address having the HiveSync attribute HS_ATT bit being '0' is received, the HiveSync monitor 1400 can exclude or ignore it from the monitoring target. On the other hand, when the HiveSync attribute HS_ATT bit is '1', the corresponding physical address indicates a physical address that is a monitoring target of the HiveSync monitor 1400. The HiveSync monitor 1400 only needs to monitor the physical address having the HiveSync attribute HS_ATT bit being '1'.

[0050] Figure 4 is a block diagram illustrating an example of a ready bit write operation of a HiveSync monitor according to some embodiments. Figure 4 In FIG. 1 , the producer 1200 of the system on chip 1000 writes 64 bytes of data to the buffer memory 1500 and then requests the HiveSync monitor 1400 to set the ready bit.

[0051] First, the producer 1200 requests to write 64 bytes of data to the buffer memory 1500. When the data writing to the buffer memory 1500 is completed, the producer will subsequently generate a request to set the ready list 1420 of the HiveSync monitor 1400. The solid arrows passing through the illustrated system interconnect 1600 represent write requests to the buffer memory 1500, and the dashed arrows represent write requests to the ready bit.

[0052] The producer 1200 sends a request to the HiveSync monitor 1400 to set the ready table 1420 corresponding to the physical address PA of the data written into the buffer memory 1500. In other words, the producer 1200 requests the HiveSync monitor 1400 to set the ready bit corresponding to the physical address PA of the buffer memory 1500 to logic '1'. Then, the HiveSync monitor 1400 sets the ready bit of the address (0x000a_1080) corresponding to the physical address PA of the buffer memory 1500 to logic '1'. The addresses (0x000a_1000 to 0x000b_0000) of the HiveSync monitor 1400 must be mappable to all physical addresses of the buffer memory 1500 in 64-byte units.

[0053] Figure 5 is a block diagram illustrating an example of a ready bit write operation of a HiveSync monitor according to some embodiments. Figure 5 , the producer 1200 of the system on chip 1000 writes a plurality of 64-byte unit data to the buffer memory 1500 and then requests the HiveSync monitor 1400 to set a plurality of ready bits.

[0054] The producer 1200 requests to write a plurality of 64 bytes of data to the buffer memory 1500. When the data writing to the buffer memory 1500 is completed, the producer 1200 will then generate a request to set the ready list 1420 of the HiveSync monitor 1400. The solid arrows passing through the illustrated system interconnect 1600 represent write requests to the buffer memory 1500, and the dashed arrows represent write requests to the ready bit.

[0055] The producer 1200 sends a request to the HiveSync monitor 1400 to set the ready table 1420 corresponding to the physical address PA of the data to be written into the buffer memory 1500. In other words, the producer 1200 requests the HiveSync monitor 1400 to set the ready bit corresponding to the physical address PA of the buffer memory 1500 to logic '1'. In some embodiments, the data written by the producer 1200 to the buffer memory 1500 is 64 bytes of data (64B×5) in 5 units. In this case, the producer 1200 sends a request to the HiveSync monitor 1400 to write the ready bit corresponding to the physical address PA of the 64 bytes of data (64B×5) in 5 units.

[0056] The HiveSync monitor 1400 will set all ready bits corresponding to the physical addresses (0x000a_1080, 0x000a_10c0, 0x000a_10d0, 0x000b_1000, 0x000b_1040) of the buffer memory 1500 to logic '1' in response to the ready bit write request from the producer 1200 .

[0057] Figure 6 is a block diagram illustrating an example of a ready bit read operation of a HiveSync monitor according to some embodiments. Figure 6 In the embodiment of the present invention, the consumer 1300 of the system on chip 1000 first accesses the HiveSync monitor 1400 to read a plurality of 64-byte data in the buffer memory 1500 to check the status of a plurality of ready bits.

[0058] Consumer 1300 schedules the reading of multiple 64-byte data stored in buffer memory 1500 based on a command from host 1100. First, before reading the multiple 64-byte data, consumer 1300 accesses ready table 1420 of HiveSync monitor 1400. That is, consumer 1300 sends a read request for the ready bit to HiveSync monitor 1400 to check the ready bit of the multiple 64-byte data. Consumer 1300 accesses buffer memory 1500 based on the value of the ready bit provided by HiveSync monitor 1400.

[0059] When all the ready bits corresponding to the addresses (0x000a_1080, 0x000a_10c0, 0x000a_10d0, 0x000b_1000, 0x000b_1040) from the HiveSync monitor 1400 are checked as logic '1', the consumer 1300 sends a read request to the buffer memory 1500. On the other hand, if any one of the ready bits corresponding to the addresses (0x000a_1080, 0x000a_10c0, 0x000a_10d0, 0x000b_1000, 0x000b_1040) from the HiveSync monitor 1400 is logic '0', the consumer 1300 stops issuing read requests to the buffer memory 1500 and waits for an interrupt from the HiveSync monitor 1400. When all the ready bits corresponding to the addresses (0x000a_1080, 0x000a_10c0, 0x000a_10d0, 0x000b_1000, 0x000b_1040) are updated to logic '1', the HiveSync monitor 1400 sends an interrupt to the consumer 1300. Then, the consumer 1300 sends a read request for the ready bits corresponding to the addresses (0x000a_1080, 0x000a_10c0, 0x000a_10d0, 0x000b_1000, 0x000b_1040) from the HiveSync monitor 1400. At this time, if all the ready bits are checked to be logic '1', the consumer 1300 will send a read request to the buffer memory 1500.

[0060] Figure 7 is a flow diagram illustrating an example of a request to write to a HiveSync monitor of a producer according to some embodiments. Figure 7 In the production device (1200, see Figure 4 ) issues a data write request to the buffer memory 1500 for communicating with the consumer (1300, see Figure 4 ) synchronizes the shared memory and then issues a ready bit write request to the HiveSync monitor 1400.

[0061] In step S110, the producer 1200 generates data according to a command or schedule of the host 1100 and issues a data write request to write the generated data to the buffer memory 1500. For example, the producer 1200 may request to write 64 bytes of data to the buffer memory 1500.

[0062] In step S120, when writing data to the buffer memory 1500 in units of 64 bytes is completed, the producer 1200 requests the HiveSync monitor 1400 to write the ready bit. To request writing of the ready bit, the producer 1200 sends a setting request for the ready table 1420 corresponding to the physical address PA of the data written in the buffer memory 1500 to the HiveSync monitor 1400. For example, the producer 1200 uses the HiveSync attribute (HS_ATT, see Figure 3 ) bits of HiveSync physical address (HS_PA, see Figure 3 ) requests HiveSync monitor 1400 to set the ready bit of the corresponding physical address to logic '1'. Then, HiveSync monitor 1400 sets the ready bit corresponding to physical address PA of buffer memory 1500 in 64-byte units to '1' in ready table 1420. When HiveSync monitor 1400 completes the setting of ready table 1420, producer 1200's ready bit write request is completed.

[0063] In the above, the process in which the producer 1200 writes data to the buffer memory 1500 and requests that the attribute bits be written to the HiveSync monitor 1400 has been described. Here, the request to write the attribute bits to the HiveSync monitor 1400 can be automatically issued by the system interconnector 1600. For example, when Figure 3 When the HiveSync attribute HS_ATT bit of the HiveSync physical address (HS_PA) is '1', the attribute bit write request is sent to the HiveSync monitor 1400 at the same time as the write request is sent to the buffer memory 1500. On the other hand, when the HiveSync attribute HS_ATT bit of the HiveSync physical address HS_PA is '0', even if a write request to the buffer memory 1500 occurs, the system interconnector 1600 can skip sending the attribute bit write request to the HiveSync monitor 1400.

[0064] Figure 8 is a flow chart illustrating an example of a process for reading attribute bits and reading data by a consumer according to some embodiments. Figure 8 In the consumer 1300 (see Figure 6 ) checks the ready bit from the HiveSync monitor 1400 and then issues a read request to the buffer memory 1500 according to the value of the ready bit.

[0065] In step S210, the consumer 1300 sends a ready bit read request to the HiveSync monitor 1400 to check the ready bit of the data stored in the buffer memory 1500. The HiveSync monitor 1400 then outputs the ready bit of the ready table 1420 to the consumer 1300, which corresponds to the physical address PA of the data stored in the buffer memory 1500. Here, it is assumed that the ready bit is output as 64 bits consisting of the ready bits of data in units of 4K bytes. That is, when the ready bits requested to be read constitute a cache line, they can be output in units of 64 bits.

[0066] In step S220, the consumer 1300 checks the status of the ready bits output from the HiveSync monitor 1400. For example, the consumer 1300 determines whether all the ready bits are logic '1'. In this case, this means that the 4K bytes of data to be written to the buffer memory 1500 by the producer 1200 have been written. If all the ready bits are logic '1' ('yes' direction), the process moves to step S250. On the other hand, if there is a logic '0' in any of the ready bits ('no' direction), the process moves to step S230.

[0067] In step S230 , the consumer 1300 requests the HiveSync monitor 1400 whether the ready bit is set. That is, when all the ready bits are set to logic '1', the consumer 1300 may request an interrupt.

[0068] In step S240, the consumer 1300 monitors the interrupt transmission from the HiveSync monitor 1400. If the interrupt from the HiveSync monitor 1400 is sent ("Yes" direction), the process moves to step S210 and starts the operation of reading the ready bit. On the other hand, if the interrupt transmission from the HiveSync monitor 1400 is not detected ("No" direction), the consumer 1300 will continue to monitor the occurrence of the interrupt.

[0069] In step S250, the consumer 1300 sends a read request to the buffer memory 1500 to read the data corresponding to the 64-bit ready bit (e.g., 4KB in size). Then, the buffer memory 1500 senses the data at the indicated physical address in response to the read request and outputs it to the consumer 1300.

[0070] Here, a method of using an interrupt to make the consumer 1300 wait for the completion of setting the ready bit of the HiveSync monitor 1400 has been described, but the present disclosure is not limited thereto. That is, when all ready bits are set to logic '1', various control signals or flags can be used to deliver status information to the consumer 1300.

[0071] Figure 9 is a table showing an example of the structure of multiple ready bits according to some embodiments. Figure 9 In the SPI, the ready bit can also be implemented as multiple bits that can contain a lot of information, rather than as a single bit flag. Here, the case of configuring the ready bit with a size of 3 bits is described as an example. Therefore, the value of the multiple ready bits can be '0' to '7'.

[0072] If the value of the multi-ready bit is the initial value '0', it indicates that data is not yet ready at the address of the corresponding buffer memory 1500. In other words, the state of the ready bit being '0' indicates that the corresponding area is in an initialization state before a data write request or before data write completion. After all data in the address area is consumed and there is no more valid data, the value of the multi-ready bit can be initialized to '0'.

[0073] If the value of the multi-ready bit has a count (1, 2, 3, 4), the data write to the address area of the corresponding buffer memory 1500 is completed, and the specified number of consumers can read it. Whenever a specified consumer reads the address area from the initial setting value, the value of the multi-ready bit counts down by 1. For example, the value of the multi-ready bit is initially set to '4'. That is, the count value is set to the number of consumers specified by the producer 1200 of the data stored in the corresponding area. Therefore, there are four consumers waiting to read data from the corresponding address area. Whenever each consumer reads data from the corresponding area, the value of the multi-ready bit is deducted by 1. Here, when deducting each count value, the consumer can request to deduct the count value only when it is the last read of the allocated area. In other words, even if a consumer attempts to read the corresponding area multiple times, the count value can be deducted only in the final read operation.

[0074] When the value of the multi-ready bit is '5', data writing to the buffer memory 1500 has been completed, but the number of waiting consumers is unknown. Therefore, after a read request occurs and the corresponding area of the buffer memory 1500 is read, it can be initialized by a request from software or the host 1100.

[0075] When the value of the multi-ready bit is "6" and "7", it corresponds to the value of the cache operation of the multi-ready bit. If the number of consumers 1300 specified by the producer 1200 has all read the data, that is, when the final read occurs when the corresponding multi-ready bit is '1', the data in the corresponding buffer memory 1500 should no longer be used. Therefore, the corresponding cache line of the ready table 1420 must be discarded. Similarly, even when the number of consumers is unknown, when reading data, the corresponding cache line of the ready table 1420 must be discarded. The value of the multi-ready bit that specifies the discard target of such data can be set to '6'. If a read request occurs when the value of the multi-ready bit is '6', it must be regarded as an error. When all discarding of data is completed, the value of the multi-ready bit changes to '7'. When the value of the multi-ready bit is '7', it indicates that reuse is possible after initialization.

[0076] Figure 10 A state machine is shown that illustrates the state of the Figure 9 The table shows an example of the operating characteristics of multiple ready bit states. Figure 10 In the example, the value of the multiple ready bits set in the ready table 1420 is changed to the next state by various write requests or read requests.

[0077] In the start state S310, the value of the multiple-ready bit is initialized to '0'. In this state, a write request for the two multiple-ready bits can be provided. For example, when the value of the multiple-ready bit is requested to be written as one of the count values (cnt=1, 2, 3, 4), the state transitions to the count state S320. On the other hand, when the value of the multiple-ready bit is requested to be written as a constant value of '5', the state transitions to the constant state S330.

[0078] In the counting state S320, the value of the multi-ready bit is subtracted by 1 from the initial count value according to a read request from at least one consumer 1300. For example, it is assumed that the number of consumers designated by the producer 1200 is initially "4". Whenever each consumer reads data from the corresponding area, the value of the multi-ready bit is deducted by 1 (ready = ready-1). Here, when subtracting each count value, the consumer 1300 can request to subtract the count value only when it is the last read of the allocated area. And when the final subtracted count value (ready-1) becomes '0', the state moves to the discarding state S340 for discarding the cache line.

[0079] When a read request occurs in the constant state S330 where the value of the multi-ready bit corresponds to '5', after reading the corresponding area of the buffer memory 1500 , the state moves to the discard state S340 at the request of the software or the host 1100 .

[0080] In the discard state S340, when the value of the multi-ready bit is '6', the corresponding cache line of the ready table 1420 begins to be discarded. When the discard operation of the cache line is completed, the value of the multi-ready bit changes to '7', and the state moves to the end state S350. When a reuse request for the buffer memory 1500 occurs in the end state S350, the value of the multi-ready bit is initialized to '0', and the state moves to the start state S310.

[0081] Figure 11 is a block diagram illustrating an example of a system on a chip according to some embodiments. Figure 11 In the embodiment, the system on chip 2000 includes a host 2100, an image signal processor ISP 2200, a network processing unit NPU 2300, a graphics processing unit GPU 2350, a HiveSync monitor 2400, a buffer memory 2500 and an on-chip network NoC 2600.

[0082] The host 2100 performs overall functions to control the system on chip 2000. The host 2100 can control the operation of the system on chip 2000 by executing programs and / or instructions stored in the buffer memory 2500 or a separate operation memory. The host 2100 can be implemented with a central processing unit CPU or a specific functional block (e.g., IP) provided in the system on chip 2000, but is not limited thereto. In some embodiments, the host 2100 can be a processor that assigns tasks to components (such as ISP 2200, NPU 2300, and GPU 2350) according to the operation of the software, or the software itself running on the processor. In particular, the host 2100 of the present invention can be started simultaneously on the ISP 2200, NPU 2300, and GPU 2350, rather than sequentially, to perform tasks such as image analysis. In this case, the data stored in the buffer memory 2500 by the ISP 2200 can be accessed and processed by the NPU 2300 and GPU 2350 in a pipeline manner.

[0083] The ISP 2200 processes image data according to a request from the host 2100 and stores the image data in the buffer memory 2500. For example, the ISP 2200 may be an image processing processor that obtains a video stream based on an image signal provided by an image sensor, subsamples the video stream in specific frame units, and converts it to a target pixel format. In addition, the ISP 2200 may scale the target pixel format to a frame size that can be processed by the NPU 2300 or GPU and store it in the buffer memory 2500.

[0084] The NPU 2300 can read and process data processed by the ISP 2200 and stored in the buffer memory 2500. For example, the NPU 2300 can perform image analysis or recognition operations, such as a deep neural network DNN or a convolutional neural network CNN. To this end, the NPU 2300 can read and process some data written to the buffer memory 2500 by the ISP 2200. That is, the NPU 2300 can read and process a specific data unit for which the ready bit of the HiveSync monitor 2400 is '1'. The NPU 2300 can store the processed data back in the buffer memory 2500 and update the ready bit of the HiveSync monitor 2400 to '1'.

[0085] The GPU 2350 may read and process data processed by the NPU 2300 and stored in the buffer memory 2500. For example, the GPU 2350 may read and process some data written by the NPU 2300 to the buffer memory 2500. That is, the GPU 2350 may read and process a specific data unit for which the ready bit of the HiveSync monitor 2400 is '1'.

[0086] The HiveSync monitor 2400 can manage the ready bits of all memory areas of the buffer memory 2500. For example, the HiveSync monitor 2400 can manage a 1-bit ready bit for each 64-byte memory address of the buffer memory 2500. That is, the HiveSync monitor 2400 divides all memory areas in the buffer memory 2500 shared by the ISP 2200, the NPU 2300, and the GPU 2350 into 64-byte units and can map the status of each 64-byte to a 1-bit ready bit. This mapping of the buffer memory 2500 and the ready bit can be managed by the ready table 2420.

[0087] The ready bit values of all data areas of the buffer memory 2500 can be written and updated in the ready table 2420. The HiveSync monitor 2400 can write or output the ready bit of the requested address in response to a write or read request from any one of the ISP 2200, NPU 2300 and GPU 2350. In addition, if the ready bit of the address requested to be read is logic '0', the HiveSync monitor 2400 can cause the consumer (2200, 2300 or 2350) that sends the read request to wait. And, when the ready bit of the address requested to be read is converted to logic '1', an interrupt can be delivered to the consumer requesting the ready bit. In response to the interrupt, the consumer can retry to read the ready bit and read data from the address area of the corresponding buffer memory 2500. The HiveSync monitor 2400 may include an SRAM for generating and updating the ready table 2420 in the form of a cache line.

[0088] Software or data for controlling various components of the host 2100 may be loaded into the buffer memory 2500. The software or data loaded into the buffer memory 2500 is executed or processed by the host 2100, the ISP 2200, the NPU 2300, and the GPU 2350. Various applications (including an operating system OS to be run by the host 2100) may be loaded into the buffer memory 2500. In particular, data to be shared by the ISP 2200, the NPU 2300, and the GPU 2350 is loaded into the buffer memory 2500. In the present disclosure, the status of the shared data area or all data areas of the buffer memory 2500 may be managed in the ready table 2420 of the HiveSync monitor 2400. That is, the HiveSync monitor 2400 may monitor and manage the ready status of the memory area of the buffer memory 2500 in specific units (e.g., 64-byte units). Therefore, even when multiple consumers use data, they can access the data by referring to the ready bit of the ready table 2420. Therefore, pipeline processing is possible for certain tasks.

[0089] The buffer memory 2500 may include, for example, a dynamic random access memory (DRAM). However, the buffer memory 2500 is not limited thereto and may include volatile memories such as static random access memory (SRAM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), and resistive RAM (ReRAM), as well as nonvolatile memories such as ferroelectric RAM (FRAM).

[0090] The NoC 2600 is connected between the components within the system on chip 2000 (i.e., the host 2100, ISP 2200, NPU 2300, GPU 2350, HiveSync monitor 2400, and buffer memory 2500). The NoC 2600 may include router circuits and switching circuits to provide a transmission path for data or signals between multiple processors. In some embodiments, the NoC 2600 may be implemented as a bus that applies a protocol with a predetermined standard bus standard. For example, the Advanced Microcontroller Bus Architecture (AMBA) protocol of ARM (Advanced RISC Machine) may be applied as a bus standard. The bus types of the AMBA protocol may include Advanced High Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced Extensible Interface (AXI), AXI4, and AXI Coherence Extension (ACE). Among the above bus types, AXI is an interface protocol between functional blocks and provides multiple prominent address functions and data interleaving functions. In addition, other types of protocols such as SONIC's uNetwork, IBM's CoreConnect, and OCP-IP's open core protocol may be applied to the NoC 2600.

[0091] As described above, the system-on-chip 2000 of the present disclosure includes a HiveSync monitor 2400 that monitors the status of a memory area of the buffer memory 2500 in fine-grained memory units. The HiveSync monitor 2400 can efficiently share data consumed by multiple consumers. In particular, when multiple consumers consume data from the buffer memory 2500, processing can be performed in a pipelined manner, thereby achieving high processing performance.

[0092] Figure 12 is a schematic diagram illustrating the use of some embodiments Figure 11 A block diagram of an example of the buffer synchronization method for the HiveSync monitor described in . Figure 12 In the embodiment of the present invention, a job launch can be sent by the host 2100 simultaneously to the ISP 2200, the NPU 2300, and the GPU 2350. In addition, the ISP (2200), the NPU (2300), and the GPU (2350) can each share data in the buffer memory (2500) in fine units using the HiveSync monitor (2400), thereby allowing parallel or pipelined processing.

[0093] The ISP 2200, the NPU 2300, and the GPU 2350 each write or read data to or from the buffer memory 2500 in response to a job start from the host 2100. After writing the data to the buffer memory 2500, the ISP 2200 sets the ready bit managed by the HiveSync monitor 2400. Then, since the HiveSync monitor 2400 manages the ready bit in fine units, the consumer (such as the NPU 2300 or the GPU 2350) can read and process only the amount prepared in the buffer memory 2500. The HiveSync monitor 2400 can provide hardware support, such as updating or setting the ready bit.

[0094] Figure 13 is a timing diagram illustrating an example of a general process when the HiveSync monitor does not support synchronization of the buffer store according to some embodiments. Figure 13 In the case where there is no synchronization of the buffer memory 2500 by the HiveSync monitor 2400, the task start of the host 2100 is also sent serially.

[0095] Host 2100 (see Figure 12 ) initializes the task at time t0. And when the task initialization is completed, the host 2100 will send the task start to the ISP 2200 at time t1. Then, the ISP 2200 processes the data according to the request of the host 2100 and starts storing it in the buffer memory 2500 at time t2.

[0096] At time t3, when ISP 2200 completes storage or synchronization of buffer memory 2500, host 2100 sends a job start to NPU 2300. At time t3, NPU 2300 reads the data stored in buffer memory 2500 in response to the request from host 2100 and performs processing such as neural network calculation. At time t4, NPU 2300 starts buffer synchronization to store the processed data in buffer memory 2500. And at time t5, buffer synchronization of NPU 2300 is completed.

[0097] At t5, when the buffer synchronization of the NPU 2300 is completed, the host 2100 sends a task start to the GPU 2350. At time t5, the GPU 2350 reads the data synchronized to the buffer memory 2500 in response to the request from the host 2100 and performs processing. At time t6, the GPU 2350 stores the processed data in the buffer memory 2500. When the data storage in the buffer memory 2500 is completed, the task is completed.

[0098] Without the HiveSync monitor 2400 of the present invention that performs synchronization of buffer memories at a fine level using the ready bit, the host 2100 has no choice but to send job launches sequentially according to the data processing status of each of the ISP 2200, NPU 2300, and GPU 2350. This results in low processing performance and reduced power efficiency.

[0099] Figure 14 is a timing diagram illustrating an example of a task initiation process for a host when using a HiveSync monitor according to some embodiments. Figure 14 In the example, when the HiveSync monitor 2400 supports synchronization of the buffer memory 2500, the job launch of the host 2100 can be delivered in parallel.

[0100] Host 2100 (see Figure 12 ) initializes the task at time T0. And when the job initialization is complete, the host 2100 will send a job start to the ISP 2200, NPU 2300, and GPU 2350 at time T1. Then, the ISP 2200, NPU 2300, and GPU 2350 can start the assigned tasks at the same time. However, at time T1, the NPU 2300 and GPU 2350 must use the data generated by the ISP 2200, so they must wait until the buffer memory 2500 is synchronized. Therefore, at time T1, only the ISP 2200 will start processing data. Then, the NPU 2300 and GPU 2350 wait until the ready bit changes to the ready state after sending a read request for the ready bit to the HiveSync monitor 2400. If the ISP 2200 synchronizes the required data units to the buffer memory 2500, the HiveSync monitor 2400 will send an interrupt to the NPU 2300 and GPU 2350.

[0101] At time T2, an interrupt is sent from HiveSync monitor 2400 to NPU 2300, and NPU 2300 starts reading and processing the data loaded into buffer memory 2500. And at time T3, an interrupt is sent from HiveSync monitor 2400 to GPU 2350, and GPU 2350 starts reading and processing the data loaded into buffer memory 2500.

[0102] In this way, the two consumer NPU 2300 and GPU 2350 can read and process the data loaded into the buffer memory 2500 by the producer (i.e., ISP) until time T4, T5, T6, and T7. Therefore, the task can be completed within a relatively short period of time T8. At this time, each of the ISP 2200, the NPU 2300, and the GPU 2350 can use the ready bit corresponding to the fine unit data (e.g., 64 bytes) of the HiveSync monitor 2400 to perform synchronization of the buffer memory 2500. Therefore, the two consumer NPU 2300 and the GPU 2350 can access the data prepared in fine units in the buffer memory 2500 and perform parallel or pipeline processing.

[0103] The producer (ISP) and the consumer (NPU, GPU) can provide high processing performance through the HiveSync monitor 2400, which uses the ready bit of the present invention to synchronize the fine unit buffer memory 2500. That is, during pipeline processing, the producer (ISP) and the consumer (NPU, GPU) can load and read synchronized data from the buffer memory 2500 without the intervention of the host 2100. In addition, due to high-speed processing, power efficiency can be improved in the system on chip 2000.

[0104] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the content that may be claimed, its equivalents, and the claims to be described later. Certain features described in the context of separate embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, in some cases, one or more features from a combination may be deleted from the combination, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0105] In addition to the above-described embodiments, the subject matter of the present disclosure may encompass additional design changes or variations. In addition, the subject matter of the present disclosure will include techniques that can be modified and implemented using the embodiments.

Claims

1. A system on chip (SoC), comprising: a host computer comprising at least one processing unit configured to generate a job launch; Buffer memory; a producer configured to generate data in response to the job being started and store the generated data in the buffer memory; a consumer configured to read the data from the buffer memory and process the data in response to the job being started; and A HiveSync monitor configured to exchange at least one ready bit with the producer and the consumer, the at least one ready bit indicating a readiness status of the data in the buffer memory, The ready bit indicates the ready state of the data divided into specific units.

2. The SoC according to claim 1, wherein: The at least one ready bit is provided as 1 bit per 64 bytes of the data.

3. The SoC according to claim 1, wherein: The HiveSync Monitor includes: an SRAM configured to store and update the at least one ready bit of the physical address for the buffer memory as a ready table; and The table manager is configured to manage the ready table according to an access request from the producer or the consumer.

4. The SoC according to claim 3, wherein: The ready table is configured to arrange the at least one ready bit corresponding to the physical address of the specific unit of the buffer memory in a cache line form.

5. The SoC according to claim 4, wherein: The table manager includes: a validity checker configured to determine the validity of the physical address using the tag of the physical address; a read control logic configured to output or wait for the ready bit according to a value of the ready bit when a read request is received from the consumer; a ready value controller configured to write the value of the ready bit according to a request from the producer or the consumer; and A table load / store controller is configured to back up or write the ready table back to the buffer memory.

6. The SoC according to claim 4, wherein: The physical address includes a HiveSync attribute bit indicating whether the HiveSync monitor is subject to ready bit management.

7. The SoC according to claim 6, wherein: When the HiveSync attribute bit is logic '1', the physical address is managed as the ready list in the HiveSync monitor.

8. The SoC according to claim 1, wherein: The consumer includes at least two processors that read the data from the buffer memory and process the read data.

9. The SoC according to claim 7, wherein: The at least two processors read the data from the buffer memory using the HiveSync monitor without intervention by the host after the job is started.

10. A method for a system on chip (SoC), comprising: The producer writes the data into the buffer memory; The producer issues a request to write the ready bit of the data to the HiveSync monitor; as well as The consumer issues a read request for the ready bit to the HiveSync monitor. When the ready bit indicates a ready state, the consumer sends a read request for the data to the buffer memory.

11. The method according to claim 10, wherein: The ready bit is allocated as 1 bit for every 64 bytes of the data stored in the buffer memory.

12. The method of claim 10, further comprising issuing, by the consumer, a set request to the HiveSync monitor when the ready bit indicates an unready state.

13. The method of claim 12, further comprising sending, by the HiveSync monitor, an interrupt to the consumer in response to the setup request. 14 . The method of claim 13 , further comprising issuing, by the consumer in response to the interrupt, a read request for the ready bit to the HiveSync monitor.

15. The method according to claim 10, wherein The ready bit is composed of multiple bits indicating three or more ready states.

16. The method according to claim 15, wherein The ready state includes a start state, the number of consumers of the data, a discard state, and an end state.

17. A system on chip (SoC), comprising: a host computer comprising at least one processing unit configured to generate a job launch; Buffer memory; a first processor configured to generate data in response to the job being started, and store the generated data in the buffer memory; a second processor configured to read the data from the buffer memory and process the data in response to the job being started; a third processor configured to read the data from the buffer memory and process the data in response to the job being started; a HiveSync monitor configured to exchange ready bits with the first processor, the second processor, and the third processor, the ready bits indicating a ready status of the data in the buffer memory; as well as a system interconnect configured to provide a communication channel for each of the host, the buffer memory, the first processor, the second processor, the third processor, and the HiveSync monitor, The ready bit is allocated as 1 bit per a specific size unit of the data stored in the buffer memory.

18. The SoC according to claim 17, wherein: The specific size corresponds to 32 bytes or 64 bytes.

19. The SoC according to claim 17, wherein: The HiveSync monitor is configured to establish a ready table that manages the ready bit according to requests from the first processor, the second processor, and the third processor.

20. The SoC according to claim 19, wherein When the ready bit of the data requested by the second processor or the third processor is logic “0”, the HiveSync monitor is configured to generate an interrupt when the ready bit becomes logic “1” and send the interrupt to the second processor or the third processor.

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