Log processing method and system, electronic equipment, vehicle, medium and program product

Abstract

The invention relates to a log processing method and system, an electronic device, a vehicle, a medium and a program product, and relates to the technical field of vehicles, the method comprises the steps that under the condition that a system-on-chip is normally powered on, a first abnormal log is acquired from a storage device, and the first abnormal log is a log generated under the condition that the system-on-chip is abnormally powered off. Thus, it is ensured that the abnormal log can be effectively generated and stored under the condition that the system-on-chip is powered off abnormally, log loss caused by abnormal power-off is avoided, and the integrity of the abnormal log of the vehicle system-on-chip is guaranteed.

Description

Technical Field

[0001] The present disclosure relates to the field of vehicle technology, and in particular, to a log processing method, system, electronic device, vehicle, medium, and program product. Background Art

[0002] As a core component of intelligent driving domain controllers, the system-on-chip (SOC) plays a crucial role in the field of intelligent connected vehicles. However, an abnormal SOC power failure is highly likely to cause system failure, data loss, and ultimately threaten vehicle safety. Therefore, accurately capturing logs of abnormal SOC power failures is crucial for ensuring safe vehicle operation and improving fault diagnosis efficiency.

[0003] In the prior art, after a system-level chip is abnormally powered off, only the log information that has been written to the disk or the serial port log can be viewed, and the log information of the abnormal power-off of the system cannot be completely and accurately obtained. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a log processing method, system, electronic device, vehicle, medium and program product.

[0005] In a first aspect, the present disclosure provides a log processing method applied to a microcontroller, the method comprising: When the system-on-chip is powered on normally, a first abnormality log is obtained from a storage device, where the first abnormality log is a log generated when the system-on-chip is powered off abnormally.

[0006] Optionally, when the system-on-chip is powered on normally, obtaining the first abnormality log from the storage device includes: Determining whether the first abnormality log exists in the storage device; In a case where the first abnormality log exists in the storage device, the first abnormality log is acquired and sent to the system-on-chip.

[0007] Optionally, determining whether the first abnormality log exists in the storage device includes: In a case where a preset flag exists in the storage device, and the preset flag is a preset abnormality log flag, the first abnormality log exists in the storage device.

[0008] Optionally, after obtaining the exception log and sending the first exception log to the system-on-chip, the method further includes: A preset flag in the storage device is changed to a preset normal log flag, where the preset normal log flag indicates that the first abnormal log does not exist in the storage device.

[0009] Optionally, sending the first exception log to the system-on-chip includes: The heartbeat status of the system-on-chip is periodically monitored, and when the heartbeat status returns to normal, the first abnormality log is sent to the system-on-chip.

[0010] Optionally, the method further includes: The heartbeat status of the system-on-chip is periodically monitored to determine whether the system-on-chip has an abnormal power-off condition.

[0011] Optionally, the method comprises: In the event that the system-level chip is abnormally powered off, a second abnormal log of the system-level chip stored in the running memory is written to the storage device, and a preset flag in the storage device is updated. The second abnormal log includes the running log of the system-level chip at the time of the abnormal power-off and before.

[0012] Optionally, the abnormal power-off situation includes a first abnormal situation and a second abnormal situation; the first abnormal situation indicates that the heartbeat state of the system-level chip is abnormal; the second abnormal situation indicates that the physical serial port output of the system-level chip is interrupted and the heartbeat state of the system-level chip is abnormal.

[0013] Optionally, the preset flag includes a preset abnormality log flag, the preset abnormality log flag indicates that an abnormality log of the system-on-chip exists in the storage device, and the preset abnormality log flag includes a first preset abnormality log flag and a second preset abnormality log flag; The updating of the preset flag in the storage device includes: When the abnormal power-off condition is the first abnormal condition, updating the preset flag to the first preset abnormal log flag; When the abnormal power-off condition is the second abnormal condition, the preset flag is updated to the second preset abnormal log flag.

[0014] Optionally, the abnormal power-off includes: abnormal power-off when the system-on-chip is turned on and abnormal power-off during operation of the system-on-chip.

[0015] In a second aspect, the present disclosure provides a log processing method applied to a system-on-chip, the method comprising: When the system-on-chip is powered on normally, receiving a first abnormality log sent by the microcontroller, and saving the first abnormality log to a running memory; The first abnormality log is a log generated when the system-level chip is abnormally powered off.

[0016] Optionally, the method comprises: generating a second abnormality log according to the operation logs of the system-level chip before and during the abnormal power-off, and writing the second abnormality log into the operation memory; The abnormal power-off includes an abnormal power-off when the SoC is turned on and an abnormal power-off during operation of the SoC.

[0017] In a third aspect, the present disclosure provides a log processing system, the log processing system comprising: A microcontroller and a system-on-chip, wherein the microcontroller and the system-on-chip communicate with each other; The microcontroller is used to send a first abnormality log to the system-level chip when the system-level chip is powered on normally; the first abnormality log is a log generated by the system-level chip when it is abnormally powered off; The system-on-chip is used to generate a second abnormality log according to the operation logs of the system-on-chip when and before the abnormal power-off.

[0018] Optionally, the log processing system further includes: an operating memory, wherein the operating memory is connected to the microcontroller and the system-on-chip respectively; The running memory is used to store the first exception log and / or the second exception log.

[0019] Optionally, the log processing system further includes: Storage devices, each of which is connected to the running memory of the microcontroller; The storage device is used to store the second exception log from the running memory, and / or transmit the first exception log to the system-on-chip through the microcontroller.

[0020] Optionally, the microcontroller is further configured to monitor the operating state of the system-on-chip, and when the operating state is normal power-on, obtain the first abnormality log from the storage device, and send the first abnormality log to the system-on-chip.

[0021] Optionally, the microcontroller is further configured to: when the operating state is abnormal power-off, store the second abnormality log from the operating memory to the storage device.

[0022] Optionally, the microcontroller is further configured to update a preset flag in the storage device according to an operating status of the system-on-chip.

[0023] Optionally, the abnormal power-off includes an abnormal power-off when the system-on-chip is turned on and an abnormal power-off during operation of the system-on-chip.

[0024] Optionally, the microcontroller is a microcontroller of a vehicle, the system-on-chip is a system-on-chip of a vehicle, and the running memory is a running memory of a vehicle.

[0025] In a fourth aspect, the present disclosure provides an electronic device, comprising: a memory and a processor; The memory stores a computer program, and the processor is used to run the computer program in the memory to execute the steps of the log processing method provided in the first aspect of the present disclosure, or to execute the steps of the log processing method provided in the second aspect of the present disclosure.

[0026] In a fifth aspect, the present disclosure provides a vehicle, which includes the log processing system provided in the third aspect of the present disclosure, or the electronic device provided in the fourth aspect of the present disclosure.

[0027] In a sixth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the log processing method provided in the first aspect of the present disclosure are implemented, or the steps of the log processing method provided in the second aspect of the present disclosure are implemented.

[0028] In a seventh aspect, the present disclosure provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the log processing method provided in the first aspect of the present disclosure, or implements the steps of the log processing method provided in the second aspect of the present disclosure.

[0029] The present disclosure provides a log processing method, which obtains a first abnormal log from a storage device when the system-level chip is powered on normally. The first abnormal log is a log generated by the system-level chip when the power is abnormally cut off. Through the above technical solution, when the microcontroller detects that the system-level chip is powered off abnormally, the log generated by the system-level chip when the power is abnormally cut off will be stored in the storage device. Subsequently, once it is detected that the system-level chip has resumed normal operation, the first abnormal log will be obtained from the storage device. This process ensures that the abnormal log can be effectively generated and saved when the system-level chip is powered off abnormally, avoids the loss of logs due to abnormal power off, and ensures the integrity of the vehicle's system-level chip abnormal log. This makes it easier for subsequent technical personnel to uniformly manage and analyze the abnormal conditions of the system-level chip based on the abnormal log, so as to quickly locate the fault point, determine the cause of the abnormal power off, improve the efficiency and accuracy of fault diagnosis, and provide strong support for the safe and stable operation of the vehicle.

[0030] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings: Figure 1 The figure is a flowchart showing a log processing method according to an exemplary embodiment.

[0032] Figure 2 The flowchart of another log processing method is shown according to an exemplary embodiment.

[0033] Figure 3 The figure is a flowchart showing a log processing method according to an exemplary embodiment.

[0034] Figure 4 The figure is a schematic diagram of communication interaction according to an exemplary embodiment.

[0035] Figure 5 The figure is a flowchart showing a log processing method according to an exemplary embodiment.

[0036] Figure 6 The figure is a block diagram showing a log processing device according to an exemplary embodiment.

[0037] Figure 7 The figure is a block diagram showing another log processing device according to an exemplary embodiment.

[0038] Figure 8 The figure is a block diagram showing another log processing device according to an exemplary embodiment.

[0039] Figure 9 The figure is a block diagram showing a log processing device according to an exemplary embodiment.

[0040] Figure 10 The figure is a block diagram showing another log processing device according to an exemplary embodiment.

[0041] Figure 11 It is a block diagram of an electronic device according to an exemplary embodiment.

[0042] Figure 12 The diagram is a block diagram of a log processing system according to an exemplary embodiment.

[0043] Figure 13 is a block diagram of a vehicle according to an exemplary embodiment.

[0044] Figure 14is a block diagram of another vehicle according to an exemplary embodiment. DETAILED DESCRIPTION

[0045] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0046] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily to be construed as implying a particular order or precedence. In addition, in the description with reference to the accompanying drawings, the same reference numerals in different drawings represent the same elements.

[0047] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0048] In the description of this disclosure, unless otherwise specified, "plurality" refers to two or more than two, and other quantifiers are similar; "at least one item", "one or more items" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item a can represent any number of a; for another example, one or more items among a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural; "and / or" is a type of relationship that describes the association of related objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " indicates that the related objects are in an "or" relationship.

[0049] Although operations or steps are described in a particular order in the drawings in the embodiments of the present disclosure, this should not be understood as requiring that these operations or steps be performed in the particular order shown or in a serial order, or that all of the operations or steps shown be performed to obtain a desired result. In the embodiments of the present disclosure, these operations or steps may be performed serially; these operations or steps may also be performed in parallel; or some of these operations or steps may be performed.

[0050] Before introducing the log processing method, system, electronic device, vehicle, medium and program product provided by the present disclosure, the application scenarios involved in the various embodiments of the present disclosure are first introduced. The present disclosure can be applied in the scenario where the system-level chip is abnormally powered off. The current system-level chip log disk storage mechanism is: the vehicle's running memory collects the system-level chip's running logs in real time, and the system-level chip obtains these running logs from the running memory according to a certain period and completes the disk storage. The technicians can view the logs that have been written to the disk. The log usually contains detailed timestamps, device information, error codes and other key data. By analyzing these logs, technicians can accurately locate the specific cause of the abnormal power off of the system-level chip, and thus take targeted repair measures.

[0051] However, in real-world scenarios, when a SoC experiences an abnormal power outage, some of the most recently acquired operational logs in memory have not yet been written to disk, putting them at risk of being lost. Once these logs are lost, technicians will be unable to obtain the latest operational status information at the moment of the SoC abnormality. This significantly hinders subsequent troubleshooting and fault location, significantly impacting the accuracy and efficiency of fault diagnosis.

[0052] In order to solve the above technical problems, the present invention provides a log processing method, system, electronic device, vehicle, medium and program product. When the microcontroller detects that the system-level chip has abnormally powered off, the log generated by the system-level chip under abnormal power-off will be stored in a storage device. Subsequently, once it is detected that the system-level chip has resumed normal operation, the first abnormal log will be obtained from the storage device. This process ensures that the abnormal log can be effectively generated and saved when the system-level chip is abnormally powered off, avoids the loss of logs due to abnormal power off, and ensures the integrity of the vehicle's system-level chip abnormal log. This makes it easier for subsequent technical personnel to uniformly manage and analyze the abnormal conditions of the system-level chip based on the abnormal log, thereby quickly locating the fault point, determining the cause of the abnormal power off, improving the efficiency and accuracy of fault diagnosis, and providing strong support for the safe and stable operation of the vehicle.

[0053] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Figure 1 This is a flow chart of a log processing method according to an exemplary embodiment. The method can be applied to a microcontroller unit (MCU) of a vehicle. The vehicle also includes a system-level chip, a running memory, and a storage device. The microcontroller, the system-level chip, the running memory, and the storage device are communicatively connected. The running memory is used to read and write the running log of the system-level chip. Figure 1Said method may comprise the following steps: In step S101 , the system-on-chip is powered on normally.

[0055] In step S102, a first abnormality log is obtained from a storage device. The first abnormality log is a log generated when the system-on-chip is abnormally powered off.

[0056] In some embodiments, the first exception log can be generated by the following method: First, the system-on-chip (SoC) operation log can be obtained in real time and cached in the vehicle's operating memory. Then, when the microcontroller determines that the SoC has abnormally powered off, the second exception log of the SoC at the time of the abnormality and before the abnormality is obtained from the operating memory and stored in a storage device to obtain the first exception log. Specifically, if it is determined that the storage device does not store the exception log, the second exception log can be stored in the storage device.

[0057] For example, the running memory may include, but is not limited to, random access memory (RAM) and other running memory, and the storage device may include, but is not limited to, flash memory space such as DataFlash (a large-capacity serial Flash memory) or hard disk space. Because running memory often has very fast read and write speeds, enabling data read and write operations to be completed in a very short time, in this embodiment, the running memory can be used to read and write the system-on-chip's running log in real time. However, running memory is volatile, and data is immediately lost upon power failure. Compared to running memory, while flash memory has relatively slow read and write speeds (but significantly faster than some traditional storage devices such as mechanical hard drives, and can, to a certain extent, meet the data storage and access speed requirements of most devices), it is non-volatile, and data stored therein can be preserved for a long time even if the device loses power. Therefore, in this embodiment, the second exception log generated based on the system-on-chip's running log cached in the running memory can be stored in a storage device to prevent the loss of the exception log.

[0058] In some embodiments, as Figure 2 As shown, obtaining the first abnormality log from the storage device in step S102 includes the following steps: In step S1021, it is determined whether the first abnormality log exists in the storage device.

[0059] In this step, if a preset flag exists in the storage device and the preset flag is a preset abnormal log flag, it is determined that the first abnormal log exists in the storage device.

[0060] Among them, the preset flag can be understood as a flag bit of the storage device, which is used to mark the storage status of the storage device. For example, when the preset flag is empty (that is, there is no preset flag), it means that no log has ever been stored in the storage device. When the preset flag is not empty, the preset flag includes a preset abnormal log flag or a preset normal log flag. Among them, the preset abnormal log flag indicates that an abnormal log of the system-level chip is stored in the storage device. The preset normal log flag indicates that there is no abnormal log of the system-level chip in the storage device. Compared with the state where the preset flag is empty, the meaning of the preset normal log flag includes that an abnormal log has been stored in the storage device, and the log was subsequently cleared after being sent to the system-level chip.

[0061] In step S1022, if the first exception log exists in the storage device, the first exception log is obtained and sent to the system-on-chip.

[0062] After the first exception log is sent to the system-on-chip, the system-on-chip stores the first exception log in the running memory.

[0063] In this step, after acquiring the first exception log, the microcontroller can transmit the first exception log to the system-on-chip via a preset communication protocol (e.g., the SomeIP protocol, a scalable, service-oriented communication protocol based on IP). The system-on-chip then stores the first exception log in the running memory, thereby completing the storage of the exception log. Because data in the running memory is easily lost, after determining that the system-on-chip has abnormally powered off, the second exception log is stored in the storage device. This effectively ensures that log data that was not promptly stored to the disk during the abnormal power-off of the system-on-chip will not be lost, thereby ensuring the integrity of the exception log.

[0064] In some embodiments, the heartbeat status of the system-level chip can be periodically monitored, and when the heartbeat status returns to normal, the first abnormality log is sent to the system-level chip. Similarly, by periodically monitoring the heartbeat status of the system-level chip, it can be determined whether the system-level chip has an abnormal power-off condition.

[0065] Specifically, when the vehicle's domain controller is powered on, the microcontroller and system-level chip in the vehicle are powered on in turn. The system-level chip can periodically send heartbeat messages to the microcontroller at preset periodic intervals, so that the microcontroller can monitor the heartbeat status of the system-level chip based on the heartbeat message, and then determine whether the system-level chip is abnormally powered off or restored to normal. Under normal circumstances, if the preset periodic interval (for example, it can be 160s) is reached and the microcontroller receives the heartbeat message sent by the system-level chip, it can be determined that the heartbeat status of the system-level chip is normal, that is, the system-level chip is operating normally. Correspondingly, if the preset periodic interval is reached and the microcontroller does not receive the heartbeat message sent by the system-level chip, it can be determined that the heartbeat status of the system-level chip is abnormal, that is, the system-level chip has an abnormal power-off situation.

[0066] For example, after the microcontroller is powered on, the timer may be started at a preset periodic interval, and after the preset periodic interval is reached, it is determined whether a heartbeat message sent by the system-on-chip is received.

[0067] To improve the accuracy of detecting abnormal power-off of a SoC, if the SoC is determined to be operating normally after the first preset periodic interval after the microcontroller is powered on, the status of the SoC's physical serial port can be used to comprehensively determine whether the SoC has been abnormally powered off after each subsequent preset periodic interval. For example, if, after the preset periodic interval has elapsed, the first abnormality log is not stored in the storage device and it is determined that the output of the SoC's physical serial port is interrupted, and if no heartbeat message from the SoC is received, then it can be determined that the SoC has been abnormally powered off.

[0068] In one implementation, when the microcontroller is powered on, it can first determine whether the first exception log of the system-on-chip is stored in the storage device. If it is determined that the first exception log of the system-on-chip is not stored in the storage device, the log module (MCULOG) of the microcontroller can switch to the write state (write_to_dataflash). The microcontroller can obtain the preset flag of the storage device by calling the NVM interface, and determine whether the first exception log of the system-on-chip is stored in the storage device based on the preset flag, that is, whether the preset flag is a preset exception log flag. For example, if the preset flag is empty or 0 (wherein, empty means that the first exception log of the system-on-chip has never been stored in the storage device, and 0 means that the first exception log has been returned and no first exception log is currently available), it indicates that the first exception log of the system-on-chip is not stored in the storage device.

[0069] Afterwards, the system-on-chip is further monitored to see if it has abnormally powered off. If it is determined that the system-on-chip has abnormally powered off, a second abnormality log is generated based on the system-on-chip's operation log cached in the vehicle's operating memory and stored in a storage device, thereby obtaining a first abnormality log. If the storage device stores the system-on-chip's abnormality log, the microcontroller's log module (MCULOG) can switch to a read state (read_from_dataflash). The system-on-chip is then continuously monitored to see if it has resumed normal operation. If it is determined that the system-on-chip's heartbeat status has returned to normal, the first abnormality log of the system-on-chip is retrieved from the storage device and sent to the system-on-chip.

[0070] If the microcontroller is powered off normally while monitoring the status of the system-on-chip after the system-on-chip is powered off abnormally, then after the microcontroller is powered on again, the microcontroller can again determine whether the first abnormality log is stored in the storage device, and continue to monitor whether the heartbeat status of the system-on-chip is normal.

[0071] In addition, after the first exception log is sent to the system-level chip, the first exception log stored in the storage device can be deleted, and the preset flag in the storage device can be changed to a preset normal log flag, which indicates that the first exception log does not exist in the storage device.

[0072] The following is a detailed description of the process of generating the first abnormality log in the storage device: Considering that the causes of abnormal power-off of a SoC at different times are different, in order to further clarify the abnormal triggering scenario of abnormal power-off of the SoC so that subsequent technicians can more quickly locate the time period when the abnormality occurs, in some embodiments, abnormal power-off of the SoC is mainly divided into the following two situations: Scenario 1: The SoC experiences an abnormal power-off during startup. This means the SoC experiences an abnormal power-off immediately after powering on, meaning it has not yet completed the normal startup process, or it experiences an abnormal power-off shortly after startup. This could be due to a power supply circuit problem (such as a loose power input connector, a faulty power adapter, or a damaged power management chip on the motherboard, resulting in an inability to provide stable initial power to the SoC), a hardware initialization failure (the SoC detects a serious hardware problem during startup and automatically cuts off power to protect the device or prevent further damage), or a software problem (such as a damaged or incomplete boot loader, which prevents the SoC from properly loading necessary drivers and system files during startup, triggering an abnormal power-off).

[0073] Scenario 2: Abnormal power failure during system-on-chip operation. This refers to an unexpected power failure during operation, meaning that after the system-on-chip has completed the startup process and entered normal operation, it suddenly and unexpectedly loses power. This could be a heat dissipation issue (the system-on-chip generates a large amount of heat due to prolonged operation, and the cooling system is unable to dissipate the heat in time, triggering the overheat protection mechanism and automatically powering off), a load issue (the system-on-chip is overloaded during operation, triggering overload protection and causing a power failure), a software anomaly (for example, a serious error or deadlock in certain processes in the operating system causes a system crash, which in turn causes the device to power off. It could also be caused by malware, viruses, or other system damage, resulting in system instability and an abnormal power failure), or a hardware failure (for example, a hardware component failure during operation may cause system instability, ultimately leading to an abnormal power failure. Additionally, issues such as aging or short circuits in capacitors on the motherboard can also cause abnormal power supply during device operation).

[0074] For the above two situations, in this embodiment, the first exception log can be generated in the following way: First, a preset flag of the storage device may be determined.

[0075] The preset flags include a preset normal log flag, a first preset abnormal flag, and a second preset abnormal flag. The preset normal log flag indicates that the first abnormal log does not exist in the storage device, the first preset abnormal flag indicates that the SoC is abnormally powered off during startup, and the second preset abnormal flag indicates that the SoC is abnormally powered off during operation.

[0076] In some embodiments, upon determining that the SoC has experienced an abnormal power-off, the microcontroller may write a second abnormality log of the SoC stored in the running memory to a storage device and update a preset flag in the storage device. The abnormal power-off of the SoC includes a first abnormality and a second abnormality. The first abnormality indicates that the SoC's heartbeat status is abnormal; the second abnormality indicates that the SoC's physical serial port output is interrupted and the SoC's heartbeat status is abnormal. The first abnormality occurs when the SoC is initially determining its heartbeat status after power-on, i.e., when the SoC determines its heartbeat status for the first time after power-on, it is determined that the heartbeat status is abnormal. The second abnormality occurs when the SoC is not initially determining its heartbeat status after power-on, in which case it is necessary to further determine whether the SoC's physical serial port output is interrupted. For example, if it is determined that the SoC's physical serial port output is interrupted and the SoC's heartbeat status is abnormal, it is determined that the SoC has experienced an abnormal power-off. Specifically, updating the preset flag in the storage device may include: when the abnormal power-off situation is the first abnormal situation, updating the preset flag to a first preset abnormal log flag; or, when the abnormal power-off situation is the second abnormal situation, updating the preset flag to a second preset abnormal log flag.

[0077] In other embodiments, the abnormal power-off conditions of the second abnormality logs can be differentiated by storing the second abnormality logs for different abnormal power-off conditions in different locations on the storage device. For example, the second abnormality log obtained under the first abnormality condition can be stored in the first data block (block 1) of the storage device. Simultaneously, the preset flag of the storage device is modified to the first preset abnormality log flag, for example, 1. The second abnormality log obtained under the second abnormality condition can be stored in the second data block (block 2) of the storage device. Simultaneously, the preset flag of the storage device is modified to the second preset abnormality log flag, for example, 2.

[0078] In this way, whether the current storage device stores an abnormality log and the abnormal power-off situation corresponding to the abnormality log can be distinguished according to the preset flag of the storage device. If the preset flag is 1 or 2, it indicates that the storage device stores an abnormality log of the system-level chip.

[0079] Secondly, a second abnormality log corresponding to the system-on-chip is obtained from the storage device.

[0080] The second abnormality log is an operation log of the system-level chip at the time of and before the abnormality occurs, which is obtained from the operation memory and stored in the storage device by the microcontroller when determining that the system-level chip has an abnormality.

[0081] Finally, a first abnormality log is obtained according to the preset flag and the second abnormality log, and when it is determined that the heartbeat state of the system-level chip has returned to normal, the first abnormality log is sent to the system-level chip.

[0082] In this way, the first abnormal log received by the system-level chip not only includes its operation log when the abnormal power-off occurs, but also a preset mark for characterizing the abnormal triggering scenario, which facilitates subsequent technical personnel to locate the fault quickly.

[0083] Using the above method, when the microcontroller detects an abnormal power failure of the system-level chip, it will store the log generated by the system-level chip during the abnormal power failure in the storage device. Subsequently, once the system-level chip is detected to have resumed normal operation, the first abnormal log will be retrieved from the storage device. This process ensures that the abnormal log can be effectively generated and saved even in the case of an abnormal power failure of the system-level chip, avoiding the loss of logs due to abnormal power failures and ensuring the integrity of the vehicle's system-level chip abnormal log. This makes it easier for subsequent technicians to uniformly manage and analyze abnormal conditions of the system-level chip based on the abnormal log, thereby quickly locating the fault point, determining the cause of the abnormal power failure, improving the efficiency and accuracy of fault diagnosis, and providing strong support for the safe and stable operation of the vehicle.

[0084] Figure 3 This is a flow chart of a log processing method according to an exemplary embodiment, which is applied to a system-on-chip of a vehicle, which also includes a microcontroller, an operating memory, and a storage device; the microcontroller, the system-on-chip, the operating memory, and the storage device are communicatively connected; the operating memory is used to read and write the operating log of the system-on-chip. Figure 3 As shown, the method may include the following steps: In step S201 , the system-on-chip is powered on normally.

[0085] In step S202, a first abnormality log sent by a microcontroller is received, and the first abnormality log is saved in a running memory.

[0086] Among them, the first exception log is sent to the system-level chip by the microprocessor when the microprocessor stores the exception log of the system-level chip in the storage device of the vehicle and determines that the system-level chip is powered on normally; the first exception log is a log generated by the system-level chip when it is abnormally powered off.

[0087] After the system-level chip is abnormally powered off and restored to normal power, the first abnormal log received from the microcontroller can be stored in the running memory to complete the writing of the abnormal log to the disk, making it easier for subsequent technicians to retrieve the abnormal log of the system-level chip from the running memory.

[0088] In some embodiments, the vehicle's operating memory can obtain the operating log of the system-level chip in real time. In this way, a second abnormal log can be generated based on the operating log of the system-level chip at the time of abnormal power failure and before, and the second abnormal log can be written into the operating memory. Among them, the abnormal power failure of the system-level chip can include abnormal power failure of the system-level chip when it is turned on and abnormal power failure during the operation of the system-level chip. The specific determination method has been Figures 1 to 2 The corresponding embodiments are described in detail and will not be elaborated here.

[0089] In some embodiments, the system-on-chip may send a heartbeat message to the microcontroller at preset periodic intervals, so that the microcontroller can determine whether the system-on-chip is abnormally powered off based on the heartbeat message.

[0090] Specifically, the heartbeat modules can be deployed for the microcontroller and the system-level chip respectively. After the microcontroller and the system-level chip are powered on in sequence, the heartbeat modules of the microcontroller and the system-level chip will run respectively. Figure 4 As shown, the heartbeat module of the system-on-chip (SOC) sends a registration message to the microcontroller (MCU) for heartbeat registration. The microcontroller confirms the registration message and notifies the heartbeat module of the SOC. After receiving the confirmation message from the microcontroller's heartbeat module, the heartbeat module of the SOC periodically sends heartbeat messages to the microcontroller. The microcontroller uses this information to determine whether the SOC is operating normally (i.e., the heartbeat status). If the heartbeat module of the SOC does not periodically send heartbeat messages, the microcontroller determines that the SOC has abnormally powered off.

[0091] Regarding the method in the above embodiment, the specific way of performing the operation in each step has been Figure 1 and Figure 2 The method is described in detail in the embodiments and will not be elaborated here.

[0092] Using the above method, when the microcontroller detects an abnormal power failure of the system-level chip, it will store the log generated by the system-level chip during the abnormal power failure in the storage device. Subsequently, once the system-level chip is detected to have resumed normal operation, the first abnormal log will be retrieved from the storage device. This process ensures that the abnormal log can be effectively generated and saved even in the case of an abnormal power failure of the system-level chip, avoiding the loss of logs due to abnormal power failures and ensuring the integrity of the vehicle's system-level chip abnormal log. This makes it easier for subsequent technicians to uniformly manage and analyze abnormal conditions of the system-level chip based on the abnormal log, thereby quickly locating the fault point, determining the cause of the abnormal power failure, improving the efficiency and accuracy of fault diagnosis, and providing strong support for the safe and stable operation of the vehicle.

[0093] Figure 5 FIG. 1 is a flow chart showing a log processing method according to an exemplary embodiment. Figure 5 As shown, the method includes the following steps: In step S301 , after being powered on, the microcontroller obtains a preset flag of the storage device.

[0094] In this embodiment, the preset flag may include empty, 0, 1, and 2. Empty indicates that no abnormality log of the SoC has been stored in the storage device; 0 indicates that no abnormality log has been returned; 1 indicates that the SoC has been abnormally powered off after power-on, and an abnormality log is stored in the first data block; and 2 indicates that the SoC has been abnormally powered off during operation, and an abnormality log is stored in the second data block.

[0095] In step S302 , it is determined whether the preset flag is empty or 0.

[0096] When it is determined that the preset flag is empty or 0, it indicates that no abnormal log is stored in the storage device, and step S303 is executed, and the log module of the microcontroller is switched to a write state.

[0097] When it is determined that the preset flag is neither empty nor 0, it indicates that an abnormality log is stored in the storage device, and step S307 is executed.

[0098] In step S303, the log module of the microcontroller switches to a write state and determines for the first time whether a heartbeat message sent by the system-on-chip is received.

[0099] Wherein, whether the heartbeat message sent by the system-level chip is received can be determined according to a preset periodic interval.

[0100] When it is determined that the heartbeat message sent by the system-on-chip is received for the first time, it indicates that the current system-on-chip is operating normally, and step S304 is executed; When it is determined for the first time that the heartbeat message sent by the system-on-chip is not received, it indicates that the current system-on-chip is abnormally powered off after being powered on, and step S305 is executed.

[0101] In step S304 , it is determined whether the output of the physical serial port of the system-on-chip is interrupted and periodically determined whether the heartbeat message sent by the system-on-chip is not received.

[0102] If it is determined that the output of the physical serial port of the SoC is interrupted and it is periodically determined that no heartbeat message sent by the SoC is received, it indicates that the current SoC is abnormally powered off, and step S306 is executed; Otherwise, return to step S304.

[0103] In step S305 , a second abnormality log of the system-on-chip is obtained from the running memory, and the second abnormality log is stored in a first data block of a storage device.

[0104] At this time, the preset flag of the storage device may be updated to 1.

[0105] In step S306, a second abnormality log of the system-on-chip is obtained from the running memory, and the second abnormality log is stored in a second data block of the storage device.

[0106] At this time, the preset flag of the storage device may be updated to 2.

[0107] After step S305 and step S306, the log modules of the microcontroller are switched to a read state.

[0108] In step S307 , the log module of the microcontroller switches to a read state and periodically determines whether a heartbeat message sent by the system-on-chip is received.

[0109] If it is determined that the heartbeat message sent by the system-level chip is received, step S308 is executed; Otherwise, return to step S307.

[0110] In step S308 , the microprocessor obtains the first abnormality log from the storage device and sends the first abnormality log to the system-on-chip.

[0111] The first abnormality log may be obtained according to the second abnormality log stored in the storage device and a preset flag of the storage device.

[0112] After the microprocessor exception log is recorded and sent to the system-on-chip, the preset flag of the storage device is updated to 0.

[0113] In step S309 , the system-on-chip stores the first abnormality log in the running memory.

[0114] Regarding the method in the above embodiment, the specific way of performing the operation in each step has been Figures 1 to 4 The method is described in detail in the embodiments and will not be elaborated here.

[0115] Using the above method, when the microcontroller detects an abnormal power failure of the system-level chip, it will store the log generated by the system-level chip during the abnormal power failure in the storage device. Subsequently, once the system-level chip is detected to have resumed normal operation, the first abnormal log will be retrieved from the storage device. This process ensures that the abnormal log can be effectively generated and saved even in the case of an abnormal power failure of the system-level chip, avoiding the loss of logs due to abnormal power failures and ensuring the integrity of the vehicle's system-level chip abnormal log. This makes it easier for subsequent technicians to uniformly manage and analyze abnormal conditions of the system-level chip based on the abnormal log, thereby quickly locating the fault point, determining the cause of the abnormal power failure, improving the efficiency and accuracy of fault diagnosis, and providing strong support for the safe and stable operation of the vehicle.

[0116] Figure 6is a block diagram of a log processing device according to an exemplary embodiment, which is applied to a microcontroller, such as Figure 6 As shown, the apparatus 400 includes: The acquisition module 401 is configured to acquire a first abnormality log from a storage device when the system-on-chip is powered on normally. The first abnormality log is a log generated when the system-on-chip is powered off abnormally.

[0117] Optionally, the acquisition module 401 is configured to determine whether the first exception log exists in the storage device; if the first exception log exists in the storage device, acquire the first exception log and send the first exception log to the system-level chip.

[0118] Optionally, the acquiring module 401 is configured to determine that, when a preset flag exists in the storage device and the preset flag is a preset abnormality log flag, the first abnormality log exists in the storage device.

[0119] Optionally, after obtaining the exception log and sending the first exception log to the system-level chip, as shown in FIG. Figure 7 As shown, the device 400 further includes: The flag module 402 is configured to change a preset flag in the storage device to a preset normal log flag, where the preset normal log flag indicates that the first abnormal log does not exist in the storage device.

[0120] Optionally, the acquisition module 401 is configured to periodically monitor the heartbeat status of the system-on-chip, and when the heartbeat status returns to normal, send the first abnormality log to the system-on-chip.

[0121] Optionally, the acquisition module 401 is further configured to periodically monitor the heartbeat status of the system-level chip to determine whether the system-level chip experiences abnormal power-off.

[0122] Alternatively, as Figure 8 As shown, the device 400 further includes: The storage module 403 is used to write the second abnormal log of the system-level chip stored in the running memory into the storage device and update the preset flag in the storage device when the system-level chip is abnormally powered off, and the second abnormal log includes the running log of the system-level chip when and before the abnormal power off occurs.

[0123] Optionally, the abnormal power-off situation includes a first abnormal situation and a second abnormal situation; the first abnormal situation indicates that the heartbeat state of the system-level chip is abnormal; the second abnormal situation indicates that the physical serial port output of the system-level chip is interrupted, and the heartbeat state of the system-level chip is abnormal.

[0124] Optionally, the preset flag includes a preset exception log flag, which indicates that there is an exception log of the system-level chip in the storage device, and the preset exception log flag includes a first preset exception log flag and a second preset exception log flag; the storage module 403 is used to update the preset flag to the first preset exception log flag when the abnormal power-off condition is the first abnormal condition; and to update the preset flag to the second preset exception log flag when the abnormal power-off condition is the second abnormal condition.

[0125] Optionally, the abnormal power-off includes: abnormal power-off when the system-level chip is turned on and abnormal power-off during operation of the system-level chip.

[0126] Using the above device, when the microcontroller detects an abnormal power failure of the SoC, it will store the log generated by the SoC during the abnormal power failure in a storage device. Subsequently, once the SoC is detected to have resumed normal operation, the first abnormal log will be retrieved from the storage device. This process ensures that the abnormal log can be effectively generated and saved even in the event of an abnormal power failure of the SoC, avoiding log loss due to abnormal power failures and ensuring the integrity of the vehicle's SoC abnormal log. This facilitates subsequent technical personnel to uniformly manage and analyze SoC abnormalities based on the abnormal log, thereby quickly locating the fault point, determining the cause of the abnormal power failure, improving the efficiency and accuracy of fault diagnosis, and providing strong support for the safe and stable operation of the vehicle.

[0127] Figure 9 is a block diagram of a log processing device according to an exemplary embodiment, which is applied to a system-level chip, such as Figure 9 As shown, the device 500 includes: When the system-level chip is powered on normally, the receiving module 501 receives the first abnormality log sent by the microcontroller and saves the first abnormality log to the running memory; the first abnormality log is a log generated when the system-level chip is powered off abnormally.

[0128] Alternatively, as Figure 10 As shown, the device 500 further includes: The writing module 502 is used to generate a second abnormal log based on the operation log of the system-level chip when and before the abnormal power-off, and write the second abnormal log into the operation memory; the abnormal power-off includes the abnormal power-off of the system-level chip when it is turned on and the abnormal power-off during the operation of the system-level chip.

[0129] Using the above device, when the microcontroller detects an abnormal power failure of the SoC, it will store the log generated by the SoC during the abnormal power failure in a storage device. Subsequently, once the SoC is detected to have resumed normal operation, the first abnormal log will be retrieved from the storage device. This process ensures that the abnormal log can be effectively generated and saved even in the event of an abnormal power failure of the SoC, avoiding log loss due to abnormal power failures and ensuring the integrity of the vehicle's SoC abnormal log. This facilitates subsequent technical personnel to uniformly manage and analyze SoC abnormalities based on the abnormal log, thereby quickly locating the fault point, determining the cause of the abnormal power failure, improving the efficiency and accuracy of fault diagnosis, and providing strong support for the safe and stable operation of the vehicle.

[0130] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0131] Figure 11 FIG. 6 is a block diagram of an electronic device 600 according to an exemplary embodiment. Figure 11 As shown, the electronic device 600 may include: a processor 601 , a memory 602 , and may further include one or more of a multimedia component 603 , an input / output (I / O) interface 604 , and a communication component 605 .

[0132] The processor 601 is used to control the overall operation of the electronic device 600 to complete all or part of the steps in the log processing method described above. The memory 602 is used to store various types of data to support the operation of the electronic device 600. This data may include, for example, instructions for any application or method operating on the electronic device 600, as well as application-related data such as contact information, sent and received messages, images, audio, and video. The memory 602 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The multimedia component 603 may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 602 or sent through the communication component 605. The audio component also includes at least one speaker for outputting audio signals. The I / O interface 604 provides an interface between the processor 601 and other interface modules, and the above-mentioned other interface modules may be a keyboard, a mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 605 is used for wired or wireless communication between the electronic device 600 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G or 4G, or a combination of one or more of them, so the corresponding communication component 605 may include: a Wi-Fi module, a Bluetooth module, an NFC module.

[0133] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-mentioned log processing method.

[0134] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided. When executed by a processor, the program instructions implement the steps of the log processing method described above. For example, the computer-readable storage medium may be the aforementioned memory 602 including the program instructions. The program instructions may be executed by the processor 601 of the electronic device 600 to perform the log processing method described above.

[0135] In another exemplary embodiment, a computer program product is further provided. The computer program product includes a computer program that can be executed by a processor. When the computer program is executed by the processor, the steps of the above-mentioned log processing method are implemented.

[0136] In some embodiments, as Figure 12 As shown, the present disclosure provides a log processing system 700, which includes: A microcontroller 701 and a system-on-chip 702 , wherein the microcontroller 701 and the system-on-chip 702 communicate with each other; The microcontroller 701 is configured to send a first abnormality log to the system-on-chip when the system-on-chip 702 is powered on normally; the first abnormality log is a log generated when the system-on-chip 702 is powered off abnormally; The microcontroller 701 is also used to implement Figures 1 to 2 The technical solutions in the provided embodiments.

[0137] The SoC 702 is configured to generate a second abnormality log according to the operation logs of the SoC 702 before and during abnormal power-off.

[0138] The system-on-chip 702 is also used to implement Figures 3 and 4 The technical solutions in the provided embodiments.

[0139] Optionally, the log processing system 700 further includes: The operating memory 703 is connected to the microcontroller 701 and the system-on-chip 702 respectively; The running memory 703 is used to store the first exception log and / or the second exception log.

[0140] Optionally, the log processing system 700 further includes: A storage device 704, which is connected to the microcontroller 701, the system-on-chip 702 and the running memory 703 respectively; The storage device 704 is configured to store the second exception log from the operating memory 703 and / or transmit the first exception log to the system-on-chip 702 via the microcontroller 701 .

[0141] Optionally, the microcontroller 701 is further configured to monitor the operating state of the system-on-chip 702 , and when the operating state is normal power-on, obtain the first exception log from the storage device 704 , and send the first exception log to the system-on-chip 702 .

[0142] So that the system-on-chip 702 stores the first abnormality log in the running memory 703.

[0143] Optionally, the microcontroller 701 is further configured to: when the operating state is abnormal power-off, store the second abnormality log from the operating memory 703 to the storage device 704 .

[0144] Optionally, the microcontroller 701 is further configured to update a preset flag in the storage device 704 according to the operating status of the system-on-chip 702 .

[0145] Specifically, the abnormal power-off condition of the system-level chip includes a first abnormal condition and a second abnormal condition; the first abnormal condition indicates that the heartbeat state of the system-level chip is abnormal; the second abnormal condition indicates that the physical serial port output of the system-level chip is interrupted and the heartbeat state of the system-level chip is abnormal. The preset flag includes a preset abnormal log flag, which indicates that an abnormal log of the system-level chip exists in the storage device, and the preset abnormal log flag includes a first preset abnormal log flag and a second preset abnormal log flag; updating the preset flag in the storage device includes: if the abnormal power-off condition is the first abnormal condition, updating the preset flag to the first preset abnormal log flag; if the abnormal power-off condition is the second abnormal condition, updating the preset flag to the second preset abnormal log flag.

[0146] Optionally, the abnormal power-off includes an abnormal power-off when the system-level chip is turned on and an abnormal power-off during operation of the system-level chip.

[0147] Optionally, the microcontroller 701 is a microcontroller of a vehicle, the system-on-chip 702 is a system-on-chip of a vehicle, and the running memory 703 is a running memory of a vehicle.

[0148] In some embodiments, respectively Figure 13 and 14 As shown, the present disclosure also provides a vehicle 800, comprising the above Figure 11 The electronic device 600 or Figure 12 A log processing system 700 is provided.

[0149] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the scope of protection of the present disclosure.

[0150] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0151] In addition, the various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A log processing method, characterized in that: Applied to a microcontroller, the method includes: When the system-on-chip is powered on normally, a first abnormality log is obtained from a storage device, where the first abnormality log is a log generated when the system-on-chip is powered off abnormally.

2. The method according to claim 1, characterized in that The step of obtaining a first abnormality log from a storage device when the system-level chip is powered on normally includes: Determining whether the first abnormality log exists in the storage device; In a case where the first abnormality log exists in the storage device, the first abnormality log is acquired and sent to the system-on-chip.

3. The method according to claim 2, characterized in that The determining whether the first abnormality log exists in the storage device includes: In a case where a preset flag exists in the storage device, and the preset flag is a preset abnormality log flag, the first abnormality log exists in the storage device.

4. The method according to claim 3, characterized in that After obtaining the exception log and sending the first exception log to the system-on-chip, the method further includes: A preset flag in the storage device is changed to a preset normal log flag, where the preset normal log flag indicates that the first abnormal log does not exist in the storage device.

5. The method according to claim 2, characterized in that The sending the first exception log to the system-on-chip includes: The heartbeat status of the system-on-chip is periodically monitored, and when the heartbeat status returns to normal, the first abnormality log is sent to the system-on-chip.

6. The method according to claim 1, characterized in that The method further comprises: The heartbeat status of the system-on-chip is periodically monitored to determine whether the system-on-chip has an abnormal power-off condition.

7. The method according to claim 6, characterized in that The method comprises: In the event that the system-level chip is abnormally powered off, a second abnormal log of the system-level chip stored in the running memory is written to the storage device, and a preset flag in the storage device is updated. The second abnormal log includes the running log of the system-level chip at the time of the abnormal power-off and before.

8. The method according to claim 7, characterized in that The abnormal power-off condition includes a first abnormal condition and a second abnormal condition; the first abnormal condition indicates that the heartbeat state of the system-level chip is abnormal; the second abnormal condition indicates that the physical serial port output of the system-level chip is interrupted and the heartbeat state of the system-level chip is abnormal.

9. The method according to claim 8, characterized in that The preset flag includes a preset abnormal log flag, the preset abnormal log flag indicates that there is an abnormal log of the system-level chip in the storage device, and the preset abnormal log flag includes a first preset abnormal log flag and a second preset abnormal log flag; The updating of the preset flag in the storage device includes: When the abnormal power-off condition is the first abnormal condition, updating the preset flag to the first preset abnormal log flag; When the abnormal power-off condition is the second abnormal condition, the preset flag is updated to the second preset abnormal log flag.

10. The method according to any one of claims 1 to 9, characterized in that The abnormal power-off includes: abnormal power-off when the SoC is turned on and abnormal power-off when the SoC is running.

11. A log processing method, characterized in that: Applied to a system-on-chip, the method includes: When the system-on-chip is powered on normally, receiving a first abnormality log sent by the microcontroller, and saving the first abnormality log to a running memory; The first abnormality log is a log generated when the system-level chip is abnormally powered off.

12. The method according to claim 11, characterized in that The method comprises: generating a second abnormality log according to the operation logs of the system-level chip before and during the abnormal power-off, and writing the second abnormality log into the operation memory; The abnormal power-off includes an abnormal power-off when the SoC is turned on and an abnormal power-off during operation of the SoC.

13. A log processing system, characterized in that: The log processing system includes: A microcontroller and a system-on-chip, wherein the microcontroller and the system-on-chip communicate with each other; The microcontroller is used to send a first abnormality log to the system-level chip when the system-level chip is powered on normally; the first abnormality log is a log generated by the system-level chip when it is abnormally powered off; The system-on-chip is used to generate a second abnormality log according to the operation logs of the system-on-chip when and before the abnormal power-off.

14. The system according to claim 13, wherein: The log processing system further includes: an operating memory, wherein the operating memory is connected to the microcontroller and the system-on-chip respectively; The running memory is used to store the first exception log and / or the second exception log.

15. The system according to claim 13, wherein: The log processing system further includes: a storage device, the storage device being connected to the microcontroller and the running memory respectively; The storage device is used to store the second exception log from the running memory, and / or transmit the first exception log to the system-on-chip through the microcontroller.

16. The system according to claim 15, wherein: The microcontroller is further configured to monitor the operating state of the system-on-chip, and when the operating state is normal power-on, obtain the first abnormality log from the storage device, and send the first abnormality log to the system-on-chip.

17. The system according to claim 16, wherein: The microcontroller is further configured to: when the operating state is abnormal power-off, store the second abnormality log from the operating memory to the storage device.

18. The system according to claim 17, wherein: The microcontroller is further configured to update a preset flag in the storage device according to the operating status of the system-on-chip.

19. The system according to any one of claims 13 to 18, characterized in that The abnormal power-off includes an abnormal power-off when the SoC is turned on and an abnormal power-off during operation of the SoC.

20. The system according to any one of claims 13 to 18, characterized in that The microcontroller is a microcontroller of a vehicle, the system-level chip is a system-level chip of a vehicle, and the running memory is the running memory of the vehicle.

21. An electronic device, characterized in that: include: memory and processor; The memory stores a computer program, and the processor is configured to run the computer program in the memory to execute the steps of the method according to any one of claims 1 to 10, or to execute the steps of the method according to any one of claims 11 to 12.

22. A vehicle, characterized in that: The vehicle includes the log processing system according to any one of claims 13 to 20, or the electronic device according to claim 21.

23. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 10, or the steps of the method according to any one of claims 11 to 12.

24. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 10, or implements the steps of the method according to any one of claims 11 to 12.

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