FPGA prototype verification coverage rate monitoring system based on multi-dimensional monitoring and dynamic optimization
By building a multi-dimensional coverage monitoring architecture and an adaptive data storage and transmission solution, combined with time-sequence-aware instrumentation technology, the problems of single monitoring dimensions, extended data reading time and inefficient storage efficiency in the FPGA prototype verification system are solved, and efficient coverage monitoring and data transmission are achieved to adapt to complex circuit designs.
Patent Information
- Application Number
- CN202510511364.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-08-08
AI Technical Summary
The monitoring dimensions in the existing FPGA prototype verification system are single, the data reading time is extended, the insert structure affects the system performance, and the data storage efficiency is inefficient, which cannot meet the verification needs of complex circuit designs.
Build a multi-dimensional coverage monitoring architecture, including coverage detection units of the foundation layer, state layer and functional layer, adopts an adaptive data storage and transmission scheme, and combines time-aware instrumentation technology to solve the problems of cross-clock domain data acquisition and instrumentation timing offset.
It realizes multi-dimensional coverage monitoring, reduces data reading delay, improves storage and transmission efficiency, ensures system performance, and adapts to complex circuit design verification.
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Figure CN120449782A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit verification, and in particular to an FPGA prototype verification coverage monitoring system based on multi-dimensional monitoring and dynamic optimization. Background Art
[0002] In the integrated circuit design process, FPGA prototyping is a critical step in ensuring the correctness of design functionality. Coverage monitoring assesses the extent to which test cases cover the design functionality, providing an important basis for design verification. However, existing FPGA prototyping coverage monitoring technologies suffer from the following significant drawbacks, which severely hinder the performance improvement and application expansion of FPGA prototyping systems: 1) The monitoring dimension is limited. Existing FPGA prototyping system coverage monitoring methods often focus on a single dimension of coverage, such as trigger flip coverage. However, actual system application coverage depends not only on flip-flops but also on multiple factors, such as state machine coverage and key control signal combinational logic. Single-dimensional monitoring cannot fully verify the functional coverage of complex designs and is difficult to meet the verification requirements of complex circuit designs. 2) Data read latency: In FPGA prototype verification systems, the traditional shift register chain read method is often used to read coverage data. This data read method is acceptable for small-scale design applications, but when the design scale increases, the latency problem will be exacerbated. In particular, when the number of triggers exceeds 10,000, the data read time will exceed the actual test time, seriously hindering the verification process. 3) The instrumentation structure significantly affects system performance. In FPGA prototype verification systems, the current mainstream instrumentation structure is a fixed instrumentation structure. This method lacks effective management of timing margins, especially in high-speed clock domains. The instrumentation structure easily introduces additional timing delays, resulting in reduced prototype system performance. No effective solution has yet been found in current FPGA prototype verification systems. 4) Data storage mode: Existing data storage solutions have limitations in targeted processing of coverage data. Coverage data is sparse, and a large amount of data contains many zero values or repeated values. Existing data storage modes do not effectively utilize this data feature, resulting in low data transmission and storage efficiency. Summary of the Invention
[0003] In order to solve the above technical problems, the present invention provides an FPGA prototype verification coverage monitoring system based on multi-dimensional monitoring and dynamic optimization.
[0004] The technical solution of the present invention is:
[0005] An FPGA prototype verification coverage monitoring system and method based on multi-dimensional monitoring and dynamic optimization includes a multi-dimensional coverage fusion monitoring architecture for FPGA prototype verification systems, an adaptive data storage and transmission part for FPGA prototype verification systems, and a timing-aware instrumentation technology part for FPGA prototype verification systems, which specifically solves the four types of problems mentioned above.
[0006] First, a three-level coverage monitoring unit was constructed for the multi-dimensional coverage fusion monitoring architecture of the FPGA prototype verification system, achieving multi-dimensional coverage monitoring. The base layer meticulously monitors D-flip flop flips, accurately capturing information about flip-flop state changes. The state layer incorporates a finite state machine state transition path recording module, providing critical support for analyzing complex state machine behavior. The functional layer incorporates a key control signal combinational logic assertion capture unit to capture key control signal combinational logic and ensure comprehensive functional verification.
[0007] Secondly, for the adaptive data storage and transmission part of the FPGA prototype verification system, the FPGA physical layout is divided into multiple independent monitoring areas, and in the independent monitoring areas, modules are used as units, and the coverage data characteristics are fully utilized to build a coverage data collection, storage, and transmission solution, which effectively reduces data reading delay and improves coverage data storage efficiency.
[0008] Finally, for the timing-aware instrumentation technology for the FPGA prototype verification system, a clock domain analysis module was built to automatically identify cross-clock domain module paths. A dedicated synchronization monitoring unit was inserted into the metastable isolation zone to prevent metastable issues from interfering with coverage monitoring. Furthermore, a dynamically adjustable sampling window was built to adapt to the changing characteristics of signals in different clock domains, and a phase compensation circuit was developed to eliminate timing deviations introduced by the instrumentation module.
[0009] Further,
[0010] The basic layer coverage detection unit identifies all D flip-flops in the monitoring module, builds a data link for the associated D flip-flop data port D / Q, and uses the system clock of the D flip-flop as the sampling clock to determine whether the D flip-flop has data flipping. When the monitored D flip-flop has data flipping, the data acquisition module is triggered to work and record the clock edge category of the current data flip, i.e., the rising edge / falling edge and the current time of the data flip. When the monitored D flip-flop has no data flipping or the basic layer coverage detection unit is not enabled, the data acquisition module remains silent and does not occupy system power consumption and coverage data storage space.
[0011] The state layer coverage detection unit identifies the state machine logic in the monitoring module. First, it uses binary coding to assign a unique code to each state in the module. Secondly, the state layer coverage detection unit will continuously monitor the state transfer trigger conditions of the state machine. The state transfer of the state machine is usually triggered by an external input signal, an internal logic condition or the edge of a clock signal. When the state transfer trigger signal is detected to be valid, the state layer coverage detection unit will immediately start the recording process to record the current state machine state and the target state of the state machine after the transfer. At the same time, the recorded content includes the state machine code and the timestamp information of the state transfer.
[0012] The functional layer coverage detection unit must first determine which signals are key control signals and which signals play a decisive role in the main functions of the circuit, and specially mark these signals; after determining the key control signals, the functional layer coverage detection unit will conduct a detailed analysis of the combination logic of these signals; by analyzing the logic design of the circuit, the functional layer coverage detection unit clearly defines the various key control signal combinations required in the monitoring module, and determines the expected functional output corresponding to each type of signal combination; based on the analysis results of the key control signal combination logic, the functional layer coverage detection unit then designs corresponding assertions to judge the occurrence of key control signal combinations and the corresponding circuit function outputs, and completes the storage of response data through the corresponding data acquisition module.
[0013] Further,
[0014] For the adaptive data storage and transmission part of the FPGA prototype verification system, first, the FPGA prototype verification platform is divided into 16 independent monitoring platforms according to resources, with built-in FPGA user logic and coverage detection unit modules. The number of 16 examples can be dynamically configured according to the total amount of FPGA logic resources, 1 PCIE high-speed transceiver controller, and 1 DDR4 high-capacity memory controller; the independent monitoring platform and the PCIE controller and DDR4 controller are transmitted through the built-in FPGA built-in network. Each monitoring platform has independent data reading, storage, and transmission modules, and can send coverage monitoring data to the network in parallel or serially.
[0015] The specific workflow is as follows:
[0016] First, the FPGA and host computer transmit configuration files via the JTAG interface. The host computer receives information about the number of monitoring platforms, PCIe controllers, and DDR4 controllers on the FPGA. It then partitions and synthesizes the original HDL code, divides the monitoring platform resources by circuit module, and inserts multi-level coverage detection unit circuits. The project is then implemented and the generated bitstream data is loaded onto the FPGA board.
[0017] Afterwards, after receiving the bitstream file sent by the host side, the FPGA side configures the internal programmable resources such as the search variable to form the corresponding logic circuit and coverage detection circuit;
[0018] At the same time, there is a coverage data processing module connected to the circuit module inside the independent monitoring platform on the FPGA side. On the one hand, this module is responsible for receiving and processing the coverage information collected by multiple circuit modules, and storing it as simplified data and complete data according to hierarchical encoding as needed; on the other hand, it is responsible for determining the PCIE / DDR4 output interface of the coverage data based on the FPGA network congestion status, the startup status of the independent monitoring platform, and the host configuration.
[0019] Going further,
[0020] In the coverage data processing module, the module receives multi-level coverage data from multiple circuit modules in the same independent monitoring platform and performs targeted encoding and storage. For multi-level coverage data, the module divides the data encoding into simplified data encoding and complete data encoding:
[0021] In the base layer simplified data encoding, the circuit module ID that receives the base layer coverage data is first stored, followed by the 2-bit coverage identifier. In the base layer complete data encoding, the circuit module ID that receives the base layer coverage data and the 2-bit coverage identifier are also first stored, followed by the trigger ID, the flip identifier corresponding to the trigger ID, the edge identifier corresponding to the trigger ID, and the flip time corresponding to the trigger ID. If the trigger ID flips several times, multiple rounds of flip mark-edge identifier-flip time recording are performed after the trigger ID.
[0022] In the state layer simplified data encoding, the circuit module id of the receiving state layer coverage data is also stored first, and then the 2-bit coverage identifier is stored. Then, if the coverage identifier is 01, several state machine coverage states are stored in sequence. In the state layer complete data encoding, the circuit module id and the 2-bit coverage identifier of the receiving state layer coverage data are also stored first, and then the state machine id, the coverage time corresponding to the state machine id, and the front-end state corresponding to the state machine id are stored. If the state machine id is covered several times, multiple rounds of coverage time-front-end state records are performed after the state machine id.
[0023] In the simplified data encoding of the functional layer, the circuit module ID of the receiving functional layer coverage data is also stored first, followed by the 2-bit coverage identifier. If the coverage identifier is 01, the coverage status of several key signal combinations are stored in sequence. In the complete data encoding of the functional layer, the circuit module ID and the 2-bit coverage identifier of the receiving functional layer coverage data are also stored first, followed by the path group ID, the coverage time corresponding to the path group ID, and the front-end status corresponding to the path group ID. If the path group ID is covered multiple times, multiple rounds of coverage time-front-end status recording are also performed after the path group ID.
[0024] In the coverage data processing module, after completing the multi-level coverage data encoding, the PCIE / DDR4 output interface of the coverage data will be determined based on the FPGA network congestion status, the startup status of the independent monitoring platform, and the host configuration.
[0025] The specific process is as follows:
[0026] First, the FPGA prototype verification system coverage data and host transmission are divided into two modes: real-time transmission and dump transmission, corresponding to the PCIE transmission interface and DDR4 transmission interface respectively. At the same time, each transmission mode can be configured to select reduced data or complete data, and the transmission priority of the basic layer, status layer, and function layer can be configured.
[0027] When the host chooses to transmit simplified / complete data in real time, the coverage data processing module in each independent monitoring platform will start the PCIE transmission interface of the monitoring platform in the completion phase according to the startup status of the monitoring platform, and send multi-level simplified / complete data to the PCIE interface in the FPGA network. When there are multiple monitoring platforms sending simplified / complete data at the same time, the coverage data transmission will be completed in sequence by layer according to the configured basic layer-status layer-functional layer transmission priority. When the host chooses to dump and transmit simplified / complete data, the coverage data processing module in each independent monitoring platform will start the DDR4 transmission interface of the monitoring platform in the startup phase according to the startup status of the monitoring platform, and continuously send multi-level simplified / complete data to the DDR storage in the FPGA. In the completion phase, the DDR4 transmission interface in the FPGA network will send the simplified / complete data in the DDR storage to the host. When the DDR4 transmission interface in the FPGA network receives completion signals from several monitoring platforms, the coverage data transmission will be completed in sequence by layer according to the configured basic layer-status layer-functional layer transmission priority.
[0028] Further,
[0029] Timing-aware instrumentation technology, the specific architecture includes
[0030] The clock domain analysis module automatically identifies cross-clock domain paths by parsing the designed netlist or hardware description language code, tracking clock signals, and analyzing the signal transmission paths between logic units controlled by different clocks.
[0031] The metastable isolation monitoring mechanism inserts dedicated synchronous monitoring units in the metastable isolation area to prevent metastable problems from affecting coverage monitoring. These synchronous monitoring units usually adopt a dual-trigger synchronizer structure to synchronize cross-clock domain signals through two-level triggers; the first-level trigger samples the signal in the source clock domain, and the second-level trigger samples it again in the target clock domain, so that the signal is stably output in the target clock domain.
[0032] The dynamic sampling window module increases the sampling window when it detects that the signal in the clock domain changes slowly; conversely, it reduces the sampling window when the signal changes rapidly.
[0033] The logic device phase compensation module integrates 32-level adjustable delay units and implements closed-loop calibration through a delay-locked loop to compensate for the timing deviation introduced by the instrumentation module. It identifies the difference between the original data delay of the original circuit and the combined data delay of the original circuit + monitoring circuit, then replaces the original data delay of the original circuit with the phase compensation module and sets its delay to the original data delay minus the delay difference, thereby completing data phase compensation.
[0034] The beneficial effects of the present invention are
[0035] First, the solution of the present invention constructs a three-level coverage monitoring unit of the basic layer, the status layer, and the functional layer to realize multi-dimensional coverage monitoring; secondly, the solution of the present invention constructs an adaptive data storage and transmission solution, which makes full use of the coverage data characteristics for data encoding and storage, saving storage space while improving transmission efficiency, and constructs multiple configurable transmission solutions to realize flexible data transmission; finally, the solution of the present invention constructs a timing-aware instrumentation technology, which fully solves the cross-clock domain data collection and instrumentation timing offset processing, and has extremely high application value. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 This is a schematic diagram of the multi-dimensional coverage fusion monitoring architecture for FPGA prototype verification system;
[0037] Figure 2 This is a schematic diagram of the architecture of an adaptive data storage and transmission solution for FPGA prototyping systems;
[0038] Figure 3 It is a data encoding diagram of an adaptive data storage and transmission scheme for FPGA prototype verification system;
[0039] Figure 4This is a schematic diagram of timing-aware instrumentation technology for FPGA prototyping systems. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0041] In response to the problems existing in existing FPGA prototype verification systems during coverage testing, such as single monitoring dimension, extended data reading time, impact of the plug-in structure on system performance, and low data storage efficiency, the present invention proposes an FPGA prototype verification coverage monitoring system based on multi-dimensional monitoring and dynamic optimization.
[0042] The specific implementation process of the present invention includes the following three aspects:
[0043] (1) Multi-dimensional coverage fusion monitoring architecture for FPGA prototype verification system
[0044] Multi-dimensional coverage fusion monitoring architecture for FPGA prototype verification system Figure 1 As shown, in the solution of the present invention, the system coverage monitoring targets are divided into three levels: the base layer coverage detection unit that monitors the flip-flop status of D flip-flops, the state layer coverage detection unit that monitors the state machine transition, and the function layer coverage detection unit that monitors the key control signal combination logic. The specific work of each unit is as follows:
[0045] The base layer coverage detection unit identifies all D flip-flops in the monitoring module, establishes a data link between the D / Q data ports of the associated D flip-flops, and uses the D flip-flop's system clock as the sampling clock to determine whether the D flip-flops have experienced a data flip. When a monitored D flip-flop experiences a data flip, the data acquisition module is triggered to record the clock edge type (rising edge / falling edge) and the current data flip time. If no data flip occurs in the monitored D flip-flop or the base layer coverage detection unit is not enabled, the data acquisition module remains silent, consuming no system power or coverage data storage space.
[0046] The state layer coverage detection unit identifies the state machine logic within the monitored module. First, it uses binary encoding to assign a unique code to each state in the module. For example, for a four-state state machine, the states can be coded as 00, 01, 10, and 11, respectively. This state machine code not only indicates the current state of the state machine, but also serves as the basis for determining state machine transitions and is a key factor in the state machine coverage data storage entry. Secondly, the state layer coverage detection unit continuously monitors the state machine's state transition trigger conditions. State machine transitions are typically triggered by external input signals, internal logic conditions, or clock signal edges. When a state transition trigger signal is detected, the state layer coverage detection unit immediately initiates a recording process, recording the current state machine state and the target state after the transition. The record includes information such as the state machine code and the timestamp of the state transition. For example, in a state machine controlling data transmission, upon receiving a data transmission completion signal, the state may transition from "data transmission in progress" to "data transmission completed." The module promptly captures this trigger event and records the state machine code corresponding to the current state "data transmission in progress," the state machine code corresponding to the target state "data transmission completed," and the time information of the state transition.
[0047] The functional coverage unit identifies the critical control signal combination logic within the monitoring module. In complex digital circuit designs, not all control signals are equally important for functional verification. The functional coverage unit first identifies which signals are critical control signals and which are crucial to the circuit's primary functionality, and specifically marks these signals. For example, in a data processing chip, signals such as data transfer enable and operation mode selection are often considered critical control signals. After identifying these critical control signals, the functional coverage unit conducts a detailed analysis of their combination logic. Functional implementation in digital circuits often relies on specific combinations of multiple control signals, with different combinations triggering different circuit behaviors. By analyzing the circuit's logic design, the functional coverage unit identifies the various critical control signal combinations required within the monitoring module and determines the expected functional outputs corresponding to each signal combination. Based on this analysis of the critical control signal combination logic, the functional coverage unit then designs corresponding assertions to determine the occurrence of these critical control signal combinations and the corresponding circuit functional outputs. The corresponding data acquisition module then stores the response data.
[0048] (2) Adaptive Data Storage and Transmission Solutions for FPGA Prototyping Systems
[0049] In order to solve the problems of long data reading delay and low coverage data storage efficiency in existing FPGA prototype verification systems, the present invention proposes an adaptive data storage and transmission solution for FPGA prototype verification systems. The specific architecture is as follows: Figure 2 As shown. First, in this solution, the FPGA prototype verification platform is divided into 16 independent monitoring platforms according to resources (with built-in FPGA user logic and coverage detection unit modules, 16 is an example number that can be dynamically configured according to the total amount of FPGA logic resources), 1 PCIE high-speed transceiver controller, and 1 DDR4 high-capacity memory controller. The independent monitoring platform and the PCIE controller and DDR4 controller are transmitted through the built-in FPGA built-in network. Each monitoring platform has independent data reading, storage, and transmission modules, which can send coverage monitoring data to the network in parallel or serially. The specific workflow is as follows:
[0050] First, the configuration file is transmitted between the FPGA and the host through the JTAG interface. The host side receives information such as the number of monitoring platforms, PCIE controller, DDR4 controller, etc. of the FPGA, partitions and synthesizes the original HDL code, and divides the monitoring platform resources according to circuit modules. Multi-level coverage detection unit circuits are inserted, and then the project implementation is completed and the produced bit stream data is loaded onto the FPGA board.
[0051] After receiving the bitstream file from the host, the FPGA side configures its internal programmable resources, such as search variables, to form the corresponding logic circuits and coverage detection circuits. Specifically, each independent monitoring platform on the FPGA side is allocated multiple circuit modules. In addition to its original functional logic circuits, each circuit module also includes coverage detection circuits inserted based on the characteristics of its functional logic circuits. The coverage detection circuits are divided into three layers: a base layer, a state layer, and a functional layer. The base layer and the functional layer are essential for monitoring the states of D flip-flops and key signals in the combinational logic, respectively. The state layer is used to monitor the state of the state machine and can be selected based on the circuit characteristics. Furthermore, in addition to the multiple circuit modules, the independent monitoring platform on the FPGA side also includes a coverage data processing module that connects to multiple circuit modules. This module is responsible for receiving and processing coverage information collected from multiple circuit modules, encoding it hierarchically and storing it as condensed and complete data as needed. It also determines the PCIE / DDR4 output interface for coverage data based on FPGA network congestion, the startup status of the independent monitoring platform, and the host configuration.
[0052] In the coverage data processing module, the module receives multi-level coverage data from multiple circuit modules in the same independent monitoring platform and performs targeted coding and storage. The specific coding method is as follows: Figure 3As shown. For multi-layer coverage data, the module divides data encoding into simplified data encoding and complete data encoding: in the simplified data encoding of the base layer, the circuit module ID that receives the base layer coverage data is first stored, and then the 2-bit coverage flag is stored (00 indicates that all D flip-flops in the circuit module are not covered, 11 indicates that all D flip-flops in the circuit module are covered, 01 indicates that the D flip-flops in the circuit module are partially covered, and 10 indicates error data). Subsequently, if the coverage flag is 01, the coverage states of multiple D flip-flops are stored in sequence (0 indicates no coverage, 1 indicates coverage). If the coverage flag is 00 / 11 / 10, there is no need to store the subsequent flip-flop states. In the base layer complete data encoding, the circuit module id and 2-bit coverage flag (00 indicates no coverage, 11 indicates full coverage, 01 indicates partial coverage, and 10 indicates erroneous data) of the base layer coverage data are first stored. Then, the trigger id, the flip flag corresponding to the trigger id (0 indicates a change from high level to low level, 1 indicates a change from low level to high level), the edge flag corresponding to the trigger id (0 indicates a falling edge change, 1 indicates a rising edge change), and the flip time corresponding to the trigger id are stored. If the trigger id is flipped multiple times, multiple rounds of "flip mark-edge flag-flip time" records are performed after the trigger id.
[0053] In the state layer simplified data encoding, the circuit module ID that receives the state layer coverage data is also stored first, followed by a 2-bit coverage flag (00 indicates that the state machine in the circuit module is not fully covered, 11 indicates that the state machine in the circuit module is fully covered, 01 indicates that the state machine in the circuit module is partially covered, and 10 indicates erroneous data). If the coverage flag is 01, multiple state machine coverage states are stored sequentially (0 indicates not covered, 1 indicates covered). If the coverage flag is 00 / 11 / 10, there is no need to store subsequent state machine states. In the state layer complete data encoding, the circuit module ID that receives the state layer coverage data and a 2-bit coverage flag (00 indicates that all are not covered, 11 indicates that all are covered, 01 indicates that part is covered, and 10 indicates that erroneous data) are also stored first. Then, the state machine ID, the coverage time corresponding to the state machine ID (the time of entering the state machine ID), and the previous state corresponding to the state machine ID (the state ID immediately before entering the state machine ID) are stored. If the state machine ID is covered multiple times, multiple rounds of "coverage time-previous state" recording are performed after the state machine ID.
[0054] In the functional layer simplified data encoding, the circuit module ID that receives the functional layer coverage data is also stored first, and then a 2-bit coverage identifier is stored (00 indicates that all key signal combinations in the circuit module are not covered, 11 indicates that all key signal combinations in the circuit module are covered, 01 indicates that the key signal combinations in the circuit module are partially covered, and 10 indicates erroneous data). Subsequently, if the coverage identifier is 01, multiple key signal combination coverage states are stored in sequence (0 indicates not covered, 1 indicates covered). If the coverage identifier is 00 / 11 / 10, there is no need to store subsequent key signal combination states. In the functional layer complete data encoding, the circuit module ID receiving the functional layer coverage data and a 2-bit coverage flag (00 indicates no coverage, 11 indicates full coverage, 01 indicates partial coverage, and 10 indicates erroneous data) are first stored. Then, the path group ID, the coverage time corresponding to the path group ID (the time when the key signal combination, i.e., the path group group, switches), and the front-end status corresponding to the path group ID (which key signal combination enters the key signal combination) are stored. If the path group ID has been covered multiple times, multiple rounds of "coverage time-front-end status" recording are also performed after the path group ID.
[0055] In the coverage data processing module, after the module completes the multi-level coverage data encoding, it will then determine the PCIE / DDR4 output interface of the coverage data based on the FPGA network congestion status, the independent monitoring platform startup status, and the host configuration status. The specific process is as follows: First, in the solution of the present invention, the FPGA prototype verification system coverage data and the host transmission are divided into real-time transmission and dump transmission, which correspond to the PCIE transmission interface and the DDR4 transmission interface respectively. At the same time, each transmission mode can be configured to select streamlined data or complete data, and can be configured with the "basic layer-status layer-functional layer" transmission priority. When the host chooses to transmit simplified / complete data in real time, the coverage data processing module in each independent monitoring platform will start the PCIE transmission interface of the monitoring platform in the completion stage according to the startup status of the monitoring platform (divided into three stages: standby, startup, and completion), and send multi-level simplified / complete data to the PCIE interface in the FPGA network. When there are multiple monitoring platforms sending simplified / complete data at the same time, the coverage data will be transmitted in order according to the configured "basic layer-state layer-function layer" transmission priority; when the host chooses to dump and transmit simplified / complete data, each The coverage data processing module in an independent monitoring platform will start the DDR4 transmission interface of the monitoring platform in the startup phase according to the startup status of the monitoring platform, and continuously send multi-level simplified / complete data to the DDR storage in the FPGA. In the completion phase, it will start the DDR4 transmission interface in the FPGA network and send the simplified / complete data in the DDR storage to the host. When the DDR4 transmission interface in the FPGA network receives completion signals from multiple monitoring platforms, it will complete the transmission of coverage data in sequence according to the configured "basic layer-status layer-functional layer" transmission priority.
[0056] (3) Timing-aware instrumentation technology for FPGA prototype verification systems
[0057] In order to solve the shortcomings of existing FPGA prototype verification systems in cross-clock domain coverage data collection and instrumentation technology timing offset, the present invention constructs a timing-aware instrumentation technology. The specific architecture is as follows: Figure 4 As shown:
[0058] First, the solution of the present invention creates a clock domain analysis module. This module automatically identifies cross-clock domain paths by parsing the design netlist or hardware description language (HDL) code, tracking clock signals and analyzing the signal transmission paths between logic units controlled by different clocks. For example, by checking the clock input signal of the register and the data transmission direction, it can determine which signals cross different clock domains.
[0059] Secondly, the present invention incorporates a metastability isolation monitoring mechanism. Dedicated synchronization monitoring units are inserted into the metastability isolation region to prevent metastability issues from affecting coverage monitoring. These synchronization monitoring units typically utilize a dual-flip-flop synchronizer structure, synchronizing cross-clock domain signals via two stages of triggers. The first stage trigger samples the signal in the source clock domain, and the second stage trigger samples it again in the target clock domain, ensuring stable signal output in the target clock domain.
[0060] At the same time, the present invention provides a dynamic sampling window module. Since the monitoring circuit module has a cross-clock domain problem, the coverage monitoring unit needs to dynamically adjust its own sampling clock to avoid missing signal changes: when the signal changes in the clock domain are detected to be relatively slow, the sampling window is appropriately increased. This is because the signal remains stable for a long time. Increasing the sampling window allows more time to detect whether the signal has changed, ensuring that the signal changes can be fully captured. Conversely, when the signal changes rapidly, the sampling window is reduced. This allows the signal to be sampled at a more precise time point, improving the accuracy and timeliness of sampling, and avoiding missing rapid signal changes due to an overly large sampling window.
[0061] Finally, the present invention incorporates a logic device phase compensation module with 32 integrated adjustable delay units (15ps steps). This module uses a delay-locked loop (DLL) to implement closed-loop calibration and compensate for the timing deviation introduced by the instrumentation module. Specifically, the difference between the original circuit's raw data delay and the combined data delay of the original circuit and the monitoring circuit is identified. The original circuit's raw data delay is then replaced with the phase compensation module, which sets its delay to the original data delay minus the delay difference, completing data phase compensation.
[0062] The above description is only a preferred embodiment of the present invention and is only used to illustrate the technical solution of the present invention, and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.
Claims
1. An FPGA prototype verification coverage monitoring system based on multi-dimensional monitoring and dynamic optimization, characterized in that: The multi-dimensional coverage fusion monitoring architecture of the FPGA prototype verification system builds a three-level coverage monitoring unit to achieve multi-dimensional coverage monitoring; including: The basic layer monitors the D flip-flop flip-flop in detail and accurately obtains the trigger state change information; The state layer sets up a finite state machine state transition path recording module to provide key support for analyzing complex state machine behaviors; At the functional layer, design the key control signal combination logic assertion capture unit to capture the key control signal combination logic and ensure the comprehensiveness of functional verification; For the adaptive data storage and transmission part of the FPGA prototype verification system, the FPGA physical layout is divided into several independent monitoring areas. In each independent monitoring area, the coverage data collection, storage, and transmission scheme is constructed by taking modules as units and making full use of the coverage data characteristics. The timing-aware instrumentation technology for FPGA prototype verification systems automatically identifies cross-clock domain module paths by building a clock domain analysis module, and inserts a dedicated synchronization monitoring unit in the metastable isolation area to prevent metastable problems from interfering with coverage monitoring. At the same time, a dynamically adjusted sampling window is constructed to adapt to the changing characteristics of signals in different clock domains, and a phase compensation circuit is developed to eliminate timing deviations introduced by the instrumentation module.
2. The system according to claim 1, wherein: The base layer coverage detection unit identifies all D flip-flops in the monitoring module, builds data links for the associated D flip-flop data ports D / Q, and uses the D flip-flop system clock as the sampling clock to determine whether data flip-flops occur. When the monitored D flip-flop undergoes data flipping, the data acquisition module is triggered to work and record the clock edge category of the current data flipping, i.e., rising edge / falling edge and the current time of the data flipping; when the monitored D flip-flop does not undergo data flipping or the base layer coverage detection unit is not enabled, the data acquisition module remains silent and does not occupy system power consumption and coverage data storage space.
3. The system according to claim 1, wherein: The state layer coverage detection unit identifies the state machine logic in the monitoring module. First, it uses binary coding to assign a unique code to each state in the module. Second, the state layer coverage detection unit will continuously monitor the state machine's state transition trigger conditions. The state machine's state transition is usually triggered by an external input signal, internal logic conditions, or the edge of the clock signal. When the state transfer trigger signal is detected to be valid, the state layer coverage detection unit will immediately start the recording process to record the current state machine state and the target state of the state machine after the transfer. The recorded content includes the state machine code and the timestamp information of the state transfer.
4. The system according to claim 1, wherein: The functional layer coverage detection unit must first determine which signals are key control signals and which signals play a decisive role in the main functions of the circuit, and specially mark these signals; After determining the key control signals, the functional layer coverage detection unit will conduct a detailed analysis of the combination logic of these signals; by analyzing the logic design of the circuit, the functional layer coverage detection unit clearly defines the various key control signal combinations required in the monitoring module, and determines the expected functional output corresponding to each signal combination; based on the analysis results of the key control signal combination logic, the functional layer coverage detection unit then designs corresponding assertions to determine the occurrence of key control signal combinations and the corresponding circuit function outputs, and completes the storage of response data through the corresponding data acquisition module.
5. The system according to claim 1, wherein: For the adaptive data storage and transmission part of the FPGA prototype verification system, first, the FPGA prototype verification platform is divided into 16 independent monitoring platforms according to resources, with built-in FPGA user logic and coverage detection unit modules. The number of 16 examples can be dynamically configured according to the total amount of FPGA logic resources, 1 PCIE high-speed transceiver controller, and 1 DDR4 high-capacity memory controller; the independent monitoring platform and the PCIE controller and DDR4 controller are transmitted through the built-in FPGA built-in network. Each monitoring platform has independent data reading, storage, and transmission modules, and can send coverage monitoring data to the network in parallel or serially.
6. The system according to claim 5, characterized in that The specific workflow is as follows: First, the FPGA and host computer transmit configuration files via the JTAG interface. The host computer receives information about the number of monitoring platforms, PCIe controllers, and DDR4 controllers on the FPGA. It then partitions and synthesizes the original HDL code, divides the monitoring platform resources by circuit module, and inserts multi-level coverage detection unit circuits. The project is then implemented and the generated bitstream data is loaded onto the FPGA board. Afterwards, after receiving the bitstream file sent by the host side, the FPGA side configures the internal programmable resources such as the search variable to form the corresponding logic circuit and coverage detection circuit; At the same time, there is a coverage data processing module connected to the circuit module inside the independent monitoring platform on the FPGA side. On the one hand, this module is responsible for receiving and processing the coverage information collected by multiple circuit modules, and storing it as simplified data and complete data according to hierarchical encoding as needed; on the other hand, it is responsible for determining the PCIE / DDR4 output interface of the coverage data based on the FPGA network congestion status, the startup status of the independent monitoring platform, and the host configuration.
7. The system according to claim 6, characterized in that In the coverage data processing module, the module receives multi-level coverage data from several circuit modules in the same independent monitoring platform and performs targeted encoding and storage on it. For multi-level coverage data, the module divides the data encoding into simplified data encoding and complete data encoding: In the base layer simplified data encoding, the circuit module ID that receives the base layer coverage data is first stored, followed by the 2-bit coverage identifier. In the base layer complete data encoding, the circuit module ID that receives the base layer coverage data and the 2-bit coverage identifier are also first stored, followed by the trigger ID, the flip identifier corresponding to the trigger ID, the edge identifier corresponding to the trigger ID, and the flip time corresponding to the trigger ID. If the trigger ID flips several times, multiple rounds of flip mark-edge identifier-flip time recording are performed after the trigger ID. In the state layer simplified data encoding, the circuit module ID of the receiving state layer coverage data is also stored first, followed by the 2-bit coverage flag. If the coverage flag is 01, several state machine coverage states are stored in sequence. In the state layer complete data encoding, the circuit module ID and the 2-bit coverage flag of the receiving state layer coverage data are also stored first, followed by the state machine ID, the coverage time corresponding to the state machine ID, and the front-end state corresponding to the state machine ID. If the state machine ID has been covered several times, multiple rounds of coverage time-front-end state recording are performed after the state machine ID. In the simplified data encoding of the functional layer, the circuit module ID of the receiving functional layer coverage data is also stored first, followed by the 2-bit coverage identifier. If the coverage identifier is 01, the coverage status of several key signal combinations are stored in sequence. In the complete data encoding of the functional layer, the circuit module ID and the 2-bit coverage identifier of the receiving functional layer coverage data are also stored first, followed by the path group ID, the coverage time corresponding to the path group ID, and the front-end status corresponding to the path group ID. If the path group ID is covered multiple times, multiple rounds of coverage time-front-end status recording are also performed after the path group ID.
8. The system according to claim 7, characterized in that In the coverage data processing module, after completing the multi-level coverage data encoding, the PCIE / DDR4 output interface of the coverage data will be determined based on the FPGA network congestion status, the startup status of the independent monitoring platform, and the host configuration. The specific process is as follows: First, the FPGA prototype verification system coverage data and host transmission are divided into two modes: real-time transmission and dump transmission, corresponding to the PCIE transmission interface and DDR4 transmission interface respectively. At the same time, each transmission mode can be configured to select reduced data or complete data, and the transmission priority of the basic layer, status layer, and function layer can be configured. When the host chooses to transmit simplified / complete data in real time, the coverage data processing module in each independent monitoring platform will start the PCIE transmission interface of the monitoring platform in the completion phase according to the startup status of the monitoring platform, and send multi-level simplified / complete data to the PCIE interface in the FPGA network. When there are multiple monitoring platforms sending simplified / complete data at the same time, the coverage data transmission will be completed in sequence by layer according to the configured basic layer-status layer-functional layer transmission priority. When the host chooses to dump and transmit simplified / complete data, the coverage data processing module in each independent monitoring platform will start the DDR4 transmission interface of the monitoring platform in the startup phase according to the startup status of the monitoring platform, and continuously send multi-level simplified / complete data to the DDR storage in the FPGA. In the completion phase, the DDR4 transmission interface in the FPGA network will send the simplified / complete data in the DDR storage to the host. When the DDR4 transmission interface in the FPGA network receives completion signals from several monitoring platforms, the coverage data transmission will be completed in sequence by layer according to the configured basic layer-status layer-functional layer transmission priority.
9. The system according to claim 1, wherein: Timing-aware instrumentation technology, the specific architecture includes The clock domain analysis module automatically identifies cross-clock domain paths by parsing the design's netlist or hardware description language code, tracking clock signals, and analyzing signal transmission paths between logic units controlled by different clocks. Metastable isolation monitoring mechanism: dedicated synchronization monitoring units are inserted into the metastable isolation area to prevent metastable problems from affecting coverage monitoring. These synchronization monitoring units usually use a dual-flip-flop synchronizer structure to synchronize cross-clock domain signals through two-stage flip-flops. The first-stage trigger samples the signal in the source clock domain, and the second-stage trigger samples it again in the target clock domain, so that the signal is output stably in the target clock domain; The dynamic sampling window module increases the sampling window when it detects that the signal in the clock domain changes slowly; conversely, it reduces the sampling window when the signal changes rapidly. The logic device phase compensation module integrates 32-level adjustable delay units and implements closed-loop calibration through a delay-locked loop to compensate for the timing deviation introduced by the instrumentation module. It identifies the difference between the original data delay of the original circuit and the combined data delay of the original circuit + monitoring circuit, then replaces the original data delay of the original circuit with the phase compensation module and sets its delay to the original data delay minus the delay difference, thereby completing data phase compensation.