Chip connection circuit, electronic device, chip driving method and storage medium

Abstract

The invention relates to a chip connection circuit, electronic equipment, a chip driving method and a storage medium. The chip connection circuit comprises a driving input end, an output end and a driving circuit, the driving circuit is connected to a connecting line between the driving input end and the output end and has different working states; wherein under the condition that the working states of the driving circuit are different, the driving currents output by the output end are different. According to the embodiment of the invention, the chip connection circuit not only can better provide the driving current, but also can adapt to different driving scenes, and has universality.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit design, and in particular to a chip connection circuit, an electronic device, a chip driving method, and a storage medium. Background Art

[0002] As portable electronic devices become increasingly lightweight, the integration of chip components within them is also increasing. More and more chips are adopting a single-wire general-purpose input / output (GPIO) integration solution, where the slave chip's power and communication pins are connected solely to the master chip's GPIO. However, as the master chip's GPIO level decreases, its drive current also decreases, making it incompatible with the slave chip. Summary of the Invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a chip connection circuit, an electronic device, a chip driving method and a storage medium, which can increase the driving current output by the chip connection circuit, thereby improving the adaptability of the main chip connected to the chip connection circuit.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a chip connection circuit, comprising: a driving input terminal, an output terminal, and a driving circuit;

[0005] The driving circuit is connected to the connection line between the driving input terminal and the output terminal and has different working states;

[0006] Wherein, when the working state of the driving circuit is different, the driving current output by the output end is different.

[0007] In some embodiments, the driving circuit has a first operating state and a second operating state;

[0008] The driving current output when the driving circuit is in the first working state is smaller than the driving current output when the driving circuit is in the second working state.

[0009] In some embodiments, the driving circuit includes:

[0010] a first power supply terminal;

[0011] a first switch circuit, connecting the first power supply terminal and the output terminal;

[0012] a second switch circuit, connecting the driving input terminal, the first power supply terminal and the output terminal;

[0013] Wherein, when the first switch circuit is in the on state and the second switch circuit is in the off state, the drive circuit is in the first working state;

[0014] When both the first switching circuit and the second switching circuit are in the on state, the driving circuit is in the second working state.

[0015] In some embodiments, the driving circuit further includes a second power supply terminal;

[0016] The second switch circuit includes a first switch component and a second switch component;

[0017] The first switch component is connected to the second power supply terminal, the driving input terminal and the second switch component;

[0018] The second switch component is connected to the first switch component, the first power supply end and the output end;

[0019] Wherein, when both the first switch component and the second switch component are in the on state, the second switch circuit is turned on.

[0020] In some embodiments, the driving circuit further includes:

[0021] a first impedance component, connected to the first power supply terminal and the second switch component, and connected in parallel with the second switch component; and / or,

[0022] a second impedance component, connected to the second power supply terminal and the first switch component, and connected in parallel with the first switch component;

[0023] The first impedance component and the second impedance component are both configured to protect the driving circuit when the driving circuit switches the working state.

[0024] In some embodiments, the first switching component includes a first transistor and the second switching component includes a second transistor;

[0025] Wherein, the first electrode of the first transistor is connected to the second power supply terminal, the second electrode of the first transistor is connected to the driving input terminal, and the third electrode of the first transistor is connected to the second transistor;

[0026] A first electrode of the second transistor is connected to the first transistor, a second electrode of the second transistor is connected to the first power supply terminal, and a third electrode of the second transistor is connected to the output terminal.

[0027] In some embodiments, the driving circuit further includes:

[0028] A third impedance component is connected to the first power supply end and the output end, and is connected in series with the first switch circuit, and is configured to adjust the driving current.

[0029] In some embodiments, the chip connection circuit further includes:

[0030] a third power supply terminal;

[0031] a communication input terminal connected to the output terminal and configured to transmit at least a communication signal;

[0032] The third switch component is connected to the third power supply terminal, the communication input terminal and the output terminal, and is configured to open or close the connection line between the communication input terminal and the output terminal.

[0033] In some embodiments, the chip connection circuit further includes:

[0034] A fourth impedance component, one end of which is connected to the third power supply terminal and the other end of which is connected to the third switch component and the communication input terminal, is configured to protect the drive circuit when the third switch component switches the connection line between the communication input terminal and the output terminal on and off.

[0035] In some embodiments, the third switch component includes a third transistor;

[0036] A first electrode of the third transistor is connected to the communication input terminal, a second electrode of the third transistor is connected to the output terminal, and a third electrode of the third transistor is connected to the third power supply terminal.

[0037] According to a second aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0038] A first chip having a first interface;

[0039] A second chip having a second interface;

[0040] The chip connection circuit as described in the first aspect above; wherein the driving input end of the chip connection circuit is connected to the first interface, and the output end of the chip connection circuit is connected to the second interface.

[0041] In some embodiments, the first chip further includes a third interface; the third interface is connected to a communication input terminal of the chip connection circuit.

[0042] According to a third aspect of an embodiment of the present disclosure, a chip driving method is provided, including:

[0043] In response to a communication instruction for a first chip and a second chip in an electronic device to communicate, generating a control instruction for a chip connection circuit connecting the first chip and the second chip;

[0044] Switching the working state of the driving circuit in the chip connection circuit based on the control instruction;

[0045] The second chip is driven based on the driving current output by the switched driving circuit.

[0046] In some embodiments, switching the working state of the driving circuit in the chip connection circuit based on the control instruction includes:

[0047] Based on the control instruction, controlling the drive circuit to switch from the first working state to the second working state;

[0048] The driving current output when the driving circuit is in the first working state is smaller than the driving current output when the driving circuit is in the second working state.

[0049] In some embodiments, controlling the driving circuit to switch from the first working state to the second working state based on the control instruction includes:

[0050] Based on the control instruction, the second switch circuit of the drive circuit is controlled to switch from an off state to an on state, so that the drive circuit is in the second working state.

[0051] According to a fourth aspect of an embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, which, when a computer program or instruction in the storage medium is executed by an electronic device, implements the steps of the method described in the third aspect above.

[0052] According to a fifth aspect of an embodiment of the present disclosure, a computer program product is provided, comprising a computer program or instructions, which, when executed by a processor, implements the steps of the method described in the third aspect above.

[0053] The technical solutions provided by the embodiments of the present disclosure may have the following beneficial effects:

[0054] In the disclosed embodiment, the driver circuit of the chip connection circuit is connected to the connection line between the drive input terminal and the output terminal and has different operating states. When the operating state of the driver circuit is different, the drive current output by the output terminal is different. In other words, the chip connection circuit of the disclosed embodiment no longer outputs a fixed drive current, but can output different drive currents. On the one hand, this enables the chip connection circuit to better provide drive current, and on the other hand, it enables the chip connection circuit to adapt to different driving scenarios and has universal applicability.

[0055] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0057] Figure 1 The figure is a schematic diagram of a level conversion circuit according to an exemplary embodiment.

[0058] Figure 2 A chip connection circuit diagram according to an exemplary embodiment is shown. Figure 1 .

[0059] Figure 3 The figure shows a chip communication scenario according to an exemplary embodiment.

[0060] Figure 4 A driving circuit diagram according to an exemplary embodiment is shown. Figure 1 .

[0061] Figure 5 A driving circuit diagram according to an exemplary embodiment is shown. Figure 2 .

[0062] Figure 6 A chip connection circuit diagram according to an exemplary embodiment is shown. Figure 2 .

[0063] Figure 7 A chip connection circuit diagram according to an exemplary embodiment is shown. Figure 3 .

[0064] Figure 8 An electronic device structure according to an exemplary embodiment is shown Figure 1 .

[0065] Figure 9 FIG. 1 is a flow chart illustrating a chip driving method according to an exemplary embodiment.

[0066] Figure 10 An electronic device frame according to an exemplary embodiment is shown Figure 2 . DETAILED DESCRIPTION

[0067] The exemplary embodiments will be described in detail herein, with examples shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of chip connection circuits, electronic devices, chip driving methods, and storage media consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0068] Figure 1 FIG. 1 is a schematic diagram of a level conversion circuit according to an exemplary embodiment. Figure 1 As shown, the level conversion circuit is provided with an input terminal S1, an output terminal S2, a first supply voltage V1, a second supply voltage V2, a first resistor R1, a second resistor R2 and a metal-oxide-semiconductor field-effect transistor (MOS) 101, and the MOS transistor includes a first gate, a second drain and a third source.

[0069] Among them, the first chip is connected to the input end, the second chip is connected to the output end, the first chip transmits a driving signal to the second chip through the level conversion circuit for communication, and the first chip transmits a driving current of the driving signal to the second chip through the level conversion circuit for power supply. One end of the first resistor is connected to the input end and the source of the MOS tube, and the other end is connected to the first power supply voltage and the gate of the MOS tube. One end of the second resistor is connected to the output end, and the other end is connected to the drain of the MOS tube and the output end.

[0070] It can be understood that when a high level is input to the input terminal, the voltage difference between the gate and source of the MOS transistor is less than a preset voltage threshold, the MOS transistor is not conducting, and the level of the output terminal is pulled up to a high level by the second supply voltage and the second resistor. That is, when a high level is input to the input terminal, the output terminal outputs a high level. When a low level is input to the input terminal, the voltage difference between the gate and source of the MOS transistor is equal to the first supply voltage, the MOS transistor conducts, and the level of the output terminal is equal to that of the input terminal. That is, when a low level is input to the input terminal, a low level is input to the output terminal. In this way, the level input to the input terminal is output to the corresponding level at the output terminal, thereby providing the voltage and current required by the chip.

[0071] However, the driving current outputted from the output end of the level conversion circuit is a fixed current value, namely, the voltage value of the second supply voltage divided by the resistance value of the second resistor, and cannot provide additional driving current. Thus, when the driving current is increased, there is an increased voltage drop, thereby affecting the communication between the chip connected to the input end and the chip connected to the output end.

[0072] Based on this, an embodiment of the present disclosure proposes a chip connection circuit that can output different driving currents. Figure 2 FIG. 1 is a schematic diagram of a chip connection circuit according to an exemplary embodiment. Figure 2 As shown, the chip connection circuit 20 includes: a driving input terminal 201, an output terminal 202 and a driving circuit 21;

[0073] The driving circuit 21 is connected to the connection line between the driving input terminal 201 and the output terminal 202 and has different working states;

[0074] In the case of different working states of the driving circuit 21 , the driving current outputted by the output terminal 202 is different.

[0075] In the embodiment of the present disclosure, the chip connection circuit is applied to the scenario of single-line communication between chips. Figure 3 FIG. 1 is a diagram showing a chip communication scenario according to an exemplary embodiment. Figure 3 As shown, the driving input terminal 201 of the chip connection circuit 20 is connected to the interface 110 of the first chip 10, and the output terminal 202 of the chip connection circuit 20 is connected to the power supply 301 of the second chip and the interface 302 of the second chip 30. In this way, based on the chip connection circuit, the voltage level of the interface of the first chip can be transmitted to the interface of the second chip for communication, and the driving current can also be provided to transmit the driving current to the power supply terminal of the second chip to power the second chip.

[0076] The driving input terminal is connected to the interface of the first chip and is used to receive a driving signal. For example, if the interface of the first chip outputs a high level, the driving input terminal of the chip connection circuit receives the high level; if the interface of the first chip outputs a low level, the driving input terminal of the chip connection circuit receives the low level.

[0077] The output terminal is connected to an interface of the second chip, and the interface of the second chip receives the driving current output by the output terminal as the power supply current of the second chip.

[0078] The driving circuit is connected to the connection line between the driving input terminal and the output terminal, that is, the driving circuit is used to transmit the driving current to the second chip.

[0079] In the embodiments of the present disclosure, the drive circuit has multiple operating states. For example, in one embodiment, the drive circuit has a first operating state and a second operating state; in another embodiment, the drive circuit may have a third operating state in addition to the first and second operating states.

[0080] In different operating states of the driving circuit, the driving current of the driving signal output by the output terminal is different. For example, in one embodiment, the driving current corresponding to the output when the driving circuit is in the first operating state is greater than the driving current corresponding to the output when the driving circuit is in the second operating state; in another embodiment, the driving current corresponding to the output when the driving circuit is in the first operating state is less than the driving current corresponding to the output when the driving circuit is in the second operating state, and the driving current corresponding to the output when the driving circuit is in the second operating state is less than the driving current corresponding to the output when the driving circuit is in the third operating state.

[0081] It should be noted that the different working states of the driving circuit are due to the fact that the components, power supply terminals or switch circuits in the driving circuit cause the output terminals of the driving circuit to output different driving currents.

[0082] For example, in one embodiment, the drive circuit may include multiple switching circuits and multiple power supply terminals, with different switching circuits transmitting drive currents from different power supply terminals to the output terminal. The number of switching circuits may be two, three, or four, and this is not limited in the present disclosure.

[0083] The voltages of the multiple power supply terminals may be the same or different. It is understood that when the voltages of the power supply terminals are the same, the driving current of one conducting switch circuit is smaller than the driving currents of multiple conducting switch circuits, i.e., different driving currents output by the drive circuit to the output terminal correspond to different operating states of the drive circuit.

[0084] In another embodiment, the drive circuit may further include multiple level shifting chips and multiple power supply terminals. The level shifting chips may control the drive circuit to be active at a high level and inactive at a low level, and may also control the drive circuit to be active at a low level and inactive at a high level. Different level shifting chips transmit drive currents from different power supply terminals to the output terminal, meaning that the drive circuit may output different drive currents to the output terminal based on different operating states.

[0085] In the disclosed embodiment, the driver circuit of the chip connection circuit is connected to the connection line between the drive input terminal and the output terminal and has different operating states; when the operating state of the driver circuit is different, the drive current output by the output terminal is different. In other words, the chip connection circuit of the disclosed embodiment no longer outputs a fixed drive current, but can output different drive currents. On the one hand, this enables the chip connection circuit to better provide drive current, and on the other hand, it enables the chip connection circuit to adapt to different driving scenarios and has universal applicability.

[0086] In one embodiment, the driving circuit has a first operating state and a second operating state;

[0087] The driving current output when the driving circuit is in the first working state is smaller than the driving current output when the driving circuit is in the second working state.

[0088] In the embodiment of the present disclosure, when the driving circuit is in the first working state, the driving current output is a first current value, and when the driving circuit is in the second working state, the driving current output is a second current value, and the first current value is smaller than the second current value.

[0089] It should be noted that when the drive circuit is in the first operating state, because the first current value is less than the second current value, the power consumption of the drive circuit in the first state is less than the power consumption of the drive circuit in the second state. Therefore, the drive circuit in the first operating state is suitable for low-power or light-load scenarios, and the first operating state corresponds to the low-power state of the drive circuit.

[0090] Similarly, when the drive circuit is in the second operating state, the second current value provided by the drive circuit is greater than the first current value, and the power consumption of the drive circuit in the second state is greater than the power consumption of the drive circuit in the first state. Therefore, the drive circuit in the second operating state is suitable for high-performance or heavy-load scenarios, and the second operating state corresponds to the strong drive state of the drive circuit.

[0091] In the disclosed embodiments, the driving current in the first operating state is less than the circuit power consumption caused by the driving current in the second operating state, thereby achieving greater energy conservation. The driving current in the second operating state can increase the circuit load in the first operating state, thereby improving operating performance. The design of two operating states increases the flexibility of the chip connection circuit's output driving current, allowing the chip connection circuit to select an appropriate driving current based on application requirements, thereby optimizing the chip connection circuit's transmission performance.

[0092] It should be noted that different operating states of the driving circuit can be switched by different switching circuits. Figure 4 FIG. 1 is a schematic diagram of a driving circuit according to an exemplary embodiment. Figure 4 As shown, in one embodiment, the driving circuit 21 includes:

[0093] a first power supply terminal 203;

[0094] A first switch circuit 211 is connected to the first power supply terminal 203 and the output terminal 202;

[0095] The second switch circuit 212 is connected to the driving input terminal 201, the first power supply terminal 203 and the output terminal 202;

[0096] When the first switch circuit 211 is in the on state and the second switch circuit 212 is in the off state, the drive circuit 21 is in the first working state;

[0097] When the first switch circuit 211 and the second switch circuit 212 are both in the on state, the drive circuit 21 is in the second working state.

[0098] In the embodiment of the present disclosure, the first power supply terminal provides voltage to the first switch circuit. It is understandable that the ratio of the voltage of the first power supply terminal to the total resistance of the first switch circuit is the current value of the driving current output by the first switch circuit to the output terminal.

[0099] The voltage of the first power supply terminal can be set according to actual conditions, and the embodiment of the present disclosure does not limit this. For example, the voltage of the first power supply terminal can be set within the range of 2V to 5V.

[0100] The first switch circuit is connected to a first connection line between the first power supply terminal and the output terminal. When the first switch circuit is turned on, a current output from the first power supply terminal to the output terminal through the turned-on first connection line is a first ratio between a voltage at the first power supply terminal and a total resistance of the first connection line.

[0101] The second switching circuit is connected to the input terminal, the first power terminal, and the output terminal, and includes a second switching circuit connected to a second connection path between the first power terminal and the output terminal. When the second switching circuit is turned on, a current output from the first power terminal to the output terminal via the second switching circuit is a second ratio of a voltage at the first power terminal to a total resistance of the second connection path.

[0102] When the first switch circuit is in the on state and the second switch circuit is in the off state, the drive current outputted by the output terminal of the drive circuit is a first ratio; when both the first switch circuit and the second switch circuit are in the on state, according to Gilchhoff's current law, the current outputted by the output terminal of the drive circuit is the sum of the first ratio and the second ratio. That is, the drive current when the first switch circuit is in the first working state is less than the drive current when the first switch circuit is in the second working state.

[0103] In the embodiment of the present disclosure, the driving circuit is placed in different working states by turning on and off the first switching circuit and the second switching circuit. The driving current output by the driving circuit in different working states is different, thereby being able to flexibly connect different chips and flexibly output the driving current to the chip through the chip connection circuit.

[0104] In the embodiment of the present disclosure, the second switch circuit may include a plurality of switch components, and the conduction and disconnection of the second switch circuit are controlled based on the conduction and disconnection of the switch components.

[0105] Illustratively, in one embodiment, the second switch circuit may include a first switch component, a second switch component, and a fourth switch component. When the first switch component, the second switch component, and the fourth switch component are connected in series in the first switch circuit, when the first switch component, the second switch component, and the fourth switch component are all turned on, the second switch circuit is turned on, and the drive circuit is in the second working state; when any one of the first switch component, the second switch component, and the fourth switch component is disconnected, the second switch circuit is disconnected, and the drive circuit is in the first working state.

[0106] In another embodiment, Figure 5 A driving circuit diagram according to an exemplary embodiment is shown. Figure 2 .like Figure 5 As shown, the driving circuit further includes a second power supply terminal 204;

[0107] The second switch circuit includes a first switch component 2121 and a second switch component 2122;

[0108] The first switch component 2121 is connected to the second power supply terminal 204, the driving input terminal 201 and the second switch component 2122;

[0109] The second switch component 2122 connects the first switch component 2121, the first power supply terminal 203 and the output terminal 202;

[0110] When the first switch component 2121 and the second switch component 2122 are both in the on state, the second switch circuit is turned on.

[0111] In the embodiments of the present disclosure, the drive circuit can be placed in different operating states by switching the switching states of the first switch component and the second switch component. For example, when the first switch component is off, the drive circuit is in the first operating state; when both the first switch component and the second switch component are on, the drive circuit is in the second operating state.

[0112] It can be understood that since the first switch component and the second switch component are both in the on state, the second switch circuit is turned on, and the second switch circuit connects the first power supply end and the output end, therefore, the second switch circuit transmits the driving current of the first power supply to the output end.

[0113] In the embodiment of the present disclosure, the second switch circuit may include multiple first switch components and multiple second switch components. The multiple first switch components may be connected in series or in parallel, and the multiple second switch components may be connected in series or in parallel. The embodiment of the present disclosure does not limit this.

[0114] For example, when the second switch circuit includes two first switch components connected in parallel and two second switch components connected in series, the second switch circuit is on when at least one first switch component is on and both second switch components are on; the second switch circuit is off when both first switch components are off; and the second switch circuit is off when at least one first switch component is on and at least one second switch component is off. That is, when the second switch circuit is on, the drive circuit is in the second operating state, and when the second switch circuit is off, the drive circuit is in the first operating state.

[0115] In the embodiment of the present disclosure, by providing the first switch component and the second switch component, the precision of the control over the second switch component is improved, thereby facilitating adjustment of the driving current at the output end to meet different application requirements.

[0116] In one embodiment, Figure 6 A chip connection circuit diagram according to an exemplary embodiment is shown. Figure 2 .like Figure 6 As shown, the first switch component includes a first transistor 221 and the second switch component includes a second transistor 222;

[0117] The first electrode of the first transistor 221 is connected to the second power supply terminal 204 , the second electrode of the first transistor 221 is connected to the driving input terminal 201 , and the third electrode of the first transistor 221 is connected to the second transistor 222 ;

[0118] A first electrode of the second transistor 222 is connected to the first transistor 221 , a second electrode of the second transistor 222 is connected to the first power supply terminal 203 , and a third electrode of the second transistor is connected to the output terminal 202 .

[0119] The first transistor and the second transistor may be a positive channel Metal Oxide Semiconductor (PMOS) transistor with an n-type substrate and a p-channel, which relies on the flow of holes to transport current, or an N-Metal-Oxide-Semiconductor (NMOS), which is not limited in the embodiments of the present disclosure.

[0120] In the embodiment of the present disclosure, the on / off control of the second switch component connected in series can be performed based on the on / off control of the first switch component. For example, the first transistor is an NMOS transistor, with the first electrode of the first transistor being the gate, the second electrode being the source, and the third electrode being the drain; and the second transistor is a PMOS transistor, with the first electrode of the second transistor being the gate, the second electrode being the source, and the third electrode being the drain.

[0121] It should be noted that, for a PMOS transistor, the gate is turned on relative to a low level of the source, and the gate is turned off relative to a high level of the source; for an NMOS transistor, the gate is turned on relative to a high level of the source, and the gate is turned off relative to a low level of the source.

[0122] It can be understood that, for the PMOS tube, when the voltage difference between the gate voltage and the source voltage of the PMOS tube is less than or equal to the first preset voltage threshold, the PMOS tube allows current to flow from the source to the drain, and the PMOS tube is turned on; when the voltage difference between the gate voltage and the source voltage of the PMOS tube is greater than the first preset voltage threshold, the PMOS tube prevents current from passing through, and the PMOS tube is turned off.

[0123] For an NMOS transistor, if the voltage difference between the gate voltage and the source voltage of the NMOS transistor is greater than a second preset voltage threshold, the NMOS transistor allows current to flow from the source to the drain, and the NMOS transistor is turned on. If the voltage difference between the gate voltage and the source voltage of the NMOS transistor is less than or equal to the preset voltage threshold, the NMOS transistor blocks current from flowing, and the NMOS transistor is turned off. Here, the first preset voltage threshold and the second preset voltage threshold can be equal or different, and this is not limited in the present embodiment.

[0124] Therefore, when the driving input terminal inputs a low level, the first transistor is turned on, the gate of the second transistor receives the low level, the second transistor is turned on, that is, the second switch circuit is turned on, and the second switch circuit outputs a driving current to the output terminal.

[0125] In the embodiment of the present disclosure, the chip connection circuit adjusts the output drive current through precise control of the first transistor and the second transistor, thereby improving the flexibility of the chip connected to the chip connection circuit.

[0126] In one embodiment, if Figure 5 and Figure 6 As shown, the driving circuit also includes:

[0127] The first impedance component 401 is connected to the first power supply terminal 203 and the second switch component 2122 and is connected in parallel with the second switch component 2122; and / or,

[0128] The second impedance component 402 is connected to the second power supply terminal 204 and the first switch component 2121 and is connected in parallel with the first switch component 2121;

[0129] The first impedance component 401 and the second impedance component 402 are both configured to protect the driving circuit when the driving circuit switches working states.

[0130] Here, the first impedance component may be an impedance adjustment element such as a resistor or an inductor, and the second impedance component may also be an impedance adjustment element such as a resistor or an inductor, which is not limited in the embodiment of the present disclosure.

[0131] The resistance values or impedance characteristics of the first impedance component and the second impedance component can be adjusted according to needs. For example, the resistance values of the first impedance component and the second impedance component are both in the range of 1 kilo-ohm to 5 kilo-ohm, which is not limited in the embodiments of the present disclosure.

[0132] It should be noted that when the first switch assembly includes a MOS transistor and the second switch assembly also includes a MOS transistor, when the drive circuit switches operating states, the gate equivalent capacitance of the MOS transistor is in an alternating state of charging and discharging. The charge stored in the gate equivalent capacitance of the MOS transistor has no discharge path, resulting in the gate electric field still storing charge. If power is applied again, the drain operating voltage of the MOS transistor increases rapidly, causing the MOS transistor to generate uncontrolled drain current, which can damage the MOS transistor.

[0133] Therefore, a first impedance component is provided between the first power supply terminal and the second switch component, and a second impedance component is provided between the second power supply terminal and the first switch component. The charge stored in the equivalent capacitance of the MOS tube gate is rapidly discharged through the loop of the impedance component. This can prevent the MOS tube from generating uncontrolled drain current when the driving circuit switches the working state, thereby preventing the MOS tube from burning out.

[0134] In the embodiment of the present disclosure, the chip connection circuit is provided with a first impedance component and a second impedance component, thereby protecting the driving circuit when the working state of the driving circuit is switched, thereby improving the reliability of the chip connection circuit.

[0135] In one embodiment, if Figure 6 As shown, the driving circuit also includes:

[0136] The third impedance component 403 is connected to the first power supply terminal 203 and the output terminal 202 and is connected in series with the first switch circuit, and is configured to adjust the driving current.

[0137] Here, the third impedance component may be an impedance adjustment element such as a resistor or an inductor, and the embodiment of the present disclosure is not limited thereto.

[0138] The resistance value or impedance characteristic of the third impedance component can be adjusted according to needs. For example, the resistance value of the third impedance component is in the range of 0.5 kilo-ohms to 2 kilo-ohms, which is not limited in the embodiment of the present disclosure.

[0139] In the embodiment of the present disclosure, the third impedance component is connected in series with the first switching circuit, that is, the third impedance component can affect the connection line of the current flowing through the first switching circuit to the output end.

[0140] It should be noted that when the voltage at the first power supply terminal is a fixed value, the drive current of the first switch circuit is inversely proportional to the resistance value of the third impedance component. For example, the greater the resistance value of the third impedance component, the smaller the drive current of the first switch circuit; and the smaller the resistance value of the third impedance component, the greater the drive current of the first switch circuit.

[0141] In the disclosed embodiments, the current in the drive circuit can be adjusted by adjusting the resistance value or impedance characteristics of the third impedance component. This allows the output drive current to be flexibly adjusted based on actual needs without changing the structure of the first switch circuit, thereby increasing the flexibility of the output drive current of the connected chip circuit.

[0142] In one embodiment, Figure 7 A chip connection circuit diagram according to an exemplary embodiment is shown. Figure 3 .like Figure 7 As shown, the chip connection circuit also includes:

[0143] A third power supply terminal 205;

[0144] a communication input terminal 206 connected to the output terminal 202 and configured to transmit at least a communication signal;

[0145] The third switch component 223 is connected to the third power supply terminal 205 , the communication input terminal 206 and the output terminal 202 , and is configured to open or close the connection line between the communication input terminal 206 and the output terminal 202 .

[0146] In the embodiment of the present disclosure, the third power supply terminal provides additional power support for the communication input terminal and the output terminal. The third power supply terminal can be an independent power supply or derived from the second power supply, which is not limited in the embodiment of the present disclosure.

[0147] The above-mentioned communication input end can be an interface for receiving or sending communication signals. Exemplarily, the communication input end includes a synchronous serial communication protocol (Inter-Integrated Circuit, I2C), a serial peripheral interface (Serial Peripheral Interface, SPI), etc., which is not limited in the embodiments of the present disclosure.

[0148] The third switch component is connected to the third power supply terminal, the communication input terminal and the output terminal, that is, the third switch component is used to control the flow of the communication signal.

[0149] The third switch component includes a third transistor, a relay or a switch, etc., which is not limited in the embodiment of the present disclosure.

[0150] Exemplarily, in one embodiment, the third switch component includes a third transistor;

[0151] The first electrode of the third transistor is connected to the communication input terminal, the second electrode of the third transistor is connected to the output terminal, and the third electrode of the third transistor is connected to the third power supply terminal.

[0152] In this way, when a high level is input to the communication input terminal, the NMOS tube is turned on, and when a low level is input to the communication input terminal, the NMOS tube is turned off.

[0153] In the embodiment of the present disclosure, by providing a third power supply terminal, a communication input terminal and a third switch component, the chip connection circuit has the ability to communicate, can transmit data or signals, and enhance the communication function of the chip connection circuit.

[0154] In one embodiment, the chip connection circuit further includes:

[0155] The fourth impedance component has one end connected to the third power supply end and the other end connected to the third switch component and the communication input end, and is configured to protect the driving circuit when the third switch component switches the connection line between the communication input end and the output end on and off.

[0156] Here, the fourth impedance component may be an impedance adjustment element such as a resistor or an inductor, and the embodiment of the present disclosure is not limited thereto.

[0157] The resistance value or impedance characteristics of the fourth impedance component can be adjusted according to needs. For example, the resistance value of the fourth impedance is in the range of 1 kilo-ohm to 5 kilo-ohm, which is not limited in the embodiment of the present disclosure.

[0158] It should be noted that when the third switch component includes a MOS tube, when the communication input terminal switches to a high level or a low level, the gate equivalent capacitance of the MOS tube is in an alternating state of charging and discharging. The charge charged by the gate equivalent capacitance of the MOS tube has no discharge loop, so that the gate electric field still stores charge. If power is turned on again, the drain operating voltage of the MOS tube rises rapidly, and the MOS tube generates an uncontrolled drain current, thereby burning the MOS tube.

[0159] Therefore, a fourth impedance component is provided between the third power supply terminal, the communication input terminal and the third switch component. The charge stored in the equivalent capacitance of the MOS transistor gate is rapidly discharged through the loop of the impedance component. This can prevent the MOS transistor from generating uncontrolled drain current when the communication input terminal switches the input high level or low level, thereby preventing the MOS transistor from burning out.

[0160] In the embodiment of the present disclosure, the chip connection circuit is provided with a fourth impedance component to protect the driving circuit when the communication input terminal switches the input high level or low level, thereby improving the reliability of the chip connection circuit in communication.

[0161] The present disclosure also provides an electronic device, including:

[0162] A first chip having a first interface;

[0163] A second chip having a second interface;

[0164] A chip connection circuit as in any of the above embodiments; wherein the driving input end of the chip connection circuit is connected to the first interface, and the output end of the chip connection circuit is connected to the second interface.

[0165] The above-mentioned electronic devices can be wearable electronic devices and mobile terminal devices. The mobile terminal device includes a mobile phone, a notebook or a tablet computer, and the wearable electronic device includes a smart watch or smart glasses. The embodiments of the present disclosure are not limited to this.

[0166] The first chip has a first interface for interacting with other chips, and the first chip integrates functional modules that need to interact with the second chip; the second chip has a second interface for interacting with other chips, and the second chip integrates functional modules that need to interact with the second chip. Here, the first interface and the second interface include I2C, SPI, or GPIO, etc., which are not limited in the embodiments of the present disclosure.

[0167] The first chip and the second chip are microcontroller chips or communication interface chips. For example, when the first chip and the second chip are microcontroller chips, they include STMicroelectronics (STM32) series or Peripheral Interface Controller (PIC) series, etc.; when the first chip and the second chip are communication interface chips, they include SPI controller chips or I2C controller chips, etc., which are not limited in the embodiments of the present disclosure.

[0168] It should be noted that the types of the first chip and the second chip can be set according to the actual needs of the electronic device, and the embodiments of the present disclosure are not limited to this. For example, when the electronic device requires audio processing function, the first chip is an audio processor and the second chip is a communication interface chip for connecting to an external audio device (such as a speaker) of the electronic device.

[0169] The drive input of the chip connection circuit is connected to the first interface of the first chip to receive signals from the first chip. The output of the chip connection circuit is connected to the second interface of the second chip to transmit the drive current processed by the chip connection circuit to the second chip. Furthermore, because the drive circuit in the chip connection circuit has different operating states, the drive current output by the drive circuit through the output terminal varies depending on the operating state of the drive circuit. This shows that the chip connection circuit is flexible and adjustable, capable of adapting to different operating environments and requirements.

[0170] In the embodiment of the present disclosure, through the chip connection circuit, the first chip and the second chip can work together to realize the function of the electronic device, and based on the different working states of the driving circuit in the chip connection circuit, the flexibility of the first chip to interact with the second chip through different driving currents is improved, and the first chip can interact with the second chip of different power, thereby improving the universality of the first chip.

[0171] In one embodiment, the first chip further includes a third interface; the third interface is connected to a communication input terminal of the chip connection circuit.

[0172] The third interface includes I2C, SPI, or GPIO, etc., which is not limited in the embodiment of the present disclosure.

[0173] It should be noted that the third interface of the first chip is connected to the communication input end of the chip connection circuit, which is used to send communication signals to the chip connection circuit. The second chip receives the communication signal transmitted from the output end of the chip connection circuit through the second interface, that is, the first chip and the second chip complete communication.

[0174] In the embodiment of the present disclosure, the third interface of the first chip can transmit communication signals, so that the first chip and the second chip can communicate while transmitting driving current, thereby improving the communication capability of the electronic device.

[0175] To better understand the chip connection circuit and electronic device in one or more of the above embodiments, the embodiments of the present disclosure are exemplified as follows:

[0176] Figure 8 An electronic device structure according to an exemplary embodiment is shown Figure 1 .like Figure 8 As shown, the electronic device includes: a first chip 10, a second chip 30, and a chip connection circuit 20;

[0177] The first chip 10 includes a first interface 110 and a third interface 120 , and the second chip 30 includes a second interface 302 ;

[0178] The chip connection circuit 20 includes a driving input terminal 201, an output terminal 202 and a driving circuit;

[0179] The driving circuit includes a first power supply terminal 203, a second power supply terminal 204, a first switch circuit 211 and a second switch circuit 212;

[0180] The first switch circuit 211 includes a third impedance component 403, a fourth switch 224 and a fifth switch 225;

[0181] The second switch circuit 212 includes a first transistor 221, a second impedance component 402, a second transistor 222, a first impedance component 401, a sixth switch 226 and a seventh switch 227;

[0182] The chip connection circuit 20 further includes a third power supply terminal 205 , a third transistor 223 and a fourth impedance component 404 .

[0183] In the disclosed embodiment, the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, and the third transistor is an NMOS transistor. As shown in the figure, the gate of the first transistor is connected to the second power supply terminal, the source is connected to the drive input terminal, and the drain is connected to the second transistor; the gate of the second transistor is connected to the first transistor, the source is connected to the first input terminal, and the drain is connected to the output terminal; the gate of the third transistor is connected to the third power supply terminal, the source is connected to the communication input terminal, and the drain is connected to the output terminal.

[0184] The voltage of the first power supply terminal is 2.8 V, and the voltage of the second power supply terminal and the third power supply terminal are both 1.8 V. The first impedance component is a 3.3 kilo-ohm resistor, the second impedance component is a 3.3 kilo-ohm resistor, the third impedance component is a 0 to 1 kilo-ohm sliding resistor, and the fourth impedance component is a 3.3 kilo-ohm resistor.

[0185] When the drive circuit is in a first operating state, the sixth and seventh switches are open, the fourth and fifth switches are closed, the first interface of the first chip transmits a high level to the drive input terminal of the chip connection circuit, the first transistor is turned off, and the second transistor is turned off. The second chip receives a drive current transmitted by the first switch circuit, where the current value is the ratio of the voltage at the first power supply terminal to the resistance value of the third impedance component.

[0186] When the drive circuit is in the second operating state, the sixth and seventh switches are closed, and the fourth and fifth switches are closed. The first interface of the first chip transmits a low level to the drive input terminal of the chip connection circuit, turning on the first transistor. The first interface then transmits a low level to the second transistor, turning on the second transistor. The second chip receives not only the drive current transmitted by the first switch circuit but also the additional drive current drawn by the second switch circuit through the second transistor to ensure normal operation of the second chip.

[0187] It should be noted that the third interface of the first chip transmits a communication signal to the communication input end of the chip connection circuit. When the third transistor is turned on, the 1.8-volt logic level signal of the third power supply end can be converted into a 2.8-volt logic level signal, which is used for the second chip to communicate with the first chip through the output end of the chip connection circuit.

[0188] In the embodiment of the present disclosure, the driving input end of the chip connection circuit transmits the electrical signal input by the chip, and the output end of the chip connection circuit outputs the driving current. The chip connection circuit also includes a driving circuit, and the driving circuit is connected to the connection line between the driving input end and the output end. It can be seen that the chip connection circuit can provide a reliable driving current for the chip, so that the chip can better perform the driving work. And the driving circuit has different working states. When the working state of the driving circuit is different, the driving current output by the driving circuit through the output end is different. It can be seen that the chip connection circuit has flexibility and adjustability, and can adapt to different working environments and needs, thereby improving the universality of the chip connected to the chip connection circuit.

[0189] Figure 9 FIG. 1 is a flow chart of a chip driving method according to an exemplary embodiment. Figure 9 As shown, the chip driving method mainly includes the following steps:

[0190] Step 1001: In response to a communication instruction for a first chip and a second chip in an electronic device to communicate, generate a control instruction for a chip connection circuit connecting the first chip and the second chip;

[0191] Step 1002: Switching the working state of the driving circuit in the chip connection circuit based on the control instruction;

[0192] Step 1003 : driving the second chip based on the driving current output by the switched driving circuit.

[0193] In step 1001, after receiving the communication instruction, the first chip generates a control instruction for the chip connection circuit. The control instruction may include a specific command code and parameters for switching the working state of the driving circuit in the chip connection circuit.

[0194] In the embodiment of the present disclosure, the operating state of the driving circuit in the chip connection circuit may include a first operating state and a second operating state, wherein the driving current output by the driving circuit in the first operating state and the second operating state is different.

[0195] It should be noted that the driving current output by the driving circuit in the first working state is smaller than the driving current output by the driving circuit in the second working state.

[0196] In step 1002, the chip connection circuit performs corresponding operations according to the received control instruction and switches the working state.

[0197] Exemplarily, the chip connection circuit receives a control instruction to switch the working state of the driving circuit from the first working state to the second working state.

[0198] It should be noted that the operation of switching the working state of the chip connection circuit includes adjusting the conduction or disconnection of the switch circuit, adjusting the impedance or resistance value, and other related operations.

[0199] In step 1003, the driving circuit of the chip connection circuit outputs a driving current, and the driving current is connected to the circuit of the second chip from the output end of the electronic device, that is, the first chip provides a driving current for the operation of the second chip based on the chip connection circuit, thereby driving the second chip to operate.

[0200] The second chip performs corresponding operations according to the received driving current. For example, the second chip can perform operations such as receiving data or executing commands according to the received driving current.

[0201] In the embodiment of the present disclosure, a chip driving method is used to realize the conversion of the working state of the driving circuit in the chip connection circuit based on communication instructions and control instructions, thereby enabling the first chip to drive the second chip according to the different driving currents output by the driving circuit in different working states, thereby improving the flexibility of the interaction between the first chip and the second chip.

[0202] In one embodiment, switching the working state of the driving circuit in the chip connection circuit based on the control instruction includes:

[0203] Based on the control instruction, controlling the driving circuit to switch from the first working state to the second working state;

[0204] The driving current output when the driving circuit is in the first working state is smaller than the driving current output when the driving circuit is in the second working state.

[0205] In an embodiment of the present disclosure, the chip connection circuit controls the drive circuit to switch from the first working state to the second working state based on the control instruction. Wherein, the drive current output when the drive circuit is in the first working state is a first current value, and the drive current output when the drive circuit is in the second working state is a second current value, and the first current value is less than the second current value. It should be noted that when the drive circuit is in the first working state, since the first current value is less than the second current value, the power consumption of the drive circuit in the first state is less than the power consumption of the drive circuit in the second state. Therefore, the drive circuit in the first working state is suitable for low-power or light-load scenarios, and the first working state is a state in which the drive circuit is in low power consumption.

[0206] It is understandable that when the first chip and the second chip are not communicating, the driving circuit does not need to provide additional driving current for the second chip to communicate and work. At this time, the driving circuit is in the first working state, which means the driving circuit is in a low power consumption state. However, when the first chip and the second chip need to communicate, the driving current needs to be increased for the second chip to work based on the communication signal. At this time, the chip connection circuit needs to be switched from the first working state to the second working state. Therefore, the driving circuit switches the first working state to the second working state based on the control instruction generated by the communication instruction for the first chip and the second chip to communicate. In the embodiment of the present disclosure, the driving circuit is controlled to switch from the first working state to the second working state based on the control instruction, so that the driving circuit provides additional driving current for the first chip and the second chip to communicate, thereby improving the stability of the communication between the first chip and the second chip, and improving the communication and work efficiency of the second chip.

[0207] In another embodiment, the chip driving method may further include: during the communication between the first chip and the second chip, in response to a communication disconnection instruction, controlling the driving circuit to switch from the second working state to the first working state.

[0208] It is understood that when the first chip and the second chip are communicating, the driving current of the driving circuit in the second operating state is used to enable the second chip to operate based on the communication signal. At this time, when the first chip and the second chip lose communication, the driving circuit does not need to provide additional driving current to the second chip for communication and operation, and the driving circuit can be switched from the second operating state to the first operating state.

[0209] The communication disconnection instruction indicates that the first chip and the second chip are switched from a communication state to a communication disconnection state.

[0210] In the embodiment of the present disclosure, the driving circuit is controlled to switch from the second working state to the first working state based on the communication disconnection instruction, thereby reducing the driving current output by the driving circuit, and thereby reducing the power of the first chip and the second chip after switching from the communication state to the communication disconnection state, thereby saving energy consumption of the first chip and the chip connection circuit.

[0211] In one embodiment, controlling the driving circuit to switch from the first working state to the second working state based on the control instruction includes:

[0212] Based on the control instruction, the second switch circuit of the driving circuit is controlled to switch from an off state to an on state, so that the driving circuit is in a second working state.

[0213] In an embodiment of the present disclosure, a drive circuit includes a first switching circuit and a second switching circuit. The first switching circuit is connected to a first connecting line between a first power supply terminal and an output terminal. When the first switching circuit is turned on, a current output from the first power supply terminal to the output terminal via the turned-on first connecting line is a first ratio of a voltage at the first power supply terminal to a total resistance of the first connecting line.

[0214] The second switching circuit is connected to the input terminal, the first power terminal, and the output terminal, and includes a second switching circuit connected to a second connection path between the first power terminal and the output terminal. When the second switching circuit is turned on, a current output from the first power terminal to the output terminal via the second switching circuit is a second ratio of the voltage at the first power terminal to the total resistance of the second connection path.

[0215] When the first switch circuit is in the on state and the second switch circuit is in the off state, the drive current outputted by the output terminal of the drive circuit is a first ratio; when both the first switch circuit and the second switch circuit are in the on state, according to Gilchhoff's current law, the current outputted by the output terminal of the drive circuit is the sum of the first ratio and the second ratio. That is, the drive current when the first switch circuit is in the first working state is less than the drive current when the first switch circuit is in the second working state.

[0216] Thus, when the second switch circuit switches from off to on, the driving current output by the driving circuit to the output end changes from the first current value to the second current value, that is, the driving circuit switches from the first working state to the second working state.

[0217] In the embodiment of the present disclosure, the driving current in the first working state helps to reduce circuit power consumption and improve energy-saving performance; the driving current in the second working state helps to increase circuit load and improve working performance. The driving circuit switches from the first working state to the second working state, thereby improving the stability of communication between the first chip and the second chip, and improving the communication and working efficiency of the second chip.

[0218] Figure 10 An electronic device frame according to an exemplary embodiment is shown Figure 2 For example, the apparatus 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

[0219] Reference Figure 10 , the device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0220] The processing component 802 generally controls the overall operation of the device 800, such as operations associated with at least one of display, phone calls, data communications, camera operation, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 802 may include one or more modules to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

[0221] The memory 804 is configured to store various types of data to support operations on the device 800. Examples of such data include at least one of the following: instructions for any application or method operating on the device 800, contact data, phone book data, messages, pictures, and videos. The memory 804 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0222] The power supply component 806 provides power to the various components of the device 800. The power supply component 806 can include at least one of the following: a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device 800.

[0223] The multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0224] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), which is configured to receive external audio signals when the device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0225] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as a keyboard, click wheel, and buttons. These buttons may include, but are not limited to, a home button, volume buttons, a start button, and a lock button.

[0226] The sensor assembly 814 includes one or more sensors for providing various aspects of the status assessment of the device 800. For example, the sensor assembly 814 can detect the open / closed state of the device 800, the relative positioning of components, such as the display and keypad of the device 800. The sensor assembly 814 can also detect changes in the position of the device 800 or a component thereof, the presence or absence of user contact with the device 800, the orientation or acceleration / deceleration of the device 800, and changes in the temperature of the device 800. The sensor assembly 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 can also include an optical sensor, such as a complementary metal oxide semiconductor (CMOS) or charge coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 can also include, but is not limited to, at least one of the following: an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, and a temperature sensor.

[0227] The communication component 816 is configured to facilitate communication between the device 800 and other devices in a wired or wireless manner. The device 800 can access a wireless network based on a communication standard, such as Wi-Fi, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0228] In an exemplary embodiment, the device 800 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0229] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including executable instructions or a computer program. The instructions or computer program can be executed by the processor 820 of the apparatus 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0230] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of a mobile terminal, enables the mobile terminal to perform any of the chip driving methods described above in the embodiments of the present disclosure. For example, the method includes: in response to a communication instruction for communication between a first chip and a second chip in an electronic device, generating a control instruction for a chip connection circuit connecting the first chip and the second chip; based on the control instruction, switching the operating state of a drive circuit in the chip connection circuit; and driving the second chip based on the drive current output by the switched drive circuit.

[0231] The present disclosure provides a computer program product comprising a computer program or executable instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or executable instructions from the computer-readable storage medium and executes the computer program or executable instructions, causing the computer device to perform any of the chip driving methods described above in the present disclosure.

[0232] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0233] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A chip connection circuit, characterized in that: include: Driving input terminal, output terminal and driving circuit; The driving circuit is connected to the connection line between the driving input terminal and the output terminal and has different working states; Wherein, when the working state of the driving circuit is different, the driving current output by the output end is different.

2. The chip connection circuit according to claim 1, characterized in that: The driving circuit has a first working state and a second working state; The driving current output when the driving circuit is in the first working state is smaller than the driving current output when the driving circuit is in the second working state.

3. The chip connection circuit according to claim 2, characterized in that: The driving circuit includes: a first power supply terminal; a first switch circuit, connecting the first power supply terminal and the output terminal; a second switch circuit, connecting the driving input terminal, the first power supply terminal and the output terminal; Wherein, when the first switch circuit is in the on state and the second switch circuit is in the off state, the drive circuit is in the first working state; When both the first switching circuit and the second switching circuit are in the on state, the driving circuit is in the second working state.

4. The chip connection circuit according to claim 3, characterized in that: The driving circuit further includes a second power supply terminal; The second switch circuit includes a first switch component and a second switch component; The first switch component is connected to the second power supply terminal, the driving input terminal and the second switch component; The second switch component is connected to the first switch component, the first power supply end and the output end; Wherein, when both the first switch component and the second switch component are in the on state, the second switch circuit is turned on.

5. The chip connection circuit according to claim 4, characterized in that: The driving circuit further includes: a first impedance component, connected to the first power supply terminal and the second switch component, and connected in parallel with the second switch component; and / or, a second impedance component, connected to the second power supply terminal and the first switch component, and connected in parallel with the first switch component; The first impedance component and the second impedance component are both configured to protect the driving circuit when the driving circuit switches the working state.

6. The chip connection circuit according to claim 4, characterized in that: The first switching component includes a first transistor and the second switching component includes a second transistor; Wherein, the first electrode of the first transistor is connected to the second power supply terminal, the second electrode of the first transistor is connected to the driving input terminal, and the third electrode of the first transistor is connected to the second transistor; A first electrode of the second transistor is connected to the first transistor, a second electrode of the second transistor is connected to the first power supply terminal, and a third electrode of the second transistor is connected to the output terminal.

7. The chip connection circuit according to any one of claims 3 to 6, characterized in that: The driving circuit further includes: A third impedance component is connected to the first power supply end and the output end, and is connected in series with the first switch circuit, and is configured to adjust the driving current.

8. The chip connection circuit according to any one of claims 1 to 6, characterized in that: The chip connection circuit further includes: a third power supply terminal; a communication input terminal connected to the output terminal and configured to transmit at least a communication signal; The third switch component is connected to the third power supply terminal, the communication input terminal and the output terminal, and is configured to open or close the connection line between the communication input terminal and the output terminal.

9. The chip connection circuit according to claim 8, characterized in that: The chip connection circuit further includes: A fourth impedance component, one end of which is connected to the third power supply terminal and the other end of which is connected to the third switch component and the communication input terminal, is configured to protect the drive circuit when the third switch component switches the connection line between the communication input terminal and the output terminal on and off.

10. The chip connection circuit according to claim 8, characterized in that: The third switch component includes a third transistor; A first electrode of the third transistor is connected to the communication input terminal, a second electrode of the third transistor is connected to the output terminal, and a third electrode of the third transistor is connected to the third power supply terminal.

11. An electronic device, characterized in that: The electronic device comprises: A first chip having a first interface; A second chip having a second interface; The chip connection circuit according to any one of claims 1 to 10; wherein the driving input end of the chip connection circuit is connected to the first interface, and the output end of the chip connection circuit is connected to the second interface.

12. The electronic device according to claim 11, wherein: The first chip further includes a third interface; the third interface is connected to the communication input end of the chip connection circuit.

13. A chip driving method, characterized in that: The method comprises: In response to a communication instruction for a first chip and a second chip in an electronic device to communicate, generating a control instruction for a chip connection circuit connecting the first chip and the second chip; Switching the working state of the driving circuit in the chip connection circuit based on the control instruction; The second chip is driven based on the driving current output by the switched driving circuit.

14. The method according to claim 13, wherein: The switching of the working state of the driving circuit in the chip connection circuit based on the control instruction includes: Based on the control instruction, controlling the drive circuit to switch from a first working state to a second working state; The driving current output when the driving circuit is in the first working state is smaller than the driving current output when the driving circuit is in the second working state.

15. The method according to claim 14, characterized in that The step of controlling the drive circuit to switch from the first working state to the second working state based on the control instruction includes: Based on the control instruction, the second switch circuit of the drive circuit is controlled to switch from an off state to an on state, so that the drive circuit is in the second working state.

16. A non-transitory computer-readable storage medium storing a computer program or instruction, characterized in that: When the computer program or instructions in the storage medium are executed by an electronic device, the steps of the method according to any one of claims 13 to 15 are implemented.

17. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 13 to 15 are implemented.

Images