Wafer graph generation method and device, storage medium and equipment
By automatically generating wafer maps using physical location information in the die failure bit test result file, the problem of low generation efficiency and error prone in the prior art is solved, and efficient and automated wafer map generation is achieved.
Patent Information
- Application Number
- CN202410175937.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-07
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, wafer diagram generation efficiency is low and error-prone, and it mainly depends on manual drawing of Excel or drawing tools.
By obtaining the die failure bit test result files of each die on the wafer, the physical location information in these files is used to automatically generate the wafer map, avoiding the manual drawing process.
It improves the efficiency of wafer map generation, reduces the probability of errors, and realizes automated and efficient wafer map generation.
Smart Images
Figure CN120449801A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method, device, storage medium and equipment for generating a wafer map. Background Art
[0002] Wafers are silicon wafers used to make silicon semiconductor circuits. Wafers are cut into individual dies, which are then packaged to create chips.
[0003] A wafer map records the distribution of the die on a wafer and is an important clue for tracing the cause of product anomalies. Analyzing the wafer map can pinpoint the possible causes of low yields.
[0004] Currently, wafer maps are mainly designed manually with the help of Excel or drawing tools, which is inefficient and prone to errors. Summary of the Invention
[0005] The problem to be solved by the present invention is: how to efficiently generate wafer images and reduce the probability of errors.
[0006] To solve the above problems, an embodiment of the present invention provides a method for generating a wafer map, the method comprising:
[0007] Obtaining a die failure bit test result file corresponding to each die on the wafer; the die failure bit test result file includes physical position information of the tested die on the wafer;
[0008] A wafer map is generated based on the die failure bit test result file.
[0009] Optionally, the die failure bit test result file includes: a .txt file recording die failure bit test result information.
[0010] Optionally, the method further includes:
[0011] The content of the .txt file is read, the total number of failed bits on each die is counted, and the statistical result is displayed on the wafer map.
[0012] Optionally, the die failure bit test result file includes: a preset format file that displays the die failure bit position.
[0013] Optionally, the preset format file is a .png file
[0014] Optionally, the method further includes:
[0015] The content of the preset format file is read, and the image in the preset format file is displayed in the wafer map.
[0016] Optionally, the file name of the die failure bit test result file includes physical location information of the tested die on the wafer.
[0017] An embodiment of the present invention further provides a wafer map generating device, the device comprising:
[0018] An acquisition unit adapted to acquire a die failure bit test result file corresponding to each die on the wafer; the die failure bit test result file includes physical position information of the tested die on the wafer;
[0019] The generating unit is adapted to generate a wafer map based on the die failure bit test result file.
[0020] Optionally, the die failure bit test result file acquired by the acquisition unit includes: a .txt file recording die failure bit test result information.
[0021] Optionally, the die failure bit test result file acquired by the acquisition unit includes: a preset format file displaying the die failure bit position.
[0022] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the steps of any of the above methods.
[0023] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above methods when running the computer program.
[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0025] Using the solution of the present invention, when testing dies on a wafer, a die failure bit test result file is generated. Because the die failure bit test result file contains information about the physical location of the tested dies on the wafer, a wafer map can be generated based on the die failure bit test result file. This eliminates the need to manually draw a wafer map using Excel or drawing tools, thereby improving the efficiency of wafer map generation and reducing the probability of errors. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a schematic flow chart of a wafer map generation method according to an embodiment of the present invention;
[0027] Figure 2 It is a schematic diagram of a wafer map drawn manually with the help of Excel;
[0028] Figure 3 It is a schematic diagram of a wafer map drawn manually with the help of a drawing tool;
[0029] Figure 4 This is a schematic diagram of a wafer map generated by the wafer map generation method according to an embodiment of the present invention;
[0030] Figure 5 This is a schematic diagram comparing the time taken to generate wafer images using different methods;
[0031] Figure 6 It is a structural schematic diagram of a wafer image generating device in an embodiment of the present invention. DETAILED DESCRIPTION
[0032] Currently, wafer maps are mainly designed manually with the help of Excel or drawing tools, which is inefficient and prone to errors.
[0033] To address this issue, the present invention provides a method for generating a wafer map. This method generates a die failure bit test result file when the die on the wafer are tested in advance. Because the die failure bit test result file contains information about the physical location of the tested die on the wafer, a wafer map can be generated based on the die failure bit test result file. This eliminates the need to manually draw a wafer map using Excel or drawing tools, thereby improving wafer map generation efficiency and reducing the probability of errors.
[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0035] Reference Figure 1 , an embodiment of the present invention provides a method for generating a wafer map, the method may include the following steps:
[0036] Step 11: Obtain a die failure bit test result file corresponding to each die on the wafer; the die failure bit test result file includes physical position information of the tested die on the wafer.
[0037] In practice, after the wafer is manufactured, all dies on the wafer need to be tested to determine the failed bits on each die. Some dies may have multiple failed bits, while some may have zero failed bits, meaning no failed bits. A bit failure on a die refers to a fault in the semiconductor structure corresponding to that bit, which is typically a static random-access memory (SRAM). By writing a data stream to the SRAM and performing a read test, it is possible to determine which bit in the SRAM has a read error.
[0038] In the prior art, the die failure bit test result file usually contains the physical location information of each failure bit in the die, and the file type usually only includes .txt files. Among them, the .txt file records the test results of each failure bit on the die in text form, and usually contains the physical location information of each failure bit in the die, that is, the physical coordinates of each failure bit in the die. The .txt file can also include the logical address of the failure bit. For example, a piece of information in the .txt file can be: 0, 0, 19.48, 348.45, where the first "0" represents the logical address, the second "0" represents the failure bit number, "19.48" represents the x-coordinate of the failure bit, and "348.45" represents the y-coordinate of the failure bit.
[0039] However, in the prior art, the naming of the .txt file has nothing to do with the physical location of the corresponding die, and the .txt file containing the test results of all the failed bits of the die on the wafer is usually stored in a folder named after the wafer identity.
[0040] In an embodiment of the present invention, before generating a wafer map, the physical locations of the failure bits in each .txt file of the wafer can be read, and a corresponding preset format file can be generated based on the physical locations of the failure bits. The preset format file can display the location of the failure bits on the die in the form of an image, that is, the file will display an image of the die and mark the location of the failure bits on the die image.
[0041] In a specific implementation, the preset format file includes but is not limited to a .png file. In this case, the .txt file and the preset format file are both used as the die failure bit test result file. The .txt file and the preset format file of the same die can have a binding relationship.
[0042] When performing a die fail bit test, the resulting die fail bit test result file can be named based on the physical location of the die on the wafer. This physical location information refers to the x and y coordinates of the die on the wafer. For example, the die fail bit test result file name might be: Die_0_1_AT000211_18_sbit.txt, where the 0 and 1 after Die represent the x and y coordinates of the die, respectively, and "AT000211_18_sbit" represents the wafer's identity.
[0043] In some embodiments, the .txt file can be named only with the physical location information of the tested die on the wafer. When the wafer map is subsequently generated, the program is executed to traverse the .txt files in the die failure bit test result folder to obtain the physical location information of the die.
[0044] In other embodiments, the preset format file may be named only according to the physical location information of the tested die on the wafer. When a wafer map is subsequently generated, the program is executed to traverse the preset format file in the die failure bit test result folder to obtain the physical location information of the die.
[0045] In some other embodiments, the .txt file and the preset format file can also be named according to the physical location information of the tested grain on the wafer. When the wafer map is subsequently generated, the program is executed to traverse the .txt file and the preset format file in the grain failure bit test result folder to obtain the physical location information of the grain.
[0046] Step 12: Generate a wafer map based on the die failure bit test result file.
[0047] In a specific implementation, after obtaining the die failure bit test result file, the die's location can be marked in the wafer map generation area based on the physical location information of the die in the die failure bit test result file name. In other words, the die is displayed in the wafer map coordinate system. In this way, by traversing the failure bit test result files of all the die, the physical location information of each die on the wafer can be obtained, thereby generating a wafer map.
[0048] In the prior art, .txt files record the physical location of each failed bit on the tested die, but do not count the total number of failed bits. In other words, based on the .txt file, the physical location of each failed bit on the tested die can be directly obtained, but the total number of failed bits on the tested die cannot be directly determined.
[0049] In one embodiment, when the die failure bit test result file containing the physical location information of the tested die on the wafer is a .txt file, after determining the physical location of the tested die on the wafer map based on the file name of the .txt file, the .txt file can also be read to count the total number of failure bits on each die, and the statistical results can be displayed on the wafer map. In this way, the total number of failure bits on each die can be intuitively determined based on the generated wafer map, which facilitates subsequent analysis.
[0050] Furthermore, after generating a wafer map based on a .txt file, a preset format file for the same die can be read, so that the image in the preset format file can be displayed in the wafer map. Specifically, the image in the preset format file can be displayed at the location of the corresponding die on the wafer map.
[0051] In another embodiment, when the die failure bit test result file containing the physical location information of the tested die on the wafer is a preset format file, after determining the physical location of the tested die on the wafer map based on the file name of the preset format file, the contents of the preset format file can be read and the image in the preset format file can be displayed on the wafer map. In this way, the location of the failure bit of each die on the die can be intuitively determined based on the generated wafer map, which facilitates subsequent analysis.
[0052] Furthermore, after generating a wafer map based on a pre-formatted file, the system can also read a .txt file for the same die, count the total number of failed bits on each die, and display the result on the wafer map. This allows the generated wafer map to intuitively determine the total number of failed bits on each die, facilitating subsequent analysis.
[0053] In another embodiment, when the die failure bit test result file containing the physical position information of the tested die on the wafer is a .txt file and a preset format file, the physical position of the tested die on the wafer map can be determined based on the file name of the .txt file, or the physical position of the tested die on the wafer map can be determined based on the file name of the preset format file.
[0054] After determining the physical location of the tested die on the wafer map, the .txt file can be read first to count the total number of failed bits on each die and display the statistical results on the wafer map. Next, the preset format file can be read and the physical location information of the tested die on the wafer in the file name of the preset format file can be matched with the physical location of each die on the wafer map. That is, the x and y coordinates in the preset format file name can be matched with the x and y coordinates of the wafer map. If the match is successful, the image in the .png file can be displayed at the corresponding die position in the wafer map.
[0055] After determining the physical location of the tested die on the wafer map, a pre-formatted file can be read first, and the image in the pre-formatted file can be displayed at the corresponding die location on the wafer map. Next, a .txt file can be read, and the x and y coordinates in the .txt file name can be matched with the x and y coordinates on the wafer map. If the match is successful, the statistical result of the total number of failed bits on the die can be displayed on the wafer map.
[0056] Figure 2 This is a schematic diagram of a wafer map drawn manually using Excel. Figure 3 It is a schematic diagram of the wafer map drawn manually with the help of a drawing tool (such as DE-G). Figure 4 This is a schematic diagram of a wafer image automatically generated by the wafer image generation method according to an embodiment of the present invention. Figures 2 to 4The number at each die location on the wafer map indicates the total number of failed bits in that die.
[0057] Figure 5 This is a schematic diagram comparing the time taken to generate a wafer image using Excel, a drawing tool, and the wafer image generation method of the present invention. Figure 5 ,use Figure 2 The method takes about 30 minutes to generate a wafer map. Figure 3 It takes about 20 minutes to generate a wafer map using the method in the embodiment of the present invention, while it only takes 1 minute to automatically generate a wafer map using the wafer map generation method in the embodiment of the present invention. Figure 2 and Figure 3 By generating wafer maps in a simple way, the efficiency can be increased by more than 95%.
[0058] From the above content, it can be seen that when the wafer image generation method in the embodiment of the present invention automatically generates a wafer image, it takes a short time, is highly efficient, and automatically executes the program, which is not prone to errors.
[0059] In order to enable those skilled in the art to better understand and implement the present invention, the apparatus, test system, electronic device and computer-readable storage medium corresponding to the above method are described in detail below.
[0060] Reference Figure 6 The embodiment of the present invention further provides a wafer map generating device 60, which may include: an acquisition unit 61 and a generation unit 62.
[0061] The acquisition unit 61 is adapted to acquire a die failure bit test result file corresponding to each die on the wafer; the die failure bit test result file includes physical position information of the tested die on the wafer;
[0062] The generating unit 62 is adapted to generate a wafer map based on the die failure bit test result file.
[0063] In some embodiments, the die failure bit test result file acquired by the acquisition unit 61 includes: a .txt file recording die failure bit test result information.
[0064] In some embodiments, the die failure bit test result file acquired by the acquisition unit 61 includes a preset format file that displays the location of the die failure bit.
[0065] In a specific implementation, the generated wafer map may include the total number of failed bits on each die, and may also include an image showing the location of the failed bits in the die.
[0066] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the steps of any of the above methods.
[0067] In a specific implementation, the computer-readable storage medium may include: ROM, RAM, magnetic disk or optical disk, etc.
[0068] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above methods when running the computer program.
[0069] Regarding the various modules / units contained in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or partly software modules / units and partly hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units contained therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on the processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units contained therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component of the chip module (such as a chip, circuit module, etc.) or in different components, or at least some of the modules / units can be implemented in the form of hardware such as circuits. The element can be implemented in the form of a software program, which runs on the processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on the processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.
[0070] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for generating a wafer map, characterized in that: include: Obtain the die failure bit test result file corresponding to each die on the wafer; The die failure bit test result file includes physical location information of the tested die on the wafer; A wafer map is generated based on the die failure bit test result file.
2. The method for generating a wafer map according to claim 1, wherein: The die failure bit test result file includes: a .txt file recording die failure bit test result information.
3. The method for generating a wafer map according to claim 2, wherein: Also includes: The content of the .txt file is read, the total number of failed bits on each die is counted, and the statistical result is displayed on the wafer map.
4. The method for generating a wafer map according to claim 1 or 2, wherein: The die failure bit test result file includes a preset format file that displays the die failure bit position.
5. The method for generating a wafer map according to claim 4, wherein: The preset format file is a .png file.
6. The method for generating a wafer map according to claim 4, wherein: Also includes: The content of the preset format file is read, and the image in the preset format file is displayed in the wafer map.
7. The method for generating a wafer map according to claim 1, wherein: The file name of the die failure bit test result file contains the physical location information of the tested die on the wafer.
8. A wafer map generating device, characterized in that: include: An acquisition unit, adapted to acquire a die failure bit test result file corresponding to each die on the wafer; The die failure bit test result file includes physical location information of the tested die on the wafer; The generating unit is adapted to generate a wafer map based on the die failure bit test result file.
9. The wafer map generating device according to claim 8, wherein: The die failure bit test result file acquired by the acquisition unit includes: a .txt file recording die failure bit test result information.
10. The wafer map generating device according to claim 8 or 9, wherein: The die failure bit test result file acquired by the acquisition unit includes a preset format file showing the location of the die failure bit.
11. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement the steps of the method according to any one of claims 1 to 7.
12. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor runs the computer program, the steps of the method according to any one of claims 1 to 7 are performed.