Time sequence sensing filling and inserting method and system based on key network

Abstract

The invention relates to a key network-based time sequence sensing filling insertion method and system, and relates to the technical field of integrated circuit design. In consideration of the influence of a coupling capacitance effect on the overall performance of the circuit, a key signal line which is easily influenced by capacitance is extracted from a layout, and a capacitance buffer area is divided around the key signal line; and dividing a candidate filling area in the layout by matching with an area occupied by the original signal line and a reserved area reserved for conforming to the DRC rule, performing rectangularization division, calculating a filling priority value, and preferentially filling a rectangular area with a large filling priority value until the layout conforms to a target density requirement. According to the invention, under the condition that the virtual filling effect is ensured, the coupling capacitance generated after virtual filling is greatly reduced, and the performance of the whole circuit is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more specifically to: 1. a fill insertion method based on timing awareness of key networks; 2. a fill insertion system based on timing awareness of key networks. Background Art

[0002] In the very large-scale integrated circuit (VLSI) manufacturing process, dummy fill is a critical back-end process. Dummy fill typically involves inserting electrically nonfunctional fill patterns into the blank areas between layouts to ensure uniform layout density. Its primary purpose is to improve chip metal flatness after CMP (Chemical Mechanical Polishing), preventing localized corrosion or dishing caused by uneven metal density, thereby improving chip yield.

[0003] However, as the process nodes of integrated circuits continue to shrink, the circuit requirements for signal integrity and timing performance become increasingly stringent, and the impact of the fill pattern itself on the electrical characteristics of the chip is also increasing.

[0004] Existing filling and insertion methods mainly focus on achieving uniform distribution of metal density, but the filling rules are relatively arbitrary and can easily adversely affect the performance of the overall circuit of the layout. Summary of the Invention

[0005] Based on this, it is necessary to provide a timing-aware fill insertion method and system based on critical networks to address the problem that the existing fill insertion method is prone to adversely affect the overall circuit performance of the layout.

[0006] The present invention is achieved by adopting the following technical solutions: In a first aspect, the present invention discloses a timing-aware padding insertion method based on a key network, comprising: S1, parse the target layout to obtain the layout; The layout characterizes the structural spatial relationship of all metal layers in the target layout. Each metal layer includes: a number of original signal lines and a number of vias. Each original signal line has a corresponding signal line label. A single via only allows a single original signal line to pass through, and is used to connect two original signal lines with the same signal line label in adjacent metal layers. S2, extract several key signal lines from the layout and divide the capacitor buffer area around the key signal lines; S3, based on the DRC (Design Rule Check) rules, divide the candidate filling area in the layout according to the position of the original signal line, key signal line and capacitor buffer area; S4, dividing the candidate filling area into a plurality of rectangular areas, and calculating a filling priority value of each rectangular area; wherein a rectangular area with a higher filling priority value has a smaller coupling capacitance generated therefrom; S5, preferentially filling rectangular areas with larger filling priority values until the layout meets the target density requirement.

[0007] This critical network-based timing-aware fill insertion method implements the method or process according to an embodiment of the present disclosure.

[0008] In a second aspect, the present invention discloses a critical network-based timing-aware fill insertion system, which uses the critical network-based timing-aware fill insertion method disclosed in the first aspect.

[0009] The timing-aware fill insertion system based on key networks includes: a layout parsing module, a capacitor buffer area division module, a candidate fill area division module, a fill sequence determination module, and a virtual fill module.

[0010] The layout parsing module is used to parse the target layout to obtain the layout. The capacitor buffer area division module is used to extract several key signal lines from the layout and divide the capacitor buffer area around the key signal lines. The candidate fill area division module is used to divide the candidate fill area in the layout according to the original signal line, the position of the key signal line and the capacitor buffer area on the basis of complying with the DRC rules. The fill order determination module is used to divide the candidate fill area into several rectangular areas and calculate the fill priority value of each rectangular area. The virtual fill module is used to give priority to filling the rectangular areas with large fill priority values until the layout meets the target density requirements.

[0011] The critical network-based timing-aware fill insertion system implements the method or process according to an embodiment of the present disclosure.

[0012] In a third aspect, the present invention discloses a computer program product, comprising a computer program. When the computer program is executed by a processor, the computer program implements the steps of the key network timing-aware padding insertion method disclosed in the first aspect.

[0013] Compared with the prior art, the present invention has the following beneficial effects: The present invention takes into account the impact of the coupling capacitance effect on the overall performance of the circuit, extracts key signal lines that are susceptible to capacitance from the layout, and divides capacitor buffer areas around the key signal lines. Furthermore, the candidate fill areas are divided in the layout based on the area occupied by the original signal lines and the reserved area set aside to comply with DRC rules. The layout is then rectangularized and the fill priority value is calculated. Rectangular areas with large fill priority values are filled first until the layout meets the target density requirements. The present invention can significantly reduce the coupling capacitance generated after virtual filling while ensuring the virtual filling effect, thereby optimizing the performance of the overall circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 Flowchart of a key network-based timing-aware fill insertion method provided in Example 1 of the present invention; Figure 2 This is an example diagram of adjacent metal layers provided in Example 1 of the present invention; Figure 3 This is an example diagram of dividing the capacitor buffer area and the reserved area provided in Example 1 of the present invention; Figure 4 This is a schematic diagram of the key signal lines, capacitor buffer area, and vertical overlapping area provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0017] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0019] First of all, it should be noted that after reverse analysis of the overall circuit performance of the layout, it was found that virtual fill easily generates coupling capacitance between signal lines. As the process nodes of integrated circuits continue to shrink, the impact of these coupling capacitances has become non-negligible, which can easily lead to higher parasitic capacitance effects, thus leading to negative effects on circuit performance.

[0020] Based on this conclusion, the present invention designs a new dummy filling strategy from the perspective of reducing coupling capacitance.

[0021] Example 1 refer to Figure 1 , shows a flowchart of the timing-aware fill insertion method based on key networks provided in Example 1, which includes the following steps: S1, parse the target layout to obtain the layout.

[0022] It should be noted that the target version Figure 1 A circuit board generally consists of a substrate, several electrical components mounted on the substrate, several stacked metal layers, and an insulating layer. The electrical components serve as the foundation for electrical functionality. Several metal layers, located above the electrical components, contain primary signal lines and vias. The insulating layer sits atop the top metal layer to electrically isolate the circuit board from the outside world.

[0023] The target layout can be digitized using layout files, such as GDS2 (Graphical Data System II) files, OASIS (Open Artwork System Interchange Standard) files, DEF (Design Exchange Format) files, etc. Then, a layout viewing and editing tool (such as KLayout based on the Python platform, which is an open source tool for handling database-related operations) can be used to process the layout file to obtain the layout.

[0024] In this embodiment 1, S1 specifically includes: Obtain the GDS format file (i.e., GDS2 file) of the target layout and process it using the layout viewing and editing tool to obtain the layout.

[0025] Then, the obtained layout characterizes the structural spatial relationship of all metal layers of the target layout.

[0026] See the above record: Each metal layer includes: several original signal lines and several through holes.

[0027] Each original signal line has a corresponding signal line label, such as: Clk (clock signal), Reset (reset signal), Data_in (data input), Enable (enable signal), Data_out (data output), etc.

[0028] A single through-hole only allows a single original signal line to pass through, and is used to connect two original signal lines with the same signal line label in adjacent metal layers. It should be noted that only original signal lines with the same signal line label can be connected.

[0029] To help understand, see Figure 2 The diagram shows the relative relationship of adjacent metal layers (k-1, k, and k+1) from a top-down perspective: the kth metal layer has two original metal wires a1 and a2; the k+1 metal layer has one original metal wire a3; and the k+1 metal layer has one original metal wire a4. a1 connects to a3 via via b1; a3 connects to a2 via b2; and a2 connects to a3 via b3.

[0030] S2, extract several key signal lines that are susceptible to capacitance from the layout, and divide capacitor buffer areas around the key signal lines.

[0031] It should be noted that as integrated circuit process nodes continue to shrink, the distance between original signal lines becomes closer and closer, and the coupling capacitance between them will increase dramatically. The coupling capacitance between two original signal lines at a certain distance can be expressed as: ; Where, C Represents coupling capacitance; d Represents the effective spacing between two original signal lines, measured by the minimum distance between their edges; L Indicates the parallel overlap length between the dummy fill and the original signal line; α 、 β is the empirical coefficient; D Indicates the shielding distance. That is, if the distance between the two original signal lines exceeds D , no coupling capacitance will be generated.

[0032] Then, based on the above formula, it can be seen that areas around the original signal lines where filling is prohibited can be divided to minimize the capacitance generated in these areas.

[0033] Although all original signal lines can be divided into capacitor buffer areas, there are many original signal lines in the layout. If all of them are divided, it will take a very long time, and the time cost is not acceptable. Therefore, it is necessary to select key signal lines and divide the capacitor buffer areas around them.

[0034] As mentioned above, the only difference between the original signal lines is their signal line labels. Based on the signal line attributes reflected by the signal line labels, several key labels susceptible to capacitance are identified. For example, Clk provides a reference for synchronous operation of the entire circuit and is susceptible to capacitance; Reset is used to initialize the circuit state and is also susceptible to capacitance; Enable is used to turn on the circuit and is also susceptible to capacitance; Data_in inputs data to the circuit, and Data_out outputs data from the circuit and is less affected by capacitance.

[0035] For any key tag, search for the corresponding original signal line (i.e., the original signal line belonging to the key tag) on any metal layer. If it exists, start with the original signal line and select both sides along the line extension direction, covering other original signal lines connected to the original signal line (including: directly connected and connected through vias) until the two line ends are reached. The entire line between the two line ends is then regarded as the key signal line. Traverse all key tags and all metal layers until all key information lines are found.

[0036] To assist understanding, see Figure 2 : Assume that the key label is Clk, and the signal line labels of a1~a4 are also Clk; then, we can start from a1, directly reach the end of the line to one side, and then reach the end of the line after passing through b1, a3, b2, a2, and a4 to the other side. Therefore, the key signal line is a1+a3+a2+a4.

[0037] In addition, this embodiment 1 also provides the algorithm steps of S2: Ⅰ, initialize an empty collection C , used to store all the key signal lines finally extracted; Ⅱ, for a key label in the layout l , initialize 3 empty sets S l 、 Visited l 、 M l : gather S l For collection and key tags l Associated key signal lines; gather Visited l Used to record the original signal lines that have been visited to avoid repeated traversal; gather M l For storage and key tags l Associated metal layers.

[0038] Ⅲ, for a key label in the layout l , do the following: Traverse each metal layer in the layout; if there is a key label in the metal layer l , then add the metal layer to the collection M l .

[0039] This step aims to identify all possible tags that may contain the current key l The metal layer of the associated signal line.

[0040] IV. Traversing the Set M l Each metal layer in the , and further traverse all original signal lines in each layer, perform the following operations: If an original signal line is associated with a key label l If it is connected and has not been visited, it is defined as the current signal line segment s and added to it S l ; Then check whether the current signal line segment s is connected (through a through-hole connection or directly connected) to another original signal line s_next; if there is a connection and the other original signal line s_next has not been accessed, first add the current signal line segment s to Visited l , and then update the other original signal line s_next to the current signal line segment s; in this way, the connection path of the current signal line segment is recursively traced until the connection can no longer be extended, and finally the key label is obtained. l Corresponding key signal line set S l .

[0041] This step recursively tracks and collects cross-layer transmission paths through physical connection relationships, thereby completely extracting the entire path of the key network.

[0042] V, will S l Merge into collection C middle; Then, after processing all key tags, return the collection C ——It includes the complete network distribution consisting of all identified key signal lines in the layout.

[0043] Then, after obtaining the key signal lines, the candidate filling areas can be divided. The methods include: Traverse all metal layers; for the key signal line in any metal layer, leave a width of D area as a capacitor buffer area.

[0044] To help understand, see Figure 3 :It shows the layout of the kth metal layer from a top-down perspective. It can be seen that a portion of the width extends around the key signal line. D The area is used as a capacitor buffer area to prevent large coupling capacitance between the critical signal line and the dummy fill.

[0045] S3, based on the DRC rules, divide the candidate filling area in the layout according to the positions of the original signal lines, key signal lines and capacitor buffer areas.

[0046] First, it's important to note that DRC rules require minimum spacing between IC layout patterns. Therefore, in this method, sufficient spacing must be maintained between adjacent original signal lines to prevent potential issues like short circuits and electric field interference, while also meeting heat dissipation requirements. Therefore, a reserved area is created around all original signal lines to comply with DRC rules.

[0047] To assist understanding, see Figure 3 :The original signal line that is not defined as a key signal line will extend to a surrounding area with a width of l The area is used as a reserved area to ensure that the signal line has sufficient manufacturability.

[0048] It should be noted that if an original signal line is a critical signal line, then its surrounding area will actually be divided into not only a capacitor buffer area but also a reserved area - these two areas overlap, and the union of them can be taken. Figure 3 , l Generally less than D Therefore, after taking the union of the two regions, it can be regarded as only the capacitor buffer region remaining.

[0049] Therefore, the methods for dividing the candidate filling area include: Traverse all metal layers; for any metal layer, exclude the area occupied by all original signal lines of the metal layer, the reserved area reserved for all original signal lines of the metal layer to comply with DRC rules, and the capacitor buffer area of all key signal lines of the metal layer to obtain the remaining blank area, and use it as a candidate filling area.

[0050] S4, dividing the candidate filling area into several rectangular areas, and calculating the filling priority value of each rectangular area.

[0051] Since signal lines and vias are rectangular in the layout, the candidate fill areas obtained by S3 are also horizontal and vertical. Therefore, the candidate fill area can be divided into several rectangular areas as candidate fill objects. It is important to note that the number of rectangular areas should be as small as possible.

[0052] Then, the calculation formula for the fill priority value is: Priority=λ1×w+λ2×A-λ3×O; Where Priority represents the fill priority value; λ1, λ2, and λ3 are all positive hyperparameters, which are set according to the process node, capacitance sensitivity, and fill strategy to balance the relationship between fill effect and coupling capacitance suppression; w represents the width of a single rectangular area, which is used to reflect the influence characteristics of the rectangular area on the shape (the larger w, the better); A represents the area of a single rectangular area, which is used to indicate the contribution of the rectangular area to the local metal density (the larger A, the better); O represents the sum of the overlapping areas of a single rectangular area and the original signal lines existing in the upper and lower adjacent metal layers when projected perpendicular to the metal layer, which is used to indicate the potential impact of the rectangular area on the coupling capacitance (the smaller O, the better).

[0053] Therefore, the rectangular area with a higher filling priority value has a smaller corresponding coupling capacitance.

[0054] For easier understanding, see Figure 4 , which shows the relative relationship of adjacent metal layers (layer k-1, layer k, layer k+1) from a side view. It should be noted that there is actually a reserved area at the end of the original signal line perpendicular to the paper, and there is actually a reserved area and capacitor buffer area at the end of the key signal line perpendicular to the paper; Figure 4 In addition, Figure 4 For the leftmost candidate filling area of the kth metal layer, its projection perpendicular to the metal layer direction all falls on the original signal lines of the upper and lower metal layers; Figure 4 For the candidate filling area in the middle of the kth metal layer, its projection perpendicular to the metal layer direction only partially overlaps with the original signal lines of the upper and lower metal layers. Figure 4 For the rightmost candidate filling area of the kth metal layer, its projection perpendicular to the metal layer direction only partially overlaps with the original signal line of the upper metal layer, and completely overlaps with the original signal line of the lower metal layer; so Figure 4 The three candidate filling areas of the k-th metal layer have different corresponding Os.

[0055] S5, preferentially filling rectangular areas with larger filling priority values until the layout meets the target density requirement.

[0056] S5 specifically includes the following steps: S501 , calculating the required filling area of the current metal layer based on the target density requirement and the current layout density.

[0057] Among them, the target density requirement can be a fixed value (i.e., the target density value) or a fixed range (generally 95%~105% of the target density value), which is determined based on actual conditions.

[0058] S502 , selectively filling the rectangular area of the current metal layer in descending order of filling priority values and in combination with the area of the rectangular area, until the layout meets the target density requirement.

[0059] Generally, the current rectangular area is determined in descending order of filling priority value, and the area of the current rectangular area is compared with the remaining fillable area to selectively fill: 1. If a fixed value is used as the target density requirement, fill the current rectangular area if the area is less than or equal to the remaining fillable area. Otherwise, do not fill the current rectangular area and update the next rectangular area to the current rectangular area for the next round of comparison.

[0060] 2. If a fixed interval is used as the target density requirement, the area of the current rectangular area is filled only when the area is less than or equal to the upper limit of the remaining fillable area (which is actually also the interval). Otherwise, the area is not filled and the next rectangular area is updated to the current rectangular area for the next round of comparison.

[0061] In this way, flexible filling is achieved while ensuring filling accuracy.

[0062] Of course, after the filling is completed, the layout processed as above can be re-output in the form of a digital file to facilitate other subsequent work (such as layout processing, etc.).

[0063] Example 2 In order to more intuitively illustrate the effect of the method of Example 1 (abbreviated as SONIC method), this Example 2 simulates and verifies Example 1, and introduces two other existing filling and insertion methods (including: rule-based method and model-based method) for comparison.

[0064] In Example 2, three layouts (including Case-A, Case-B, and Case-C) were selected as experimental subjects. Case-A is an application-specific integrated circuit (ASIC) for accelerating cryptographic computations, with a die size of 1400μm × 1400μm and a GDS file size of 111MB. Case-B is a system-on-chip (SoC) based on the PicoRV32, with a die size of 2150μm × 900μm and a GDS file size of 206MB. Case-C is a linear insertion sort accelerator, with a die size of 3000μm × 3500μm and a GDS file size of 358MB.

[0065] The comparison results of the three methods are shown in Table 1.

[0066] Table 1 Simulation verification comparison results

[0067] As can be seen from Table 1, the method of Example 1 achieved the minimum capacitance value in the processing of the three experimental objects, which illustrates the superiority of this method.

[0068] Example 3 This embodiment 3 provides a key network-based timing-aware fill insertion system, which uses the key network-based timing-aware fill insertion method provided in embodiment 1.

[0069] The timing-aware fill insertion system based on key networks includes: a layout parsing module, a capacitor buffer area division module, a candidate fill area division module, a fill sequence determination module, and a virtual fill module.

[0070] The layout parsing module is configured to parse the target layout to obtain a layout.

[0071] The capacitor buffer region partitioning module is configured to extract a number of key signal lines from the layout and partition capacitor buffer regions around the key signal lines.

[0072] The candidate filling area division module is configured to divide the candidate filling area in the layout according to the positions of the original signal lines, key signal lines and capacitor buffer areas on the basis of complying with DRC rules.

[0073] The filling order determination module is configured to divide the candidate filling area into a plurality of rectangular areas and calculate the filling priority value of each rectangular area.

[0074] The virtual fill module is configured to preferentially fill rectangular areas with large fill priority values until the layout meets the target density requirement.

[0075] Since this system uses the key network-based timing-aware filling insertion method in Example 1, it also has the same effect and will not be repeated here.

[0076] Example 4 This embodiment 4 discloses a computer device including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the key network-based timing-aware fill insertion method disclosed in embodiment 1 are implemented.

[0077] Computer devices can be either mobile or fixed terminals. Examples of the former include mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals). Examples of the latter include digital TVs and desktop computers.

[0078] This embodiment 4 also discloses a readable storage medium, which stores computer program instructions. When the computer program instructions are read and executed by a processor, the steps of the key network-based timing-aware filling insertion method disclosed in embodiment 1 are executed.

[0079] Among them, the readable storage medium may include, but is not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0080] This embodiment 4 further discloses a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the key network-based timing-aware padding insertion method disclosed in embodiment 1 are implemented.

[0081] It should be noted that the computer program for executing the above-mentioned operations can be written in one or more programming languages or a combination thereof. Programming languages include object-oriented programming languages such as Java, Smalltalk, and C++, as well as conventional procedural programming languages such as "C" or similar programming languages. The above-mentioned computer program can be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN).

[0082] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A timing-aware padding insertion method based on a critical network, characterized in that; It includes: S1, parse the target layout to obtain the layout; The layout characterizes the structural spatial relationship of all metal layers in the target layout. Each metal layer includes: a number of original signal lines and a number of vias. Each original signal line has a corresponding signal line label. A single via only allows a single original signal line to pass through, and is used to connect two original signal lines with the same signal line label in adjacent metal layers. S2, extract several key signal lines that are susceptible to capacitance from the layout, and divide the capacitor buffer area around the key signal lines; S3, based on the DRC rules, divide the candidate filling area in the layout according to the position of the original signal line, the key signal line and the capacitor buffer area; S4, dividing the candidate filling area into a plurality of rectangular areas, and calculating a filling priority value of each rectangular area; wherein a rectangular area with a higher filling priority value has a smaller coupling capacitance generated therefrom; S5, preferentially filling rectangular areas with larger filling priority values until the layout meets the target density requirement.

2. The method for inserting padding based on timing awareness of key networks according to claim 1, characterized in that: S1 includes: Obtain the GDS format file of the target layout and process it using the layout viewing and editing tool to obtain the layout.

3. The method for inserting padding based on timing awareness of key networks according to claim 1, characterized in that: The extraction methods of key signal lines in S2 include: According to the signal line attributes reflected by the signal line labels, several key labels that are easily affected by capacitance are determined; For any key tag, search for the corresponding original signal line on any metal layer. If it exists, start with the original signal line and select and cover other original signal lines connected to it along the line extension direction until the two line ends are reached. The entire line between the two line ends is then regarded as the key signal line. Traverse all key tags and all metal layers until all key information lines are found.

4. The method for inserting padding based on timing awareness of a critical network according to claim 1, characterized in that: In S2, the capacitor buffer area division method includes: Traverse all metal layers; for the key signal line in any metal layer, leave a width of D The area is used as a capacitor buffer area; D Indicates the shielding distance; if the distance between the two original signal lines exceeds D , no capacitance will be generated.

5. The method for inserting padding based on timing awareness of key networks according to claim 1, characterized in that: In S3, the candidate filling area division method includes: Traverse all metal layers; for any metal layer, exclude the area occupied by all original signal lines of the metal layer, the reserved area reserved for all original signal lines of the metal layer to comply with DRC rules, and the capacitor buffer area of all key signal lines of the metal layer to obtain the remaining blank area, and use it as a candidate filling area.

6. The method for inserting padding based on timing awareness of key networks according to claim 1, characterized in that: In S4, the fewer the number of rectangular regions, the better.

7. The method for inserting padding based on timing awareness of key networks according to claim 1, characterized in that: In S4, the calculation formula for filling priority value is: Priority=λ1×w+λ2×A-λ3×O; Where Priority represents the fill priority value; λ1, λ2, and λ3 are all hyperparameters; w represents the width of a single rectangular region; A represents the area of a single rectangular region; and O represents the sum of the overlapping areas of a single rectangular region and the original signal lines existing in the upper and lower adjacent metal layers when projected perpendicular to the metal layer.

8. The method for inserting padding based on timing awareness of a key network according to claim 1, wherein S5 include: Calculate the required filling area of the current metal layer based on the target density requirement and the current layout density; Selectively fill the rectangular area of the current metal layer in descending order of fill priority values and in combination with the area of the rectangular area until the layout meets the target density requirements.

9. A timing-aware fill insertion system based on a critical network, characterized in that It uses the key network-based timing-aware fill insertion method according to any one of claims 1 to 8; The key network-based timing-aware fill insertion system includes: A layout parsing module is used to parse the target layout to obtain the layout; A capacitor buffer area division module is used to extract several key signal lines from the layout and divide the capacitor buffer area around the key signal lines; The candidate filling area division module is used to divide the candidate filling area in the layout according to the positions of the original signal lines, key signal lines and capacitor buffer areas on the basis of complying with DRC rules; a filling order determination module, which is used to divide the candidate filling area into a plurality of rectangular areas and calculate the filling priority value of each rectangular area; and The virtual filling module is used to preferentially fill rectangular areas with large filling priority values until the layout meets the target density requirements.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the critical network-based timing-aware fill insertion method are implemented as described in any one of claims 1 to 8.

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