Method for establishing dynamic grid stress aging test prediction model of power device

Abstract

A power device dynamic grid stress aging test prediction model establishment method comprises the steps of experimental scheme design and data acquisition, neural network architecture design, neural network training and optimization, and training result generation. The influence of various factors such as temperature, square wave frequency, square wave positive level and stress time on the gate oxide aging of the power device is comprehensively considered, errors caused by simplification and hypothesis of a traditional method are overcome, key aging indexes such as threshold voltage positive drift are accurately predicted, the prediction accuracy and reliability are improved, and the method is suitable for large-scale popularization and application. Powerful technical support is provided for reliable application of the power device in a power electronic system, the fault risk caused by aging of the device is effectively reduced, stable operation and long-term service life of the system are guaranteed, and the market competitiveness and economic benefits of related products are improved.

Description

Technical Field

[0001] The present invention relates to a prediction method, in particular to a method for establishing a dynamic gate stress test prediction model for a power device based on a neural network, and in particular to a method for establishing a dynamic gate stress aging test prediction model for a SiC MOSFET, and belongs to the field of electronic component design. Background Art

[0002] As power electronics technology advances toward high efficiency and high power density, SiC MOSFETs, with their excellent material properties, show broad application prospects in numerous fields. However, the gate oxide reliability of SiC MOSFETs has become a key factor restricting their long-term stable operation. Under actual operating conditions, SiC MOSFETs are subject to dynamic gate stress, which gradually degrades the gate oxide over time, affecting the device's electrical parameters and overall performance. This can ultimately lead to device failure, impacting the reliability and stability of the entire power electronics system.

[0003] Currently, research on dynamic gate stress aging of SiC MOSFETs primarily relies on traditional experimental methods and analytical approaches based on physical models. While traditional dynamic gate stress bias aging experiments can directly obtain device aging data under stress, these experiments require precise control of multiple complex stress conditions, such as temperature, square wave frequency, square wave positive level, and stress duration. High-precision test equipment is also required to monitor changes in the device's electrical parameters, making the experimental process extremely complex and costly. Not only does the purchase and maintenance of experimental equipment and the establishment of the experimental environment require significant investment, but obtaining statistically reliable data also requires extensive testing of numerous device samples, further increasing labor, material, and time costs.

[0004] In addition, the existing methods for dynamic gate stress aging of SiC MOSFETs have the following defects:

[0005] High Experimental Costs: Research on SiC MOSFET dynamic gate stress aging currently relies primarily on extensive real-world aging experiments. These experiments require high-precision and expensive experimental equipment, such as temperature-controlled chambers capable of precise temperature control, high-resolution signal generators, and sophisticated power analyzers. Furthermore, to obtain statistically reliable data, a large number of SiC MOSFET device samples must be tested over a long period of time. This not only significantly increases device costs but also consumes significant human and material resources, driving up research costs.

[0006] Time-consuming: Due to the need for extensive sample testing and complex experimental condition adjustments, the entire research process, from experimental design and data collection to results analysis, is time-consuming. For companies and institutions that need to quickly understand SiC MOSFET aging characteristics for product development and application, this significantly prolongs product development cycles and time to market, reducing market competitiveness. Summary of the Invention

[0007] In order to solve the defects in the prior art, the present invention discloses a method for establishing a prediction model for a dynamic gate stress test of a power device based on a neural network. The technical solution is as follows:

[0008] A method for establishing a prediction model for a SiC MOSFET dynamic gate stress aging test is characterized by comprising the following steps:

[0009] Step 1: Experimental design and data collection: including the establishment of experimental samples, dynamic square wave parameter setting, temperature control, stress time monitoring, and data screening and organization process;

[0010] Step 2: Neural network architecture design: including the input layer: designed with 4 nodes corresponding to the four key input variables in the experiment: temperature, dynamic square wave frequency, square wave positive level, and stress time; hidden layer: including convolution layer, which can automatically extract local features and spatial correlations in the data. The size, number, and step size parameters of the convolution kernel will be optimized according to the characteristics of the experimental data and the results of multiple tests. After the convolution layer, an appropriate number of fully connected layers are added to further integrate and nonlinearly transform the features output by the convolution layer. By adjusting the number of neurons and activation function of the fully connected layer, the network can learn more complex mapping relationships between input and output; the output layer has 1 neuron, and its activation function is selected as the ReLu function according to the actual situation, so as to directly output continuous threshold voltage positive drift prediction values, so that the model can accurately predict the aging degree of SiC MOSFET under different stress conditions.

[0011] Step 3: Neural network training and optimization; including data partitioning: the collected multiple sets of valid data are divided into training set, validation set and test set in a ratio of 6:2:2, 60% of the data is used as the training set for model training, 20% of the data is used as the validation set to adjust the model's hyperparameters and prevent overfitting, and the remaining data is used as the test set to evaluate the model's final performance and generalization ability; training algorithm selection: a gradient descent-based optimization algorithm is used to minimize the loss function between the predicted value and the actual threshold voltage positive drift value; during the training process, the gradient of the loss function with respect to the weights and biases of each layer in the network is calculated through the backpropagation algorithm, and these parameters are updated according to the selected optimization algorithm, so that the network gradually learns the accurate mapping relationship between input variables and outputs; hyperparameter adjustment: during the training process, some hyperparameters of the neural network need to be optimized and adjusted; by using the validation set for multiple experiments and cross-validation, the optimal hyperparameter combination is found, and a traversal search is performed within a certain parameter range to find the hyperparameter setting that minimizes the loss function on the validation set.

[0012] Step 4: Generation of training results.

[0013] The present invention also discloses a device for establishing a SiCMOSFET dynamic gate stress aging test prediction model.

[0014] The present invention also discloses an electronic device, characterized in that it includes a processor, a memory and a communication interface, the memory stores a prediction model program generated by the above method, and the processor executes the program to predict SiC MOSFET aging indicators.

[0015] The present invention also discloses a SiC MOSFET device, characterized in that its dynamic gate stress aging characteristics are predicted by the above method, and the device operating parameters are optimized according to the prediction results.

[0016] Beneficial effects

[0017] Using a neural network to predict the positive drift of the SiC MOSFET's threshold voltage under dynamic gate stress can largely avoid reliance on a large number of expensive and complex aging experiments. Its powerful nonlinear mapping capabilities and adaptive generalization capabilities for various operating conditions allow researchers to establish highly accurate degradation prediction models using only experimental data. This not only reduces the investment in high-cost experimental equipment, but also reduces the need for massive device samples and long-cycle testing, thereby significantly shortening the time and resource investment required for the entire research process, providing a more efficient and economical technical means for rapid product development and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the SiC MOSFET experimental sample of the present invention;

[0019] Figure 2 This is a diagram of the experimental equipment of the present invention;

[0020] Figure 3 This is a diagram of the neural network structure of the present invention;

[0021] Figure 4 This figure shows the threshold voltage positive drift prediction results of our invention: This figure shows the neural network prediction results arranged in ascending order. As can be seen from the figure, the predicted values of the 180 test data sets are highly consistent with the experimental values, verifying that our designed neural network model can accurately predict the degradation mechanism of SiC MOSFETs under dynamic gate stress.

[0022] Figure 5 This is a schematic diagram of the threshold voltage prediction probability of the present invention; this figure is the training prediction result of the model, and the prediction probability is the ratio of the predicted value to the experimental value. It can be seen from the figure that the accuracy of the prediction data of the 180 groups of test sets is above 97%, further proving the accuracy of the prediction model.

[0023] Figure 6 This is a schematic diagram of the actual error predicted by the present invention; the figure shows the actual error of the threshold voltage positive drift case arranged from small to large. It can be seen from the figure that the error between the predicted value and the actual value is between 0.02-0.11, which proves the powerful prediction ability and good prediction accuracy of the neural network model;

[0024] Figure 7 This is the MSE error plot of the present invention: The MSE distribution plot helps evaluate the model's prediction accuracy. Most errors are small, indicating that the neural network model effectively captures the degradation patterns of SiC MOSFETs and the prediction results are highly reliable. If the errors are large, further model optimization or data cleaning is necessary. DETAILED DESCRIPTION

[0025] See attached Figure 1-7 A method for establishing a prediction model for a dynamic gate stress aging test of a power device is characterized by comprising the following steps:

[0026] Step 1: Experimental design and data collection: including the establishment of experimental samples, dynamic square wave parameter setting, temperature control, stress time monitoring, and data screening and organization process;

[0027] Experimental samples: 150 SiC planar MOSFET devices were selected as experimental objects to ensure that they had similar initial electrical characteristics and parameters to reduce the impact of individual device differences on the experimental results.

[0028] Dynamic square wave parameter settings:

[0029] (1) Frequency: The dynamic square wave frequencies applied to the device were set to 100 kHz, 200 kHz, 300 kHz, 400 kHz, and 500 kHz, respectively. A high-precision signal generator was used to generate stable and accurate square wave signals to study the effects of stress at different frequencies on device aging.

[0030] In dynamic gate stress bias experiments, varying the square wave frequency significantly affects the threshold voltage. Square wave frequency refers to the frequency at which the gate voltage varies, affecting the number of times the device experiences stress within a specific cycle. Generally speaking, a higher frequency means the SiC MOSFET experiences more gate stress per unit time, accelerating the device aging process. As the square wave frequency increases, the device's threshold voltage typically degrades more rapidly, manifesting as a decrease in threshold voltage. This phenomenon is related to the device's charge trapping and discharge effects. At higher frequencies, the device undergoes more switching cycles per cycle, causing changes in trap states in the gate oxide layer, which in turn affects the threshold voltage.

[0031] Conversely, a lower square wave frequency results in fewer gate stress applications, a relatively slow degradation rate, and a slower threshold voltage change. Therefore, the choice of frequency is crucial for studying the positive drift characteristics of the threshold voltage under dynamic gate stress. Higher frequencies increase the device aging rate and more pronounced positive threshold voltage drift.

[0032] (2) Positive level: The positive level of the square wave is set to 25V, 27V, 29V, 31V, 33V and 35V respectively. A precision voltage regulating device is used to accurately control the level amplitude of the square wave to simulate electric field stress of different intensities acting on the device gate.

[0033] The magnitude of the square wave's positive voltage level directly affects the gate voltage amplitude. Changes in the gate voltage amplitude exert varying degrees of stress on the SiC MOSFET's gate oxide. Increasing the square wave's positive voltage level increases the gate voltage amplitude, subjecting the gate oxide to higher electric field strengths. This higher electric field strength causes more charge to accumulate in gate oxide traps, leading to an increase in oxide defects. As the device ages, these defects cause a significant decrease in the threshold voltage. A relatively small positive voltage level reduces the gate electric field strength, thereby slowing the aging process of the gate oxide and slowing the rate of positive threshold voltage drift. A smaller electric field strength reduces charge accumulation and the generation of oxide defects, resulting in a slower change in threshold voltage.

[0034] Temperature Control: During the experiment, high-precision temperature control equipment was used to precisely control the ambient temperature at 100°C, 125°C, 150°C, 175°C, and 200°C. This allowed us to investigate the effect of temperature on the dynamic gate stress aging process of SiC MOSFETs, as temperature is one of the key factors affecting the performance and reliability of semiconductor devices.

[0035] Increased temperature enhances the thermal excitation of carriers, making traps in the gate oxide more active. This also promotes the injection of electrons or holes into the oxide layer and interface traps, leading to increased charge capture. Furthermore, high temperatures exacerbate the generation of interface states and accelerate oxide degradation, leading to a significant drop in threshold voltage. Therefore, at higher temperatures, SiC MOSFETs degrade faster, and the threshold voltage decay is more pronounced.

[0036] At low temperatures, the thermal excitation effect of carriers weakens, the activity of oxide traps decreases, and the rate of interface state generation is also low. These factors will reduce the degradation rate of the threshold voltage. Therefore, at lower temperatures, the aging process of SiC MOSFETs is slower and the threshold voltage changes less.

[0037] Stress Time Monitoring: For each device, high-resolution electrical testing equipment was used to accurately measure the threshold voltage and record degradation at time points (10, 12, 14, 16, 18, and 20 hours) after stress application. This long-term monitoring provides data on the device's aging evolution over time under different stress conditions. In dynamic gate stress bias experiments, time is a significant factor influencing the positive drift of the SiC MOSFET's threshold voltage. Over time, devices undergo a gradual aging process, which is closely related to changes in their electrical performance. As the stress duration increases, traps in the gate oxide layer gradually become trapped by charge. The increase in these traps leads to changes in the gate electric field, causing the threshold voltage to gradually decrease. Prolonged stress increases the opportunity for charge accumulation, accelerating device degradation and significantly reducing the threshold voltage.

[0038] The purpose of acquiring a time-related data set is to add the characteristic variable of aging time to the input of the neural network to predict the internal aging mechanism of SiC MOSFET. During the aging experiment, the electrical parameter scanning measurement was performed using a power analyzer commonly used for SiC MOSFET testing.

[0039] Data Screening and Collation: After completing numerous experimental tests, the collected raw data was carefully examined and analyzed, eliminating any failed experiments due to equipment failure, operational errors, or device defects. Through rigorous data screening, 900 sets of valid data were successfully collected, which will serve as the foundation for subsequent neural network training and model building.

[0040] Each SiC MOSFET device undergoes a long-term stress test under specific dynamic gate stress bias conditions, with time intervals set at 10, 12, or 14 hours. A power analyzer, commonly used for power devices, is used as the test equipment during the experiment. During the experiment, some data may deviate from the normal range due to equipment failure, improper operation, or device defects. For example, abnormal fluctuations in test equipment readings or damage to devices that cannot withstand the stress during certain tests should be identified and eliminated. During the data collection phase, statistical analysis methods (such as standard deviation analysis and outlier detection) are used to detect data that does not meet experimental expectations and remove unqualified data to ensure the validity and reliability of the analyzed data. After removing the anomalous data and undergoing careful inspection, the final 900 sets of valid data will include threshold voltage positive drift data for all qualified devices at each time interval. This data will serve as the foundation for subsequent neural network training and model building, providing solid support for the model's accuracy and generalization capabilities.

[0041] Step 2: Neural network architecture design: including the input layer: designed with 4 nodes corresponding to the four key input variables in the experiment: temperature, dynamic square wave frequency, square wave positive level, and stress time; hidden layer: including convolution layer, which can automatically extract local features and spatial correlations in the data. The size, number, and step size parameters of the convolution kernel will be optimized according to the characteristics of the experimental data and the results of multiple tests. After the convolution layer, an appropriate number of fully connected layers are added to further integrate and nonlinearly transform the features output by the convolution layer. By adjusting the number of neurons and activation function of the fully connected layer, the network can learn a more complex mapping relationship between input and output. The output layer has 1 neuron, representing the degradation of the threshold voltage. Its activation function selects a linear function according to the actual situation to directly output a continuous threshold voltage positive drift prediction value, so that the model can accurately predict the aging degree of SiC MOSFET under different stress conditions.

[0042] 1. Input layer design

[0043] The input layer is designed based on four key input variables collected during the experiment: temperature, dynamic square wave frequency, square wave positive level, and stress time. Each input variable is normalized to a value between 0 and 1 to prevent variables of varying magnitude from influencing model training. Before training the neural network, these input data must be preprocessed:

[0044]

[0045] Among them, min(x) and max(x) represent the minimum and maximum values of the data set respectively, and x * This is the result of normalization. This method eliminates dimensional differences in the data by shifting and scaling it so that all values fall within a uniform range, making it easier for machine learning models to process and analyze.

[0046] 2. Convolutional layer design

[0047] The main task of the convolutional layer is to extract local features and spatial correlations from the input data. Considering that there may be some implicit temporal and spatial patterns in the experimental data, the convolutional layer can effectively learn these features. The specific implementation is as follows:

[0048] Convolution Kernel Design: The size, number, and stride of the convolution kernels are key to convolutional layer design. Our experimental data is a one-dimensional vector (four input variables). This data can be organized into a four-dimensional matrix (time, frequency, level, and temperature), and multiple convolution kernels can be designed to capture different features. During each convolution operation, the kernel slides over the input data, extracting local features, such as the changing patterns of temperature and frequency, or the relationship between stress time and square wave level.

[0049] Choosing the number of convolution kernels and stride: The number of convolution kernels is typically adjusted based on the complexity of the experimental data. Each kernel extracts different features, so a larger number of kernels allows the network to learn a richer set of features. The stride determines the length of time the convolution operation moves across the input data. A too large stride results in loss of detail, while a too small stride results in excessive computational overhead. Based on multiple experiments and empirical results, a stride of 1 and a kernel size of 3 were chosen for this experiment.

[0050] Convolutional layer activation function: To improve the nonlinearity of the model, the ReLU activation function is often used after the convolutional layer. ReLU can effectively solve the vanishing gradient problem, accelerate training, and maintain the sparsity of the model.

[0051] 3. Fully connected layer design

[0052] The features extracted by the convolutional layer are passed to the fully connected layer for further processing. The function of the fully connected layer is to integrate the local features output by the convolutional layer and learn more complex relationships between input and output through nonlinear transformation.

[0053] 4. Output layer design

[0054] The output layer is responsible for predicting the threshold voltage based on the features output by the fully connected layer. Since the threshold voltage is a continuous value, the number of neurons in the output layer is set to 1.

[0055] Step 3: Neural network training and optimization; including data division: the collected multiple groups of valid data are divided into training set, validation set and test set according to a certain ratio, and a part of the data is used as the training set for model training, another part of the data is used as the validation set to adjust the model's hyperparameters and prevent overfitting, and the remaining part of the data is used as the test set to evaluate the model's final performance and generalization ability; training algorithm selection: a gradient descent-based optimization algorithm is used to minimize the loss function between the predicted value and the actual threshold voltage positive drift value; during the training process, the gradient of the loss function to the weights and biases of each layer in the network is calculated by the backpropagation algorithm, and these parameters are updated according to the selected optimization algorithm, so that the network gradually learns the accurate mapping relationship between input variables and outputs; hyperparameter adjustment: during the training process, some hyperparameters of the neural network need to be optimized and adjusted; by using the validation set for multiple experiments and cross-validation, the optimal hyperparameter combination is found, and a traversal search is performed within a certain parameter range to find the hyperparameter setting that minimizes the loss function on the validation set.

[0056] Loss function: The mean square error (MSE) is used as the loss function to measure the difference between the predicted value and the actual threshold voltage. By minimizing the loss function, the model parameters are optimized.

[0057]

[0058] where y i and are the true value and predicted value of the data respectively, and n is the number of samples.

[0059] 5. Model training and optimization

[0060] Training process: During model training, the backpropagation algorithm is used to adjust the weights and biases of each layer. The Adam optimizer is used to update model parameters, and prediction accuracy is gradually improved through iterative optimization.

[0061] Verification and adjustment: Use cross-validation techniques to select the best hyperparameters (such as the number of convolution kernels, the number of neurons in the fully connected layer, and the learning rate) to avoid overfitting or underfitting of the model.

[0062] Step 4: Generation of training results.

[0063] The present invention leverages the advantage of neural networks in being able to handle complex relationships among multiple variables, comprehensively and comprehensively considering the effects of multiple factors such as temperature, square wave frequency, square wave positive level, and stress time on SiC MOSFET gate oxide aging. This overcomes the errors caused by simplification and assumptions in traditional methods, accurately predicts key aging indicators such as the threshold voltage positive drift, improves the accuracy and reliability of the prediction, and provides strong technical support for the reliable application of SiC MOSFETs in power electronic systems. This effectively reduces the risk of failure caused by device aging, ensures the stable operation and long-term life of the system, and enhances the market competitiveness and economic benefits of related products. The present invention utilizes the powerful self-learning and nonlinear mapping capabilities of neural networks, and through learning and training on limited, carefully designed experimental data, constructs a prediction model that can accurately reflect the dynamic gate stress aging characteristics of SiC MOSFETs. This significantly reduces the reliance on large-scale, high-cost experiments, reduces the investment in experimental equipment and device samples, improves research efficiency, significantly shortens the research cycle, and achieves rapid and low-cost acquisition of SiC MOSFET aging prediction results under different operating conditions.

[0064] The core of this invention lies in combining SiC MOSFET degradation testing with the predictive capabilities of a neural network algorithm, leveraging the neural network's powerful learning capabilities to predict device failure mechanisms. Once the model is trained, traditional experimental procedures can be skipped, significantly reducing experimental costs and device usage. Traditional degradation experiments often severely damage devices, rendering them unreusable. The application of a neural network model can effectively avoid this problem, significantly reducing the high costs associated with device damage and lengthy experiments. Innovations in the specific structure of the neural network include dimensional expansion of the input features and data convolution.

[0065] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions merely illustrate the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for establishing a prediction model for a dynamic gate stress aging test of a power device, characterized in that: The following steps are involved: Step 1: Experimental design and data collection: Establish experimental samples, set dynamic square wave parameters, control temperature, monitor stress time, and obtain valid data sets through data screening and organization; Step 2: Neural Network Architecture Design: The input layer includes four input variables: temperature, dynamic square wave frequency, square wave positive level, and stress time; The hidden layer includes a convolutional layer and a fully connected layer. The convolutional layer is used to extract local features and spatial correlation of the input variables, and the fully connected layer is used to integrate features and perform nonlinear mapping. The output layer is a single neuron structure that outputs the predicted value of the threshold voltage positive drift; Step 3: Neural network training and optimization: Divide the dataset into training, validation, and test sets, use the gradient descent optimization algorithm to minimize the prediction error, and adjust the hyperparameters using the validation set; Step 4: Generate a prediction model to accurately predict the threshold voltage positive drift of the power device under different dynamic stress conditions.

2. The method for establishing a dynamic gate stress aging test prediction model for power devices according to claim 1 is characterized in that: the frequency range of the dynamic square wave parameters is 100KHz to 500KHz, the positive level range is 25V to 35V, the temperature control range is 100℃ to 200℃, and the stress time range is 10 hours to 20 hours.

3. The method for establishing a prediction model for a dynamic gate stress aging test of a power device according to claim 1, wherein: The experimental samples were multiple SiC planar MOSFET devices with similar initial electrical characteristics. The screening criteria included an initial threshold voltage range of ±5% and consistency in leakage current test values.

4. The method for establishing a prediction model for a dynamic gate stress aging test of a power device according to claim 1, wherein the data normalization adopts a Min-Max normalization formula: in, x is the original value of the input variable, minxmin and maxxmax are the minimum and maximum values of the experimental data.

5. The method for establishing a dynamic gate stress aging test prediction model for power devices according to claim 1, wherein when the validation set is used to adjust hyperparameters, a grid search is used to traverse the number of convolution kernels including 32, 64, 128 and the number of neurons in the fully connected layer.

6. The method for establishing a prediction model for a dynamic gate stress aging test of a power device according to claim 1, wherein: The model evaluation indicators include root mean square error RMSE < 0.1 and determination coefficient R 2 >0.

95.

7. A power device dynamic gate stress aging test prediction device based on neural network, characterized in that: include: Data acquisition module: used to obtain temperature, dynamic square wave frequency, square wave positive level, and stress time data; Preprocessing module: normalizes the input data; neural network module: a prediction model constructed based on any method of claims 1-6; output module: generates a threshold voltage positive drift prediction value and an error analysis report.

8. An electronic device, characterized in that: The method comprises a processor, a memory and a communication interface, wherein the memory stores a prediction model program generated by any one of the methods of claims 1 to 6, and the processor executes the program to predict SiC MOSFET aging indicators.

9. A SiC MOSFET device, characterized in that: Its dynamic gate stress aging characteristics are predicted by any method of claims 1-6, and the device operating parameters are optimized according to the prediction results.

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