Real-time generation method, system and device for superconducting quantum bit measurement and control waveform

Abstract

The present invention discloses a method, system and device for real-time generation of superconducting quantum bit measurement and control waveforms, which relate to the field of quantum computing technology. The method comprises the following steps: a waveform envelope signal with varying amplitude is read from an envelope storage based on an envelope parameter; a synchronous controller triggers a state register of a finite state machine to be held or idle according to a hold instruction, and outputs a waveform envelope signal with constant amplitude or restores the idle state; a frequency control word and a phase control word cached by the synchronous controller are loaded into a digital carrier generator; a digital phase signal is synthesized by a phase generation module; and a coefficient obtained by looking up a table of the digital phase signal is used to perform spline interpolation calculation on a cosine function to generate an orthogonal carrier signal; all waveform envelope signals and the carrier signal are fed back to a modulator for addition and multiplication operations to generate a final measurement and control waveform; and the method for real-time generation of measurement and control waveforms can quickly and accurately respond to dynamic adjustment of multiple parameters of the measurement and control waveform by a quantum computing circuit.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, and in particular to a method, system, and device for real-time generation of superconducting quantum bit measurement and control waveforms. Background Art

[0002] In superconducting quantum computing systems, the execution of quantum algorithms relies on the support of high-precision, high-stability measurement and control waveform generation circuits. Existing technology calculates all waveform sampling data in a host computer, transmits it via a communication interface, and writes it to the memory of an arbitrary waveform generator. The arbitrary waveform generator then directly reads the waveform sampling data during qubit measurement and control experiments.

[0003] In this method, on the one hand, the storage space required by the arbitrary waveform generator increases linearly with the execution time of the quantum circuit. If the quantum circuit to be executed is long, the storage resources of the memory will limit the waveform generation capability, resulting in the waveform generator being unable to be applied to certain experiments. On the other hand, since the waveform calculation process is executed in the host computer, once the quantum circuit encounters a situation where the feedback parameters need to be adjusted according to the system state, the host computer can only be required to recalculate and retransmit and write to the memory inside the waveform generator. This feedback delay is very long, equivalent to interrupting the circuit, and the life of the quantum bit is very short, so this traditional method is not suitable for situations where the measurement and control signal needs to be dynamically adjusted. Summary of the Invention

[0004] Based on the technical problems existing in the background technology, the present invention proposes a real-time generation method, system and equipment for superconducting quantum bit measurement and control waveforms, which can quickly and accurately respond to the dynamic adjustment of multiple parameters of the measurement and control waveform by the quantum computing circuit.

[0005] The method for real-time generation of superconducting quantum bit measurement and control waveforms proposed in the present invention includes:

[0006] Based on the envelope parameter, the waveform envelope signal with amplitude variation is read from the envelope storage. The synchronous controller triggers the state register of the finite state machine to hold or idle according to the hold instruction, outputs the waveform envelope signal with constant amplitude or restores the idle state, and caches all the waveform envelope signals according to the envelope data and the correction data.

[0007] The frequency control word and phase control word cached by the synchronization controller are loaded into the digital carrier generator. The digital phase signal is synthesized by the phase generation module and the coefficients obtained by looking up the digital phase signal table are used to perform spline interpolation calculation on the cosine function to generate an orthogonal carrier signal.

[0008] All waveform envelope signals and the orthogonal carrier signal are loaded into the modulator for addition and multiplication operations to generate the final measurement and control waveform.

[0009] Furthermore, the envelope parameters include an envelope initial address and an envelope length. In the step of reading the waveform envelope signal with amplitude variation from the envelope storage based on the envelope parameters, specifically:

[0010] The finite state machine starts the counter according to the synchronous trigger signal from the external source, and the counter increments by 1 bit in each clock cycle;

[0011] Convert the counter value in each clock cycle into an offset address and add it to the initial envelope address to obtain the address of the waveform envelope signal to be read at the current moment;

[0012] When the counter value is equal to the envelope length, the counter stops incrementing and the waveform envelope signal reading ends.

[0013] Furthermore, all waveform envelope signals are cached according to the envelope data and the correction data, specifically:

[0014] The waveform envelope signal read out in each clock cycle is returned to the synchronization buffer submodule of the synchronization controller, and the waveform envelope signal is disassembled into envelope data and correction data and cached;

[0015] An external synchronization trigger signal is connected to the synchronization buffer submodule, and the synchronization buffer submodule delays reading data in a registered manner, thereby synchronizing with other parameters or internal signals.

[0016] Furthermore, the frequency control word and phase control word cached by the synchronization controller are loaded into the digital carrier generator. The digital phase signal is synthesized by the phase generation module and the coefficients obtained by looking up the digital phase signal table are used to perform spline interpolation calculation on the cosine function to generate an orthogonal carrier signal. Specifically,

[0017] The frequency control word and phase control word cached by the synchronous controller are used as inputs of the phase generation module, and a periodic digital phase signal is obtained through accumulation processing by the accumulator.

[0018] The periodic digital phase signal is divided into two paths, wherein a coefficient one is obtained through a coefficient lookup table, and a cosine function is spline interpolated using the coefficient one and the digital phase signal to obtain a cosine oscillation carrier;

[0019] Taking the remainder of the other path, obtaining coefficient 2 through a coefficient lookup table, and performing spline interpolation on the cosine function using coefficient 2 and the remainder of the digital phase signal to obtain a sinusoidal oscillation carrier;

[0020] The sine oscillation carrier and the cosine oscillation carrier are used as a pair of orthogonal carrier signals.

[0021] Furthermore, the frequency control word and phase control word cached by the synchronization controller are used as inputs of the phase generation module, and the periodic digital phase signal is obtained through accumulation processing by the accumulator, specifically:

[0022] The frequency control word is connected to the input of the accumulator, and the output of the accumulator is also connected to the input of the accumulator after a delay of one clock cycle, thereby realizing digital accumulation;

[0023] When the accumulated value of the accumulator exceeds the maximum value of the accumulator, the accumulator subtracts a full amplitude value due to overflow, and the accumulation process starts to cycle;

[0024] The phase control word is summed with the output value of the accumulator through a digital adder as the initial bias of the phase signal, and finally a periodic digital phase signal is output.

[0025] Furthermore, the process of the spline interpolation method is as follows:

[0026] (b1) Use the coefficient lookup table to get The three coefficients of the cosine function corresponding to the spline interpolation in the interval ;

[0027] (b2) The coefficient With the digital phase signal After multiplication, the coefficient Do the addition, and the addition output value is again combined with the digital phase signal Perform multiplication, multiply the multiplier output value and the coefficient Do the addition to get the value of the cosine function approximated by the binomial;

[0028] (b3) Digital phase signal input in each clock cycle Steps (b1) to (b2) are performed, thereby obtaining an oscillating carrier wave having a period equal to that of the digital phase signal.

[0029] Further,

[0030] The waveform envelope signals and the orthogonal carrier signal are fed back to the modulator for multiplication to generate the final measurement and control waveform, specifically:

[0031] A pair of orthogonal carrier signals are summed up through a first adder as a first intermediate variable;

[0032] The envelope data and the correction data are added together by a second adder to form a second intermediate variable;

[0033] The correction data is negated and added to the envelope data through a third adder to form a third intermediate variable;

[0034] The first intermediate variable is multiplied by the envelope data through a first multiplier, the second intermediate variable is multiplied by the sine oscillation carrier in a pair of orthogonal carrier signals through a second multiplier, and the third intermediate variable is multiplied by the cosine oscillation carrier in the orthogonal carrier signal through a third multiplier;

[0035] The output of the second multiplier is negated and added to the output of the first multiplier through a fourth adder. The output of the fourth adder is multiplied by the amplitude value through a fourth multiplier. The output of the fourth multiplier is then added to the offset value through a fifth adder to obtain envelope modulated data.

[0036] The output of the third multiplier is negated and added to the output of the first multiplier through a sixth adder. The output of the sixth adder is multiplied by the amplitude value through a fifth multiplier. The output of the fifth multiplier is then added to the offset value through a seventh adder to obtain corrected modulated data.

[0037] The envelope modulated data and the rectified modulated data are used as the generated final measurement and control waveform.

[0038] A real-time generation system for superconducting quantum bit measurement and control waveforms, including a synchronization controller, an envelope generation module, a digital carrier generator, and a modulator;

[0039] The envelope generation module reads a waveform envelope signal with varying amplitude from an envelope storage based on an envelope parameter, and the synchronization controller triggers a state register of a finite state machine to be held or idle according to a hold instruction, outputs a waveform envelope signal with constant amplitude or restores the idle state, and caches all waveform envelope signals according to envelope data and correction data;

[0040] The digital carrier generator loads the frequency control word and phase control word cached by the synchronization controller into the digital carrier generator, synthesizes the digital phase signal through the phase generation module, and uses the coefficients obtained by looking up the digital phase signal in the table to perform spline interpolation calculation on the cosine function to generate an orthogonal carrier signal;

[0041] The modulator loads all waveform envelope signals and the orthogonal carrier signal into the modulator for addition and multiplication operations to generate a final measurement and control waveform.

[0042] Furthermore, the digital carrier generator includes a phase generation module and an amplitude generation module;

[0043] The phase generation module takes the frequency control word and phase control word cached by the envelope generation module as input, and obtains a periodic digital phase signal through accumulation processing by the accumulator;

[0044] The amplitude generation module divides the periodic digital phase signal into two paths, one of which obtains coefficient one through a coefficient lookup table, and uses coefficient one and the digital phase signal to perform spline interpolation on the cosine function to obtain a cosine oscillation carrier; the other path is obtained after taking the remainder through a coefficient lookup table to obtain coefficient two, and uses coefficient two and the remainder of the digital phase signal to perform spline interpolation on the cosine function to obtain a sine oscillation carrier, and the sine oscillation carrier and the cosine oscillation carrier are input into the modulator as a pair of orthogonal carrier signals.

[0045] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned method when executing the computer program.

[0046] The advantages of the real-time generation method, system and equipment for superconducting quantum bit measurement and control waveforms provided by the present invention are: pre-stored envelope reading and a high-precision digital carrier generator are used to synthesize orthogonal carrier signals and realize modulation, which is completely based on digital circuits, realizing high-precision generation of quantum bit measurement and control waveforms; at the same time, the waveform envelope signal and the orthogonal carrier signal are independently generated and modulated in real time, ensuring low-latency waveform output, and using parameter control to realize real-time waveform synthesis, avoiding the direct transmission and storage of large amounts of waveform data; using hold instructions to support segmented generation of special waveforms, only pre-stored dynamic edge information of the envelope, reducing storage waste of continuously repeated data. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the process of the present invention;

[0048] Figure 2 Generate system schematics for real-time measurement and control waveforms;

[0049] Figure 3 This is a schematic diagram of the structure of the envelope generation module;

[0050] Figure 4 This is a signal timing diagram for outputting a long flat-top waveform using the HOLD state;

[0051] Figure 5 It is a structural diagram of a digital carrier generator;

[0052] Figure 6 Schematic diagram of the modulator structure. DETAILED DESCRIPTION

[0053] The technical solutions of the present invention are described in detail below through specific embodiments. Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0054] like Figures 1 to 6 As shown, the real-time generation method of superconducting quantum bit measurement and control waveform proposed by the present invention includes:

[0055] Step 1: Reading a waveform envelope signal with amplitude variation from an envelope storage based on an envelope parameter; triggering the state register of the finite state machine to hold or idle according to a hold instruction; outputting a waveform envelope signal with constant amplitude or restoring the idle state; and caching all waveform envelope signals according to envelope data and correction data;

[0056] Step 2: Load the frequency control word and phase control word cached by the synchronization controller into the digital carrier generator, synthesize the digital phase signal through the phase generation module, and use the coefficients obtained by looking up the digital phase signal table to perform spline interpolation calculation on the cosine function to generate an orthogonal carrier signal;

[0057] Step 3: Load all waveform envelope signals and the orthogonal carrier signal into the modulator for addition and multiplication operations to generate the final measurement and control waveform.

[0058] This embodiment is designed specifically for measurement and control systems for superconducting quantum computing. It aims to combine multiple technologies for real-time generation and modulation of digital signals, efficiently utilize waveform parameter information, and achieve highly flexible, real-time, and synchronized measurement and control waveform generation and modulation, thus providing support for the execution of large-scale complex quantum algorithms.

[0059] This embodiment adopts a pre-stored envelope reading and real-time carrier generation scheme based on high-precision on-chip numerical calculation to achieve high-precision generation of quantum bit measurement and control waveforms. The waveform envelope signal and orthogonal carrier signal are independently generated and modulated in real time to ensure low-latency waveform output. Parameter control (input signals such as envelope initial address, envelope length, amplitude value, offset value, frequency control word, phase control word, and waveform hold indication) is used to achieve real-time waveform synthesis, avoiding the direct transmission and storage of large amounts of waveform data; hold instructions are used to support the segmented generation of special waveforms, and only the dynamic edge information of the envelope is pre-stored to reduce the storage waste of continuously repeated data.

[0060] That is, based on traditional waveform generation technology, this embodiment introduces a real-time waveform generation scheme with multi-independent parameter control, designs an envelope generation module using real-time address self-generation technology, carrier generation of a digital carrier generator, and a resource-optimized digital waveform modulator, and designs a self-control module to be set in the synchronization controller to schedule the workflow of each waveform generation and modulator, support the real-time generation of multi-degree-of-freedom measurement and control waveforms, and can quickly and accurately respond to the dynamic adjustment of multiple parameters such as the measurement and control waveform shape, amplitude, frequency, phase, and bias by the quantum computing circuit, thereby meeting the high performance requirements of the superconducting quantum computing measurement and control system.

[0061] The measurement and control waveform is the microwave control pulse for the superconducting qubit. Its parameters, such as phase and time integral, determine the direction and degree of evolution of the qubit state. To achieve higher logic gate fidelity, the shape of certain measurement and control waveforms can be corrected based on the derivative of the main control pulse waveform, achieving control operations as close to adiabatic as possible. This embodiment fully decomposes and extracts the key characteristics of the measurement and control waveform using multiple independent parameters. Combined with digital carrier synthesis technology based on on-chip numerical computation, it achieves high-precision generation and modulation of each waveform component. Waveform signal generation is implemented within the digital circuit. After the quantum circuit begins execution, if the input waveform parameters are modified by feedback signals within the measurement and control system, this embodiment can respond to the parameter adjustments in real time without requiring external communication with the host computer. This makes it highly suitable for applications requiring real-time control of qubit states, such as quantum computing circuits based on error correction algorithms, and comprehensively meets the measurement and control waveform accuracy, flexibility, and synchronization requirements of superconducting quantum computing systems.

[0062] In this embodiment, the above-mentioned measurement and control waveform real-time generation method can be implemented by a measurement and control waveform real-time generation system, such as Figure 2 As shown, the real-time measurement and control waveform generation system includes a synchronization controller, an envelope generation module, a digital carrier generator and a modulator;

[0063] The envelope generation module reads a waveform envelope signal with varying amplitude from an envelope storage based on an envelope parameter, and the synchronization controller triggers a state register of a finite state machine to be held or idle according to a hold instruction, outputs a waveform envelope signal with constant amplitude or restores the idle state, and caches all waveform envelope signals according to envelope data and correction data;

[0064] The digital carrier generator loads the frequency control word and phase control word cached by the synchronization controller into the digital carrier generator, synthesizes the digital phase signal through the phase generation module, and uses the coefficients obtained by looking up the digital phase signal in the table to perform spline interpolation calculation on the cosine function to generate an orthogonal carrier signal;

[0065] The modulator loads all waveform envelope signals and the orthogonal carrier signal into the modulator for addition and multiplication operations to generate a final measurement and control waveform.

[0066] Among them, the synchronous controller is used to cache envelope data, correction data, bias value, amplitude value, frequency control word and phase control word, where the envelope data and correction data are the envelope shape of the waveform, and the bias value, amplitude value, frequency control word and phase control word are the modulation parameters of the measurement and control waveform.

[0067] In one embodiment, Figure 3 As shown, the envelope generation module includes a finite state machine, an address self-generation mechanism, an envelope memory, and a synchronous cache mechanism;

[0068] Specifically, the generation of the waveform envelope signal utilizes an address self-generation mechanism, combining two timing control architectures: a finite state machine and a counter. The finite state machine starts the counter based on an external synchronous trigger signal to read the waveform envelope signal with varying amplitude. The counter serves as a timing function, and its value can be converted into an offset address. Combined with the input envelope initial address and envelope length, it generates the storage address of the envelope data in real time, which is used to read data from the envelope memory in real time and decompose it into envelope data and correction data. When the number of waveform envelope signals read reaches the envelope length required by the input parameters, the counter automatically stops working, and the state machine determines the state of the envelope output port based on parameter information such as the hold indication, while waiting for the next synchronous trigger.

[0069] When reading a waveform envelope signal with varying amplitude, specifically: a finite state machine starts a counter based on an external synchronous trigger signal, and the counter increments by 1 bit in each clock cycle; the counter value in each clock cycle is converted into an offset address and then added to the initial address of the envelope to obtain the address of the waveform envelope signal to be read at the current moment; when the counter value is equal to the envelope length, the counter stops incrementing, and the waveform envelope signal reading ends.

[0070] A1. The relevant input envelope parameters are: synchronous trigger pulse, waveform hold instruction, envelope initial address and envelope total length. The specific workflow for reading and generating envelope data is as follows (a1) to (a4):

[0071] (a1) Finite State Machine Control: Three signals—a synchronous trigger pulse, a waveform hold instruction, and an internal counter count-end flag—are connected to the finite state machine's state register to control the machine's state transitions. When the state register value is IDLE or HOLD, receiving a synchronous trigger pulse changes the state register value to READ. When the state register value is READ, if the internal counter count-end flag is valid and the hold instruction is valid, the state register value changes to HOLD. If the internal counter count flag is valid and the hold instruction is invalid, the state register value changes to IDLE.

[0072] (a2) Generation of the waveform envelope signal read address: The state register value of the finite state machine serves as the waveform envelope signal read enable. When the state machine is in the READ state, the internal counter increments by 1 bit during each clock cycle. The counter value and the input envelope initial address are connected to a digital adder for addition. The result of the addition is the address of the waveform envelope signal to be read at the current moment. The counter value serves as a marker for the end of counting and envelope reading. When the counter value equals the envelope length, the counter stops incrementing. At the same time, the finite state machine state is activated by this signal to jump to a state other than READ, and the read enable is disabled.

[0073] (a3) Reading the waveform envelope signal: The data structure inside the envelope memory is 4 bytes per word, of which the upper 2 bytes and lower 2 bytes are the envelope data (ENVE) and the correction data (DRAG), respectively. The two are stored in a one-to-one correspondence based on the sampling time. The envelope memory is a dual-port random access memory (DPRAM). The types of envelope data used in quantum computing experiments are limited and can be loaded into the envelope memory through a set of ports before the experiment begins. During the experiment, the address generated by the above-mentioned counter and the envelope initial address is input to the other port of the memory and addressed. The envelope memory can return a data value of one word length at the corresponding address in one clock cycle. This data value is connected to the input of the controller's synchronous cache mechanism.

[0074] It can be understood that the envelope memory of this embodiment is a read-only memory within the module, and the total storage space is small. After the quantum circuit starts executing, only the envelope generation module will perform a read operation on it, so data reading can be achieved within one clock cycle.

[0075] In addition, in existing quantum measurement and control waveform generation methods, the hardware circuit does not have an envelope memory structure. Because envelope data is a configuration parameter for the measurement and control waveform, the existing method is to perform memory access and calculation on it in the host computer, and then transmit it to the memory of the waveform transmission circuit through the communication interface; when the host computer executes the software algorithm, the delay of operations such as accessing envelope data, calculating the waveform, transmitting waveform data, and writing to the memory of the waveform generation circuit is much greater than that of this embodiment. Therefore, this embodiment can realize waveform data generation in the experimental process, which cannot be achieved by the classical method.

[0076] (a4) Synchronous caching of waveform envelope signals: During the period when the above-mentioned read enable is valid, the readout data of each clock cycle is returned to the synchronous cache submodule of the synchronous controller and is disassembled into two 2-byte data (envelope data and correction data) for caching. The input synchronous trigger signal is connected to the synchronous cache submodule, which delays the readout data in the form of shift register to achieve precise synchronization with other parameters or internal signals; the cache delay time is determined by simulation and other methods. The synchronous cache only appropriately extends the time for each set of sampled data to arrive at the output port (the delay time is on the order of ns) without slowing down the data transmission rate, thereby supporting the precise synchronization of multi-qubit parallel operations and avoiding calculation errors caused by timing deviations;

[0077] Reading any waveform envelope signal using this method only requires externally providing the envelope initial address and length, along with a synchronization trigger pulse for timing synchronization. This reduces communication between different chip modules, thereby achieving lower latency and more flexible control. Furthermore, the synchronization controller of this embodiment includes a synchronization control mechanism that can receive external synchronization trigger signals to ensure timing consistency across multiple channels.

[0078] A2. When reading a waveform envelope signal with constant amplitude, specifically: using an external hold instruction to trigger the state register value of the finite state machine to hold, and outputting a waveform envelope signal with constant amplitude.

[0079] In this embodiment, the state register value of the finite state machine is input into the synchronous cache submodule as an indication signal. When the state register value is HOLD, the synchronous cache stops shifting and stores the last set of data values ​​input into the synchronous cache submodule and keeps them at the output end.

[0080] The conventional sequential reading or point-by-point calculation of waveform data controlled by a sequence controller is used as a comparative example of "using an external hold instruction to trigger the finite state machine to hold the state register value and output a waveform envelope signal with a constant amplitude" described in this embodiment, as follows:

[0081] Existing methods usually use a sequence controller to control the sequential reading or point-by-point calculation of waveform data. It is impossible to predict whether the waveform contains a shape with constant amplitude (such as a flat-top waveform). Therefore, the waveform data needs to be read or calculated normally during this stage with constant amplitude.

[0082] The real-time generation method of this embodiment uses "hold instruction" as a label of the waveform, and with multiple synchronous trigger pulses, it can realize the segmented generation of flat-top waveforms. For example, a flat-top waveform data of length T (such as Figure 4 ), among the envelope data ENVE[0:T-1], only the rising edge ENVE_rise[0:t-1]=ENVE [0:t-1] and the falling edge ENVE_fall[0:t-1]=ENVE[Tt:T-1], a total of 2t (t≪T) data, have amplitude changes. ENVE[t]= ENVE[t+1]=...=ENVE[Tt-1] is the envelope data of the waveform amplitude constant segment. When this embodiment generates the above waveform under the control of the on-chip control center, the envelope memory only stores two segments of envelope data (including their corresponding correction data) of the rising edge ENVE_rise and the falling edge ENVE_fall. This embodiment receives a synchronous trigger at the starting time of the rising edge (t0) and the starting time of the falling edge (t1). At t0, the waveform parameters input simultaneously with the synchronous pulse maintain the instruction signal at a high level (valid) and the initial address of the envelope is the initial address addr0 of ENVE_rise in the envelope; at t1, the waveform parameters input simultaneously with the synchronous pulse maintain the instruction signal at a low level (invalid) and the initial address of the envelope is the initial address addr1 of ENVE_fall in the envelope; the envelope length is t (edge ​​point number) during the two synchronous triggers. Starting from t0, the controller of the waveform generation circuit sequentially reads the envelope rising edge data ENVE_rise according to the envelope initial address parameters and generates a carrier according to other parameters and modulates it into Figure 4 The rising edge of the waveform in the middle, after reading out n data, the rising edge ends, the counter stops counting and the synchronous cache of the envelope (and correction) data stops updating data under the action of the hold instruction, and the envelope amplitude is maintained at ENVE_rise[t-1]=ENVE[t-1]= ENVE[t]=...= ENVE[Tt]. During this period, the carrier is normally generated and modulated with the above-mentioned envelope data to form Figure 4 The waveform style of the constant amplitude segment; until the controller receives the synchronization trigger again at time t1 and reads the envelope falling edge data ENVE_fall in sequence according to the parameters and generates a carrier according to other parameters and modulates it into Figure 4As mentioned above, using the "hold instruction" as a waveform label can decompose a long flat-top (or similarly shaped) waveform into multiple segments. The envelope memory only stores the envelope data for the phases where the waveform amplitude changes. This allows the waveform generation mechanism of single waveform multiple triggers to generate long waveforms in segments. This mechanism not only reduces the waste of hardware resources and power consumption caused by repeated storage or calculation of the same data, but also provides a solution that supports the output of longer single waveforms.

[0083] In one embodiment, Figure 5 As shown, the digital carrier generator is specifically:

[0084] The digital carrier generator consists of two submodules: a phase generation module based on a digital accumulator and an amplitude generation module based on a spline interpolation algorithm. The main input signals are the frequency control word, the phase control word, and the accumulator clear signal.

[0085] The phase generation module is specifically as follows: the frequency control word is connected to the input of the accumulator, and the output of the accumulator is also connected to the input of the accumulator after a clock cycle delay to achieve digital accumulation. Therefore, the output of the accumulator is an increasing step signal; when the accumulated value of the accumulator exceeds the maximum value of the accumulator, the accumulator subtracts a full-scale value due to overflow, and the accumulation process begins a cycle; the phase control word is summed with the output value of the accumulator through a digital adder, which serves as the initial offset of the phase signal, and finally outputs a periodic digital phase signal.

[0086] The phase generation module's digital phase signal generation process simulates the periodic phase evolution of a trigonometric function. Therefore, the output of the phase generation module is a periodic digital phase signal. The length of the period is determined by the value of the input frequency control word. A larger frequency control word value results in a smaller period of the phase signal. The phase control word is summed with the accumulator output value via a digital adder to serve as the initial offset for the phase signal. A clear signal is directly connected to the accumulator to clear the current accumulator value and restart phase generation.

[0087] The amplitude generation module divides the periodic digital phase signal into two paths, wherein one path obtains coefficient one through a coefficient lookup table, and uses coefficient one and the digital phase signal to perform spline interpolation on the cosine function to obtain a cosine oscillation carrier; the other path is obtained after taking the remainder through a coefficient lookup table to obtain coefficient two, and uses coefficient two and the remainder of the digital phase signal to perform spline interpolation on the cosine function to obtain a sine oscillation carrier; the sine oscillation carrier and the cosine oscillation carrier are used as a pair of orthogonal carrier signals.

[0088] The two paths have the same spline interpolation method, which is to use the coefficients and the digital phase signal to perform spline interpolation on the cosine function to obtain the oscillation carrier. Specifically:

[0089] (b1) Use the coefficient lookup table to get The three coefficients of the cosine function corresponding to the spline interpolation in the interval ;

[0090] The spline interpolation algorithm formula is as follows:

[0091] , (1);

[0092] in, The digital phase signal generated by the phase generation module, For the interval The interpolating polynomial on , that is, the binomial approximation of the above cosine function, They are The lower and upper limits of the interval, are the polynomial coefficients, which depend on the interval index , that is, each interval has different coefficients, which are determined by the interpolated function and the number of interval segments.

[0093] In the formula for The value range Segments, assuming that the value interval is divided into N (N is a positive integer) segments, then there is a constraint . Searching for a digital phase signal The segmented interval can be realized by right shift and truncation operations instead of comparison operations. For example, if the value interval is divided into N= (M is a positive integer) subintervals, then for the m-bit (m is an integer) digital phase signal Shift right by (mM) bits, and the value of the remaining high M bits is equal to The segment interval number ;.

[0094] The principle of the interpolation algorithm is to use a simple polynomial function that is easy to implement in hardware to approximate the value of a complex function. The spline interpolation algorithm divides the value interval of the independent variable into multiple sub-intervals, and each sub-interval uses a different coefficient ( etc.) to improve the approximation accuracy. In addition, the coefficient According to the approximated function (For example, in this embodiment, the cosine function) is calculated by calculating some sampling points, which can be pre-calculated and loaded into the coefficient lookup table. The multiplication and addition operations in the formula are implemented by the hardware multiplier and hardware adder, and the segment interval number is Look up the coefficient lookup table to get the coefficient .

[0095] (b2) The coefficient With the digital phase signal After multiplication, the coefficient Do the addition, and the addition output value is again combined with the digital phase signal Perform multiplication, multiply the multiplier output value and the coefficient Addition is performed to obtain the cosine function value of the binomial approximation; the multiplication and addition are respectively completed by a hardware multiplier and a hardware adder.

[0096] (b3) Digital phase signal input in each clock cycle Steps (b1) to (b2) are performed, thereby obtaining an oscillating carrier wave having a period equal to that of the digital phase signal;

[0097] By utilizing the symmetry and periodicity of trigonometric functions, this embodiment only The cosine function of the interval is used to perform the above spline interpolation algorithm, as shown in the following example: The symmetry and periodicity shown in the figure can be adjusted to calculate the cosine function value at any sampling point in the period; further, the relationship between the sine function and the cosine function can be used to calculate the cosine function value at any sampling point in the period. , the input digital phase signal After taking the remainder, the spline interpolation algorithm is executed to calculate the sinusoidal oscillation carrier at any sampling point within the period.

[0098] It can be understood that the two paths set in the amplitude generation module obtain coefficient one and coefficient two through the same coefficient lookup table, and spline interpolation is performed on the cosine function based on coefficient one and the digital phase signal to obtain a cosine oscillation carrier. Spline interpolation is performed on the cosine function based on coefficient two and the remainder of the digital phase signal to obtain a sine oscillation carrier.

[0099] According to steps (b1) to (b3), existing classic digital carrier generation circuits usually use an amplitude lookup table to store the cosine function value corresponding to each phase signal value to achieve phase-amplitude mapping. This embodiment utilizes the polynomial approximation principle of the function and combines the symmetry and periodicity of trigonometric functions, thereby greatly reducing the storage overhead required for function mapping.

[0100] In this embodiment, the overall execution process of the algorithm for generating a pair of orthogonal carrier signals (i.e., a sine oscillation carrier and a cosine oscillation carrier) of the digital carrier generator in hardware is as follows: Before using this embodiment, it is pre-loaded into the coefficient lookup table. When using this embodiment to generate waveform data, the accumulator adds the input frequency control word and the output of the accumulator, and sums them with the phase control word to output a digital phase signal x that changes periodically at a certain frequency; this signal is divided into two paths, one of which is taken as the remainder. , the high bits of the two phase signals are intercepted as the segment interval numbers 、 , and are different segmented intervals, Input into the coefficient lookup table to get coefficient 1 ,Will Input into the coefficient lookup table to get coefficient two The two sets of coefficients and the corresponding phase signals are calculated in parallel according to the spline interpolation formula, and the final output is a pair of binomial approximations of orthogonal carrier signals whose frequency and phase match the input parameters, where and in and It is to distinguish different segment intervals and has no practical significance. and Subscript and It is just to distinguish the coefficients corresponding to different segmented intervals.

[0101] The conventional digital sine-cosine carrier generation method is used to obtain a carrier signal as a comparison example of obtaining a pair of orthogonal carrier signals by setting a spline interpolation algorithm in this embodiment. The advantages of using spline interpolation in this embodiment are as follows:

[0102] The existing conventional digital sine and cosine carrier generation method uses a periodic oscillating sawtooth wave signal as an address to generate sine and cosine waves by addressing a lookup table that stores the mapping relationship between linear amplitude and cosine amplitude. The core of this algorithm is to use the amplitude value stored in the coefficient lookup table to achieve The phase resolution of The sine wave between The sampling of the sampling points and recording of all the sampling data, for example, if L=32 and the quantization bit width of the sampling data is 4 bytes, 4MB of storage space is required to record the amplitude data of the cosine wave. The shortage of hardware storage resources will limit the number of sampling points, and thus limit the achievable digital carrier phase accuracy. In the classic measurement and control waveform generation circuit, it is often only the digital circuit that generates the fundamental frequency oscillation of the waveform, and further uses analog devices with more guaranteed accuracy (such as local oscillators) for mixing and up-conversion. In this embodiment, a hardware-implemented spline interpolation algorithm is introduced with a small amount of logic resource overhead to Within range The sampling points are divided into N( Segments, each segment stores only The function value of any sampling point can be calculated by a total of two multiplications and two additions, which optimizes the consumption of hardware storage resources and provides a solution for high-precision digital carrier generation.

[0103] In one embodiment, the modulator is specifically:

[0104] The waveform modulation formula can be expressed as:

[0105]

[0106]

[0107] in, for The envelope modulated data at the moment, for Corrected modulated data at time, for The envelope data generated by the moment envelope generation module is used as the main waveform of the superconducting quantum bit measurement and control signal. for The corrected data generated by the moment envelope generation module is The derivative of is proportional to the waveform shape, which is used as a correction term to adjust the waveform shape, so that the effect of the control pulse on the superconducting quantum bit is closer to the adiabatic process; the two carrier waves and It is the orthogonal carrier signal generated by the digital carrier generator, and the modulation amplitude value and modulation bias value BIAS as input parameters, is the angular frequency, The initial phase.

[0108] The measurement and control principle of superconducting qubits requires that the frequency of the measurement and control waveform resonate with the controlled qubit. However, the eigenfrequency of qubits is concentrated in the GHz range. In multi-bit superconducting quantum computing systems, the eigenfrequencies of different qubits can vary by tens of megahertz. The function of an orthogonal modulator is to ensure that the generated measurement and control waveform has a certain frequency adjustment range, which can be applied to control different qubits. The carrier modulated waveform has frequency and phase controlled by the frequency and phase control words, waveform amplitude controlled by the amplitude parameter, and waveform bias controlled by the bias parameter.

[0109] The core components of the modulator are a series of digital multipliers and adders, which perform quadrature modulation calculations on the two data (orthogonal carrier data and waveform envelope signal) received in each clock cycle; in addition, the modulator receives a modulation amplitude value AMP and a bias amplitude value BIAS, which can be multiplied by the digital multiplier with the waveform data to adjust the overall amplitude of the waveform. Figure 6 As shown in Figure 2, the modulation process of the modulator is as follows:

[0110] A pair of orthogonal carrier signals are summed up through a first adder as a first intermediate variable;

[0111] The envelope data and the correction data are added together by a second adder to form a second intermediate variable;

[0112] The correction data is negated and added to the envelope data through a third adder to form a third intermediate variable;

[0113] The first intermediate variable is multiplied by the envelope data through a first multiplier, the second intermediate variable is multiplied by the sine oscillation carrier in a pair of orthogonal carrier signals through a second multiplier, and the third intermediate variable is multiplied by the cosine oscillation carrier in the orthogonal carrier signal through a third multiplier;

[0114] The output of the second multiplier is negated and added to the output of the first multiplier through a fourth adder. The output of the fourth adder is multiplied by the amplitude value through a fourth multiplier. The output of the fourth multiplier is then added to the offset value through a fifth adder to obtain envelope modulated data.

[0115] The output of the third multiplier is negated and added to the output of the first multiplier through a sixth adder. The output of the sixth adder is multiplied by the amplitude value through a fifth multiplier. The output of the fifth multiplier is then added to the offset value through a seventh adder to obtain corrected modulated data.

[0116] The envelope modulated data and the rectified modulated data are used as the generated final measurement and control waveform.

[0117] The modulation process of the modulator can be expressed in the following mathematical form:

[0118]

[0119]

[0120] in, Envelope data generated by the envelope generation module, Corrected data generated by the envelope generation module, and It is the envelope modulated data and the corrected modulated data, BIAS is the bias amplitude value, and AMP is the modulation amplitude value.

[0121] Expanding the above formulas (4) and (5) to verify that the values ​​of the two output data are the same as those of the above modulation formulas (2) and (3), and by reusing the intermediate variables, each modulator optimizes the logic resources of a multiplier (that is, the number of digital multipliers required by the modulator can be reduced from 6 in the conventional design to 5), which is equivalent to 1 / 6 of the total number of digital multipliers. This embodiment shows a single-channel structure, and a parallel multi-channel design will be adopted in actual applications, so the use of logic resources will also be reduced by the same proportion. Therefore, this embodiment achieves a certain degree of hardware resource optimization.

[0122] The real-time measurement and control waveform generation method of this embodiment dynamically responds to the control effects of multiple independent parameters on waveform generation. By using real-time readout of pre-stored envelopes and real-time digital carrier synthesis, it achieves high-precision measurement and control waveform generation and synchronous control, leveraging the highly flexible, accurate, and reliable characteristics of digital circuits. It offers high precision, real-time performance, flexibility, synchronicity, and stability, making it suitable for superconducting quantum computing measurement and control systems.

[0123] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A method for real-time generation of superconducting quantum bit measurement and control waveforms, characterized in that: include: Based on the envelope parameter, the waveform envelope signal with amplitude variation is read from the envelope storage. The synchronous controller triggers the state register of the finite state machine to hold or idle according to the hold instruction, outputs the waveform envelope signal with constant amplitude or restores the idle state, and caches all the waveform envelope signals according to the envelope data and the correction data. The frequency control word and phase control word cached by the synchronization controller are loaded into the digital carrier generator. The digital phase signal is synthesized by the phase generation module and the coefficients obtained by looking up the digital phase signal table are used to perform spline interpolation calculation on the cosine function to generate an orthogonal carrier signal. All waveform envelope signals and the orthogonal carrier signal are loaded into the modulator for addition and multiplication operations to generate the final measurement and control waveform.

2. The generation method according to claim 1, characterized in that The envelope parameters include an envelope initial address and an envelope length. In the step of reading the waveform envelope signal with amplitude variation from the envelope storage based on the envelope parameters, specifically: The finite state machine starts the counter according to the synchronous trigger signal from the external source, and the counter increments by 1 bit in each clock cycle; Convert the counter value in each clock cycle into an offset address and add it to the initial envelope address to obtain the address of the waveform envelope signal to be read at the current moment; When the counter value is equal to the envelope length, the counter stops incrementing and the waveform envelope signal reading ends.

3. The generation method according to claim 1, characterized in that All waveform envelope signals are cached according to the envelope data and correction data, specifically: Returning the waveform envelope signal read out in each clock cycle to the synchronous buffer submodule of the controller, decomposing the waveform envelope signal into envelope data and correction data and buffering them; An external synchronization trigger signal is connected to the synchronization buffer submodule, and the synchronization buffer submodule delays reading data in a registered manner, thereby synchronizing with other parameters or internal signals.

4. The generation method according to claim 1, characterized in that The frequency control word and phase control word cached by the synchronization controller are loaded into the digital carrier generator. The digital phase signal is synthesized by the phase generation module and the coefficients obtained by looking up the digital phase signal table are used to perform spline interpolation calculation on the cosine function to generate the orthogonal carrier signal. Specifically: The frequency control word and phase control word cached by the synchronous controller are used as inputs of the phase generation module, and a periodic digital phase signal is obtained through accumulation processing by the accumulator. The periodic digital phase signal is divided into two paths, wherein a coefficient one is obtained through a coefficient lookup table, and a cosine function is spline interpolated using the coefficient one and the digital phase signal to obtain a cosine oscillation carrier; Taking the remainder of the other path, obtaining coefficient 2 through a coefficient lookup table, and performing spline interpolation on the cosine function using coefficient 2 and the remainder of the digital phase signal to obtain a sinusoidal oscillation carrier; The sine oscillation carrier and the cosine oscillation carrier are used as a pair of orthogonal carrier signals.

5. The generation method according to claim 4, characterized in that The frequency control word and phase control word cached by the synchronization controller are used as inputs of the phase generation module, and the periodic digital phase signal is obtained through accumulation processing by the accumulator, specifically: The frequency control word is connected to the input of the accumulator, and the output of the accumulator is also connected to the input of the accumulator after a delay of one clock cycle, thereby realizing digital accumulation; When the accumulated value of the accumulator exceeds the maximum value of the accumulator, the accumulator subtracts a full amplitude value due to overflow, and the accumulation process starts to cycle; The phase control word is summed with the output value of the accumulator through a digital adder as the initial bias of the phase signal, and finally a periodic digital phase signal is output.

6. The generation method according to claim 4, characterized in that The process of the spline interpolation method is as follows: (b1) Use the coefficient lookup table to get The three coefficients of the cosine function corresponding to the spline interpolation in the interval ; (b2) The coefficient With the digital phase signal After multiplication, the coefficient Do the addition, and the addition output value is again combined with the digital phase signal Perform multiplication, multiply the multiplier output value and the coefficient Do the addition to get the value of the cosine function approximated by the binomial; (b3) Digital phase signal input in each clock cycle Steps (b1) to (b2) are performed, thereby obtaining an oscillating carrier wave having a period equal to that of the digital phase signal.

7. The generation method according to claim 4, characterized in that The waveform envelope signals and the orthogonal carrier signal are fed back to the modulator for multiplication to generate the final measurement and control waveform, specifically: A pair of orthogonal carrier signals are summed up through a first adder as a first intermediate variable; The envelope data and the correction data are added together by a second adder to form a second intermediate variable; The correction data is negated and added to the envelope data through a third adder to form a third intermediate variable; The first intermediate variable is multiplied by the envelope data through a first multiplier, the second intermediate variable is multiplied by the sine oscillation carrier in a pair of orthogonal carrier signals through a second multiplier, and the third intermediate variable is multiplied by the cosine oscillation carrier in the orthogonal carrier signal through a third multiplier; The output of the second multiplier is negated and added to the output of the first multiplier through a fourth adder. The output of the fourth adder is multiplied by the amplitude value through a fourth multiplier. The output of the fourth multiplier is then added to the offset value through a fifth adder to obtain envelope modulated data. The output of the third multiplier is negated and added to the output of the first multiplier through a sixth adder. The output of the sixth adder is multiplied by the amplitude value through a fifth multiplier. The output of the fifth multiplier is then added to the offset value through a seventh adder to obtain corrected modulated data. The envelope modulated data and the rectified modulated data are used as the generated final measurement and control waveform.

8. A real-time generation system for superconducting quantum bit measurement and control waveforms, characterized in that: It includes a synchronous controller, an envelope generation module, a digital carrier generator and a modulator; The envelope generation module reads a waveform envelope signal with varying amplitude from an envelope storage based on an envelope parameter, and the synchronization controller triggers a state register of a finite state machine to be held or idle according to a hold instruction, outputs a waveform envelope signal with constant amplitude or restores the idle state, and caches all waveform envelope signals according to envelope data and correction data; The digital carrier generator loads the frequency control word and phase control word cached by the synchronization controller into the digital carrier generator, synthesizes the digital phase signal through the phase generation module, and uses the coefficients obtained by looking up the digital phase signal in the table to perform spline interpolation calculation on the cosine function to generate an orthogonal carrier signal; The modulator loads all waveform envelope signals and the orthogonal carrier signal into the modulator for addition and multiplication operations to generate a final measurement and control waveform.

9. The generation system according to claim 8, characterized in that The digital carrier generator includes a phase generation module and an amplitude generation module; The phase generation module takes the frequency control word and phase control word cached by the envelope generation module as input, and obtains a periodic digital phase signal through accumulation processing by the accumulator; The amplitude generation module divides the periodic digital phase signal into two paths, one of which obtains coefficient one through a coefficient lookup table, and uses coefficient one and the digital phase signal to perform spline interpolation on the cosine function to obtain a cosine oscillation carrier; the other path is obtained after taking the remainder through a coefficient lookup table to obtain coefficient two, and uses coefficient two and the remainder of the digital phase signal to perform spline interpolation on the cosine function to obtain a sine oscillation carrier, and the sine oscillation carrier and the cosine oscillation carrier are input into the modulator as a pair of orthogonal carrier signals.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

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