Driver, display panel and display device

Abstract

The invention discloses a driver, a display panel and a display device. The driver includes a plurality of stages. At least one stage of the plurality of stages includes: an input circuit configured to transmit an input signal to a Q node in response to a first clock signal, where the Q node includes a first Q node and a second Q node; a first QB node control circuit configured to control a voltage of the first QB node based on the voltage of the first Q node and a first QB control signal; an output circuit configured to output an output signal having a high gate voltage based on a voltage of the second Q node, and the output circuit configured to output the output signal having a first low gate voltage based on the voltage of the first QB node; and a first QB node discharge circuit configured to discharge the first QB node when the high gate voltage and the first low gate voltage are disabled.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device, and more particularly, to a driver, a display panel, and a display device. Background Art

[0002] The display device may include: a display panel including a plurality of pixels; a data driver providing data signals to the plurality of pixels; a gate driver providing gate signals to the plurality of pixels; an emission driver providing emission signals to the plurality of pixels; and a controller controlling the data driver, the gate driver, and the emission driver.

[0003] The display device may execute a power-off sequence in response to a power-off signal. If the power-off sequence is executed, the signals and voltages provided to the gate driver and / or emission driver may be disabled. However, even if the signals and voltages provided to the gate driver and / or emission driver are disabled, internal nodes (e.g., QB nodes) of the gate driver and / or emission driver may be maintained at a previous voltage. Summary of the Invention

[0004] Some embodiments provide a driver capable of discharging the QB node during a power-off period.

[0005] Some embodiments provide a display panel capable of discharging a QB node during a power-off period.

[0006] Some embodiments provide a display device including a driver capable of discharging a QB node in a power-off period.

[0007] According to an embodiment, a driver is provided that includes a plurality of stages. At least one of the plurality of stages includes: an input circuit configured to transmit an input signal to a Q node in response to a first clock signal, wherein the Q node includes a first Q node and a second Q node; a first QB node control circuit configured to control the voltage of the first QB node based on a voltage of the first Q node and a first QB control signal; an output circuit configured to output an output signal having a high gate voltage based on the voltage of the second Q node, and the output circuit is configured to output the output signal having a first low gate voltage based on the voltage of the first QB node; and a first QB node discharge circuit configured to discharge the first QB node when the high gate voltage and the first low gate voltage are disabled.

[0008] In an embodiment, when a display device including the driver is powered off, the high gate voltage and the first low gate voltage may be disabled to a ground voltage, and the first QB node discharge circuit may discharge the first QB node to the ground voltage.

[0009] In an embodiment, the at least one stage may further include: a reset circuit configured to reset the first Q node in response to a reset signal. The first QB node discharge circuit may include: a first transistor including a gate receiving the reset signal, a first terminal connected to a line transmitting the first QB control signal, and a second terminal connected to the first QB node.

[0010] In an embodiment, the at least one stage may further include: a reset circuit configured to reset the first Q node in response to a reset signal. The first QB node discharge circuit may include: a first transistor including a gate receiving the reset signal, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to the first QB node.

[0011] In an embodiment, the first QB node discharge circuit may include: a first transistor including a gate connected to a line transmitting a second low gate voltage lower than the first low gate voltage, a first terminal connected to a line transmitting the first QB control signal, and a second terminal connected to the first QB node.

[0012] In an embodiment, the first QB node discharge circuit may include: a first transistor including a gate connected to a line transmitting a second low gate voltage lower than the first low gate voltage, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to the first QB node.

[0013] In an embodiment, the input circuit may include a second transistor including a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal connected to the first Q-node.

[0014] In an embodiment, the first QB node control circuit may provide a second low gate voltage lower than the first low gate voltage to the first QB node when the voltage of the first Q node has a high level, and the first QB node control circuit may provide the first QB control signal when the voltage of the first Q node has a low level.

[0015] In an embodiment, the first QB node control circuit may include: a third transistor including a gate receiving the first QB control signal, a first terminal receiving the first QB control signal, and a second terminal; a fourth transistor including a gate connected to the second terminal of the third transistor, a first terminal receiving the first QB control signal, and a second terminal; a first capacitor including a first electrode connected to the gate of the fourth transistor and a second electrode connected to the first QB node; a fifth transistor including a gate connected to the first Q node, a first terminal connected to the gate of the fourth transistor, and a second terminal connected to a line transmitting the first low gate voltage; and a sixth transistor including a gate connected to the first Q node, a first terminal connected to the first QB node, and a second terminal connected to a line transmitting a second low gate voltage lower than the first low gate voltage.

[0016] In an embodiment, the first QB node control circuit may further include: a seventh transistor connected between the second terminal of the fourth transistor and the first QB node. The seventh transistor may include a gate receiving a second clock signal different from the first clock signal, a first terminal connected to the second terminal of the fourth transistor, and a second terminal connected to the first QB node.

[0017] In an embodiment, the output circuit may include: an eighth transistor including a gate connected to the second Q node, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to an output node at which the output signal is output; a second capacitor including a first electrode connected to the second Q node and a second electrode connected to the output node; and a ninth transistor including a gate connected to the first QB node, a first terminal connected to the output node, and a second terminal connected to a line transmitting the first low gate voltage.

[0018] In an embodiment, the output circuit may include: an eighth transistor including a gate connected to the Q node, a first terminal receiving a second clock signal different from the first clock signal, and a second terminal connected to an output node outputting the output signal; and a ninth transistor including a gate connected to the first QB node, a first terminal connected to the output node, and a second terminal connected to a line transmitting the first low gate voltage.

[0019] In an embodiment, the at least one stage may further include: a node separation circuit provided at the Q node, and the node separation circuit is configured to separate the Q node into the first Q node and the second Q node.

[0020] In an embodiment, the node separation circuit may include: a tenth transistor including a gate connected to a line transmitting the high gate voltage, a first terminal connected to the first Q node, and a second terminal connected to the second Q node.

[0021] In an embodiment, the at least one stage may further include: a boost circuit configured to boost the voltage of the second Q node in response to a second clock signal different from the first clock signal.

[0022] In an embodiment, the boost circuit may include: an eleventh transistor including a gate connected to the second Q node, a first terminal receiving the second clock signal, and a second terminal; and a third capacitor including a first electrode connected to the second Q node and a second electrode connected to the second terminal of the eleventh transistor.

[0023] In an embodiment, the at least one stage may further include: a carry circuit configured to output a carry signal having the high gate voltage based on the voltage of the second Q node and to output the carry signal having a second low gate voltage lower than the first low gate voltage based on the voltage of the first QB node.

[0024] In an embodiment, the carry circuit may include: a twelfth transistor, including a gate connected to the second Q node, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to a carry node at which the carry signal is output; and a thirteenth transistor, including a gate connected to the first QB node, a first terminal connected to the carry node, and a second terminal connected to a line transmitting the second low gate voltage.

[0025] In an embodiment, the carry circuit may include: a twelfth transistor including a gate connected to the Q node, a first terminal receiving a second clock signal different from the first clock signal, and a second terminal connected to a carry node outputting the carry signal; a fourth capacitor including a first electrode connected to the Q node and a second electrode connected to the carry node; and a thirteenth transistor including a gate connected to the first QB node, a first terminal connected to the carry node, and a second terminal connected to a line transmitting the second low gate voltage.

[0026] In an embodiment, the at least one stage may further include: a reset circuit configured to provide the first low gate voltage to the first Q node in response to a reset signal.

[0027] In an embodiment, the reset circuit may include a fourteenth transistor including a gate receiving the reset signal, a first terminal connected to the first Q node, and a second terminal connected to a line transmitting the first low gate voltage.

[0028] In an embodiment, the at least one stage may further include: a reset circuit configured to provide a second low gate voltage, which is lower than the first low gate voltage, to the first Q node in response to a reset signal.

[0029] In an embodiment, the reset circuit may include a fourteenth transistor including a gate receiving the reset signal, a first terminal connected to the first Q node, and a second terminal connected to a line transmitting the second low gate voltage.

[0030] In an embodiment, the second transistor included in the input circuit may include a first sub-transistor and a second sub-transistor connected in series. The at least one stage may further include: a leakage prevention circuit configured to provide the high gate voltage to a node between the first sub-transistor and the second sub-transistor in response to the voltage of the first Q-node.

[0031] In an embodiment, the leakage prevention circuit may include: a fifteenth transistor, including a gate connected to the first Q node, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to the node between the first sub-transistor and the second sub-transistor.

[0032] In an embodiment, the at least one stage may further include a first stabilization circuit configured to provide a second low gate voltage lower than the first low gate voltage to the first Q node when the voltage of the first QB node has a high level.

[0033] In an embodiment, the first stabilization circuit may include a sixteenth transistor including a gate connected to the first QB node, a first terminal connected to the first Q node, and a second terminal connected to a line transmitting the second low gate voltage.

[0034] In an embodiment, the first stabilization circuit may include: a seventeenth transistor, including a gate receiving a second clock signal different from the first clock signal, a first terminal connected to the Q node, and a second terminal; and an eighteenth transistor, including a gate connected to the first QB node, a first terminal connected to the second terminal of the seventeenth transistor, and a second terminal connected to a carry node outputting a carry signal.

[0035] In an embodiment, the transistors included in the at least one stage may be n-type metal oxide semiconductor (NMOS) transistors.

[0036] In an embodiment, at least one of the transistors included in the at least one stage may have a double gate structure including a top gate and a bottom gate, and the bottom gate may be connected to the top gate.

[0037] In an embodiment, the at least one stage may further include: a second QB node control circuit configured to control the voltage of the second QB node based on the voltage of the first Q node and a second QB control signal; and a second QB node discharge circuit configured to discharge the second QB node when the high gate voltage and the first low gate voltage are disabled. The output circuit may output the output signal having the first low gate voltage when the voltage of the first QB node is at a high level or when the voltage of the second QB node is at a high level.

[0038] In an embodiment, in a first frame period, the first QB control signal may have the high gate voltage, the second QB control signal may have a second low gate voltage lower than the first low gate voltage, and the output circuit may output the output signal having the first low gate voltage when the voltage of the first QB node has a high level. In a second frame period, the first QB control signal may have the second low gate voltage, the second QB control signal may have the high gate voltage, and the output circuit may output the output signal having the first low gate voltage when the voltage of the first QB node has a high level.

[0039] In an embodiment, the at least one stage may further include: a first stabilization circuit configured to provide a second low gate voltage lower than the first low gate voltage to the first Q node when the voltage of the first QB node has a high level; and a second stabilization circuit configured to provide the second low gate voltage to the first Q node when the voltage of the second QB node has a high level.

[0040] According to an embodiment, a display panel included in a display device is provided. The display panel includes: a first pixel transistor including a gate connected to a first node, a first terminal connected to a line transmitting a first power supply voltage, and a second terminal connected to a second node; a storage capacitor connected between the first node and the second node; a second pixel transistor including a gate receiving a write signal, a first terminal connected to a data line, and a second terminal connected to the first node; a third pixel transistor including a gate receiving a reference signal, a first terminal receiving a reference voltage, and a second terminal connected to the first node; a fourth pixel transistor including a gate receiving an initialization signal, a first terminal connected to an anode of a light-emitting element, and a second terminal receiving an initialization voltage; a light-emitting element including the anode and a cathode connected to a line transmitting a second power supply voltage; a first transistor including a gate receiving a reset signal, a first terminal connected to a line transmitting a QB control signal, and a second terminal connected to a QB node; a second transistor including a gate receiving a first clock signal, a first terminal receiving an input signal, and a second terminal connected to a Q node; a third transistor including a gate receiving the QB control signal, a first terminal receiving the QB control signal, and a second terminal; a fourth transistor including a gate connected to the second terminal of the third transistor. a gate, a first terminal receiving the QB control signal, and a second terminal; a first capacitor including a first electrode connected to the gate of the fourth transistor and a second electrode connected to the QB node; a fifth transistor including a gate connected to the Q node, a first terminal connected to the gate of the fourth transistor, and a second terminal connected to a line transmitting a first low gate voltage; a sixth transistor including a gate connected to the Q node, a first terminal connected to the QB node, and a second terminal connected to a line transmitting a second low gate voltage lower than the first low gate voltage; a seventh transistor including a gate receiving a second clock signal different from the first clock signal, a first terminal connected to the second terminal of the fourth transistor, and a second terminal connected to the QB node; an eighth transistor including a gate connected to the Q node, a first terminal connected to a line transmitting a high gate voltage, and a second terminal connected to an output node where an output signal is output; a second capacitor including a first electrode connected to the Q node and a second electrode connected to the output node; and a ninth transistor including a gate connected to the QB node, a first terminal connected to the output node, and a second terminal connected to the line transmitting the first low gate voltage. The output signal is the write signal, the reference signal, or the initialization signal.

[0041] In an embodiment, the first pixel transistor, the second pixel transistor, the third pixel transistor, the fourth pixel transistor and the light-emitting element may form a pixel, and the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the second capacitor and the ninth transistor may form a stage of a driver.

[0042] According to an embodiment, a display device is provided, comprising: a display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; an emission driver configured to provide emission signals to the plurality of pixels; a power management circuit configured to provide a high gate voltage, a first low gate voltage, and a second low gate voltage to at least one of the gate driver and the emission driver; and a controller configured to control the data driver, the gate driver, the emission driver, and the power management circuit. The controller receives a power-off signal. During at least one first frame period after receiving the power-off signal, a black data voltage is provided as the data signal to the plurality of pixels. During at least one second frame period following the first frame period, a start signal provided to the at least one driver is maintained at the second low gate voltage, first and second clock signals, and a QB control signal are maintained at the high gate voltage, and a reset signal provided to the at least one driver is disabled and set to a ground voltage. In a power-off period following the second frame period, the high gate voltage, the first low gate voltage, the second low gate voltage, the start signal, the first clock signal, the second clock signal, and the QB control signal are disabled to the ground voltage, and the stage of the at least one driver discharges the QB node through a path from the QB node of the stage to the line transmitting the QB control signal in response to the reset signal.

[0043] In an embodiment, the controller may receive a power-on signal. In at least one third frame period after receiving the power-on signal, the high gate voltage, the first low gate voltage, and the second low gate voltage may be activated, and the reset signal may be maintained at the high gate voltage. In at least one fourth frame period after the third frame period, the start signal may be maintained at the second low gate voltage, and the first clock signal and the second clock signal may be periodically switched. In at least one fifth frame period after the fourth frame period, the start signal having the high gate voltage may be applied to the at least one driver, the first clock signal and the second clock signal may be periodically switched, and the black data voltage may be provided to the plurality of pixels as the data signal.

[0044] According to an embodiment, a display device is provided, comprising: a display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; an emission driver configured to provide emission signals to the plurality of pixels; and a controller configured to control the data driver, the gate driver, and the emission driver. At least one of the gate driver and the emission driver comprises a plurality of stages. At least one of the plurality of stages comprises: an input circuit configured to transmit an input signal to a Q node in response to a first clock signal; a QB node control circuit configured to control the voltage of the QB node based on a voltage of the Q node and a QB control signal; an output circuit configured to output an output signal having a high gate voltage based on the voltage of the Q node and to output the output signal having a low gate voltage based on the voltage of the QB node; and a QB node discharge circuit configured to discharge the QB node when the high gate voltage and the low gate voltage are disabled.

[0045] As described above, in the driver, display panel, and display device according to the embodiments, at least one stage may include a QB node discharge circuit that discharges the QB node when the high gate voltage and the low gate voltage are disabled. Therefore, during the power-off period, the internal node or QB node of the driver stage can be discharged normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0047] Figure 1 is a block diagram illustrating a driver according to an embodiment.

[0048] Figure 2 is used to describe Figure 1 A timing diagram of an example of the operation of the driver.

[0049] Figure 3 is a circuit diagram showing a stage of a driver according to an embodiment.

[0050] Figure 4 is used to describe Figure 3 A timing diagram of an example of the operation of the stage.

[0051] Figure 5 is used to describe Figure 3 A circuit diagram of an example of the operation of the stage in a first time period.

[0052] Figure 6 is used to describe Figure 3 A circuit diagram of an example of the operation of the stage in the second time period.

[0053] Figure 7 is used to describe Figure 3 A circuit diagram of an example of the operation of the stage in the third time period.

[0054] Figure 8 is used to describe Figure 3 A circuit diagram of an example of operation of a stage in a fourth time period.

[0055] Figure 9 It is used to describe the execution of the power-off sequence. Figure 3 A timing diagram of an example of the operation of the stage.

[0056] Figure 10 is used to describe Figure 3 Circuit diagram of an example in which the QB node of a stage is discharged during a power-off period.

[0057] Figure 11 is a circuit diagram showing a stage of a driver according to an embodiment.

[0058] Figure 12 is a circuit diagram showing a stage of a driver according to an embodiment.

[0059] Figure 13 is a circuit diagram showing a stage of a driver according to an embodiment.

[0060] Figure 14 is a circuit diagram showing a stage of a driver according to an embodiment.

[0061] Figure 15 is a circuit diagram showing a stage of a driver according to an embodiment.

[0062] Figure 16 is a circuit diagram showing a stage of a driver according to an embodiment.

[0063] Figure 17 is a circuit diagram showing a stage of a driver according to an embodiment.

[0064] Figure 18 is a circuit diagram showing a stage of a driver according to an embodiment.

[0065] Figure 19 is a timing diagram illustrating an example of the QB control signal and the second QB control signal.

[0066] Figure 20 is a circuit diagram showing a stage of a driver according to an embodiment.

[0067] Figure 21 is a circuit diagram showing a stage of a driver according to an embodiment.

[0068] Figure 22 is a circuit diagram showing a stage of a driver according to an embodiment.

[0069] Figure 23 is a circuit diagram showing a stage of a driver according to an embodiment.

[0070] Figure 24 is a circuit diagram illustrating a display panel including a stage of pixels and a driver according to an embodiment.

[0071] Figure 25 is a block diagram illustrating a display device according to an embodiment.

[0072] Figure 26 is a circuit diagram illustrating an example of a pixel included in a display device according to an embodiment.

[0073] Figure 27 is a timing chart showing an example of a power-off sequence of the display device according to the embodiment.

[0074] Figure 28 is a timing chart showing an example of a power-on sequence of the display device according to the embodiment.

[0075] Figure 29 is a block diagram illustrating an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0076] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section. Thus, the "first element," "first component," "first area," "first layer," or "first section" discussed below may be referred to as the "second element," "second component," "second area," "second layer," or "second section" without departing from the teachings herein.

[0077] The terms used herein are only for the purpose of describing a particular embodiment and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, "one", "one (kind / person)", "described (the)" and "at least one (kind / person)" do not represent a restriction on quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" and "at least one element" have the same meaning. "At least one (kind / person)" should not be interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. It will be further understood that, when used in this specification, the terms "include" and / or "comprise" or "have" and / or "contain" illustrate the presence of stated features, regions, entireties, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and / or their groups.

[0078] Embodiments are described more fully hereinafter with reference to the accompanying drawings.Like or similar reference numerals refer to like or similar elements throughout.

[0079] Figure 1 is a block diagram showing a driver according to an embodiment, and Figure 2 is used to describe Figure 1 A timing diagram of an example of the operation of the driver.

[0080] Reference Figure 1 , the driver 100 according to an embodiment may include a plurality of stages STG1, STG2, STG3, STG4, etc. The driver 100 may be implemented in the form of a shift register in which the plurality of stages STG1, STG2, STG3, STG4, etc. sequentially output output signals OUT1, OUT2, OUT3, OUT4, etc. In some embodiments, the driver 100 may be formed in a display panel of a display device. For example, the driver 100 may be integrated or formed on a substrate of the display panel, but is not limited thereto.

[0081] A plurality of stages STG1, STG2, STG3, STG4, etc. may sequentially output output signals OUT1, OUT2, OUT3, OUT4, etc. based on a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2. The first stage STG1 may receive the start signal FLM as an input signal, and subsequent stages STG2, STG3, STG4, etc. may receive carry signals CR1, CR2, CR3, etc. of the previous stage as input signals. For example, the second stage STG2 may receive the first carry signal CR1 of the first stage STG1 as an input signal, the third stage STG3 may receive the second carry signal CR2 of the second stage STG2 as an input signal, and the fourth stage STG4 may receive the third carry signal CR3 of the third stage STG3 as an input signal.

[0082] Reference Figure 1 , also refer to Figure 2 In some embodiments, each odd-numbered stage STG1, STG3, etc. may receive an input signal in response to a first clock signal CLK1, and may output an output signal OUT1, OUT3, etc. having a high gate voltage VGH or a low gate voltage VGL (in other words, a "first low gate voltage") and a carry signal CR1, CR3, etc. having the high gate voltage VGH or a second low gate voltage VGL2 lower than the low gate voltage VGL in response to a second clock signal CLK2. Each even-numbered stage STG2, STG4, etc. may receive an input signal in response to a second clock signal CLK2, and may output an output signal OUT2, OUT4, etc. having a high gate voltage VGH or a low gate voltage VGL and a carry signal CR2, CR4, etc. having the high gate voltage VGH or the second low gate voltage VGL2 in response to the first clock signal CLK1.

[0083] For example, Figure 1 and Figure 2 As shown in , when the start signal FLM has a high level (or a high gate voltage VGH) and the first clock signal CLK1 becomes a high level (or a high gate voltage VGH), the first stage STG1 can receive the start signal FLM having a high level. When the second clock signal CLK2 becomes a high level (or a high gate voltage VGH), the first stage STG1 can output a first output signal OUT1 having a high gate voltage VGH and a first carry signal CR1 having a high gate voltage VGH. Thereafter, when the start signal FLM has a low level (or a second low gate voltage VGL2) and the second clock signal CLK2 becomes a high level (or a high gate voltage VGH), the first stage STG1 can output a first output signal OUT1 having a low gate voltage VGL and a first carry signal CR1 having a second low gate voltage VGL2.

[0084] Further, when the first carry signal CR1 has a high level (or a high gate voltage VGH) and the second clock signal CLK2 becomes a high level, the second stage STG2 can receive the first carry signal CR1 having a high level. When the first clock signal CLK1 becomes a high level, the second stage STG2 can output a second output signal OUT2 having a high gate voltage VGH and a second carry signal CR2 having a high gate voltage VGH. Thereafter, when the first carry signal CR1 has a low level (or a second low gate voltage VGL2) and the first clock signal CLK1 becomes a high level, the second stage STG2 can output a second output signal OUT2 having a low gate voltage VGL and a second carry signal CR2 having a second low gate voltage VGL2.

[0085] Further, when the second carry signal CR2 has a high level and the first clock signal CLK1 becomes a high level, the third stage STG3 can receive the second carry signal CR2 having a high level. When the second clock signal CLK2 becomes a high level, the third stage STG3 can output the third output signal OUT3 having a high gate voltage VGH and the third carry signal CR3 having the high gate voltage VGH. Thereafter, when the second carry signal CR2 has a low level and the second clock signal CLK2 becomes a high level, the third stage STG3 can output the third output signal OUT3 having a low gate voltage VGL and the third carry signal CR3 having the second low gate voltage VGL2.

[0086] Further, when the third carry signal CR3 has a high level and the second clock signal CLK2 becomes a high level, the fourth stage STG4 can receive the third carry signal CR3 having a high level. When the first clock signal CLK1 becomes a high level, the fourth stage STG4 can output the fourth output signal OUT4 having a high gate voltage VGH and the fourth carry signal CR4 having the high gate voltage VGH. Thereafter, when the third carry signal CR3 has a low level and the first clock signal CLK1 becomes a high level, the fourth stage STG4 can output the fourth output signal OUT4 having a low gate voltage VGL and the fourth carry signal CR4 having the second low gate voltage VGL2.

[0087] In this way, multiple stages STG1, STG2, STG3, STG4, etc. can sequentially output output signals OUT1, OUT2, OUT3, OUT4, etc. and carry signals CR1, CR2, CR3, CR4, etc. while delaying or shifting the output signals OUT1, OUT2, OUT3, OUT4, etc. and carry signals CR1, CR2, CR3, CR4, etc. by one horizontal time 1H (or half of the period (or cycle) of the first clock signal CLK1 and the second clock signal CLK2).

[0088] although Figure 2 An example is shown in which the on period (or high period) of each of the first clock signal CLK1 and the second clock signal CLK2 is shorter than the off period (or low period) of each of the first clock signal CLK1 and the second clock signal CLK2, but the first clock signal CLK1 and the second clock signal CLK2 provided to the driver 100 according to the embodiment are not limited to Figure 2 In another example, the first clock signal CLK1 and the second clock signal CLK2 may have a duty cycle of about 50%.

[0089] In some embodiments, the plurality of stages STG1, STG2, STG3, STG4, etc. may further receive a reset signal SESR having a high level (or a high gate voltage VGH) during an initial power-on period in which the display device is powered on. The plurality of stages STG1, STG2, STG3, STG4, etc. may reset the Q nodes of the plurality of stages STG1, STG2, STG3, STG4, etc. during the initial power-on period in response to the reset signal SESR.

[0090] Figure 3 is a circuit diagram showing a stage of a driver according to an embodiment.

[0091] Reference Figure 3 According to the embodiment, at least one stage 200 of the driver may include: an input circuit 210, which transmits an input signal SIN to the Q nodes Q1 and Q2; a QB node control circuit 220 (in other words, a "first QB node control circuit"), which controls the voltage of the QB node QB (in other words, the "first QB node"); an output circuit 230, which outputs the output signal OUT; and a QB node discharge circuit 240 (in other words, the "first QB node discharge circuit"), which discharges the QB node QB.

[0092] In some embodiments, the stage 200 may further include: a node separation circuit 250, the node separation circuit 250 separating the Q nodes Q1 and Q2 into a first Q node Q1 and a second Q node Q2; a boost circuit 260, the boost circuit 260 boosting the voltage of the second Q node Q2; a carry circuit 270 outputting a carry signal CR; a reset circuit 280, the reset circuit 280 resetting the Q nodes Q1 and Q2 (e.g., the first Q node Q1); a leakage prevention circuit 285, the leakage prevention circuit 285 preventing leakage current from the Q nodes Q1 and Q2 (e.g., the first Q node Q1); and a stabilization circuit 290 (in other words, a "first stabilization circuit") stabilizing the voltage of the Q nodes Q1 and Q2 (e.g., the first Q node Q1).

[0093] The input circuit 210 may transmit the input signal SIN to the Q nodes Q1 and Q2 or the first Q node Q1 in response to the first clock signal CLK1. In some embodiments, if the stage 200 is the first stage, the input signal SIN may be the start signal FLM, and if the stage 200 is the subsequent stage, the input signal SIN may be the carry signal PCR of the previous stage.

[0094] In some embodiments, the input circuit 210 may include a second transistor T2. For example, the second transistor T2 may include a gate receiving the first clock signal CLK1, a first terminal receiving the input signal SIN, and a second terminal connected to the first Q-node Q1.

[0095] The QB node control circuit 220 can control the voltage of the QB node QB based on the voltage of the first Q node Q1 and the QB control signal GBI (in other words, the "first QB control signal"). For example, the QB node control circuit 220 can provide the second low gate voltage VGL2 to the QB node QB when the voltage of the first Q node Q1 has a high level, and can provide the QB control signal GBI to the QB node QB when the voltage of the first Q node Q1 has a low level. In some embodiments, the second low gate voltage VGL2 can be lower than the low gate voltage VGL of the output signal OUT. In addition, the QB control signal GBI can have a high gate voltage VGH. In some embodiments, as Figure 3 As shown in , the line for transmitting the QB control signal GBI may be different from the line for transmitting the high gate voltage VGH. In other embodiments, as shown below with reference to Figure 16 As described above, a high gate voltage VGH may be used instead of the QB control signal GBI, and the QB node control circuit 220 may be connected to a line that transmits the high gate voltage VGH. Figure 3 As shown in , the QB node control circuit 220 may receive the second clock signal CLK2. In this case, the QB node control circuit 220 may provide the QB control signal GBI to the QB node QB when the voltage of the first Q node Q1 has a low level and the second clock signal CLK2 has a high level.

[0096] In some embodiments, the QB node control circuit 220 may include a third transistor T3, a fourth transistor T4, a first capacitor C1, a fifth transistor T5, and a sixth transistor T6. For example, the third transistor T3 may include a gate receiving the QB control signal GBI, a first terminal receiving the QB control signal GBI, and a second terminal. The fourth transistor T4 may include a gate connected to the second terminal of the third transistor T3, a first terminal receiving the QB control signal GBI, and a second terminal. The first capacitor C1 may include a first electrode connected to the gate of the fourth transistor T4 and a second electrode connected to the QB node QB. The fifth transistor T5 may include a gate connected to the first Q node Q1, a first terminal connected to the gate of the fourth transistor T4, and a second terminal connected to a line transmitting a low gate voltage VGL. The sixth transistor T6 may include a gate connected to the first Q node Q1, a first terminal connected to the QB node QB, and a second terminal connected to a line transmitting a second low gate voltage VGL2. In some embodiments, the QB node control circuit 220 may further include a seventh transistor T7 connected between the second terminal of the fourth transistor T4 and the QB node QB. For example, the seventh transistor T7 may include a gate receiving the second clock signal CLK2 , a first terminal connected to the second terminal of the fourth transistor T4 , and a second terminal connected to the QB node QB.

[0097] The node separation circuit 250 may be provided at the Q-nodes Q1 and Q2 and may separate the Q-nodes Q1 and Q2 into a first Q-node Q1 and a second Q-node Q2. The node separation circuit 250 may connect the first Q-node Q1 and the second Q-node Q2 to each other most of the time, but may disconnect the first Q-node Q1 from the second Q-node Q2 when the voltage of the second Q-node Q2 is boosted. Therefore, when the voltage of the second Q-node Q2 is at a boosted high level, the voltage of the second Q-node Q2 may be prevented from being transmitted to the first Q-node Q1.

[0098] In some embodiments, the node separation circuit 250 may include a tenth transistor T10. For example, the tenth transistor T10 may include a gate connected to a line transmitting a high gate voltage VGH, a first terminal connected to the first Q node Q1, and a second terminal connected to the second Q node Q2.

[0099] The boost circuit 260 can boost the voltage of the second Q-node Q2 in response to the second clock signal CLK2. For example, when the second clock signal CLK2 changes from a low level to a high level, the boost circuit 260 can boost the voltage of the second Q-node Q2 from a high level to a boosted high level by using a boost capacitor (or the third capacitor C3).

[0100] In some embodiments, the boost circuit 260 may include an eleventh transistor T11 and a third capacitor C3. For example, the eleventh transistor T11 may include a gate connected to the second Q-node Q2, a first terminal receiving the second clock signal CLK2, and a second terminal, and the third capacitor C3 may include a first electrode connected to the second Q-node Q2 and a second electrode connected to the second terminal of the eleventh transistor T11.

[0101] The output circuit 230 may output an output signal OUT having a high gate voltage VGH based on the voltage of the second Q node Q2, and may output an output signal OUT having a low gate voltage VGL based on the voltage of the QB node QB. For example, the output circuit 230 may output an output signal OUT having a high gate voltage VGH in response to the voltage of the second Q node Q2 having a boosted high level, and may output an output signal OUT having a low gate voltage VGL in response to the voltage of the QB node QB having a high level.

[0102] In some embodiments, the output circuit 230 may include an eighth transistor T8, a second capacitor C2, and a ninth transistor T9. For example, the eighth transistor T8 may include a gate connected to the second Q node Q2, a first terminal connected to a line transmitting a high gate voltage VGH, and a second terminal connected to an output node NO at which an output signal OUT is output, the second capacitor C2 may include a first electrode connected to the second Q node Q2 and a second electrode connected to the output node NO, and the ninth transistor T9 may include a gate connected to the QB node QB, a first terminal connected to the output node NO, and a second terminal connected to a line transmitting a low gate voltage VGL.

[0103] The carry circuit 270 may output a carry signal CR having a high gate voltage VGH based on the voltage of the second Q node Q2, and may output a carry signal CR having a second low gate voltage VGL2 based on the voltage of the QB node QB. For example, the carry circuit 270 may output the carry signal CR having a high gate voltage VGH in response to the voltage of the second Q node Q2 having a boosted high level, and may output the carry signal CR having a second low gate voltage VGL2 in response to the voltage of the QB node QB having a high level.

[0104] In some embodiments, the carry circuit 270 may include a twelfth transistor T12 and a thirteenth transistor T13. For example, the twelfth transistor T12 may include a gate connected to the second Q node Q2, a first terminal connected to a line transmitting a high gate voltage VGH, and a second terminal connected to a carry node NC at which a carry signal CR is output, and the thirteenth transistor T13 may include a gate connected to the QB node QB, a first terminal connected to the carry node NC, and a second terminal connected to a line transmitting a second low gate voltage VGL2.

[0105] The reset circuit 280 can provide a low gate voltage VGL to the first Q node Q1 in response to a reset signal SESR. In some embodiments, the reset signal SESR can have a high level (or a high gate voltage VGH) during an initial power-on period when the display device is powered on, and the reset circuit 280 can provide the low gate voltage VGL to the first Q node Q1 in response to the high level reset signal SESR during the initial power-on period. Furthermore, the low gate voltage VGL of the first Q node Q1 can be transmitted to the second Q node Q2 via the tenth transistor T10. Therefore, the reset circuit 280 can reset the first and second Q nodes Q1, Q2, to the low gate voltage VGL during the initial power-on period.

[0106] In some embodiments, the reset circuit 280 may include a fourteenth transistor T14. For example, the fourteenth transistor T14 may include a gate receiving the reset signal SESR, a first terminal connected to the first Q node Q1, and a second terminal connected to a line transmitting a low gate voltage VGL.

[0107] The stabilization circuit 290 may provide the second low gate voltage VGL2 to the first Q node Q1 when the voltage of the QB node QB has a high level. The second low gate voltage VGL2 of the first Q node Q1 may be transmitted to the second Q node Q2 through the tenth transistor T10. In order to make the Q nodes Q1 and Q2, or the first Q node Q1 and the second Q node Q2, have a low level or the second low gate voltage VGL2 most of the time, the stabilization circuit 290 may stabilize the voltages of the first Q node Q1 and the second Q node Q2 by providing the second low gate voltage VGL2 to the first Q node Q1 and the second Q node Q2.

[0108] In some embodiments, the stabilization circuit 290 may include a sixteenth transistor T16. For example, the sixteenth transistor T16 may include a gate connected to the QB node QB, a first terminal connected to the first Q node Q1, and a second terminal connected to a line transmitting the second low gate voltage VGL2.

[0109] In some embodiments, as Figure 3As shown in FIG, each of the second transistor T2, the fourteenth transistor T14, and the sixteenth transistor T16 can be implemented as a dual transistor including two sub-transistors connected in series to reduce leakage current from the first Q-node Q1. In addition, to further prevent leakage current, the leakage prevention circuit 285 can provide a high gate voltage VGH to the node between the two sub-transistors in response to the voltage of the first Q-node Q1. In other words, the leakage prevention circuit 285 can provide the high gate voltage VGH to the node between the two sub-transistors when the first Q-node Q1 has the high gate voltage VGH, thereby further preventing leakage current.

[0110] In some embodiments, the leakage prevention circuit 285 may include a fifteenth transistor T15. For example, the fifteenth transistor T15 may include a gate connected to the first Q node Q1, a first terminal connected to a line transmitting a high gate voltage VGH, and a second terminal connected to a node between the two sub-transistors.

[0111] The QB node discharge circuit 240 can discharge the QB node QB during a power-off period in which the high gate voltage VGH and the low gate voltage VGL are disabled. For example, when the display device is powered off, the high gate voltage VGH and the low gate voltage VGL can be disabled to the ground voltage, and the QB node discharge circuit 240 can discharge the QB node QB from the high gate voltage VGH to the ground voltage. In some embodiments, as described below with reference to Figure 10 As described above, the QB node discharge circuit 240 may form a path for the discharge current IDIS from the QB node QB to the line transmitting the QB control signal GBI in response to the reset signal SESR in the power-off period POFF.

[0112] In some embodiments, the QB node discharge circuit 240 may include a first transistor T1 that receives a reset signal SESR and is connected between the QB node QB and a line transmitting a QB control signal GBI. For example, the first transistor T1 may include a gate that receives the reset signal SESR, a first terminal connected to the line transmitting the QB control signal GBI, and a second terminal connected to the QB node QB.

[0113] In the case where the stage 200 does not include the QB node discharge circuit 240, even if the signals SIN, CLK1, CLK2, SESR, and GBI and the voltages VGH, VGL, and VGL2 provided to the stage 200 are disabled as the ground voltage during the power-off period POFF, the QB node QB may not be discharged to the ground voltage and may be maintained at the high gate voltage VGH for at least a certain time. In particular, when the threshold voltages of the transistors T2 to T16 included in the stage 200 shift (e.g., shift in the positive direction), the QB node QB may not be discharged to the ground voltage. However, in the stage 200 of the driver according to the embodiment, the first transistor T1 can be turned off in response to the reset signal SESR having the second low gate voltage VGL2 in most periods other than the initial power-on period, and therefore the threshold voltage of the first transistor T1 may not shift. Therefore, in the power-off period POFF in which the reset signal SESR and the QB control signal GBI are disabled to the ground voltage, the discharge current IDIS may flow from the QB node QB through the first transistor T1 to the line transmitting the QB control signal GBI, and the QB node QB may be discharged to the ground voltage.

[0114] In some embodiments, as Figure 3 As shown in FIG, the first transistor T1 to the sixteenth transistor T16 included in the stage 200 may be N-type metal oxide semiconductor (NMOS) transistors, but are not limited thereto. In addition, in some embodiments, the first transistor T1 to the sixteenth transistor T16 included in the stage 200 may be oxide transistors having an active region including an oxide semiconductor, but are not limited thereto. In other embodiments, at least a portion of the first transistor T1 to the sixteenth transistor T16 included in the stage 200 may be P-type metal oxide semiconductor (PMOS) transistors.

[0115] Furthermore, in some embodiments, at least a portion of the first to sixteenth transistors T1 to T16 included in the stage 200 may be implemented as dual transistors each including two sub-transistors connected in series. Figure 3 As shown in FIG, each of the second transistor T2, the third transistor T3, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 may include two sub-transistors connected in series.

[0116] Figure 4 is used to describe Figure 3 A timing diagram of an example of the operation of the stage, Figure 5 is used to describe Figure 3 A circuit diagram of an example of the operation of the stage in the first time period, Figure 6 is used to describe Figure 3 A circuit diagram of an example of the operation of the stage in the second time period, Figure 7 is used to describe Figure 3 A circuit diagram of an example of the operation of the stage in the third time period, and Figure 8 is used to describe Figure 3 A circuit diagram of an example of operation of a stage in a fourth time period.

[0117] Reference Figure 3 and Figure 4 , also refer to Figure 5 、 Figure 6 、 Figure 7 and Figure 8 , the stage 200 may receive the input signal SIN in response to the first clock signal CLK1. When the second clock signal CLK2 becomes high after the input signal SIN has a high level, the stage 200 may output a carry signal CR having a high gate voltage VGH and an output signal OUT having a high gate voltage VGH. In addition, when the second clock signal CLK2 becomes high after the input signal SIN has a low level, the stage 200 may output a carry signal CR having a second low gate voltage VGL2 and an output signal OUT having a low gate voltage VGL.

[0118] For example, in the first period TP1 in which the input signal SIN has a high level H and the first clock signal CLK1 has a high level H, as shown in FIG. Figure 5As shown in FIG, the second transistor T2 may be turned on in response to the first clock signal CLK1 having a high level H and may transmit the input signal SIN having a high level H to the first Q-node Q1. Therefore, the voltage of the first Q-node Q1 may have a high level H. The fifteenth transistor T15 may be turned on in response to the voltage of the first Q-node Q1 having a high level H and may transmit the high gate voltage VGH to the node between the two sub-transistors of each of the second transistor T2, the fourteenth transistor T14, and the sixteenth transistor T16. The tenth transistor T10 may be turned on in response to the high gate voltage VGH and may transmit the voltage of the first Q-node Q1 to the second Q-node Q2. Therefore, the voltage of the second Q-node Q2 may have a high level H. The eleventh transistor T11 may be turned on in response to the voltage of the second Q-node Q2 having a high level H and may transmit the second clock signal CLK2 having a low level L to the second electrode of the third capacitor C3. The voltage of the second Q node Q2 having a high level H may be applied to the gates of the eighth transistor T8 and the twelfth transistor T12, and the voltage levels of the output signal OUT and the carry signal CR may increase. However, since the voltage of the second Q node Q2 is not higher than the high gate voltage VGH applied to the first terminals (e.g., sources) of the eighth transistor T8 and the twelfth transistor T12, the eighth transistor T8 and the twelfth transistor T12 may not be fully (or completely) turned on, and the high gate voltage VGH may not be output as the output signal OUT and the carry signal CR.

[0119] Furthermore, during the first period TP1, the sixth transistor T6 may be turned on in response to the voltage of the first Q node Q1 having a high level (H) and may transmit the second low gate voltage VGL2 to the QB node QB. Consequently, the voltage of the QB node QB may have a low level (L). The ninth transistor T9, the thirteenth transistor T13, and the sixteenth transistor T16 may be turned off in response to the voltage of the QB node QB having a low level (L). The third transistor T3 may transmit the QB control signal GBI having a high gate voltage (VGH) to the gate of the fourth transistor T4, but the fifth transistor T5 may transmit the low gate voltage (VGL) to the gate of the fourth transistor T4 in response to the voltage of the first Q node Q1 having a high level (H). Consequently, a voltage between the high gate voltage (VGH) and the low gate voltage (VGL) may be applied to the gate of the fourth transistor T4, and the fourth transistor T4 may be turned off. Furthermore, the seventh transistor T7 may be turned off in response to the second clock signal CLK2 having a low level (L), and the QB control signal GBI may not be transmitted to the QB node QB.

[0120] In the second period TP2 in which the input signal SIN has a high level H and the second clock signal CLK2 has a high level H, as shown in FIG. Figure 6As shown in FIG, the eleventh transistor T11 can transmit the second clock signal CLK2 to the second electrode of the third capacitor C3. When the second clock signal CLK2 applied to the second electrode of the third capacitor C3 increases from a low level L to a high level H, the voltage of the second Q-node Q2 connected to the first electrode of the third capacitor C3 can also increase from the high level H to a boosted high level BH. Because the high gate voltage VGH applied to the gate of the tenth transistor T10 is lower than the voltage of the second Q-node Q2 having the boosted high level BH, the tenth transistor T10 can be turned off and the voltage of the second Q-node Q2 having the boosted high level BH can be prevented from being transmitted to the first Q-node Q1. The eighth transistor T8 can be fully turned on in response to the voltage of the second Q-node Q2 having the boosted high level BH and can output the high gate voltage VGH as the output signal OUT. Furthermore, the twelfth transistor T12 can be fully turned on in response to the voltage of the second Q-node Q2 having the boosted high level BH and can output the high gate voltage VGH as the carry signal CR.

[0121] In addition, in the second period TP2, the sixth transistor T6 may transmit the second low gate voltage VGL2 to the QB node QB, and the ninth transistor T9, the thirteenth transistor T13, and the sixteenth transistor T16 may be turned off. Although the seventh transistor T7 is turned on in response to the second clock signal CLK2 having a high level H, the fourth transistor T4 is turned off, and thus the QB control signal GBI may not be transmitted to the QB node QB.

[0122] In the third period TP3 in which the input signal SIN has a low level L and the first clock signal CLK1 has a high level H, as shown in FIG. Figure 7 As shown in , the second transistor T2 may transmit the input signal SIN having a low level L to the first Q-node Q1, and the tenth transistor T10 may transmit the voltage of the first Q-node Q1 to the second Q-node Q2. Therefore, the voltages of the first Q-node Q1 and the second Q-node Q2 may have a low level L. The fifth transistor T5, the sixth transistor T6, and the fifteenth transistor T15 may be turned off in response to the voltage of the first Q-node Q1 having a low level L, and the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 may be turned off in response to the voltage of the second Q-node Q2 having a low level L.

[0123] Furthermore, during the third period TP3, although the fourth transistor T4 is turned on in response to the QB control signal GBI transmitted through the third transistor T3, the seventh transistor T7 is turned off in response to the second clock signal CLK2 having a low level L, and therefore the QB control signal GBI may not be transmitted to the QB node QB. Therefore, the voltage of the QB node QB may be maintained at a low level L. Therefore, the ninth transistor T9, the thirteenth transistor T13, and the sixteenth transistor T16 may be turned off in response to the voltage of the QB node QB having a low level L. During the third period TP3, the eighth transistor T8 and the ninth transistor T9 may be turned off, and the output signal OUT may be maintained at the previous voltage or the high gate voltage VGH. Furthermore, during the third period TP3, the twelfth transistor T12 and the thirteenth transistor T13 may be turned off, and the carry signal CR may be maintained at the previous voltage or the high gate voltage VGH.

[0124] In the fourth period TP4 in which the input signal SIN has a low level L and the second clock signal CLK2 has a high level H, as shown in FIG. Figure 8 As shown in , the first clock signal CLK1, the voltage of the first Q node Q1 and the voltage of the second Q node Q2 may have a low level L, and the second transistor T2, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12 and the fifteenth transistor T15 may be turned off.

[0125] Furthermore, during a fourth period TP4, the fourth transistor T4 may be turned on in response to the QB control signal GBI transmitted through the third transistor T3, and the seventh transistor T7 may be turned on in response to the second clock signal CLK2 having a high level H. Thus, the QB control signal GBI having a high gate voltage VGH may be transmitted to the QB node QB via the fourth transistor T4 and the seventh transistor T7. Consequently, the voltage of the QB node QB may have a high level H. The sixteenth transistor T16 may provide the second low gate voltage VGL2 to the first Q node Q1 in response to the voltage of the QB node QB having a high level H. The ninth transistor T9 may be turned on in response to the voltage of the QB node QB having a high level H and may output the low gate voltage VGL as the output signal OUT. Furthermore, the thirteenth transistor T13 may be turned on in response to the voltage of the QB node QB having a high level H and may output the second low gate voltage VGL2 as the carry signal CR.

[0126] In addition, if Figures 5 to 8As shown in FIG, in the first to fourth time periods TP1 to TP4, the reset signal SESR may have a low level L (eg, the second low gate voltage VGL2). The first transistor T1 and the fourteenth transistor T14 may be turned off in response to the reset signal SESR having the second low gate voltage VGL2. Figures 3 to 8 Although not shown, the reset signal SESR may have a high level H or a high gate voltage VGH during the initial power-on period. Therefore, during the initial power-on period, the fourteenth transistor T14 may reset the first Q node Q1 and / or the second Q node Q2 to the low gate voltage VGL, and the first transistor T1 may reset the QB node QB to the high gate voltage VGH of the QB control signal GBI. Furthermore, during the initial power-on period, the high gate voltage VGH of the QB control signal GBI may be transmitted not only to the QB node QB via the first transistor T1 but also to the QB node QB via the fourth transistor T4 and the seventh transistor T7.

[0127] In a period other than the initial power-on period in which the display device performs a normal operation, the first transistor T1 may be maintained in an off state. Therefore, the threshold voltage of the first transistor T1 may not shift while the display device performs a normal operation. Figure 10 , the first transistor T1 , whose threshold voltage is not shifted, may be used to discharge the QB node QB in the power-off period POFF.

[0128] In the following, reference will be made to Figure 3 、 Figure 9 and Figure 10 Describes the process of executing a power-off sequence for a display device. Figure 3 An example of the operation of stage 200.

[0129] Figure 9 It is used to describe the execution of the power-off sequence. Figure 3 The timing diagram of an example of the operation of the stage, and Figure 10 is used to describe Figure 3 Circuit diagram of an example in which the QB node of a stage is discharged during a power-off period.

[0130] Reference Figure 3 and Figure 9In at least one first frame period FP1-1 and FP1-2 after the display device receives the power-off signal SOFF, the high gate voltage VGH, the low gate voltage VGL, the second low gate voltage VGL2, the start signal FLM, the first clock signal CLK1, the second clock signal CLK2, the QB control signal GBI, and the reset signal SESR can be provided to each stage 200 in the same manner as in the frame period in which the normal operation is performed. Therefore, the driver according to the embodiment can perform the normal operation in the first frame period FP1-1 and FP1-2. However, in the first frame period FP1-1 and FP1-2, as will be referred to below Figure 27 As described above, a black data voltage corresponding to the lowest gray level (eg, gray level 0) may be provided as a data signal to the plurality of pixels. Therefore, in the first frame periods FP1-1 and FP1-2, the plurality of pixels may display a black image or may not emit light.

[0131] In at least one second frame period FP2-1 and FP2-2 following the first frame periods FP1-1 and FP1-2, the high gate voltage VGH, the low gate voltage VGL, and the second low gate voltage VGL2 may be maintained in an active state. Furthermore, the start signal FLM may be maintained at the second low gate voltage VGL2, and the first and second clock signals CLK1 and CLK2, as well as the QB control signal GBI, may be maintained at the high gate voltage VGH. Therefore, in the second frame periods FP2-1 and FP2-2, based on the start signal FLM having the second low gate voltage VGL2 and the first and second clock signals CLK1 and CLK2 having the high gate voltage VGH, the Q nodes Q1 and Q2 of all stages 200 of the driver may be reset to the second low gate voltage VGL2, and the QB nodes QB of all stages 200 of the driver may be reset to the high gate voltage VGH. Furthermore, in some embodiments, in the second frame periods FP2-1 and FP2-2, the reset signal SESR may be disabled to the ground voltage VGND.

[0132] In the power-off period POFF after the second frame periods FP2-1 and FP2-2, the high gate voltage VGH, the low gate voltage VGL, the second low gate voltage VGL2, the start signal FLM, the first clock signal CLK1 and the second clock signal CLK2, and the QB control signal GBI may be disabled to the ground voltage VGND. In addition, the Q nodes Q1 and Q2 of all stages 200 of the driver may have the ground voltage VGND by the current flowing through the transistor (e.g., the sixteenth transistor T16) of each stage 200.

[0133] However, in the case where the stage 200 does not include the QB node discharge circuit 240 or the first transistor T1, in the power-off period POFF, the QB node QB may not be discharged to the ground voltage VGND and may be maintained at the high gate voltage VGH for at least a certain time. In particular, when the threshold voltage of the sixth transistor T6 and / or the seventh transistor T7 connected to the QB node QB shifts (e.g., shifts forward), the QB node QB may not be discharged to the ground voltage VGND. However, in the stage 200 of the driver according to the embodiment, the first transistor T1 may not be turned on during normal operation of the driver, and thus the threshold voltage of the first transistor T1 may not shift. Therefore, as Figure 10 As shown in FIG, the first transistor T1 receiving the reset signal SESR having the ground voltage VGND can form a path for a discharge current IDIS (or leakage current) from the QB node QB having the high gate voltage VGH to the line transmitting the QB control signal GBI having the ground voltage VGND. Therefore, in the stage 200 of the driver according to the embodiment, the QB node QB can be discharged to the ground voltage VGND through the first transistor T1.

[0134] Figure 11 is a circuit diagram showing a stage of a driver according to an embodiment.

[0135] Reference Figure 11 , also refer to Figure 10 At least one stage 200a of the driver according to the embodiment may include a first transistor T1a, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2 and a third capacitor C3. Figure 11 The level 200a can be used with Figure 3 The stage 200 has a similar configuration and a similar operation, except that the QB node discharge circuit 240 a may be connected to a line transmitting the high gate voltage VGH instead of a line transmitting the QB control signal GBI.

[0136] During the power-off period POFF, QB node discharge circuit 240a can form a path for discharge current IDIS from QB node QB to a line transmitting high gate voltage VGH in response to reset signal SESR having ground voltage VGND. In some embodiments, QB node discharge circuit 240a may include a first transistor T1a having a gate that receives reset signal SESR, a first terminal connected to a line transmitting high gate voltage VGH, and a second terminal connected to QB node QB. Thus, QB node QB of stage 200a can discharge normally during the power-off period POFF.

[0137] Figure 12 is a circuit diagram showing a stage of a driver according to an embodiment.

[0138] Reference Figure 12 , also refer to Figure 10 At least one stage 200b of the driver according to the embodiment may include a first transistor T1b, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Figure 12 The level 200b can be used with Figure 3 The stage 200 has a similar configuration and a similar operation, except that the QB node discharge circuit 240 b may receive the second low gate voltage VGL2 instead of the reset signal SESR.

[0139] During the power-off period (POFF), QB node discharge circuit 240b can form a path for discharge current IDIS from QB node QB to the line transmitting QB control signal GBI in response to the second low gate voltage VGL2, which is disabled as ground voltage VGND. In some embodiments, QB node discharge circuit 240b can include a first transistor T1b having a gate connected to the line transmitting the second low gate voltage VGL2, a first terminal connected to the line transmitting QB control signal GBI, and a second terminal connected to QB node QB. During normal operation of the driver, first transistor T1b can be turned off in response to the second low gate voltage VGL2, and thus the threshold voltage of first transistor T1b can not shift. Therefore, QB node QB of stage 200b can discharge normally during the power-off period (POFF).

[0140] Figure 13 is a circuit diagram showing a stage of a driver according to an embodiment.

[0141] Reference Figure 13 , also refer to Figure 10 At least one stage 200c of the driver according to the embodiment may include a first transistor T1c, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Figure 13 The Level 200c can be used with Figure 3 The stage 200 has a similar configuration and a similar operation, except that the QB node discharge circuit 240c may be connected to a line transmitting a high gate voltage VGH instead of a line transmitting a QB control signal GBI and may receive a second low gate voltage VGL2 instead of the reset signal SESR.

[0142] During the power-off period POFF, QB node discharge circuit 240c can form a path for discharge current IDIS from QB node QB to a line transmitting high gate voltage VGH in response to second low gate voltage VGL2 having ground voltage VGND. In some embodiments, QB node discharge circuit 240c can include a first transistor T1c having a gate connected to a line transmitting second low gate voltage VGL2, a first terminal connected to a line transmitting high gate voltage VGH, and a second terminal connected to QB node QB. Thus, QB node QB of stage 200c can discharge normally during the power-off period POFF.

[0143] Figure 14 is a circuit diagram showing a stage of a driver according to an embodiment.

[0144] Reference Figure 14 At least one stage 200d of the driver according to the embodiment may include a first transistor T1d, a second transistor T2, a third transistor T3d, a fourth transistor T4d, a fifth transistor T5d, a sixth transistor T6d, a seventh transistor T7, an eighth transistor T8d, a ninth transistor T9d, a tenth transistor T10, an eleventh transistor T11d, a twelfth transistor T12d, a thirteenth transistor T13d, a fourteenth transistor T14d, a fifteenth transistor T15d, a sixteenth transistor T16d, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Figure 14 The Level 200d can be used with Figure 3The stage 200 has a similar configuration and similar operation, except that some transistors T1d, T3d, T4d, T5d, T6d, T8d, T9d, T11d, T12d, T13d, T14d, T15d and T16d of the stage 200d may have a dual-gate structure including a top gate and a bottom gate.

[0145] In some embodiments, the first transistor T1d, the third transistor T3d, the fourth transistor T4d, the fifth transistor T5d, the sixth transistor T6d, the eighth transistor T8d, the ninth transistor T9d, the eleventh transistor T11d, the twelfth transistor T12d, the thirteenth transistor T13d, the fourteenth transistor T14d, the fifteenth transistor T15d, and the sixteenth transistor T16d may have a dual-gate structure. Furthermore, in each of the first transistor T1d, the third transistor T3d, the fourth transistor T4d, the fifth transistor T5d, the sixth transistor T6d, the eighth transistor T8d, the ninth transistor T9d, the eleventh transistor T11d, the twelfth transistor T12d, the fourteenth transistor T14d, and the fifteenth transistor T15d, the bottom gate may be connected to the top gate. In some embodiments, these transistors T1d, T3d, T4d, T5d, T6d, T8d, T9d, T11d, T12d, T14d, and T15d may be referred to as gate-synchronous transistors. Furthermore, a bottom gate of each of the thirteenth and sixteenth transistors T13 d and T16 d may be connected to one terminal of a corresponding one of the thirteenth and sixteenth transistors T13 d and T16 d .

[0146] In addition, in some embodiments, each of the second transistor T2, the third transistor T3d, the fourteenth transistor T14d, the fifteenth transistor T15d, and the sixteenth transistor T16d may be implemented as a double transistor including two sub-transistors connected in series. Each sub-transistor of the third transistor T3d, the fourteenth transistor T14d, and the fifteenth transistor T15d may include a top gate and a bottom gate connected to the top gate. Furthermore, one of the two sub-transistors of the sixteenth transistor T16d may include a top gate and a bottom gate connected to one terminal of the one of the two sub-transistors of the sixteenth transistor T16d.

[0147] Figure 15 is a circuit diagram showing a stage of a driver according to an embodiment.

[0148] Reference Figure 15At least one stage 200e of the driver according to the embodiment may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14e, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2 and a third capacitor C3. Figure 15 The Level 200e can be used with Figure 3 The stage 200 has a similar configuration and a similar operation, except that the reset circuit 280 e may be connected to a line transmitting the second low gate voltage VGL2 instead of the line transmitting the low gate voltage VGL.

[0149] The reset circuit 280e can provide a second low gate voltage VGL2 to the first Q-node Q1 in response to a reset signal SESR during an initial power-on period. During the initial power-on period, the input signal SIN can have the second low gate voltage VGL2, and the first Q-node Q1 can be reset to the second low gate voltage VGL2, thereby preventing a short circuit defect between the line transmitting the input signal SIN and the first Q-node Q1. In some embodiments, the reset circuit 280e can include a fourteenth transistor T14e, which includes a gate that receives the reset signal SESR, a first terminal connected to the first Q-node Q1, and a second terminal connected to the line transmitting the second low gate voltage VGL2.

[0150] Figure 16 is a circuit diagram showing a stage of a driver according to an embodiment.

[0151] Reference Figure 16 At least one stage 200f of the driver according to the embodiment may include a first transistor T1f, a second transistor T2, a third transistor T3f, a fourth transistor T4f, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2 and a third capacitor C3. Figure 16 The level 200f can be used with Figure 3 The stage 200 has a similar configuration and similar operation, except that a high gate voltage VGH can be used instead of Figure 3 The QB control signal GBI shown in .

[0152] In the stage 200f, the QB node control circuit 220f and the QB node discharge circuit 240f may be connected to the line transmitting the high gate voltage VGH instead of the line transmitting the high gate voltage VGH. Figure 3 That is, the third transistor T3f and the fourth transistor T4f of the QB node control circuit 220f and the first transistor T1f of the QB node discharge circuit 240f may not be connected to the transmission line of the QB control signal GBI shown in FIG. Figure 3 Instead of the line of the QB control signal GBI shown in FIG, it can be connected to a line transmitting a high gate voltage VGH.

[0153] Figure 17 is a circuit diagram showing a stage of a driver according to an embodiment.

[0154] Reference Figure 17 At least one stage 300 of the driver according to the embodiment may include an input circuit 310, a QB node control circuit 320, an output circuit 330, a QB node discharge circuit 340, a carry circuit 370, a reset circuit 380, a leakage prevention circuit 385 and a stabilization circuit 390. Figure 17 The level 300 can be used with Figure 3 The stage 200 has a similar configuration and similar operation, except that the stage 300 may not include Figure 3 The node separation circuit 250 and the boost circuit 260 shown in FIG; the QB node control circuit 320 may not include Figure 3 The seventh transistor T7 shown in FIG; the output circuit 330 and the carry circuit 370 may receive the second clock signal CLK2 instead of the high gate voltage VGH; the output circuit 330 may not include Figure 3 the second capacitor C2 shown in FIG; the carry circuit 370 may further include a fourth capacitor C4; and the stabilization circuit 390 may include a seventeenth transistor T17 and an eighteenth transistor T18.

[0155] Level 300 may not include Figure 3 The node separation circuit 250 shown in FIG, and the gate of the eighth transistor T8 'of the output circuit 330 and the gate of the twelfth transistor T12 'of the carry circuit 370 may be connected to the Q node Q. In addition, the stage 300 may not include Figure 3 , and the voltage of the Q node Q can be boosted using the second clock signal CLK2 and the fourth capacitor C4 of the carry circuit 370. For example, when the voltage of the Q node Q has a high level and the second clock signal CLK2 changes from a low level to a high level, the voltage of the Q node Q can be boosted from the high level to the boosted high level by the fourth capacitor C4.

[0156] The QB node control circuit 320 may provide the second low gate voltage VGL2 to the QB node QB when the voltage of the Q node Q has a high level, and may provide the QB control signal GBI to the QB node QB when the voltage of the Q node Q has a low level. The QB node control circuit 320 may not include Figure 3 Therefore, the QB node control circuit 320 may not receive the second clock signal CLK2.

[0157] The output circuit 330 may receive the second clock signal CLK2 instead of the high gate voltage VGH and may not include Figure 3 In some embodiments, the output circuit 330 may include an eighth transistor T8′ and a ninth transistor T9, wherein the eighth transistor T8′ includes a gate connected to the Q node Q, a first terminal receiving the second clock signal CLK2, and a second terminal connected to the output node NO at which the output signal OUT is output, and the ninth transistor T9 includes a gate connected to the QB node QB, a first terminal connected to the output node NO, and a second terminal connected to a line transmitting the low gate voltage VGL.

[0158] The carry circuit 370 may receive the second clock signal CLK2 instead of the high gate voltage VGH, and may include a fourth capacitor C4 for boosting the voltage of the Q node Q. In some embodiments, the carry circuit 370 may include a twelfth transistor T12′, a fourth capacitor C4, and a thirteenth transistor T13. The twelfth transistor T12′ includes a gate connected to the Q node Q, a first terminal receiving the second clock signal CLK2, and a second terminal connected to the carry node NC where the carry signal CR is output. The fourth capacitor C4 includes a first electrode connected to the Q node Q and a second electrode connected to the carry node NC. The thirteenth transistor T13 includes a gate connected to the QB node QB, a first terminal connected to the carry node NC, and a second terminal connected to a line transmitting the second low gate voltage VGL2.

[0159] The stabilization circuit 390 may include a seventeenth transistor T17 and an eighteenth transistor T18, and may provide the second low gate voltage VGL2 to the Q-node Q through the thirteenth transistor T13, the eighteenth transistor T18, and the seventeenth transistor T17 when the voltage of the QB node QB has a high level. In some embodiments, the seventeenth transistor T17 may include a gate receiving the second clock signal CLK2, a first terminal connected to the Q-node Q, and a second terminal, and the eighteenth transistor T18 may include a gate connected to the QB node QB, a first terminal connected to the second terminal of the seventeenth transistor T17, and a second terminal connected to the carry node NC.

[0160] It will be understood by those skilled in the art that any embodiment may be combined with any other embodiment. For example, in stage 300, the first transistor T1 may be as shown in FIG. Figure 11 2 is connected to the line transmitting the high gate voltage VGH instead of the line transmitting the QB control signal GBI as in the stage 200a shown in FIG. Figure 12 As in the stage 200b shown in FIG, some transistors may receive the second low gate voltage VGL2 instead of the reset signal SESR. Figure 14 The fourteenth transistor T14 may have a dual gate structure as in the stage 200d shown in FIG. Figure 15 The stage 200e shown in FIG may be connected to a line transmitting the second low gate voltage VGL2 instead of a line transmitting the low gate voltage VGL, or may be connected to a line transmitting the second low gate voltage VGL2 instead of a line transmitting the low gate voltage VGL as in FIG. Figure 16 As in the stage 200f shown in FIG, a high gate voltage VGH is used instead of the QB control signal GBI.

[0161] Figure 18 is a circuit diagram showing a stage of a driver according to an embodiment, and Figure 19 is a timing diagram illustrating an example of the QB control signal and the second QB control signal.

[0162] Reference Figure 18 According to the embodiment, at least one stage 400 of the driver may include an input circuit 210, a QB node control circuit (or a first QB node control circuit) 220, a second QB node control circuit 420, an output circuit 430, a QB node discharge circuit (or a first QB node discharge circuit) 240, a second QB node discharge circuit 440, a node separation circuit 250, a boost circuit 260, a carry circuit 470, a reset circuit 280, a leakage prevention circuit 285, a stabilization circuit (or a first stabilization circuit) 290 and a second stabilization circuit 490. Figure 18 The level 400 can be used with Figure 3 The stage 200 has a similar configuration and similar operation, except that: the stage 400 may also include a second QB node control circuit 420, a second QB node discharge circuit 440 and a second stabilization circuit 490 associated with the second QB node QB2; the output circuit 430 may also include a ninth-second transistor T9-2 that operates based on the voltage of the second QB node QB2; and the carry circuit 470 may also include a thirteenth-second transistor T13-2 that operates based on the voltage of the second QB node QB2.

[0163] The QB node control circuit 220 may control the voltage of the QB node QB based on the voltage of the first Q node Q1 and the QB control signal GBI, and the second QB node control circuit 420 may control the voltage of the second QB node QB2 based on the voltage of the first Q node Q1 and the second QB control signal GBI2. For example, the second QB node control circuit 420 may include a third-second transistor T3-2, a fourth-second transistor T4-2, a fifth-second transistor T5-2, a sixth-second transistor T6-2, a seventh-second transistor T7-2, and a first-second capacitor C1-2, which correspond to the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the first capacitor C1 of the QB node control circuit 220, respectively.

[0164] In some embodiments, as Figure 19 As shown in FIG, in the odd-numbered frame periods FP1 and FP3, the QB control signal GBI may have a high gate voltage VGH, and the second QB control signal GBI2 may have a second low gate voltage VGL2. Therefore, in the odd-numbered frame periods FP1 and FP3, the QB node control circuit 220 may control the voltage of the QB node QB to the high gate voltage VGH or the second low gate voltage VGL2 according to the voltage of the first Q node Q1 and / or the second clock signal CLK2, but the second QB node control circuit 420 may control the voltage of the second QB node QB2 to the second low gate voltage VGL2 regardless of the voltage of the first Q node Q1 and the second clock signal CLK2. In addition, in the even-numbered frame periods FP2 and FP4, the QB control signal GBI may have the second low gate voltage VGL2, and the second QB control signal GBI2 may have a high gate voltage VGH. Therefore, in the even frame periods FP2 and FP4, the second QB node control circuit 420 can control the voltage of the second QB node QB2 to the high gate voltage VGH or the second low gate voltage VGL2 according to the voltage of the first Q node Q1 and / or the second clock signal CLK2, but the QB node control circuit 220 can control the voltage of the QB node QB to the second low gate voltage VGL2 regardless of the voltage of the first Q node Q1 and the second clock signal CLK2.

[0165] Also refer to Figure 18The output circuit 430 can output an output signal OUT having a high gate voltage VGH when the voltage of the second Q node Q2 is at a boosted high level, and can output an output signal OUT having a low gate voltage VGL when the voltage of the QB node QB is at a high level or when the voltage of the second QB node QB2 is at a high level. To perform this operation, the output circuit 430 may include not only an eighth transistor T8, a second capacitor C2, and a ninth transistor T9 but also a ninth-second transistor T9-2, the ninth-second transistor T9-2 including a gate connected to the second QB node QB2, a first terminal connected to an output node at which the output signal OUT is output, and a second terminal connected to a line transmitting the low gate voltage VGL.

[0166] For example, Figure 19 As shown in FIG, in the odd frame periods FP1 and FP3, the QB node QB may have the high gate voltage VGH or the second low gate voltage VGL2, the second QB node QB2 may have the second low gate voltage VGL2, the ninth-second transistor T9-2 may be turned off, and the ninth transistor T9 may output the output signal OUT having the low gate voltage VGL when the voltage of the QB node QB has the high gate voltage VGH. In addition, in the even frame periods FP2 and FP4, the QB node QB may have the second low gate voltage VGL2, the second QB node QB2 may have the high gate voltage VGH or the second low gate voltage VGL2, the ninth transistor T9 may be turned off, and the ninth-second transistor T9-2 may output the output signal OUT having the low gate voltage VGL when the voltage of the second QB node QB2 has the high gate voltage VGH. Therefore, since the ninth-second transistor T9-2 is turned off in the odd frame periods FP1 and FP3 and the ninth transistor T9 is turned off in the even frame periods FP2 and FP4, degradation and / or threshold voltage shift of the ninth transistor T9 and the ninth-second transistor T9-2 can be reduced.

[0167] Also refer to Figure 18 The carry circuit 470 can output a carry signal CR having a high gate voltage VGH when the voltage of the second Q node Q2 has a boosted high level, and can output a carry signal CR having a second low gate voltage VGL2 when the voltage of the QB node QB has a high level or when the voltage of the second QB node QB2 has a high level. To perform this operation, the carry circuit 470 may include not only the twelfth transistor T12 and the thirteenth transistor T13 but also a thirteenth-second transistor T13-2, the thirteenth-second transistor T13-2 including a gate connected to the second QB node QB2, a first terminal connected to the carry node NC where the carry signal CR is output, and a second terminal connected to a line transmitting the second low gate voltage VGL2.

[0168] For example, Figure 19 As shown in FIG, in the odd frame periods FP1 and FP3, the QB node QB may have the high gate voltage VGH or the second low gate voltage VGL2, the second QB node QB2 may have the second low gate voltage VGL2, the thirteenth-second transistor T13-2 may be turned off, and the thirteenth transistor T13 may output the carry signal CR having the second low gate voltage VGL2 when the voltage of the QB node QB has the high gate voltage VGH. In addition, in the even frame periods FP2 and FP4, the QB node QB may have the second low gate voltage VGL2, the second QB node QB2 may have the high gate voltage VGH or the second low gate voltage VGL2, the thirteenth transistor T13 may be turned off, and the thirteenth-second transistor T13-2 may output the carry signal CR having the second low gate voltage VGL2 when the voltage of the second QB node QB2 has the high gate voltage VGH. Therefore, in stage 400, since the thirteenth-second transistor T13-2 is turned off in the odd frame periods FP1 and FP3 and the thirteenth transistor T13 is turned off in the even frame periods FP2 and FP4, degradation and / or threshold voltage shift of the thirteenth transistor T13 and the thirteenth-second transistor T13-2 can be reduced.

[0169] Also refer to Figure 18 The stabilization circuit 290 may provide the second low gate voltage VGL2 to the first Q node Q1 when the voltage of the QB node QB has a high level, and the second stabilization circuit 490 may provide the second low gate voltage VGL2 to the first Q node Q1 when the voltage of the second QB node QB2 has a high level. For example, the second stabilization circuit 490 may include a sixteenth-second transistor T16-2 corresponding to the sixteenth transistor T16.

[0170] Reference Figure 18 , also refer to Figure 10During a power-off period POFF in which the high gate voltage VGH and the low gate voltage VGL are disabled, the QB node discharge circuit 240 can discharge the QB node QB, and the second QB node discharge circuit 440 can discharge the second QB node QB2. In some embodiments, the QB node discharge circuit 240 may include a first transistor T1 for forming a path for a discharge current IDIS from the QB node QB to a line transmitting the QB control signal GBI in response to the reset signal SESR disabled at the ground voltage VGND, and the second QB node discharge circuit 440 may include first and second transistors T1-2 for forming a path for a discharge current IDIS from the second QB node QB2 to a line transmitting the second QB control signal GBI2 in response to the reset signal SESR disabled at the ground voltage VGND. Therefore, the QB node QB and the second QB node QB2 of the stage 400 can be discharged normally during the power-off period POFF.

[0171] Figure 20 is a circuit diagram showing a stage of a driver according to an embodiment.

[0172] Reference Figure 20 , also refer to Figure 10 At least one stage 400a of the driver according to the embodiment may include a first transistor T1a, a first-second transistor T1-2a, a second transistor T2, a third transistor T3, a third-second transistor T3-2, a fourth transistor T4, a fourth-second transistor T4-2, a fifth transistor T5, a fifth-second transistor T5-2, a sixth transistor T6, a sixth-second transistor T6-2, a seventh transistor T7, a seventh-second transistor T7-2, an eighth transistor T8, a ninth transistor T9, a ninth-second transistor T9-2, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a thirteenth-second transistor T13-2, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a sixteenth-second transistor T16-2, a first capacitor C1, a first-second capacitor C1-2, a second capacitor C2, and a third capacitor C3. Figure 20 The level 400a can be used with Figure 18 The stage 400 has a similar configuration and similar operation, except that: the QB node discharge circuit 240a can be connected to the line transmitting the high gate voltage VGH instead of the line transmitting the QB control signal GBI; and the second QB node discharge circuit 440a can be connected to the line transmitting the high gate voltage VGH instead of the line transmitting the second QB control signal GBI2.

[0173] During the power-off period POFF, the first transistor T1a of the QB node discharge circuit 240a can form a path for the discharge current IDIS from the QB node QB to the line transmitting the high gate voltage VGH in response to the reset signal SESR having the ground voltage VGND, and the first and second transistors T1-2a of the second QB node discharge circuit 440a can form a path for the discharge current IDIS from the second QB node QB2 to the line transmitting the high gate voltage VGH in response to the reset signal SESR having the ground voltage VGND. Therefore, the QB node QB and the second QB node QB2 of the stage 400a can be normally discharged during the power-off period POFF.

[0174] Figure 21 is a circuit diagram showing a stage of a driver according to an embodiment.

[0175] Reference Figure 21 , also refer to Figure 10 At least one stage 400b of the driver according to the embodiment may include a first transistor T1b, a first-second transistor T1-2b, a second transistor T2, a third transistor T3, a third-second transistor T3-2, a fourth transistor T4, a fourth-second transistor T4-2, a fifth transistor T5, a fifth-second transistor T5-2, a sixth transistor T6, a sixth-second transistor T6-2, a seventh transistor T7, a seventh-second transistor T7-2, an eighth transistor T8, a ninth transistor T9, a ninth-second transistor T9-2, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a thirteenth-second transistor T13-2, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a sixteenth-second transistor T16-2, a first capacitor C1, a first-second capacitor C1-2, a second capacitor C2, and a third capacitor C3. Figure 21 The level 400b can be used with Figure 18 The stage 400 has a similar configuration and a similar operation, except that the QB node discharge circuit 240 b and the second QB node discharge circuit 440 b may receive the second low gate voltage VGL2 instead of the reset signal SESR.

[0176] During the power-off period POFF, the first transistor T1b of the QB node discharge circuit 240b can form a path for the discharge current IDIS from the QB node QB to the line transmitting the QB control signal GBI in response to the second low gate voltage VGL2 disabled to the ground voltage VGND, and the first-second transistors T1-2b of the second QB node discharge circuit 440b can form a path for the discharge current IDIS from the second QB node QB2 to the line transmitting the second QB control signal GBI2 in response to the second low gate voltage VGL2 disabled to the ground voltage VGND. Therefore, the QB node QB and the second QB node QB2 of the stage 400b can be normally discharged during the power-off period POFF.

[0177] Figure 22 is a circuit diagram showing a stage of a driver according to an embodiment.

[0178] Reference Figure 22 , also refer to Figure 10 At least one stage 400c of the driver according to the embodiment may include a first transistor T1c, a first-second transistor T1-2c, a second transistor T2, a third transistor T3, a third-second transistor T3-2, a fourth transistor T4, a fourth-second transistor T4-2, a fifth transistor T5, a fifth-second transistor T5-2, a sixth transistor T6, a sixth-second transistor T6-2, a seventh transistor T7, a seventh-second transistor T7-2, an eighth transistor T8, a ninth transistor T9, a ninth-second transistor T9-2, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a thirteenth-second transistor T13-2, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a sixteenth-second transistor T16-2, a first capacitor C1, a first-second capacitor C1-2, a second capacitor C2, and a third capacitor C3. Figure 22 The Level 400c can be used with Figure 18 The stage 400 has a similar configuration and similar operation, except that: the QB node discharge circuit 240c can be connected to the line transmitting the high gate voltage VGH instead of the line transmitting the QB control signal GBI; the second QB node discharge circuit 440c can be connected to the line transmitting the high gate voltage VGH instead of the line transmitting the second QB control signal GBI2; and the QB node discharge circuit 240c and the second QB node discharge circuit 440c can receive the second low gate voltage VGL2 instead of the reset signal SESR.

[0179] During the power-off period POFF, the first transistor T1c of the QB node discharge circuit 240c can form a path for the discharge current IDIS from the QB node QB to the line transmitting the high gate voltage VGH in response to the second low gate voltage VGL2 disabled as the ground voltage VGND, and the first-second transistors T1-2c of the second QB node discharge circuit 440c can form a path for the discharge current IDIS from the second QB node QB2 to the line transmitting the high gate voltage VGH in response to the second low gate voltage VGL2 disabled as the ground voltage VGND. Therefore, the QB node QB and the second QB node QB2 of the stage 400c can be normally discharged during the power-off period POFF.

[0180] Figure 23 is a circuit diagram showing a stage of a driver according to an embodiment.

[0181] Reference Figure 23 , at least one stage 500 of the driver according to the embodiment may include an input circuit 310, a QB node control circuit (or a first QB node control circuit) 320, a second QB node control circuit 520, an output circuit 530, a QB node discharge circuit (or a first QB node discharge circuit 340), a second QB node discharge circuit 540, a carry circuit 570, a reset circuit 380, a leakage prevention circuit 385 and a stabilization circuit 590. Figure 23 The Level 500 can be used with Figure 17 The stage 300 has a similar configuration and similar operation, except that: the stage 500 may also include a second QB node control circuit 520 and a second QB node discharge circuit 540 associated with the second QB node QB2; the output circuit 530 may also include a ninth-second transistor T9-2 operated based on the voltage of the second QB node QB2; the carry circuit 570 may also include a thirteenth-second transistor T13-2 operated based on the voltage of the second QB node QB2; and the stabilization circuit 590 may also include an eighteenth-second transistor T18-2 operated based on the voltage of the second QB node QB2.

[0182] The QB node control circuit 320 may control the voltage of the QB node QB based on the voltage of the Q node Q and the QB control signal GBI, and the second QB node control circuit 520 may control the voltage of the second QB node QB2 based on the voltage of the Q node Q and the second QB control signal GBI2. For example, the second QB node control circuit 520 may include a third-second transistor T3-2, a fourth-second transistor T4-2, a fifth-second transistor T5-2, a sixth-second transistor T6-2, and a first-second capacitor C1-2, which correspond to the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the first capacitor C1 of the QB node control circuit 320, respectively.

[0183] The output circuit 530 can output an output signal OUT having a high gate voltage VGH when the voltage of the Q node Q is at a high level (or a boosted high level), and can output an output signal OUT having a low gate voltage VGL when the voltage of the QB node QB is at a high level or when the voltage of the second QB node QB2 is at a high level. To perform this operation, the output circuit 530 can include not only the eighth transistor T8' and the ninth transistor T9 but also a ninth-second transistor T9-2, which includes a gate connected to the second QB node QB2. Therefore, degradation and / or threshold voltage shift of the ninth transistor T9 and the ninth-second transistor T9-2 can be reduced.

[0184] The carry circuit 570 can output a carry signal CR having a high gate voltage VGH when the voltage of the Q node Q has a high level (or a boosted high level), and can output a carry signal CR having a second low gate voltage VGL2 when the voltage of the QB node QB has a high level or when the voltage of the second QB node QB2 has a high level. To perform this operation, the carry circuit 570 can include not only the twelfth transistor T12', the fourth capacitor C4, and the thirteenth transistor T13 but also the thirteenth-second transistor T13-2, which includes a gate connected to the second QB node QB2. Therefore, degradation and / or threshold voltage shift of the thirteenth transistor T13 and the thirteenth-second transistor T13-2 can be reduced.

[0185] The stabilization circuit 590 may provide the second low gate voltage VGL2 to the Q node Q when the voltage of the QB node QB is high or when the voltage of the second QB node QB2 is high. The stabilization circuit 590 may include not only the seventeenth transistor T17 and the eighteenth transistor T18 but also the eighteenth-second transistor T18-2, the eighteenth-second transistor T18-2 including a gate connected to the second QB node QB2. For example, the stabilization circuit 590 may provide the second low gate voltage VGL2 to the Q node Q through the thirteenth transistor T13, the eighteenth transistor T18, and the seventeenth transistor T17 when the voltage of the QB node QB is high, and may provide the second low gate voltage VGL2 to the Q node Q through the thirteenth-second transistor T13-2, the eighteenth-second transistor T18-2, and the seventeenth transistor T17 when the voltage of the second QB node QB2 is high.

[0186] Reference Figure 23 , also refer to Figure 10During a power-off period POFF in which the high gate voltage VGH and the low gate voltage VGL are disabled, the QB node discharge circuit 340 can discharge the QB node QB, and the second QB node discharge circuit 540 can discharge the second QB node QB2. In some embodiments, the QB node discharge circuit 340 may include a first transistor T1 for forming a path for a discharge current IDIS from the QB node QB to a line transmitting the QB control signal GBI in response to the reset signal SESR disabled to the ground voltage VGND, and the second QB node discharge circuit 540 may include first and second transistors T1-2 for forming a path for a discharge current IDIS from the second QB node QB2 to a line transmitting the second QB control signal GBI2 in response to the reset signal SESR disabled to the ground voltage VGND. Therefore, the QB node QB and the second QB node QB2 of the stage 500 can be discharged normally during the power-off period POFF.

[0187] Figure 24 is a circuit diagram illustrating a display panel including a stage of pixels and a driver according to an embodiment.

[0188] Reference Figure 24 , the display panel 600 according to the embodiment may include a plurality of pixels PX in the display region DR, and may include a plurality of stages STG of a driver in the peripheral region PR adjacent to the display region DR.

[0189] Each pixel PX may include: a first pixel transistor PXT1 including a gate connected to a first node N1, a first terminal connected to a line transmitting a first power voltage ELVDD (e.g., a high power voltage), and a second terminal connected to a second node N2; a storage capacitor CST connected between the first node N1 and the second node N2; a second pixel transistor PXT2 including a gate receiving a write signal GW, a first terminal connected to a data line DL, and a second terminal connected to the first node N1; a third pixel transistor PXT3 including a gate receiving a reference signal GR, a first terminal receiving a reference voltage VREF, and a second terminal connected to the first node N1; a fourth pixel transistor PXT4 including a gate receiving an initialization signal GI, a first terminal connected to an anode of the light emitting element EL, and a second terminal receiving an initialization voltage VINT; and a light emitting element EL including an anode and a cathode connected to a line transmitting a second power voltage ELVSS (e.g., a low power voltage). Although Figure 24 An example is shown in which the pixel PX has a 4T1C structure (four transistors and one capacitor), but the pixel PX of the display panel 600 according to the embodiment is not limited to Figure 24 .

[0190] Each stage STG may include: a first transistor T1 including a gate receiving a reset signal SESR, a first terminal connected to a line transmitting a QB control signal GBI, and a second terminal connected to a QB node QB; a second transistor T2 including a gate receiving a first clock signal CLK1, a first terminal receiving an input signal SIN, and a second terminal connected to a Q-node Q; a third transistor T3 including a gate receiving a QB control signal GBI, a first terminal receiving the QB control signal GBI, and a second terminal; a fourth transistor T4 including a gate connected to the second terminal of the third transistor T3, a first terminal receiving the QB control signal GBI, and a second terminal connected to the QB node QB; a first capacitor C1 including a first electrode connected to the gate of the fourth transistor T4 and a second electrode connected to the QB node QB; a fifth transistor T5 including a gate connected to the Q-node Q, a first terminal connected to the gate of the fourth transistor T4, and a second terminal connected to the transmission line. The first terminal of the line transmitting the low gate voltage VGL is connected to the first clock signal CLK1; the second terminal of the line transmitting the low gate voltage VGL is connected to the first clock signal CLK1; the sixth transistor T6 includes a gate connected to the Q node Q, a first terminal connected to the QB node QB, and a second terminal connected to the line transmitting a second low gate voltage VGL2 lower than the low gate voltage VGL; the seventh transistor T7 includes a gate receiving a second clock signal CLK2 different from the first clock signal CLK1, a first terminal connected to the second terminal of the fourth transistor T4, and a second terminal connected to the QB node QB; the eighth transistor T8 includes a gate connected to the Q node Q, a first terminal connected to the line transmitting the high gate voltage VGH, and a second terminal connected to the output node at which the output signal OUT is output; the second capacitor C2 includes a first electrode connected to the Q node Q and a second electrode connected to the output node; and the ninth transistor T9 includes a gate connected to the QB node QB, a first terminal connected to the output node, and a second terminal connected to the line transmitting the low gate voltage VGL. The stage STG can output the write signal GW, the reference signal GR, or the initialization signal GI as the output signal OUT. For example, the output signal OUT can be the write signal GW, and the output node of the stage STG can be connected to the gate of the second pixel transistor PXT2 of the pixel PX via a gate line. In another example, the output signal OUT may be the reference signal GR, and the output node of the stage STG may be connected to the gate of the third pixel transistor PXT3 of the pixel PX through a gate line. In yet another example, the output signal OUT may be the initialization signal GI, and the output node of the stage STG may be connected to the gate of the fourth pixel transistor PXT4 of the pixel PX through a gate line. Figure 24 An example is shown in which the stage STG has a 9T2C structure (nine transistors and two capacitors), but the stage STG of the driver formed in the display panel 600 according to the embodiment is not limited to Figure 24For example, the STG level can be Figure 3 Level 200, Figure 11 Level 200a, Figure 12 Level 200b, Figure 13 Level 200c, Figure 14 Level 200d, Figure 15 Level 200e, Figure 16 Level 200f, Figure 17 Level 300, Figure 18 Level 400, Figure 20 Level 400a, Figure 21 Level 400b, Figure 22 Level 400c, Figure 23 The stage 500 or a stage having a similar configuration.

[0191] Figure 25 is a block diagram showing a display device according to an embodiment, Figure 26 is a circuit diagram showing an example of a pixel included in a display device according to an embodiment, Figure 27 is a timing diagram showing an example of a power-off sequence of a display device according to an embodiment, and Figure 28 is a timing chart showing an example of a power-on sequence of the display device according to the embodiment.

[0192] Reference Figure 25 According to an embodiment, the display device 1000 may include: a display panel 1010, the display panel 1010 includes a plurality of pixels PX; a data driver 1030, the data driver 1030 provides a data signal DS to the plurality of pixels PX; a gate driver 1050, the gate driver 1050 provides a gate signal GS to the plurality of pixels PX; an emission driver 1070, the emission driver 1070 provides an emission signal EM to the plurality of pixels PX; a power management circuit 1080, the power management circuit 1080 provides a high gate voltage VGH, a low gate voltage VGL and a second low gate voltage VGL2 to the gate driver 1050 and / or the emission driver 1070; and a controller 1090, the controller 1090 controls the data driver 1030, the gate driver 1050, the emission driver 1070 and the power management circuit 1080.

[0193] The display panel 1010 may include data lines, gate lines, emission lines, and a plurality of pixels PX connected to the data lines, gate lines, and emission lines. In some embodiments, each pixel PX may include a light emitting element, and the display panel 1010 may be a light emitting display panel.

[0194] For example, Figure 26As shown in , each pixel PX may include: a first pixel transistor PXT1, including a gate connected to a first node N1, a first terminal connected to a line transmitting a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second terminal connected to a second node N2; a storage capacitor CST, connected between the first node N1 and the second node N2; a second pixel transistor PXT2, including a gate receiving a write signal GW, a first terminal connected to a data line DL, and a second terminal connected to the first node N1; a third pixel transistor PXT3, including a gate receiving a reference signal GR, a first terminal receiving a reference voltage VREF, and a second terminal connected to the first node N1; a fourth pixel transistor PXT4, including a gate receiving an initialization signal GI, a first terminal connected to an anode of the light emitting element EL, and a second terminal receiving an initialization voltage VINT; and a light emitting element EL, including an anode and a cathode connected to a line transmitting a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0195] In some embodiments, each pixel PX may further include: a fifth pixel transistor PXT5 connected between a line transmitting a first power supply voltage ELVDD and the first pixel transistor PXT1; a sixth pixel transistor PXT6 connected between a second node N2 and the anode of the light-emitting element EL; and a holding capacitor CHOLD connected between the line transmitting the first power supply voltage ELVDD and the second node N2. For example, the fifth pixel transistor PXT5 may include a gate receiving the first emission signal EM1, a first terminal connected to the line transmitting the first power supply voltage ELVDD, and a second terminal connected to the first terminal of the first pixel transistor PXT1; the sixth pixel transistor PXT6 may include a gate receiving the second emission signal EM2, a first terminal connected to the second node N2, and a second terminal connected to the anode of the light-emitting element EL; and the holding capacitor CHOLD may include a first electrode connected to the line transmitting the first power supply voltage ELVDD and a second electrode connected to the second node N2. In addition, in some embodiments, the first pixel transistor PXT1 may further include a bottom gate connected to the second node N2.

[0196] In some embodiments, the light emitting element EL may be an organic light emitting diode (OLED). In other embodiments, the light emitting element EL may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element.

[0197] although Figure 26 An example is shown in which the pixel PX has a 6T2C structure (six transistors and two capacitors), but the pixel PX of the display device 1000 according to the embodiment is not limited to Figure 26.

[0198] Also refer to Figure 25 The data driver 1030 can generate a data signal DS based on the data control signal DCTRL and the output image data ODAT received from the controller 1090, and can provide the data signal DS to the plurality of pixels PX via the data line. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some embodiments, the data driver 1030 and the controller 1090 can be implemented as a single integrated circuit, and the single integrated circuit can be referred to as a timing controller embedded data driver (TED) integrated circuit. In other embodiments, the data driver 1030 and the controller 1090 can be implemented as separate integrated circuits.

[0199] The gate driver 1050 may generate a gate signal GS based on a gate control signal GCTRL received from the controller 1090 and may sequentially provide the gate signal GS to a plurality of pixels PX through the gate lines on a row-by-row basis. In some embodiments, the gate control signal GCTRL may include, but is not limited to, Figure 18 , a start signal FLM (e.g., a write start signal, a reference start signal, and an initialization start signal), a first clock signal CLK1 (e.g., a first write clock signal, a first reference clock signal, and a first initialization clock signal), a second clock signal CLK2 (e.g., a second write clock signal, a second reference clock signal, and a second initialization clock signal), a reset signal SESR, a QB control signal GBI, and a second QB control signal GBI2. In addition, in some embodiments, the gate signal GS provided to each pixel PX may include, but is not limited to, a write signal GW, a reference signal GR, and an initialization signal GI. According to an embodiment, the gate driver 1050 may include a plurality of stages, and each stage may be Figure 3 Level 200, Figure 11 Level 200a, Figure 12 Level 200b, Figure 13 Level 200c, Figure 14 Level 200d, Figure 15 Level 200e, Figure 16 Level 200f, Figure 17 Level 300, Figure 18 Level 400, Figure 20 Level 400a, Figure 21 Level 400b, Figure 22 Level 400c, Figure 23 In some embodiments, as Figure 25As shown in FIG, the gate driver 1050 may be integrated or formed in the display panel 1010. In other embodiments, the gate driver 1050 may be implemented as one or more integrated circuits.

[0200] The emission driver 1070 may generate an emission signal EM based on the emission control signal ECTRL received from the controller 1090 and may sequentially provide the emission signal EM to the plurality of pixels PX through the emission lines on a row-by-row basis. In some embodiments, the emission control signal ECTRL may include, but is not limited to: Figure 18 , the start signal FLM (e.g., emission start signal), the first clock signal CLK1 (e.g., first emission clock signal), the second clock signal CLK2 (e.g., second emission clock signal), the reset signal SESR, the QB control signal GBI, and the second QB control signal GBI2. In addition, in some embodiments, the emission signal EM provided to each pixel PX may include but is not limited to Figure 26 According to an embodiment, the emission driver 1070 may include a plurality of stages, and each stage may be Figure 3 Level 200, Figure 11 Level 200a, Figure 12 Level 200b, Figure 13 Level 200c, Figure 14 Level 200d, Figure 15 Level 200e, Figure 16 Level 200f, Figure 17 Level 300, Figure 18 Level 400, Figure 20 Level 400a, Figure 21 Level 400b, Figure 22 Level 400c, Figure 23 In some embodiments, as Figure 25 As shown in FIG, the emission driver 1070 may be integrated or formed in the display panel 1010. In other embodiments, the emission driver 1070 may be implemented as one or more integrated circuits.

[0201] The power management circuit 1080 can provide voltages for the operation of the display device 1000. In some embodiments, the power management circuit 1080 can provide a high gate voltage VGH, a low gate voltage VGL, and a second low gate voltage VGL2 to the gate driver 1050 and / or the emission driver 1070, and can provide a first power supply voltage ELVDD, a second power supply voltage ELVSS, a reference voltage VREF, and an initialization voltage VINT to a plurality of pixels PX of the display panel 1010. In some embodiments, the power management circuit 1080 can be implemented as an integrated circuit (which can be referred to as a power management integrated circuit (PMIC)). In other embodiments, the power management circuit 1080 can be included in the controller 1090 or the data driver 1030.

[0202] The controller 1090 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. The control signal CTRL may include a power-on signal SON indicating that the display device 1000 is powered on, and a power-off signal SOFF indicating that the display device 1000 is powered off. In some embodiments, the control signal CTRL may also include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a main clock signal. The controller 1090 may generate output image data ODAT, a data control signal DCTRL, a gate control signal GCTRL, and an emission control signal ECTRL based on the input image data IDAT and the control signal CTRL. The controller 1090 may control the operation of the data driver 1030 by providing the output image data ODAT and the data control signal DCTRL to the data driver 1030 , may control the operation of the gate driver 1050 by providing the gate control signal GCTRL to the gate driver 1050 , and may control the operation of the emission driver 1070 by providing the emission control signal ECTRL to the emission driver 1070 .

[0203] The display device 1000 according to the embodiment may perform a power-off sequence in response to the power-off signal SOFF. Figure 27As shown in FIG, in at least one first frame period FP1-1 and FP1-2 after receiving the power-off signal SOFF, the data driver 1030 may provide a black data voltage BDV corresponding to the lowest grayscale (e.g., grayscale 0) instead of the data voltage DV corresponding to the input image data IDAT (or output image data ODAT) as the data signal DS to the plurality of pixels PX. In addition, the power management circuit 1080 may disable the first power supply voltage ELVDD and the second power supply voltage ELVSS to the ground voltage VGND. Therefore, the plurality of pixels PX may not emit light.

[0204] Reference Figure 25 and Figure 27 , also refer to Figure 24 In at least one second frame period FP2-1 and FP2-2 following the first frame periods FP1-1 and FP1-2, the reference voltage VREF, the reset signal SESR, and the data signal DS may be disabled to the ground voltage VGND. The write start signal GW_FLM, the reference start signal GR_FLM, the initialization start signal GI_FLM, and the emission start signal EM_FLM may be maintained at the second low gate voltage VGL2. The first and second write clock signals GW_CLK, the first and second reference clock signals GR_CLK, the first and second initialization clock signals GI_CLK, the first and second emission clock signals EM_CLK, the QB control signals GBI and the second QB control signal GBI2 may be maintained at the high gate voltage VGH. Therefore, the Q node Q of the stage STG of the gate driver 1050 and / or the emission driver 1070 may be reset to the second low gate voltage VGL2, and the QB node QB of the stage STG may be reset to the high gate voltage VGH.

[0205] In the power-off period POFF after the second frame periods FP2-1 and FP2-2, the high gate voltage VGH, the low gate voltage VGL, the second low gate voltage VGL2, the initialization voltage VINT, the write start signal GW_FLM, the reference start signal GR_FLM, the initialization start signal GI_FLM, the emission start signal EM_FLM, the first and second write clock signals GW_CLK, the first and second reference clock signals GR_CLK, the first and second initialization clock signals GI_CLK, the first and second emission clock signals EM_CLK, the QB control signal GBI and the second QB control signal GBI2 may be disabled to the ground voltage VGND. In addition, the QB node QB of the stage STG of the gate driver 1050 and / or the emission driver 1070 may be discharged to the ground voltage VGND through the QB node discharge circuit of each stage STG.

[0206] In addition, the display device 1000 according to the embodiment may perform a power-on sequence in response to the power-on signal SON. Figure 28 As shown in, also refer to Figure 24 In at least one third frame period FP3-1 and FP3-2 after receiving the power-on signal SON, the high gate voltage VGH, the low gate voltage VGL, and the second low gate voltage VGL2 may be activated, and the reset signal SESR may have the high gate voltage VGH. Consequently, the Q node Q of the stage STG of the gate driver 1050 and / or the emission driver 1070 may be reset to the low gate voltage VGL (or the second low gate voltage VGL2), and the QB node QB of the stage STG may be reset to the high gate voltage VGH. Furthermore, the write start signal GW_FLM, the reference start signal GR_FLM, the initialization start signal GI_FLM, and the emission start signal EM_FLM may be maintained at the second low gate voltage VGL2. Furthermore, the first and second write clock signals GW_CLK, the first and second reference clock signals GR_CLK, the first and second initialization clock signals GI_CLK, the first and second emission clock signals EM_CLK, the QB control signal GBI and the second QB control signal GBI2 may be maintained at the high gate voltage VGH. Furthermore, the initialization voltage VINT and the reference voltage VREF may be activated.

[0207] In at least one fourth frame period FP4-1, FP4-2, FP4-3, and FP4-4 after the third frame periods FP3-1 and FP3-2, the reset signal SESR may be changed to the second low gate voltage VGL2, the write start signal GW_FLM, the reference start signal GR_FLM, the initialization start signal GI_FLM, and the emission start signal EM_FLM may be maintained at the second low gate voltage VGL2, but the first and second write clock signals GW_CLK, the first and second reference clock signals GR_CLK, the first and second initialization clock signals GI_CLK, and the first and second emission clock signals EM_CLK may be periodically switched. For example, in the fourth frame period FP4-2, the first and second emission clock signals EM_CLK may begin to periodically switch, and the emission driver 1070 may output the emission signal EM having the low gate voltage VGL. In the fourth frame period FP4-3, the first and second reference clock signals GR_CLK and the first and second initialization clock signals GI_CLK may start to periodically switch, and the gate driver 1050 may output the reference signal GR having the low gate voltage VGL and the initialization signal GI having the low gate voltage VGL. In the fourth frame period FP4-4, the first and second write clock signals GW_CLK may start to periodically switch, and the gate driver 1050 may output the write signal GW having the low gate voltage VGL.

[0208] In at least one fifth frame period FP5-1 and FP5-2 after the fourth frame periods FP4-1, FP4-2, FP4-3, and FP4-4, a write start signal GW_FLM, a reference start signal GR_FLM, an initialization start signal GI_FLM, and an emission start signal EM_FLM having a high gate voltage VGH may be provided, the first and second write clock signals GW_CLK, the first and second reference clock signals GR_CLK, the first and second initialization clock signals GI_CLK, and the first and second emission clock signals EM_CLK may be periodically switched, and the QB control signal GBI and the second QB control signal GBI2 may alternately have a high gate voltage VGH or a second low gate voltage VGL2. Thus, the gate driver 1050 and the emission driver 1070 may perform normal operations. In addition, the first power supply voltage ELVDD and the second power supply voltage ELVSS may be activated. However, the data driver 1030 may provide a black data voltage BDV as the data signal DS to the plurality of pixels PX, and the plurality of pixels PX may display a black image or may not emit light. After the fifth frame periods FP5 - 1 and FP5 - 2 , the display apparatus 1000 may perform a normal operation of displaying an image corresponding to the input image data IDAT.

[0209] As described above, in the display device 1000 according to the embodiment, at least one stage STG of the gate driver 1050 and / or the emission driver 1070 may include a QB node discharge circuit for discharging the QB node QB during the power-off period POFF. Therefore, the QB node QB of the stage STG of the gate driver 1050 and / or the emission driver 1070 may be normally discharged during the power-off period POFF.

[0210] Figure 29 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0211] Reference Figure 29 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0212] The processor 1110 can perform various computing functions or tasks. The processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 can be connected to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the processor 1110 can also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0213] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0214] The storage device 1130 may be a solid-state drive (SSD), a hard disk drive (HDD), a compact disc read-only memory (CD-ROM), etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be connected to other components via a bus or other communication link.

[0215] In the display device 1160, at least one stage of a driver (e.g., a gate driver and / or an emission driver) may include a QB node discharge circuit that discharges the QB node when the high gate voltage and the low gate voltage are disabled. Thus, the internal node or QB node of the driver stage may be discharged normally during a power-off period.

[0216] The present invention can be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, the present invention can be applied to smartphones, wearable electronic devices, mobile phones, televisions (TVs) (e.g., digital TVs, 3D TVs, etc.), personal computers (PCs) (e.g., tablet computers, laptop computers), home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0217] The foregoing is illustrative of embodiments and should not be construed as limiting thereof. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A drive, wherein: The driver comprises a plurality of stages, at least one of the plurality of stages comprising: an input circuit configured to transmit an input signal to a Q node in response to a first clock signal, wherein the Q node includes a first Q node and a second Q node; a first QB node control circuit configured to control a voltage of the first QB node based on a voltage of the first Q node and a first QB control signal; an output circuit configured to output an output signal having a high gate voltage based on the voltage of the second Q node, and the output circuit configured to output the output signal having a first low gate voltage based on the voltage of the first QB node; and A first QB node discharge circuit is configured to discharge the first QB node when the high gate voltage and the first low gate voltage are disabled.

2. The driver according to claim 1, wherein When a display device including the driver is powered off, the high gate voltage and the first low gate voltage are disabled to a ground voltage, and the first QB node discharge circuit discharges the first QB node to the ground voltage.

3. The driver according to claim 1, wherein The at least one stage further comprises: a reset circuit configured to reset the first Q node in response to a reset signal, and Wherein, the first QB node discharge circuit includes: The first transistor includes a gate receiving the reset signal, a first terminal connected to a line transmitting the first QB control signal, and a second terminal connected to the first QB node.

4. The driver according to claim 1, wherein The at least one stage further comprises: a reset circuit configured to reset the first Q node in response to a reset signal, and Wherein, the first QB node discharge circuit includes: The first transistor includes a gate receiving the reset signal, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to the first QB node.

5. The driver according to claim 1, wherein The first QB node discharge circuit includes: A first transistor includes a gate connected to a line transmitting a second low gate voltage lower than the first low gate voltage, a first terminal connected to a line transmitting the first QB control signal, and a second terminal connected to the first QB node. The driver according to claim 1 , wherein: The first QB node discharge circuit includes: A first transistor includes a gate connected to a line transmitting a second low gate voltage lower than the first low gate voltage, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to the first QB node.

7. The driver according to claim 1, wherein: The input circuit comprises: The second transistor includes a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal connected to the first Q node.

8. The driver according to claim 1, wherein The first QB node control circuit includes: a third transistor comprising a gate receiving the first QB control signal, a first terminal receiving the first QB control signal, and a second terminal; a fourth transistor comprising a gate connected to the second terminal of the third transistor, a first terminal receiving the first QB control signal, and a second terminal; a first capacitor including a first electrode connected to the gate of the fourth transistor and a second electrode connected to the first QB node; a fifth transistor including a gate connected to the first Q-node, a first terminal connected to the gate of the fourth transistor, and a second terminal connected to a line transmitting the first low gate voltage; a sixth transistor including a gate connected to the first Q node, a first terminal connected to the first QB node, and a second terminal connected to a line transmitting a second low gate voltage lower than the first low gate voltage; and A seventh transistor includes a gate receiving a second clock signal different from the first clock signal, a first terminal connected to the second terminal of the fourth transistor, and a second terminal connected to the first QB node.

9. The driver according to claim 1, wherein The output circuit includes: an eighth transistor including a gate connected to the second Q node, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to an output node at which the output signal is output; a second capacitor including a first electrode connected to the second Q-node and a second electrode connected to the output node; and A ninth transistor includes a gate connected to the first QB node, a first terminal connected to the output node, and a second terminal connected to a line transmitting the first low gate voltage.

10. The driver according to claim 1, wherein The at least one stage further comprises: a node separation circuit provided at the Q node, wherein the node separation circuit is configured to separate the Q node into the first Q node and the second Q node, and Wherein, the node separation circuit includes: A tenth transistor includes a gate connected to a line transmitting the high gate voltage, a first terminal connected to the first Q-node, and a second terminal connected to the second Q-node.

11. The driver according to claim 10, wherein: The at least one stage further comprises: a boost circuit configured to boost the voltage of the second Q node in response to a second clock signal different from the first clock signal, and Wherein, the boost circuit comprises: an eleventh transistor including a gate connected to the second Q-node, a first terminal receiving the second clock signal, and a second terminal; and A third capacitor includes a first electrode connected to the second Q-node and a second electrode connected to the second terminal of the eleventh transistor.

12. The driver according to claim 1, wherein The at least one stage further comprises: a carry circuit configured to output a carry signal having the high gate voltage based on the voltage of the second Q node and to output the carry signal having a second low gate voltage lower than the first low gate voltage based on the voltage of the first QB node, and Wherein, the carry circuit includes: a twelfth transistor including a gate connected to the second Q node, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to a carry node at which the carry signal is output; and A thirteenth transistor includes a gate connected to the first QB node, a first terminal connected to the carry node, and a second terminal connected to a line transmitting the second low gate voltage.

13. The driver according to claim 1, wherein The at least one stage further comprises: a reset circuit configured to provide the first low gate voltage to the first Q node in response to a reset signal, and Wherein, the reset circuit includes: The fourteenth transistor includes a gate receiving the reset signal, a first terminal connected to the first Q node, and a second terminal connected to a line transmitting the first low gate voltage.

14. The driver according to claim 1, wherein The second transistor included in the input circuit includes a first sub-transistor and a second sub-transistor connected in series, Wherein, the at least one stage further comprises: a leakage prevention circuit configured to provide the high gate voltage to a node between the first sub-transistor and the second sub-transistor in response to the voltage of the first Q-node, and Wherein, the leakage prevention circuit includes: A fifteenth transistor includes a gate connected to the first Q node, a first terminal connected to a line transmitting the high gate voltage, and a second terminal connected to the node between the first sub-transistor and the second sub-transistor.

15. The driver according to claim 1, wherein The at least one stage further comprises: a first stabilization circuit configured to provide a second low gate voltage lower than the first low gate voltage to the first Q node when the voltage of the first QB node has a high level, and Wherein, the first stabilization circuit includes: A sixteenth transistor includes a gate connected to the first QB node, a first terminal connected to the first Q node, and a second terminal connected to a line transmitting the second low gate voltage.

16. The driver according to claim 1, wherein The at least one stage further comprises: a second QB node control circuit configured to control a voltage of a second QB node based on the voltage of the first Q node and a second QB control signal; and a second QB node discharge circuit configured to discharge the second QB node when the high gate voltage and the first low gate voltage are disabled, and The output circuit outputs the output signal having the first low gate voltage when the voltage of the first QB node has a high level or when the voltage of the second QB node has a high level.

17. The driver according to claim 16, wherein The at least one stage further comprises: a first stabilization circuit configured to provide a second low gate voltage, which is lower than the first low gate voltage, to the first Q node when the voltage of the first QB node has a high level; and A second stabilization circuit is configured to provide the second low gate voltage to the first Q node when the voltage of the second QB node has a high level.

18. A display panel, wherein: The display panel is included in a display device, and the display panel includes: a first pixel transistor including a gate connected to a first node, a first terminal connected to a line transmitting a first power supply voltage, and a second terminal connected to a second node; a storage capacitor connected between the first node and the second node; a second pixel transistor including a gate receiving a write signal, a first terminal connected to the data line, and a second terminal connected to the first node; a third pixel transistor including a gate receiving a reference signal, a first terminal receiving a reference voltage, and a second terminal connected to the first node; a fourth pixel transistor including a gate receiving an initialization signal, a first terminal connected to an anode of the light emitting element, and a second terminal receiving an initialization voltage; a light emitting element including the anode and a cathode connected to a line transmitting a second power supply voltage; a first transistor including a gate receiving a reset signal, a first terminal connected to a line transmitting a QB control signal, and a second terminal connected to a QB node; a second transistor including a gate receiving the first clock signal, a first terminal receiving an input signal, and a second terminal connected to the Q node; a third transistor comprising a gate receiving the QB control signal, a first terminal receiving the QB control signal, and a second terminal; a fourth transistor comprising a gate connected to the second terminal of the third transistor, a first terminal receiving the QB control signal, and a second terminal; a first capacitor including a first electrode connected to the gate of the fourth transistor and a second electrode connected to the QB node; a fifth transistor including a gate connected to the Q node, a first terminal connected to the gate of the fourth transistor, and a second terminal connected to a line transmitting a first low gate voltage; a sixth transistor including a gate connected to the Q node, a first terminal connected to the QB node, and a second terminal connected to a line transmitting a second low gate voltage lower than the first low gate voltage; a seventh transistor including a gate receiving a second clock signal different from the first clock signal, a first terminal connected to the second terminal of the fourth transistor, and a second terminal connected to the QB node; an eighth transistor including a gate connected to the Q node, a first terminal connected to a line transmitting a high gate voltage, and a second terminal connected to an output node at which an output signal is output; a second capacitor including a first electrode connected to the Q node and a second electrode connected to the output node; and a ninth transistor including a gate connected to the QB node, a first terminal connected to the output node, and a second terminal connected to the line transmitting the first low gate voltage, The output signal is the write signal, the reference signal or the initialization signal.

19. A display device, wherein: The display device includes: a display panel comprising a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; an emission driver configured to provide emission signals to the plurality of pixels; a power management circuit configured to provide a high gate voltage, a first low gate voltage, and a second low gate voltage to at least one of the gate driver and the emission driver; and a controller configured to control the data driver, the gate driver, the emission driver, and the power management circuit, Wherein, the controller receives a power-off signal, wherein, in at least one first frame period after receiving the power-off signal, a black data voltage is provided to the plurality of pixels as the data signal, wherein, in at least one second frame period after the first frame period, the start signal provided to the at least one driver is maintained at the second low gate voltage, the first clock signal and the second clock signal and the QB control signal are maintained at the high gate voltage, and the reset signal provided to the at least one driver is disabled and is the ground voltage, and wherein, in a power-off period following the second frame period, the high gate voltage, the first low gate voltage, the second low gate voltage, the start signal, the first clock signal, the second clock signal, and the QB control signal are disabled to the ground voltage, and the stage of the at least one driver discharges the QB node through a path from the QB node of the stage to the line transmitting the QB control signal in response to the reset signal.

20. A display device, wherein: The display device includes: a display panel comprising a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; an emission driver configured to provide emission signals to the plurality of pixels; and a controller configured to control the data driver, the gate driver, and the emission driver, Wherein, at least one of the gate driver and the emission driver includes a plurality of stages, and at least one of the plurality of stages includes: an input circuit configured to transmit an input signal to the Q node in response to a first clock signal; A QB node control circuit configured to control the voltage of the QB node based on the voltage of the Q node and a QB control signal; an output circuit configured to output an output signal having a high gate voltage based on the voltage of the Q node, and configured to output the output signal having a low gate voltage based on the voltage of the QB node; and A QB node discharge circuit is configured to discharge the QB node when the high gate voltage and the low gate voltage are disabled.

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