Display system, display data transmission method, and serial-to-parallel converter

Abstract

The invention relates to a display system, a display data transmission method and a serial-to-parallel converter. The display system comprises a display control card and N cascaded display modules, the display control card comprises a programmable logic module and a serial-to-parallel converter; the serial-to-parallel converter is used for performing signal conversion processing on the M paths of serial data signals according to a preset data coding rule to obtain N * P paths of parallel data signals corresponding to the N groups of cascade display modules, and transmitting the N * P paths of parallel data signals to the N groups of cascade display modules through N * P paths of parallel data transmission channels; by introducing the serial-to-parallel converter, the resource limitation of the programmable logic module in the aspect of the number of pins is effectively relieved, the interface pressure caused by directly driving a large number of display modules is avoided, and the expandability and the design flexibility of the display system are improved. And meanwhile, the stability and the high efficiency of data communication between the display control card and each cascade display module are effectively guaranteed.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display system, a display data transmission method, and a serial-to-parallel converter. Background Art

[0002] Existing LED display systems typically consist of a control card and multiple cascaded LED modules. The FPGA (Field-Programmable Gate Array) within the control card processes image information and then sends data and clock signals directly to each cascaded LED module through the FPGA's multiple output ports. However, as the number of LED modules increases, the FPGA's pin resources quickly become depleted, severely limiting the system's scalability and flexibility.

[0003] Currently, no effective solution has been proposed to address the problems of poor scalability and low flexibility of display systems in related technologies. Summary of the Invention

[0004] Based on this, it is necessary to provide a display system, a display data transmission method and a serial-to-parallel converter to address the above technical problems.

[0005] In a first aspect, the present application provides a display system, comprising a display control card and N groups of cascaded display modules; the display control card comprises a programmable logic module and a serial-to-parallel converter; M serial data transmission channels are provided between the programmable logic module and the serial-to-parallel converter; P parallel data transmission channels are provided between the serial-to-parallel converter and each group of the cascaded display modules; M is less than N×P;

[0006] The programmable logic module is configured to perform data encoding processing on the image information to be displayed according to a preset data encoding rule to generate M serial data signals, and transmit the M serial data signals to the serial-to-parallel converter via the M serial data transmission channels;

[0007] The serial-to-parallel converter is configured to perform signal conversion processing on the M serial data signals according to the preset data encoding rule to obtain N×P parallel data signals corresponding to the N groups of cascaded display modules, and transmit the N×P parallel data signals to the N groups of cascaded display modules via the N×P parallel data transmission channels;

[0008] The N groups of cascaded display modules are used to perform corresponding display control according to the N×P parallel data signals.

[0009] In one embodiment, the serial-to-parallel converter is further used to perform voltage adjustment on the N×P parallel data signals so that the voltage of each parallel data signal meets a preset voltage condition; the preset voltage condition is determined based on the electrical characteristics of the cascade display module.

[0010] In one embodiment, the serial-to-parallel converter includes a data processing module; the data processing module is communicatively connected to the programmable logic module;

[0011] The programmable logic module is further configured to generate a first clock signal and transmit the first clock signal to the data processing module;

[0012] The data processing module is configured to extract a plurality of display data packets from each of the serial data signals according to the preset data encoding rule and the first clock signal; for each display data packet, determine a target parallel data transmission channel that matches the display data packet from the N×P parallel data transmission channels according to a preset data packet mapping relationship; load the display data packet into a target parallel data signal corresponding to the target parallel data transmission channel, and transmit the target parallel data signal to the corresponding cascade display module through the target parallel data transmission channel;

[0013] The preset data packet mapping relationship includes a corresponding relationship between a plurality of display data packets and a plurality of parallel data transmission channels.

[0014] In one embodiment, the serial-to-parallel converter further includes a rate control module; the rate control module is in communication with the data processing module;

[0015] The bit rate control module is configured to generate a bit rate control signal according to a preset clock signal, and transmit the bit rate control signal to the data processing module;

[0016] The data processing module is further configured to determine a target data transmission rate for the N×P parallel data signals according to the bit rate control signal; and transmit the N×P parallel data signals to the N groups of cascaded display modules via the N×P parallel data transmission channels according to the target data transmission rate;

[0017] The target data transmission rate is lower than the data transmission rate of the serial data signal.

[0018] In one embodiment, the bit rate control module is communicatively connected to the N groups of cascade display modules;

[0019] The bit rate control module is further configured to generate a second clock signal according to the preset clock signal, and transmit the second clock signal to the N groups of cascaded display modules; the clock frequency of the second clock signal is lower than the clock frequency of the first clock signal;

[0020] Each group of the cascaded display modules is further configured to extract a corresponding display data packet from each of the parallel data signals corresponding to the cascaded display modules according to the second clock signal; and perform corresponding display control according to the display data packet.

[0021] In one embodiment, the serial-to-parallel converter further includes a cache module; the cache module is communicatively connected to the bit rate control module and the data processing module respectively;

[0022] The cache module is used to cache the display data packet.

[0023] In a second aspect, the present application provides a display data transmission method, which is applied to the serial-to-parallel converter of the display control card described in any one of the embodiments of the first aspect above, the method comprising:

[0024] According to a preset data encoding rule, signal conversion processing is performed on the M serial data signals sent by the programmable logic module in the display control card to obtain N×P parallel data signals corresponding to the N groups of cascaded display modules; wherein the M serial data signals are generated by the programmable logic module performing data encoding processing on the image information to be displayed according to the preset data encoding rule;

[0025] The N×P parallel data signals are transmitted to the N groups of cascade display modules via N×P parallel data transmission channels, so that the N groups of cascade display modules perform corresponding display control according to the N×P parallel data signals.

[0026] In one embodiment, the serial data signal carries multiple display data packets; and according to a preset data encoding rule, performing signal conversion processing on the M serial data signals sent by the programmable logic module in the display control card to obtain N×P parallel data signals corresponding to N groups of cascaded display modules includes:

[0027] extracting a plurality of display data packets from each of the serial data signals according to the preset data encoding rule and the first clock signal sent by the programmable logic module;

[0028] For each display data packet, determining a target parallel data transmission channel that matches the display data packet from the N×P parallel data transmission channels according to a preset data packet mapping relationship; wherein the preset data packet mapping relationship includes a correspondence between a plurality of display data packets and a plurality of parallel data transmission channels;

[0029] The display data packet is loaded into a target parallel data signal corresponding to the target parallel data transmission channel, and the target parallel data signal is transmitted to the corresponding cascade display module through the target parallel data transmission channel.

[0030] In one embodiment, the preset data encoding rule is any one of a plurality of encoding rules; the encoding rule includes at least a first encoding rule, a second encoding rule, a third encoding rule, and a fourth encoding rule;

[0031] The first encoding rule is to sequentially load the display data packets corresponding to the red light, green light, and blue light required by each group of the cascaded display modules into the corresponding serial data signals;

[0032] The second encoding rule is to sequentially load P groups of display data packets required by each group of the cascaded display modules into corresponding serial data signals; the P groups of display data packets correspond one-to-one to P parallel data transmission channels respectively;

[0033] The third encoding rule is to sequentially load N groups of display data packets of the same light color required by the N groups of cascaded display modules into the same serial data signal; the N groups of display data packets of the same light color correspond one-to-one to the parallel data transmission channels corresponding to the corresponding light colors of the N groups of cascaded display modules;

[0034] The fourth encoding rule is to group the data packet sequences corresponding to the N groups of cascaded display modules according to a preset division step to obtain L groups of data packet groups; load multiple display data packets in the L groups of data packet groups into L serial data signals in sequence; L is greater than 1.

[0035] In one embodiment, the method further comprises:

[0036] generating a bit rate control signal according to a preset clock signal;

[0037] determining a target data transmission rate of the N×P parallel data signals according to the rate control signal;

[0038] According to the target data transmission rate, the N×P parallel data signals are transmitted to the N groups of cascaded display modules via the N×P parallel data transmission channels;

[0039] The target data transmission rate is lower than the data transmission rate of the serial data signal.

[0040] In one embodiment, the method further comprises:

[0041] generating a second clock signal according to the preset clock signal, and transmitting the second clock signal to the N groups of the cascaded display modules, so that each group of the cascaded display modules extracts a corresponding display data packet from each of the parallel data signals corresponding to the cascaded display modules according to the second clock signal, and performs corresponding display control according to the display data packet;

[0042] The clock frequency of the second clock signal is lower than the clock frequency of the first clock signal.

[0043] In a third aspect, the present application provides a serial-to-parallel converter, wherein the serial-to-parallel converter is configured to execute the display data transmission method according to any one of the embodiments of the second aspect above;

[0044] The serial-to-parallel converter comprises at least a data processing module, a bit rate control module and a buffer module; the data processing module is communicatively connected with the bit rate control module and the buffer module respectively.

[0045] In a fourth aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method described in any one of the embodiments of the second aspect when executing the computer program.

[0046] In a fifth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the embodiments of the second aspect above.

[0047] In a sixth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the method described in any one of the embodiments of the second aspect above.

[0048] The above-mentioned display system, display data transmission method and serial-to-parallel converter, wherein the display system includes a display control card and N groups of cascaded display modules; the display control card includes a programmable logic module and a serial-to-parallel converter; M serial data transmission channels are provided between the programmable logic module and the serial-to-parallel converter; P parallel data transmission channels are provided between the serial-to-parallel converter and each group of cascaded display modules; M is less than N×P; the programmable logic module is used to perform data encoding processing on the image information to be displayed according to a preset data encoding rule, generate M serial data signals, and transmit the M serial data signals to the serial-to-parallel converter via the M serial data transmission channels; the serial-to-parallel converter is used to perform signal conversion processing on the M serial data signals according to the preset data encoding rule, obtain N×P parallel data signals corresponding to the N groups of cascaded display modules, and transmit the N×P parallel data signals to the N groups of cascaded display modules via the N×P parallel data transmission channels; the N groups of cascaded display modules are used to perform corresponding display control according to the N×P parallel data signals. Based on this, a display control card consisting of a programmable logic module and a serial-to-parallel converter is used to convert the serial data signal output by the programmable logic module into multiple parallel data signals via the serial-to-parallel converter. These signals are then transmitted to N groups of cascaded display modules via parallel data transmission channels, achieving serial-to-parallel conversion of the data signal. The introduction of the serial-to-parallel converter effectively alleviates the resource limitations of the programmable logic module in terms of the number of pins, avoids the interface pressure caused by directly driving a large number of display modules, and improves the scalability and design flexibility of the display system. At the same time, the parallel data transmission channels are used to distribute the multiple parallel data signals in parallel to the corresponding cascaded display modules, effectively ensuring the stability and efficiency of data communication between the display control card and each cascaded display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 The overall structure diagram of the display system in one embodiment is shown;

[0051] Figure 2 A schematic structural diagram of a serial-to-parallel converter in one embodiment;

[0052] Figure 3 It is a diagram showing the overall structure of the system in a specific embodiment;

[0053] Figure 4A schematic flow chart showing a data transmission method according to an embodiment;

[0054] Figure 5 1 is a flow chart of a signal conversion process step in one embodiment;

[0055] Figure 6 Schematic diagram of a first encoding rule in one embodiment;

[0056] Figure 7 is a schematic diagram of a second encoding rule in one embodiment;

[0057] Figure 8 is a schematic diagram of the third encoding rule in one embodiment;

[0058] Figure 9 is a schematic diagram of a fourth encoding rule in one embodiment;

[0059] Figure 10 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0061] In one embodiment, Figure 1 As shown, Figure 1 : This is an overall structural diagram of a display system in one embodiment; the display system includes a display control card and N groups of cascaded display modules; the display control card includes a programmable logic module and a serial-to-parallel converter; M serial data transmission channels are provided between the programmable logic module and the serial-to-parallel converter; P parallel data transmission channels are provided between the serial-to-parallel converter and each group of cascaded display modules; M is less than N×P; where M, N, and P are all positive integers;

[0062] a programmable logic module, configured to perform data encoding processing on the image information to be displayed according to a preset data encoding rule, generate M serial data signals, and transmit the M serial data signals to the serial-to-parallel converter via the M serial data transmission channels;

[0063] a serial-to-parallel converter, configured to perform signal conversion processing on M serial data signals according to a preset data encoding rule to obtain N×P parallel data signals corresponding to the N groups of cascaded display modules, and transmit the N×P parallel data signals to the N groups of cascaded display modules via N×P parallel data transmission channels;

[0064] N groups of cascaded display modules are used to perform corresponding display control according to N×P parallel data signals.

[0065] A programmable logic module refers to an integrated circuit device that can be configured through software to implement specific logic functions. Programmable logic modules can include, but are not limited to, FPGAs and CPLDs (Complex Programmable Logic Devices), and are not specifically defined here.

[0066] Among them, the preset data encoding rules refer to the data encoding format and conversion logic determined in advance and solidified in the programmable logic module and the serial-to-parallel converter, which are used to ensure that the serial data signal can be transmitted correctly, efficiently and stably between the programmable logic module and the serial-to-parallel converter.

[0067] In an exemplary embodiment, the preset data encoding rule is any one of a plurality of encoding rules, which are not specifically limited herein. The encoding rules include at least a first encoding rule, a second encoding rule, a third encoding rule, and a fourth encoding rule. The first encoding rule is to sequentially load display data packets corresponding to red light, green light, and blue light required by each group of cascaded display modules into corresponding serial data signals. The second encoding rule is to sequentially load P groups of display data packets required by each group of cascaded display modules into corresponding serial data signals. The P groups of display data packets correspond one-to-one to P parallel data transmission channels. The third encoding rule is to sequentially load N groups of display data packets of the same light color required by N groups of cascaded display modules into the same serial data signal. The N groups of display data packets of the same light color correspond one-to-one to the parallel data transmission channels corresponding to the corresponding light colors of the N groups of cascaded display modules. The fourth encoding rule is to group the data packet sequences corresponding to the N groups of cascaded display modules according to a preset division step size to obtain L groups of data packets. The multiple display data packets in the L groups of data packets are sequentially loaded into the L serial data signals. L is greater than 1.

[0068] It is understandable that only some encoding rules are listed in the above embodiment. In actual application, other encoding rules can be adopted according to specific needs, and no specific limitation is made here.

[0069] Among them, the image information to be displayed refers to the original image data corresponding to the image to be presented on the display system; it can be understood that the image information to be displayed can come from an external image processor, a video input interface, a pre-stored screen, etc., and is not specifically limited here.

[0070] The serial data signal comprises multiple display data packets arranged sequentially according to preset data encoding rules. Each display data packet carries corresponding image data, ensuring that the cascaded display module can accurately interpret and restore the image content. It should be noted that because the serial data signal is directly output by the programmable logic module, it inherently has high-frequency characteristics.

[0071] The serial data transmission channel is a physical transmission medium provided between the programmable logic module and the serial-to-parallel converter, used to reliably transmit serial data signals from the programmable logic module to the serial-to-parallel converter. The serial data transmission channel can be, but is not limited to, a high-speed signal line. The specific implementation method should be adaptively selected based on the data transmission rate of the serial data signal and is not specifically limited here.

[0072] It should be noted that the number M of serial data transmission channels and serial data signals is related to the processing performance of the serial-to-parallel converter and preset data encoding rules, and is not specifically limited here.

[0073] The serial-to-parallel converter has at least signal conversion and bit rate adjustment functions. The signal conversion function refers to the ability of the serial-to-parallel converter to convert serial signal formats into parallel signal formats during data transmission. Specifically, the signal conversion function of the serial-to-parallel converter can convert M serial data signals according to preset data encoding rules to obtain N×P parallel data signals corresponding to N groups of cascaded display modules.

[0074] Rate adjustment refers to the ability of a serial-to-parallel converter to adaptively adjust the data rate of the output signal (i.e., N x P parallel data signals) during data transmission. This function deserializes M serial data signals into N x P parallel data signals and, while maintaining the integrity of the original image information, down-converts each parallel data signal to adapt it to the receiving capabilities of the cascaded display modules and the transmission limitations of the physical interface.

[0075] It's important to note that the display control card and N sets of cascaded display modules are typically located in different board-level structures, connected by cables and physically separated. Due to the inherent characteristics of these cables, high-frequency signals are susceptible to interference, especially over longer transmission distances. This can lead to reduced signal integrity and even data errors, making stable data communication impossible.

[0076] By introducing a serial-to-parallel converter into the display control card of the display system, the high-frequency serial data signal output by the programmable logic module (FPGA) is first deserialized locally into multiple low-frequency parallel data signals, and then transmitted to the corresponding cascade display module at the remote end through a parallel data channel. This not only alleviates the pin resource pressure of the programmable logic module, but also effectively improves the stability and reliability of cross-board data transmission through a high-to-low bit rate conversion mechanism.

[0077] The parallel data signal includes at least one display data packet, and the display data packet is used to drive the corresponding cascade display module to perform corresponding display control.

[0078] It can be understood that the total number of display data packets carried by the M serial data signals is consistent with the total number of display data packets contained in the N×P parallel data signals output after the M serial data signals are disassembled through the serial-to-parallel converter, so as to achieve lossless mapping and complete distribution of data.

[0079] The parallel data transmission channel is a physical transmission medium provided between the serial-to-parallel converter and the N groups of cascaded display modules. It is used to reliably transmit multiple parallel data signals from the display control card to each cascaded display module. The parallel data transmission channel can be, but is not limited to, a cable. The specific implementation method should be adaptively selected based on the data transmission rate of the parallel data signals and is not specifically limited here.

[0080] It is understandable that, since parallel data signals operate at a relatively low frequency, the requirements for transmission bandwidth are relatively low, and therefore a common physical connection method in the prior art can be used for cross-board communication.

[0081] Each set of cascade display modules includes multiple cascaded LED modules (such as Figure 1 As shown); wherein, the LED module includes a driving circuit and an LED (not shown in the figure); the LED module is used to obtain its own corresponding display data packet from the parallel data signal to perform corresponding display control.

[0082] For example, see Figure 1 , taking the programmable logic module as FPGA as an example, the FPGA performs data encoding processing on the image information to be displayed according to the preset data encoding rules to generate M serial data signals; the M serial data signals include DATA-H1~DATA-Hm, where m=M; the M serial data signals are transmitted to the serial-to-parallel converter through the M serial data transmission channels.

[0083] After receiving M serial data signals, the serial-to-parallel converter performs signal conversion processing on the M serial data signals according to a preset data encoding rule to obtain N×P parallel data signals corresponding to the N groups of cascaded display modules; the N×P parallel data signals include DATA-L1-1~DATA-L1-p, to DATA-Ln-1~DATA-Ln-p, where n=N, p=P; the N×P parallel data signals are transmitted to the N groups of cascaded display modules via the N×P parallel data transmission channels; the N groups of cascaded display modules perform corresponding display control according to the received N×P parallel data signals.

[0084] Among them, each group of cascade display modules includes multiple LED display modules. For example, the first group of cascade display modules includes LED module 1-1, LED module 1-2, LED module 1-3, etc.; the Nth group of cascade display modules includes LED module N-1, LED module N-2, LED module N-3, etc.

[0085] In this embodiment, a display control card consisting of a programmable logic module and a serial-to-parallel converter is employed to convert the serial data signal output by the programmable logic module into multiple parallel data signals via the serial-to-parallel converter. These signals are then transmitted to N groups of cascaded display modules via parallel data transmission channels, achieving serial-to-parallel conversion of the data signal. The introduction of the serial-to-parallel converter effectively alleviates the resource limitations of the programmable logic module in terms of the number of pins, avoids the interface pressure caused by directly driving a large number of display modules, and enhances the scalability and design flexibility of the display system. Furthermore, the parallel data transmission channels are used to distribute the multiple parallel data signals in parallel to the corresponding cascaded display modules, effectively ensuring the stability and efficiency of data communication between the display control card and each cascaded display module.

[0086] In one embodiment, the serial-to-parallel converter is further configured to perform voltage adjustment on N×P parallel data signals so that the voltage of each parallel data signal satisfies a preset voltage condition.

[0087] Among them, the serial-to-parallel converter also has a level conversion function; the level conversion function refers to the ability of the serial-to-parallel converter to adaptively adjust the voltage amplitude of the output signal (i.e., N×P parallel data signals) during data transmission to meet the electrical requirements of each level of cascade display modules for the interface level.

[0088] The preset voltage conditions are determined based on the electrical characteristics of the cascaded display modules. It is understood that these conditions are pre-set based on the electrical interface specifications of the cascaded display modules and the operating voltage range of the driver circuits in the LED modules, ensuring that the parallel data signals can be correctly identified and processed at the cascaded display module end.

[0089] For example, in actual applications, the pin voltage of a programmable logic module (such as an FPGA) may differ from the input level of the cascade display module. For example, the parallel data signal output by the FPGA may be a 3.3V logic level, while the cascade display module only supports the 5V level standard. If the two are directly connected, it may lead to problems such as signal recognition errors and communication failures. To this end, a serial-to-parallel converter with a level conversion function is introduced in this embodiment to perform voltage adaptation on the output parallel data signal while completing the data format conversion. Specifically, the serial-to-parallel converter increases the original 3.3V signal level to 5V to meet the electrical interface requirements of the cascade display module, thereby ensuring that the data can be accurately identified and stably transmitted between the sending end and the receiving end.

[0090] In this embodiment, by integrating the level conversion function into the serial-to-parallel converter, not only the interface compatibility problem between different voltage domains is solved, but also the peripheral circuit design is simplified, thereby improving the integration and engineering applicability of the display system.

[0091] In one embodiment, Figure 2 As shown, Figure 2 Schematic diagram of the structure of a serial-to-parallel converter in one embodiment; the serial-to-parallel converter includes a data processing module; the data processing module is communicatively connected with the programmable logic module;

[0092] The programmable logic module is further configured to generate a first clock signal and transmit the first clock signal to the data processing module;

[0093] a data processing module configured to extract a plurality of display data packets from each serial data signal according to a preset data encoding rule and a first clock signal; for each display data packet, determine a target parallel data transmission channel that matches the display data packet from the N×P parallel data transmission channels according to a preset data packet mapping relationship; load the display data packet into a target parallel data signal corresponding to the target parallel data transmission channel, and transmit the target parallel data signal to the corresponding cascade display module through the target parallel data transmission channel;

[0094] The preset data packet mapping relationship includes a correspondence between a plurality of display data packets and a plurality of parallel data transmission channels. It is understandable that each display data packet has a unique corresponding target parallel data transmission channel.

[0095] Among them, the first clock signal is used to ensure the timing consistency between the programmable logic module and the serial-to-parallel converter, so that each serial data signal can be sampled and analyzed at the correct clock edge, that is, the clock edge (such as the rising edge or the falling edge) of the first clock signal is the sampling trigger reference.

[0096] In an exemplary embodiment, the first clock signal is also used to provide a reference clock for the serial-to-parallel converter, so that the serial-to-parallel converter generates a second clock signal with a clock frequency lower than the first clock signal, and transmits it to the cascade display module.

[0097] Among them, the preset data encoding rule is any one of a plurality of encoding rules; it can be understood that in each communication process, the programmable logic module and the data processing module need to perform data processing and analysis based on the same preset data encoding rule to ensure that the encoding method of the data at the sending end is consistent with the decoding method of the data at the receiving end; only when both parties adopt the same preset data encoding rule can the correct restoration and stable transmission of the image data be achieved, avoiding data misreading, communication failure or display abnormality due to encoding differences.

[0098] The data processing module is connected to multiple data input terminals; see Figure 2 , multiple data input terminals include Din1~Din M; data input terminals Din 1~Din M are used to receive M serial data signals and transmit them to the data processing module. The data processing module is also connected to the clock input terminal; see Figure 2 , the clock input end includes Cin; the clock input end Cin is used to receive the first clock signal and transmit it to the data processing module.

[0099] It is understandable that the number of data input terminals needs to be set according to actual data transmission requirements and is not specifically limited here.

[0100] Furthermore, the data processing module is also connected to a plurality of data output terminals; see Figure 2 The multiple data output terminals include Dout 1 to Dout N×P; the multiple data output terminals Dout 1 to Dout N×P are used to output N×P parallel data signals.

[0101] The data processing module may include, but is not limited to, a mapping logic unit. The mapping logic unit is configured to perform corresponding distribution control for each display data packet according to a preset data packet mapping relationship. That is, according to the preset data packet mapping relationship, the mapping logic unit determines a target parallel data transmission channel that matches the display data packet from N×P parallel data transmission channels, thereby implementing data loading and distribution based on the target parallel data transmission channel corresponding to the display data packet.

[0102] Exemplarily, the data processing module decodes and parses each received serial data signal according to a preset data encoding rule and the clock edge of the first clock signal, thereby extracting multiple display data packets from each serial data signal. The display data packets are used to drive corresponding cascaded display modules to display images.

[0103] Furthermore, for each display data packet, the data processing module determines the target parallel data transmission channel that matches the display data packet from the N×P parallel data transmission channels according to the preset data packet mapping relationship; then, the display data packet is loaded into the target parallel data signal corresponding to the target parallel data transmission channel, and the target parallel data signal is transmitted to the corresponding cascade display module through the target parallel data transmission channel, thereby completing the directional transmission of the display data packet.

[0104] In this embodiment, based on the preset data encoding rules and the first clock signal, accurate acquisition and efficient analysis of the serial data signal are achieved, ensuring the integrity and timing synchronization of the serial data signal during high-speed transmission; based on the preset data packet mapping relationship, each display data packet can be accurately distributed to the corresponding cascade display module, thereby achieving orderly transmission of display data packets between multiple cascade display modules, and improving the overall display consistency and scalability of the display system.

[0105] In one embodiment, Figure 2 As shown, the serial-to-parallel converter further includes a rate control module; the rate control module is in communication with the data processing module;

[0106] A rate control module is used to generate a rate control signal according to a preset clock signal and transmit the rate control signal to the data processing module;

[0107] The data processing module is further configured to determine a target data transmission rate of N×P parallel data signals according to the bit rate control signal; and transmit the N×P parallel data signals to the N groups of cascaded display modules via the N×P parallel data transmission channels according to the target data transmission rate;

[0108] The target data transmission rate is lower than the data transmission rate of the serial data signal.

[0109] The preset clock signal is a reference clock, and is used to generate a rate control signal. It should be noted that the preset clock signal may be, but is not limited to, the first clock signal, an external clock signal, or a clock signal built into the rate control module itself, and is not specifically limited here.

[0110] The bit rate control signal is used to adjust the data output rate of the data processing module during data transmission to achieve rate matching and flow control between the serial-to-parallel converter and each cascade display module.

[0111] The bit rate control signal carries data transmission rate information, and the data transmission rate information is used to characterize the required data transmission rate matching relationship between the transmitting end (serial-parallel converter) and the receiving end (each cascade display module).

[0112] In an exemplary embodiment, by parsing the bit rate control signal, the data processing module can adjust the target data transmission rate of N×P parallel data signals according to the data transmission rate information carried by the bit rate control signal, so that the target data transmission rate is lower than the data transmission rate of the serial data signal; then, according to the target data transmission rate, the N×P parallel data signals are transmitted to N groups of cascaded display modules through N×P parallel data transmission channels to alleviate the problems of electromagnetic interference, signal attenuation and impedance mismatch faced by high-frequency serial data signals in long-distance transmission, thereby improving the reliability of overall communication.

[0113] In this embodiment, based on the bit rate control signal transmitted by the bit rate control module, the data processing module realizes the rate matching and adjustment between the serial-to-parallel converter and each level of cascade display modules; at the same time, by adopting a high-to-low bit rate conversion mechanism, the stability and reliability of cross-board data transmission are effectively improved, thereby further improving the reliability of the display system.

[0114] In one embodiment, the bit rate control module is communicatively connected to the N groups of cascaded display modules;

[0115] The bit rate control module is further configured to generate a second clock signal according to the preset clock signal, and transmit the second clock signal to the N groups of cascaded display modules; the clock frequency of the second clock signal is lower than the clock frequency of the first clock signal;

[0116] Each group of cascaded display modules is further configured to extract a corresponding display data packet from each parallel data signal corresponding to the cascaded display module according to the second clock signal; and perform corresponding display control according to the display data packet.

[0117] The preset clock signal is a reference clock and is also used to generate a second clock signal. It should be noted that the preset clock signal can be, but is not limited to, the first clock signal, an external clock signal, or a clock signal built into the bit rate control module itself, and is not specifically limited here.

[0118] The second clock signal is used to ensure that the cascaded display module samples the parallel data signal at the correct clock edge, thereby achieving accurate recognition and processing of data.

[0119] The clock frequency of the second clock signal is lower than the clock frequency of the first clock signal.

[0120] It should be noted that each high-speed serial data signal output by the programmable logic module carries multiple display data packets intended to be sent to multiple groups of cascaded display modules; since the amount of information carried by each serial data signal per unit time is higher than the amount of information carried by each parallel data signal, in order to ensure that the serial-to-parallel converter can receive, accurately parse and distribute this data in a timely manner, the programmable logic module must send the serial data signal at a higher frequency, that is, use a high-frequency first clock signal as the timing reference of the sending end.

[0121] On the serial-to-parallel converter side, each parallel data signal generated contains only the data required by the corresponding cascaded display module, so the data output rate requirement is relatively low. This embodiment sets the clock frequency of the second clock signal to be lower than the clock frequency of the first clock signal. This not only achieves rate matching from high-frequency serial input to low-frequency parallel output, but also ensures the programmable logic module's ability to stably transmit high-throughput data, ensuring the data transmission efficiency of the entire display system.

[0122] For example, see Figure 2 , the bit rate control module is connected to the clock output terminal Cout; taking the preset clock signal as the first clock signal as an example for explanation, the bit rate control module performs frequency division processing on the first clock signal to generate a second clock signal, and the second clock signal is transmitted to N groups of cascaded display modules through the clock output terminal Cout, so that each group of cascaded display modules extracts a corresponding display data packet from each parallel data signal corresponding to the cascaded display module according to the clock edge (rising edge or falling edge, which needs to be pre-set according to actual needs) of the second clock signal, and performs corresponding display control according to the display data packet.

[0123] In this embodiment, based on the bit rate control module, a second clock signal with a clock frequency lower than the first clock signal is generated, and then the cascaded display modules are driven by the second clock signal to perform parallel data signal sampling, which can effectively reduce the risks of electromagnetic interference and other risks faced by high-frequency signals during long-distance transmission, and improve the stability and reliability of cross-board communication; at the same time, based on the second clock signal, it also ensures the timing consistency and synchronization of data reception between multiple cascaded display modules, further improving the communication stability and display reliability of the display system.

[0124] In one embodiment, see Figure 2 , the serial-to-parallel converter also includes a cache module; the cache module is respectively communicated with the rate control module and the data processing module;

[0125] The cache module is used to cache display data packets.

[0126] It is understandable that the cache module provides fault tolerance for the display system, which can effectively avoid problems such as data packet loss caused by unstable communication links or other anomalies, and further ensure the stability and reliability of data transmission in the display system.

[0127] In one embodiment, see Figure 3 For example, with M=N=4 and P=3, the display system includes a display control card and four cascaded display modules. Four serial data transmission channels are provided between the programmable logic module and the serial-to-parallel converter. Three parallel data transmission channels are provided between the serial-to-parallel converter and each cascaded display module. The programmable logic module is an FPGA.

[0128] After receiving the image information to be displayed, the FPGA performs data encoding processing on the image information to be displayed according to the preset data encoding rules, generates 4 serial data signals, and transmits the 4 serial data signals to the serial-to-parallel converter through 4 serial data transmission channels.

[0129] After receiving the 4-way serial data signal, the serial-to-parallel converter samples and decomposes the 4-way serial data signal according to the preset data encoding rules to obtain 12-way parallel data signals corresponding to the 4 groups of cascaded display modules, and transmits the 12-way parallel data signals to the 4 groups of cascaded display modules through the 12-way parallel data transmission channels, so that the 4 groups of cascaded display modules perform corresponding display control according to the received 12-way parallel data signals.

[0130] In one embodiment, Figure 4 As shown, Figure 4 The flowchart of a display data transmission method according to one embodiment is shown; the display data transmission method is applied to the serial-to-parallel converter of the display control card described in any one of the above embodiments, comprising the following steps:

[0131] Step S401 : performing signal conversion processing on M serial data signals sent by the programmable logic module in the display control card according to a preset data encoding rule to obtain N×P parallel data signals corresponding to N groups of cascaded display modules.

[0132] The M serial data signals are generated by the programmable logic module encoding the image information to be displayed according to a preset data encoding rule. The image information to be displayed refers to the original image data corresponding to the image to be presented on the display system.

[0133] It should be noted that M is related to the processing performance of the serial-to-parallel converter and the preset data encoding rules, and is not specifically limited here.

[0134] The serial data signal includes a plurality of display data packets arranged continuously according to preset data encoding rules; each display data packet carries corresponding image data to ensure that the cascaded display module can accurately parse and restore the image content.

[0135] Among them, the preset data encoding rules refer to the data encoding format and conversion logic determined in advance and solidified in the programmable logic module and the serial-to-parallel converter, which are used to ensure that the serial data signal can be transmitted correctly, efficiently and stably between the programmable logic module and the serial-to-parallel converter.

[0136] In an exemplary embodiment, a method for performing signal conversion processing on M serial data signals sent by a programmable logic module in a display control card may be: performing signal sampling and signal decomposition processing on the M serial data signals sent by the programmable logic module in the display control card.

[0137] The parallel data signal includes at least one display data packet, and the display data packet is used to drive the corresponding cascade display module to perform corresponding display control.

[0138] It can be understood that the total number of display data packets carried by the M serial data signals is consistent with the total number of display data packets contained in the N×P parallel data signals output after the M serial data signals are disassembled through the serial-to-parallel converter, so as to achieve lossless mapping and complete distribution of data.

[0139] In step S402 , N×P parallel data signals are transmitted to N groups of cascaded display modules via N×P parallel data transmission channels, so that the N groups of cascaded display modules perform corresponding display control according to the N×P parallel data signals.

[0140] It is understandable that each group of cascaded display modules has corresponding P-channel parallel data signals for implementing corresponding display control according to the P-channel parallel data signals.

[0141] It should be noted that the specific structure of the serial-to-parallel converter has been described in detail in the above embodiments and will not be repeated here.

[0142] In this embodiment, the serial data signal output by the programmable logic module is converted into multiple parallel data signals via a serial-to-parallel converter and transmitted to N groups of cascaded display modules via parallel data transmission channels, achieving serial-to-parallel conversion of the data signal. The introduction of the serial-to-parallel converter effectively alleviates the resource constraints of the programmable logic module in terms of the number of pins, avoids the interface pressure caused by directly driving a large number of display modules, and improves the scalability and design flexibility of the display system. Furthermore, the parallel data transmission channels are used to distribute the multiple parallel data signals in parallel to the corresponding cascaded display modules, effectively ensuring the stability and efficiency of data communication between the display control card and each cascaded display module.

[0143] In one embodiment, the serial data signal is loaded with a plurality of display data packets; the plurality of display data packets are arranged continuously according to a preset data encoding rule;

[0144] like Figure 5 As shown, Figure 5 The flowchart of the signal conversion processing steps in one embodiment is as follows; according to preset data encoding rules, signal conversion processing is performed on M serial data signals sent by the programmable logic module in the display control card to obtain N×P parallel data signals corresponding to N groups of cascaded display modules, including the following steps:

[0145] Step S501 : extracting a plurality of display data packets from each serial data signal according to a preset data encoding rule and a first clock signal sent by a programmable logic module.

[0146] Step S502 : for each display data packet, according to a preset data packet mapping relationship, a target parallel data transmission channel that matches the display data packet is determined from the N×P parallel data transmission channels.

[0147] The preset data packet mapping relationship includes a corresponding relationship between a plurality of display data packets and a plurality of parallel data transmission channels;

[0148] In step S503 , the display data packet is loaded into a target parallel data signal corresponding to the target parallel data transmission channel, and the target parallel data signal is transmitted to the corresponding cascade display module through the target parallel data transmission channel.

[0149] The clock edge (such as rising edge or falling edge) of the first clock signal is a sampling trigger reference, which is used to control the serial-to-parallel converter to sample the serial data signal at the clock edge of the first clock signal.

[0150] The preset data encoding rule is any one of a plurality of encoding rules; the encoding rule includes at least a first encoding rule, a second encoding rule, a third encoding rule and a fourth encoding rule.

[0151] Among them, the first encoding rule is to sequentially load the display data packets corresponding to the red light, green light, and blue light required by each group of cascaded display modules into the corresponding serial data signals.

[0152] For example, taking the first group of cascaded display modules as an example, see Figure 6 The first encoding rule is to sequentially load the display data packet R corresponding to red light, the display data packet G corresponding to green light, and the display data packet B corresponding to blue light required by the first group of cascaded display modules into the serial data signal DATA-H.

[0153] It is understandable that Figure 6 The serial data signal DATA-H in the display is converted by a serial-to-parallel converter into three parallel data signals corresponding to the first cascaded display module: DATA-L1-1, DATA-L1-2, and DATA-L1-3. Parallel data signal DATA-L1-1 includes display data packet R corresponding to red light, parallel data signal DATA-L1-2 includes display data packet G corresponding to green light, and parallel data signal DATA-L1-3 includes display data packet B corresponding to blue light.

[0154] The second encoding rule is to sequentially load the P groups of display data packets required by each group of cascaded display modules into the corresponding serial data signals; wherein the P groups of display data packets correspond one-to-one to the P parallel data transmission channels respectively.

[0155] For example, taking the first group of cascaded display modules as an example, it is assumed that the first group of cascaded display modules requires D1 to Dp, a total of P groups of display data packets; see Figure 7 The second encoding rule is to load the display data packets D1 to Dp required by the first group of cascaded display modules, these P groups of display data packets, into the serial data signal DATA-H in sequence.

[0156] It is understandable that Figure 7 The serial data signal DATA-H in the first cascade display module is converted by a serial-to-parallel converter to obtain P parallel data signals corresponding to the first cascade display module, namely DATA-L1-1 to DATA-L1-p, where p = P. The parallel data signal DATA-L1-1 includes a display data packet D1, the parallel data signal DATA-L1-2 includes a display data packet D2, the parallel data signal DATA-L1-3 includes a display data packet D3, and so on, and will not be further described here.

[0157] Among them, the third encoding rule is to load N groups of display data packets of the same light color required by N groups of cascaded display modules into the same serial data signal in sequence; the N groups of display data packets of the same light color correspond one-to-one to the parallel data transmission channels corresponding to the corresponding light colors of the N groups of cascaded display modules.

[0158] For example, assuming that each of the N groups of cascaded display modules requires a group of display data packets corresponding to red light, a group of display data packets corresponding to green light, and a group of display data packets corresponding to blue light; see Figure 8 The third encoding rule is to sequentially load the N groups of red light display data packets (R1~Rn) required by the N groups of cascaded display modules into the serial data signal DATA-H1, and sequentially load the N groups of green light display data packets (G1~Gn) required by the N groups of cascaded display modules into the serial data signal DATA-H2; and sequentially load the N groups of blue light display data packets (B1~Bn) required by the N groups of cascaded display modules into the serial data signal DATA-H3.

[0159] It is understandable that Figure 8 The serial data signal DATA-H1 in the example is converted by a serial-to-parallel converter to produce parallel data signals corresponding to each of the N groups of cascaded display modules, namely DATA-L1-1, DATA-L2-1, DATA-L3-1, ..., DATA-Ln-1, where n = N. The parallel data signal DATA-L1-1 includes a display data packet R1, which corresponds to the parallel data transmission channel corresponding to the red light of the first group of cascaded display modules. The parallel data signal DATA-L2-1 includes a display data packet R2, which corresponds to the parallel data transmission channel corresponding to the red light of the second group of cascaded display modules, and so on. These details are not repeated here.

[0160] Figure 8 The serial data signal DATA-H2 in the serial communication circuit is converted by a serial-to-parallel converter to obtain parallel data signals corresponding to each of the N groups of cascaded display modules, namely DATA-L1-2, DATA-L2-2, DATA-L3-2, ..., DATA-Ln-2, where n = N. The parallel data signal DATA-L1-2 includes a display data packet G1, which corresponds to the parallel data transmission channel corresponding to the green light of the first group of cascaded display modules. The parallel data signal DATA-L2-2 includes a display data packet G2, which corresponds to the parallel data transmission channel corresponding to the green light of the second group of cascaded display modules, and so on. These details are not further detailed here.

[0161] Figure 8The serial data signal DATA-H3 in the image is converted by a serial-to-parallel converter to produce parallel data signals corresponding to each of the N groups of cascaded display modules, namely DATA-L1-3, DATA-L2-3, DATA-L3-3, ..., DATA-Ln-3, where n = N. The parallel data signal DATA-L1-3 includes a display data packet B1, which corresponds to the parallel data transmission channel corresponding to the blue light of the first group of cascaded display modules. The parallel data signal DATA-L2-3 includes a display data packet B2, which corresponds to the parallel data transmission channel corresponding to the blue light of the second group of cascaded display modules, and so on. These details are not repeated here.

[0162] Among them, the fourth encoding rule is to group the data packet sequences corresponding to N groups of cascaded display modules according to a preset division step to obtain L groups of data packet groups; load multiple display data packets in the L groups of data packet groups into L serial data signals in sequence; L is greater than 1.

[0163] The preset division step size needs to be set based on actual encoding requirements and is not specifically limited here. For example, if each parallel data transmission channel needs to transmit S display data packets, then N groups of cascaded display modules require a total of S×P×N display data packets; S is greater than 1. In this case, the preset division step size can be equal to S×P, N×P, or S×N. If the preset division step size is equal to S×P, then L=N; if the preset division step size is equal to N×P, then L=S; if the preset division step size is equal to S×N, then L=P. Where S, P, and N are all greater than 1.

[0164] For example, see Figure 9 , for example, each parallel data transmission channel needs to transmit S=2 display data packets, that is, each parallel data signal includes 2 display data packets, N groups of cascaded display modules require a total of S×P×N=2×3×3=18 display data packets, and the preset division step is equal to N×P=3×3=9; S×P×N=2×3×3=18 data packets are sequentially sorted to obtain a corresponding data packet sequence, which is display data packet D1 to display data packet D18; among which, display data packets D1 to display data packet D6 correspond to the first group of cascaded display modules; display data packets D7 to display data packet D12 correspond to the second group of cascaded display modules; display data packets D13 to display data packets D18 correspond to the third group of cascaded display modules.

[0165] The data packet sequences corresponding to the three groups of cascaded display modules are grouped according to a preset division step size of N×P=3×3=9 to obtain two groups of data packet groups; the first group of data packet groups includes display data packets D1 to display data packets D9; the second group of data packet groups includes display data packets D10 to display data packets D18; the multiple display data packets in the first group of data packet groups (i.e., display data packets D1 to display data packets D9) are sequentially loaded into the serial data signal DATA-H1; the multiple display data packets in the second group of data packet groups (i.e., display data packets D10 to display data packets D18) are sequentially loaded into the serial data signal DATA-H2.

[0166] It is understandable that Figure 9 After serial data signals DATA-H1 and DATA-H2 are converted by a serial-to-parallel converter, a total of nine parallel data signals corresponding to three groups of cascaded display modules can be obtained: DATA-L1-1, DATA-L1-2, DATA-L1-3, DATA-L2-1, DATA-L2-2, DATA-L2-3, DATA-L3-1, DATA-L3-2, and DATA-L3-3. Parallel data signal DATA-L1-1 includes display data packets D1 and D2; parallel data signal DATA-L1-2 includes display data packets D3 and D4, and so on. These are not further detailed here.

[0167] It is understandable that the encoding rules may also include other encoding rules, which need to be flexibly set according to actual encoding requirements and are not specifically limited here.

[0168] Exemplarily, each received serial data signal is decoded and parsed according to a preset data encoding rule and the clock edge of the first clock signal, so as to extract multiple display data packets from each serial data signal. Figure 6 For example, if the preset data encoding rule is the first encoding rule, each serial data signal DATA-H can be decomposed into display data packet R, display data packet G and display data packet B according to the first encoding rule and the clock edge of the first clock signal.

[0169] by Figure 7 For example, if the preset data encoding rule is the second encoding rule, then each serial data signal DATA-H can be decomposed into display data packets D1 to Dp according to the second encoding rule and the clock edge of the first clock signal.

[0170] by Figure 8For example, if the preset data encoding rule is the third encoding rule, then according to the third encoding rule and the clock edge of the first clock signal, the serial data signal DATA-H1 corresponding to the red light can be disassembled into display data packets R1 to display data packets Rn; the serial data signal DATA-H2 corresponding to the green light can be disassembled into display data packets G1 to display data packets Gn; and the serial data signal DATA-H3 corresponding to the blue light can be disassembled into display data packets B1 to display data packets Bn.

[0171] by Figure 9 For example, if the preset data encoding rule is the fourth encoding rule, then according to the fourth encoding rule and the clock edge of the first clock signal, the serial data signal DATA-H1 can be disassembled into display data packets D1 to display data packets D9, and the serial data signal DATA-H2 can be disassembled into display data packets D10 to display data packets D18.

[0172] Furthermore, for each display data packet, according to the preset data packet mapping relationship, a target parallel data transmission channel that matches the display data packet is determined from the N×P parallel data transmission channels, the display data packet is loaded into the target parallel data signal corresponding to the target parallel data transmission channel, and the target parallel data signal is transmitted to the corresponding cascade display module through the target parallel data transmission channel.

[0173] In this embodiment, based on the preset data encoding rules and the first clock signal, accurate acquisition and efficient analysis of the serial data signal are achieved, ensuring the integrity and timing synchronization of the serial data signal during high-speed transmission; based on the preset data packet mapping relationship, each display data packet can be accurately distributed to the corresponding cascade display module, thereby achieving orderly transmission of display data packets between multiple cascade display modules, and improving the overall display consistency and scalability of the display system.

[0174] In one embodiment, the display data transmission method further includes the following steps:

[0175] Step 1: Generate a rate control signal according to a preset clock signal.

[0176] The preset clock signal is a reference clock, and is used to generate a rate control signal. It should be noted that the preset clock signal may be, but is not limited to, the first clock signal, an external clock signal, or a clock signal built into the rate control module itself, and is not specifically limited here.

[0177] The bit rate control signal is used to adjust the data output rate during data transmission to achieve rate matching and flow control between the serial-to-parallel converter and each cascade display module.

[0178] The bit rate control signal carries data transmission rate information; the data transmission rate information is used to characterize the data transmission rate matching relationship required between the serial-to-parallel converter and each cascade display module.

[0179] Step 2: Determine the target data transmission rate of the N×P parallel data signals according to the rate control signal.

[0180] Step 3: According to the target data transmission rate, N×P parallel data signals are transmitted to N groups of cascaded display modules through N×P parallel data transmission channels.

[0181] The target data transmission rate is lower than the data transmission rate of the serial data signal.

[0182] Exemplarily, a bit rate control signal is generated according to a preset clock signal. Further, by analyzing the bit rate control signal, a target data transmission rate of N×P parallel data signals is obtained. Then, according to the target data transmission rate, the N×P parallel data signals are transmitted to N groups of cascaded display modules through N×P parallel data transmission channels to alleviate the problems of electromagnetic interference, signal attenuation and impedance mismatch faced by high-frequency serial data signals in long-distance transmission, thereby improving the reliability of the overall communication.

[0183] In this embodiment, based on the bit rate control signal, rate matching and adjustment are achieved between the serial-to-parallel converter and each level of cascade display modules; at the same time, by adopting a high-to-low bit rate conversion mechanism, the stability and reliability of cross-board data transmission are effectively improved, further improving the reliability of the display system.

[0184] In one embodiment, the display data transmission method further includes the following steps:

[0185] Generating a second clock signal according to a preset clock signal, and transmitting the second clock signal to N groups of cascaded display modules, so that each group of cascaded display modules extracts a corresponding display data packet from each parallel data signal corresponding to the cascaded display module according to the second clock signal, and performs corresponding display control according to the display data packet;

[0186] The preset clock signal serves as a reference clock and is also used to generate a second clock signal. This second clock signal ensures that the cascaded display module samples the parallel data signal at the correct clock edge, thereby enabling accurate data recognition and processing. The second clock signal has a lower frequency than the first clock signal.

[0187] For example, taking the preset clock signal as the first clock signal as an example, the first clock signal is frequency-divided to generate a second clock signal, and the second clock signal is transmitted to N groups of cascaded display modules, so that each group of cascaded display modules extracts the corresponding display data packet from each parallel data signal corresponding to the cascaded display module according to the clock edge of the second clock signal (rising edge or falling edge, which needs to be pre-set according to actual needs), and performs corresponding display control according to the display data packet.

[0188] In this embodiment, a second clock signal having a clock frequency lower than that of the first clock signal is generated according to a preset clock signal, and the cascaded display modules are then driven by the second clock signal to perform parallel data signal sampling. This can effectively reduce the risks of electromagnetic interference and other risks faced by high-frequency signals during long-distance transmission, thereby improving the stability and reliability of cross-board communication. At the same time, based on the second clock signal, the timing consistency and synchronization of data reception between multiple cascaded display modules are also ensured, further improving the communication stability and display reliability of the display system.

[0189] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0190] In one embodiment, see Figure 2 , provides a serial-to-parallel converter, which is used to execute the display data transmission method recorded in the above embodiment and will not be repeated here.

[0191] The serial-to-parallel converter comprises at least a data processing module, a code rate control module and a buffer module; the data processing module is communicatively connected with the code rate control module and the buffer module respectively.

[0192] It should be noted that the corresponding functions of the data processing module, the bit rate control module and the cache module have been described in detail in the above embodiments and will not be repeated here.

[0193] The serial-to-parallel converter of this embodiment effectively alleviates the resource limitation of the programmable logic module in terms of the number of pins, avoids the interface pressure caused by directly driving a large number of display modules, and improves the scalability and design flexibility of the display system.

[0194] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 10 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store data related to display data transmission. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a display data transmission method is implemented.

[0195] Those skilled in the art will understand that Figure 10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0196] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0197] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0198] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0199] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0200] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0201] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0202] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A display system, characterized in that: The display system includes a display control card and N groups of cascaded display modules; the display control card includes a programmable logic module and a serial-to-parallel converter; M serial data transmission channels are provided between the programmable logic module and the serial-to-parallel converter; P parallel data transmission channels are respectively provided between the serial-to-parallel converter and each group of the cascaded display modules; M is less than N × P; The programmable logic module is configured to perform data encoding processing on the image information to be displayed according to a preset data encoding rule to generate M serial data signals, and transmit the M serial data signals to the serial-to-parallel converter via the M serial data transmission channels; The serial-to-parallel converter is configured to perform signal conversion processing on the M serial data signals according to the preset data encoding rule to obtain N×P parallel data signals corresponding to the N groups of cascaded display modules, and transmit the N×P parallel data signals to the N groups of cascaded display modules via the N×P parallel data transmission channels; The N groups of cascaded display modules are used to perform corresponding display control according to the N×P parallel data signals.

2. The display system according to claim 1, wherein: The serial-to-parallel converter is further used to adjust the voltage of the N×P parallel data signals so that the voltage of each parallel data signal meets a preset voltage condition; the preset voltage condition is determined according to the electrical characteristics of the cascade display module.

3. The display system according to claim 1, wherein: The serial-to-parallel converter includes a data processing module; the data processing module is communicatively connected with the programmable logic module; The programmable logic module is further configured to generate a first clock signal and transmit the first clock signal to the data processing module; The data processing module is configured to extract a plurality of display data packets from each of the serial data signals according to the preset data encoding rule and the first clock signal; and for each display data packet, determine a target parallel data transmission channel that matches the display data packet from the N×P parallel data transmission channels according to a preset data packet mapping relationship; Loading the display data packet into a target parallel data signal corresponding to the target parallel data transmission channel, and transmitting the target parallel data signal to the corresponding cascade display module through the target parallel data transmission channel; The preset data packet mapping relationship includes a corresponding relationship between a plurality of display data packets and a plurality of parallel data transmission channels.

4. The display system according to claim 3, wherein: The serial-to-parallel converter further includes a rate control module; the rate control module is communicatively connected to the data processing module; The bit rate control module is configured to generate a bit rate control signal according to a preset clock signal, and transmit the bit rate control signal to the data processing module; The data processing module is further configured to determine a target data transmission rate of the N×P parallel data signals according to the rate control signal; According to the target data transmission rate, the N×P parallel data signals are transmitted to the N groups of cascaded display modules via the N×P parallel data transmission channels; The target data transmission rate is lower than the data transmission rate of the serial data signal.

5. The display system according to claim 4, wherein: The bit rate control module is communicatively connected with the N groups of cascade display modules; The bit rate control module is further configured to generate a second clock signal according to the preset clock signal, and transmit the second clock signal to the N groups of cascaded display modules; The clock frequency of the second clock signal is lower than the clock frequency of the first clock signal; Each group of the cascaded display modules is further configured to extract a corresponding display data packet from each of the parallel data signals corresponding to the cascaded display modules according to the second clock signal; and perform corresponding display control according to the display data packet.

6. The display system according to claim 4, wherein: The serial-to-parallel converter further includes a cache module; the cache module is communicatively connected to the bit rate control module and the data processing module respectively; The cache module is used to cache the display data packet.

7. A display data transmission method, characterized in that: A serial-to-parallel converter applied to a display control card according to any one of claims 1 to 6, the method comprising: According to a preset data encoding rule, signal conversion processing is performed on the M serial data signals sent by the programmable logic module in the display control card to obtain N×P parallel data signals corresponding to the N groups of cascaded display modules; wherein the M serial data signals are generated by the programmable logic module performing data encoding processing on the image information to be displayed according to the preset data encoding rule; The N×P parallel data signals are transmitted to the N groups of cascade display modules via N×P parallel data transmission channels, so that the N groups of cascade display modules perform corresponding display control according to the N×P parallel data signals.

8. The method according to claim 7, characterized in that The serial data signal is loaded with multiple display data packets; according to the preset data encoding rules, the M serial data signals sent by the programmable logic module in the display control card are subjected to signal conversion processing to obtain N×P parallel data signals corresponding to N groups of cascaded display modules, including: extracting a plurality of display data packets from each of the serial data signals according to the preset data encoding rule and the first clock signal sent by the programmable logic module; For each display data packet, determining a target parallel data transmission channel that matches the display data packet from the N×P parallel data transmission channels according to a preset data packet mapping relationship; wherein the preset data packet mapping relationship includes a correspondence between a plurality of display data packets and a plurality of parallel data transmission channels; The display data packet is loaded into a target parallel data signal corresponding to the target parallel data transmission channel, and the target parallel data signal is transmitted to the corresponding cascade display module through the target parallel data transmission channel.

9. The method according to claim 8, characterized in that The preset data encoding rule is any one of a plurality of encoding rules; the encoding rule includes at least a first encoding rule, a second encoding rule, a third encoding rule and a fourth encoding rule; The first encoding rule is to sequentially load the display data packets corresponding to the red light, green light, and blue light required by each group of the cascaded display modules into the corresponding serial data signals; The second encoding rule is to sequentially load the P groups of display data packets required by each group of the cascaded display modules into the corresponding serial data signals; The P groups of display data packets correspond one-to-one to P parallel data transmission channels respectively; The third encoding rule is to sequentially load N groups of display data packets of the same light color required by the N groups of cascaded display modules into the same serial data signal; The N groups of display data packets of the same light color correspond one-to-one to the parallel data transmission channels corresponding to the corresponding light colors of the N groups of cascaded display modules; The fourth encoding rule is to group the data packet sequences corresponding to the N groups of cascaded display modules according to a preset division step size to obtain L groups of data packet groups; Multiple display data packets in L groups of data packets are sequentially loaded into L serial data signals; L is greater than 1.

10. The method according to claim 8, characterized in that The method further comprises: generating a bit rate control signal according to a preset clock signal; determining a target data transmission rate of the N×P parallel data signals according to the rate control signal; According to the target data transmission rate, the N×P parallel data signals are transmitted to the N groups of cascaded display modules via the N×P parallel data transmission channels; The target data transmission rate is lower than the data transmission rate of the serial data signal.

11. The method according to claim 10, characterized in that The method further comprises: generating a second clock signal according to the preset clock signal, and transmitting the second clock signal to the N groups of the cascaded display modules, so that each group of the cascaded display modules extracts a corresponding display data packet from each of the parallel data signals corresponding to the cascaded display modules according to the second clock signal, and performs corresponding display control according to the display data packet; The clock frequency of the second clock signal is lower than the clock frequency of the first clock signal.

12. A serial-to-parallel converter, characterized in that: The serial-to-parallel converter is used to perform the display data transmission method according to any one of claims 7 to 11; The serial-to-parallel converter comprises at least a data processing module, a bit rate control module and a buffer module; the data processing module is communicatively connected with the bit rate control module and the buffer module respectively.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 7 to 11 are implemented.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 7 to 11 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 7 to 11 are implemented.

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