Storage array, manufacturing method and read-only memory
By introducing encrypted information storage units into read-only memory and using carbon nanotube field effect transistors to control current, the problem of easy leakage of stored information is solved and the security of stored information is improved.
Patent Information
- Application Number
- CN202510588910.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-08
- Publication Date
- 2025-08-08
AI Technical Summary
Existing read-only memory (ROM) storage information is easily leaked through integrated circuit reverse engineering technology, resulting in insufficient security.
An encrypted information storage unit is introduced, and a carbon nanotube field effect transistor is used as the channel material. The current size between the source and drain is controlled by modulation of the gate to form an encrypted information storage unit. It is impossible to determine the storage information through optical recognition technology.
Effectively block the integrated circuit reverse engineering to extract stored information through optical means, improving the security of stored information.
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Figure CN120452507A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic information technology, and in particular to a storage array, a manufacturing method and a read-only memory. Background Art
[0002] Read-Only Memory (ROM) is a nonvolatile memory used to permanently store data. Once data is written to ROM, it remains in place even if power is removed. This makes ROM ideal for storing firmware or other programs that don't need to be changed frequently.
[0003] In traditional ROMs, storage cells are often masks or fuses, which are marked with their stored values by whether or not a current flows through them at the factory. While this method can effectively distinguish the stored information of each storage cell, it is easily accessible to reverse engineering techniques such as ICs, where the information stored in the ROM can be obtained by photographing the layout. This leads to the vulnerability of stored information to leakage and insecurity.
[0004] Therefore, how to improve the security of stored information is an urgent problem that those skilled in the art need to solve. Summary of the Invention
[0005] Based on the above problems, the present application provides a storage array, a manufacturing method and a read-only memory. By introducing an encrypted information storage unit, it can effectively shield the integrated circuit reverse engineering from extracting stored information through optical means, thereby improving the security of the stored information.
[0006] In a first aspect, an embodiment of the present application provides a storage array, the storage array comprising: n encryption information storage units; n is a positive integer;
[0007] The storage array is connected to an address decoder, and is used to determine a corresponding target storage unit from the n encrypted information storage units according to a target word line selected by parsing an input address by the address decoder, and output storage information corresponding to the target storage unit;
[0008] The encryption information storage unit cannot determine the corresponding storage information through optical recognition technology.
[0009] Optionally, the target storage unit includes: a first field effect transistor and a second field effect transistor;
[0010] The drain of the first field effect transistor is connected to a power supply, and the gate is connected to the target word line;
[0011] The drain of the second field effect transistor is connected to the source of the first field effect transistor, and the source is grounded;
[0012] The gate voltage of the second field effect transistor is at a low level;
[0013] The second field effect transistor is one of a first type carbon nanotube field effect transistor or a second type carbon nanotube field effect transistor;
[0014] The first-type carbon nanotube field-effect transistor is used to control the target storage unit to be in a closed state, and the second-type carbon nanotube field-effect transistor is used to control the target storage unit to be in a conducting state.
[0015] Optionally, the first-type carbon nanotube field-effect transistor is a semiconducting carbon nanotube field-effect transistor;
[0016] The semiconductor carbon nanotube field effect transistor is produced by using semiconductor carbon nanotube materials with a purity of not less than 99.9999%.
[0017] Optionally, when the second field effect transistor in the target storage unit is the semiconductor carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 1.
[0018] Optionally, the second-type carbon nanotube field effect transistor is a metallic carbon nanotube field effect transistor or a preset carbon nanotube field effect transistor;
[0019] The purity of the semiconducting carbon nanotube material used to produce the predetermined carbon nanotube field effect transistor is lower than the purity of the semiconducting carbon nanotube material used to produce the semiconducting carbon nanotube field effect transistor.
[0020] Optionally, when the second field effect transistor in the target storage unit is the metallic carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 0.
[0021] Optionally, when the second field effect transistor in the target storage unit is the preset carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 0.
[0022] In a second aspect, an embodiment of the present application provides a method for manufacturing a memory array, the method comprising:
[0023] providing a substrate;
[0024] forming a metallic carbon nanotube material layer in a first region on the substrate based on a preset storage requirement;
[0025] forming a semiconducting carbon nanotube material layer on the metallic carbon nanotube material layer and in the second region based on the preset storage requirement, thereby obtaining a metallic carbon nanotube field-effect transistor and a semiconducting carbon nanotube field-effect transistor;
[0026] A gate layer, a source layer, and a drain layer are formed on the metallic carbon nanotube field effect transistor and the semiconducting carbon nanotube field effect transistor.
[0027] Optionally, the method further includes:
[0028] The substrate is thinned and flattened.
[0029] In a third aspect, an embodiment of the present application provides a read-only memory, which is manufactured by the storage array as described above.
[0030] It can be seen from the above technical solutions that compared with the existing technology, this application has the following advantages:
[0031] The storage array provided in this application includes: n encrypted information storage units, where n is a positive integer. The storage array is connected to an address decoder, and is configured to determine a corresponding target storage unit from the n encrypted information storage units based on a target word line selected by parsing an input address by the address decoder, and output the storage information corresponding to the target storage unit. The encrypted information storage unit cannot be identified by optical recognition technology. Thus, by introducing the encrypted information storage unit, it is possible to effectively shield the integrated circuit from reverse engineering by optical means from extracting the stored information, thereby improving the security of the stored information. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0033] Figure 1 A schematic diagram of the overall circuit structure of a ROM provided in an embodiment of the present application;
[0034] Figure 2 A circuit structure diagram of a ROM storage unit provided in an embodiment of the present application;
[0035] Figure 3 A schematic diagram of the structure of a storage array provided in an embodiment of the present application;
[0036] Figure 4A schematic structural diagram of a carbon nanotube field-effect transistor provided in an embodiment of the present application;
[0037] Figure 5 A circuit diagram of a target storage unit provided in an embodiment of the present application;
[0038] Figure 6 A circuit diagram of another target storage unit provided in an embodiment of the present application;
[0039] Figure 7 A circuit diagram of another target storage unit provided in an embodiment of the present application;
[0040] Figure 8 A flowchart of a method for manufacturing a memory array provided in an embodiment of the present application;
[0041] Figure 9 A schematic diagram of generating a metallic carbon nanotube pattern from stored data provided in an embodiment of the present application. DETAILED DESCRIPTION
[0042] As mentioned above, existing storage cells are prone to leakage, which in turn leads to the problem of insecure stored information. Specifically, in the storage array of existing ROMs, each storage cell is constructed using a mask or fuse, and it is necessary to mark the stored value by whether it is blown by current at the factory. If the mask or fuse is broken, the stored content is 1; if the mask or fuse is not broken, the stored content is 0. In this way, although the stored information can be clearly distinguished, it is easy to use integrated circuit reverse engineering technology to take pictures of the layout for identification, and then obtain the information stored in the ROM, resulting in insecure stored information.
[0043] To address the aforementioned issues, embodiments of the present application provide a memory array, manufacturing method, and read-only memory, wherein the memory array includes: n encrypted information storage cells, where n is a positive integer. The memory array is connected to an address decoder, configured to determine a corresponding target memory cell from the n encrypted information storage cells based on a target word line selected by parsing an input address by the address decoder, and output the storage information corresponding to the target memory cell. The encrypted information storage cells cannot be identified using optical recognition technology.
[0044] In this way, by introducing the encrypted information storage unit, it is possible to effectively shield the integrated circuit reverse engineering from extracting the stored information through optical means, thereby improving the security of the stored information.
[0045] It should be noted that the memory array, manufacturing method, and read-only memory provided in this application can be applied to the field of electronic information technology. The above is only an example and does not limit the application field of the memory array, manufacturing method, and read-only memory provided in this application.
[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0047] Figure 1 A schematic diagram of the overall circuit structure of a ROM provided in an embodiment of the present application. Figure 1 As shown in the figure, during ROM operation, the storage address is input into the address decoder as input information. The address decoder analyzes the storage address and selects the corresponding word line, which is then mapped to a memory cell in the memory array. Finally, the storage information corresponding to the memory cell selected by the word line is output through the output port, completing the entire data reading process. Figure 2 A ROM storage unit circuit structure diagram provided in an embodiment of the present application. Figure 2 The figure shows four memory cells. The gate of the field-effect transistor in each memory cell is connected to a word line. When the word line selects a memory cell, the gate of its field-effect transistor is high. Assuming that the gates of the field-effect transistors in all four memory cells are high, if the mask is disconnected, the output storage information is 1; if the masks are interconnected, the output storage information is 0; if the fuse is disconnected, the output storage information is 1; if the fuse is interconnected, the output storage information is 0.
[0048] Figure 3 A schematic diagram of the structure of a storage array provided in an embodiment of the present application. Figure 3 As shown, the storage array includes: n encryption information storage units; n is a positive integer;
[0049] The storage array is connected to an address decoder, and is used to determine a corresponding target storage unit from the n encrypted information storage units according to a target word line selected by parsing an input address by the address decoder, and output storage information corresponding to the target storage unit;
[0050] The encryption information storage unit cannot determine the corresponding storage information through optical recognition technology.
[0051] Specifically, the memory array provided in the embodiments of the present application includes n encrypted information storage units, where n can be any positive integer such as 1 or 2. Each encrypted information storage unit is connected to a unique storage address in the address decoder via a word line. When a storage address is input to the ROM, the address decoder parses the storage address and sends a word select signal to the memory array using the corresponding word line, thereby outputting the storage information indicated by the corresponding encrypted information storage unit (target storage unit). Figure 4 A schematic diagram of the structure of a carbon nano field effect transistor provided in an embodiment of the present application. Figure 4 As shown, the encrypted information storage unit provided by the present application eliminates traditional masks or fuses and uses carbon nanotube field-effect transistors as the channel material, forming a voltage-controlled current source device that controls the current between the source and drain by modulating the gate. This makes the stored information independent of the layout pattern, solving the problem of optical identification of the stored information in the storage device during integrated circuit reverse engineering.
[0052] Figure 5 A circuit diagram of a target storage unit provided in an embodiment of the present application. Figure 5 As shown, the target memory cell includes: a first field effect transistor and a second field effect transistor;
[0053] The drain of the first field effect transistor is connected to a power supply, and the gate is connected to the target word line;
[0054] The drain of the second field effect transistor is connected to the source of the first field effect transistor, and the source is grounded;
[0055] The gate voltage of the second field effect transistor is at a low level;
[0056] The second field effect transistor is one of a first type carbon nanotube field effect transistor or a second type carbon nanotube field effect transistor;
[0057] The first-type carbon nanotube field-effect transistor is used to control the target storage unit to be in a closed state, and the second-type carbon nanotube field-effect transistor is used to control the target storage unit to be in a conducting state.
[0058] Specifically, the circuit structure of each encrypted information storage unit includes a first field-effect transistor and a second field-effect transistor, both of which are carbon nanotube field-effect transistors. Compared to silicon-based field-effect transistors, the most significant difference between carbon nanotube field-effect transistors and single-crystal silicon field-effect transistors is that the channel material in the storage unit is changed from single-crystal silicon to carbon nanotubes. The drain of the first field-effect transistor is connected to a power supply, the gate is connected to a word line, and the source is connected to the drain of the second field-effect transistor. The gate voltage of the second field-effect transistor is low, and its source is grounded. The target word line is the word line that transmits the word select signal, which corresponds to the address input to the address decoder and the selected target storage unit. At this time, the bit select is high, and the polarity of the second field-effect transistor determines whether the circuit is conductive, thereby distinguishing the stored information. It is understood that the second field-effect transistor includes a first-type carbon nanotube field-effect transistor and a second-type carbon nanotube field-effect transistor. Each encrypted information storage unit needs to decide whether to select the first-type carbon nanotube field-effect transistor or the second-type carbon nanotube field-effect transistor as the second field-effect transistor connected to the circuit based on the information to be stored. The first type of carbon nanotube field effect transistor can control the circuit to be in an off state, and the second type of carbon nanotube field effect transistor can control the circuit to be in an on state.
[0059] As an embodiment, regarding how to design a first-type carbon nanotube field-effect transistor, the first-type carbon nanotube field-effect transistor is a semiconductor carbon nanotube field-effect transistor;
[0060] The semiconductor carbon nanotube field effect transistor is produced by using semiconductor carbon nanotube materials with a purity of not less than 99.9999%.
[0061] Specifically, the diameters of the first and second carbon nanotube field-effect transistors range from 1 to 3 nm. Within the encrypted information storage unit, they can be divided into array and network structures based on the manufacturing process. The conductive properties of carbon nanotubes are determined by the energy difference between their band gaps. Semiconducting carbon nanotube field-effect transistors can be selected as the first-type carbon nanotube field-effect transistors, thereby ensuring that the target storage unit can be controlled to be in an off state when the gate voltage is low and the bit select is high. It is understood that the channel material of the semiconducting carbon nanotube field-effect transistor requires extremely high purity (greater than 99.9999%) of semiconducting carbon nanotube material.
[0062] Figure 6 A circuit diagram of another target storage unit provided in an embodiment of the present application. Figure 6 As shown, when the second field effect transistor in the target storage unit is the semiconductor carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 1.
[0063] Specifically, when the second field effect transistor in the target memory cell is a semiconductor carbon nanotube field effect transistor, since its gate voltage is a low voltage, the target memory cell is in a closed state, and the output result is 1 at this time.
[0064] As an embodiment, regarding how to design a second-type carbon nanotube field-effect transistor, the second-type carbon nanotube field-effect transistor is a metallic carbon nanotube field-effect transistor or a preset carbon nanotube field-effect transistor;
[0065] The purity of the semiconducting carbon nanotube material used to produce the predetermined carbon nanotube field effect transistor is lower than the purity of the semiconducting carbon nanotube material used to produce the semiconducting carbon nanotube field effect transistor.
[0066] Specifically, a metallic carbon nanotube field effect transistor or a preset carbon nanotube field effect transistor (low-purity carbon nanotube field effect transistor) can be selected as the second type of carbon nanotube field effect transistor, thereby ensuring that the target storage unit can be controlled to be in the on state when the gate voltage is low and the bit select is high.
[0067] Figure 7 A circuit diagram of another target storage unit provided in an embodiment of the present application. Figure 7 As shown, when the second field effect transistor in the target storage unit is the metallic carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 0.
[0068] Specifically, when the second field effect transistor in the target memory cell is a metallic carbon nanotube field effect transistor, although its gate voltage is low, the channel is still in the on state due to the presence of the metallic carbon nanotubes, and the output result is 0 at this time.
[0069] As an implementation manner, regarding how to set the second field effect transistor, when the second field effect transistor in the target storage unit is the preset carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 0.
[0070] Specifically, when the second field effect transistor in the target memory cell is a preset carbon nanotube field effect transistor, since the purity of the semiconductor carbon nanotube material contained therein is low, the channel is still in the on state even though the gate voltage is low, and the output result is 0.
[0071] In summary, the storage array provided in this application includes: n encrypted information storage units, where n is a positive integer. The storage array is connected to an address decoder, configured to determine a corresponding target storage unit from the n encrypted information storage units based on a target word line selected by parsing an input address by the address decoder, and output the storage information corresponding to the target storage unit. The encrypted information storage unit cannot be identified by optical recognition technology. Thus, by introducing the encrypted information storage unit, it is possible to effectively shield the integrated circuit from reverse engineering by optical means from extracting the stored information, thereby improving the security of the stored information.
[0072] Figure 8 A flowchart of a method for manufacturing a memory array provided in an embodiment of the present application. Figure 8 As shown, the method for manufacturing the memory array as described above comprises:
[0073] S1: providing a substrate.
[0074] In practical applications, a metallic carbon nanotube field-effect transistor (FET) and a semiconducting FET can be stacked to construct an encrypted information storage unit. In this case, a semiconducting FET is used as the first FET. Depending on the type of information being stored, a metallic or semiconducting FET is then selected as the second FET, stacked with the first to form a complete storage array. Specifically, a chip substrate is first provided.
[0075] In addition, since the pre-processing methods for the substrate are different, the embodiments of the present application can illustrate a possible pre-processing method.
[0076] In one embodiment, the method further comprises:
[0077] The substrate is thinned and flattened.
[0078] In practical applications, the substrate material needs to be thinned and smoothed before depositing the metallic carbon nanotube material layer.
[0079] S2: forming a metallic carbon nanotube material layer in a first region on the substrate based on preset storage requirements.
[0080] In practical applications, you can choose to first construct a metallic carbon nanotube material layer and then construct a semiconducting carbon nanotube material layer in a superposition manner, or you can choose to first construct a semiconducting carbon nanotube material layer and then construct a metallic carbon nanotube material layer in a superposition manner. In the embodiment of the present application, taking the construction of the metallic carbon nanotube material layer as an example, S2 specifically includes two steps (S201 and S202). Among them, S201 is to prepare a layer of metallic carbon nanotube material on the surface of the substrate by growth, deposition, solution adhesion, etc. S202 is to remove the metallic carbon nanotube material layer outside the first area by etching. It can be understood that the first area is specified by the preset storage requirements, and the storage information referred to by this area is 0. In addition, the metallic carbon nanotube material can be replaced with a low-purity carbon nanotube material or directly with a metal layer.
[0081] S3: forming a semiconducting carbon nanotube material layer on the metallic carbon nanotube material layer and in the second region based on the preset storage requirement to obtain a metallic carbon nanotube field effect transistor and a semiconducting carbon nanotube field effect transistor.
[0082] In practical applications, S3 also includes two steps (S301 and S302). S301 involves forming a layer of semiconducting carbon nanotube material on the substrate surface by growth, deposition, solution adhesion, or other methods. S302 involves removing the semiconducting carbon nanotube material layer outside the first region (B) and the second region (A) by etching. It is understood that the second region is also specified by a preset storage requirement, and the storage information referred to by this region is 1.
[0083] S4: forming a gate layer, a source layer, and a drain layer on the metallic carbon nanotube field effect transistor and the semiconducting carbon nanotube field effect transistor.
[0084] In practical applications, after constructing metallic carbon nanotube field-effect transistors and semiconducting carbon nanotube field-effect transistors, a gate layer, a source layer, and a drain layer are constructed on top of them based on conventional production process flow to obtain a storage array.
[0085] Figure 9 A schematic diagram of generating a metallic carbon nanotube pattern from stored data provided in an embodiment of the present application. Figure 9As shown, when both the first field-effect transistor and the second field-effect transistor are semiconducting carbon nanotube field-effect transistors, the value stored in the encrypted information storage unit is 1; and when the transistors are semiconducting carbon nanotube field-effect transistors superimposed on metallic carbon nanotube field-effect transistors, the value stored in the encrypted information storage unit is 0. To this end, the present embodiment also proposes a method for dynamically changing the ROM content during the production process. This method uses a mask to produce the chip's other layers except the metallic carbon nanotube material layer, and uses a direct-write maskless lithography machine to produce the pattern of the metallic carbon nanotube material layer. In this way, dynamic changes in the storage content of the carbon nanotube field-effect transistor ROM chip can be achieved, improving application flexibility.
[0086] In summary, the present application provides a method for manufacturing a storage array, which first provides a substrate. Then, based on preset storage requirements, a metallic carbon nanotube material layer is formed in a first region on the substrate; based on the preset storage requirements, a semiconducting carbon nanotube material layer is formed on the metallic carbon nanotube material layer and in a second region to obtain a metallic carbon nanotube field effect transistor and a semiconducting carbon nanotube field effect transistor. Finally, a gate layer, a source layer, and a drain layer are formed on the metallic carbon nanotube field effect transistor and the semiconducting carbon nanotube field effect transistor to form a storage array. In this way, the introduction of an encrypted information storage unit can effectively shield the integrated circuit reverse engineering from extracting stored information through optical means, thereby improving the security of the stored information.
[0087] In addition, an embodiment of the present application provides a read-only memory, which is manufactured by the memory array described above.
[0088] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A storage array, characterized in that: The storage array comprises: n encryption information storage units; n is a positive integer; The storage array is connected to an address decoder, and is used to determine a corresponding target storage unit from the n encrypted information storage units according to a target word line selected by parsing an input address by the address decoder, and output storage information corresponding to the target storage unit; The encryption information storage unit cannot determine the corresponding storage information through optical recognition technology.
2. The storage array according to claim 1, wherein: The target storage unit includes: a first field effect transistor and a second field effect transistor; The drain of the first field effect transistor is connected to a power supply, and the gate is connected to the target word line; The drain of the second field effect transistor is connected to the source of the first field effect transistor, and the source is grounded; The gate voltage of the second field effect transistor is at a low level; The second field effect transistor is one of a first type carbon nanotube field effect transistor or a second type carbon nanotube field effect transistor; The first-type carbon nanotube field-effect transistor is used to control the target storage unit to be in a closed state, and the second-type carbon nanotube field-effect transistor is used to control the target storage unit to be in a conducting state.
3. The storage array according to claim 2, wherein: The first type carbon nanotube field effect transistor is a semiconducting carbon nanotube field effect transistor; The semiconductor carbon nanotube field effect transistor is produced by using semiconductor carbon nanotube materials with a purity of not less than 99.9999%.
4. The storage array according to claim 3, wherein: When the second field effect transistor in the target storage unit is the semiconducting carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 1.
5. The storage array according to claim 3, wherein: The second-type carbon nanotube field effect transistor is a metallic carbon nanotube field effect transistor or a preset carbon nanotube field effect transistor; The purity of the semiconducting carbon nanotube material used to produce the predetermined carbon nanotube field effect transistor is lower than the purity of the semiconducting carbon nanotube material used to produce the semiconducting carbon nanotube field effect transistor.
6. The storage array according to claim 5, wherein: When the second field effect transistor in the target storage unit is the metallic carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 0.
7. The storage array according to claim 5, wherein: When the second field effect transistor in the target storage unit is the preset carbon nanotube field effect transistor, the storage information corresponding to the target storage unit is 0.
8. A method for manufacturing a memory array, characterized in that: The method comprises: providing a substrate; forming a metallic carbon nanotube material layer in a first region on the substrate based on preset storage requirements; forming a semiconducting carbon nanotube material layer on the metallic carbon nanotube material layer and in the second region based on the preset storage requirement, thereby obtaining a metallic carbon nanotube field-effect transistor and a semiconducting carbon nanotube field-effect transistor; A gate layer, a source layer, and a drain layer are formed on the metallic carbon nanotube field effect transistor and the semiconducting carbon nanotube field effect transistor.
9. The method according to claim 8, characterized in that The method further comprises: The substrate is thinned and flattened.
10. A read-only memory, characterized in that: The read-only memory is made by the memory array according to any one of claims 1 to 7.