Semiconductor package design with terminal for connection to external capacitor

Abstract

Embodiments of the present disclosure relate to a semiconductor package design having a terminal for connection to an external capacitor. The present disclosure relates to a packaged semiconductor component and a circuit assembly including such a packaged semiconductor component and a capacitor. The packaged semiconductor component includes a semiconductor die including a field effect transistor, a side source terminal positioned on a first side of the packaged semiconductor component and connected to a source of the field effect transistor, and a drain terminal positioned on a second side of the packaged semiconductor component and connected to a drain of the field effect transistor. And a drain terminal positioned on the second side of the packaged semiconductor component and connected to the field effect transistor drain, wherein the first side is adjacent to the second side. The capacitor is electrically connected between the source terminal and the drain terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 550,927, filed February 7, 2024, entitled “SEMICONDUCTOR PACKAGE DESIGN WITH CONTACTS FOR CONNECTING TO EXTERNAL CAPACITOR,” the disclosure of which is hereby incorporated by reference in its entirety and for all purposes. Technical Field

[0003] The present disclosure relates to semiconductor packages. Specifically, embodiments of the present disclosure relate to semiconductor packages having contacts to achieve low parasitic inductance for connecting to external capacitors and related manufacturing methods. Background Art

[0004] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices may incorporate multiple electrically connected components. Such connections can result in undesirable parasitic inductance. Parasitic inductance can also lead to technical problems, such as distortion of electrical signals between components. Summary of the Invention

[0005] The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some of the prominent features of the disclosure will now be briefly described.

[0006] One aspect of the present disclosure is a circuit assembly comprising a packaged semiconductor component and a capacitor. The packaged semiconductor component includes a semiconductor die including a field-effect transistor, a side source terminal, and a drain terminal. The side source terminal is positioned on a first side of the packaged semiconductor component and connected to the source of the field-effect transistor. The drain terminal is positioned on a second side of the packaged semiconductor component and connected to the drain of the field-effect transistor. The capacitor is electrically connected between the source terminal and the drain terminal. The first side is adjacent to the second side. The capacitor is external to the packaged semiconductor component and electrically connected between the source terminal and the drain terminal.

[0007] In one embodiment, the circuit assembly further comprises a printed circuit board. The packaged semiconductor component and the capacitor are positioned on the printed circuit board. The packaged semiconductor component further comprises a heat sink opposite the printed circuit board. In addition, the side source terminal provides a mechanical support point for the heat sink.

[0008] In one embodiment, the packaged semiconductor component further comprises a plurality of additional drain terminals on the second side and connected to the drain of the field effect transistor, and a plurality of source terminals on a third side of the packaged semiconductor component and connected to the source of the field effect transistor, wherein the third side is opposite to the second side.

[0009] In one embodiment, the packaged semiconductor component further includes a second side source terminal on an opposite side to the first side.

[0010] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a leadframe.

[0011] In one embodiment, the circuit assembly further includes a second packaged semiconductor component and a second capacitor electrically connected between lateral source and drain terminals of the second packaged semiconductor component. The second packaged semiconductor component is rotated 180 degrees relative to the packaged semiconductor component.

[0012] In one embodiment, the circuit assembly further comprises a printed circuit board. The printed circuit board comprises traces, and the capacitor is connected to one of the traces.

[0013] Another aspect of the present disclosure is a packaged semiconductor component. The packaged semiconductor component includes a semiconductor die including a field-effect transistor having a source, a gate, and a drain, a plurality of drain terminals, a side source terminal, and a plurality of source terminals. The plurality of drain terminals are on a first side of the packaged semiconductor component and connected to the drain, the side source terminals are on a second side of the packaged semiconductor component and connected to the source, and the plurality of source terminals are on a third side of the packaged semiconductor component and connected to side source terminals within the packaged semiconductor component. The third side is opposite the first side, and the second side is adjacent to both the first side and the third side. In addition, the side source terminal is positioned closer to the first side than the third side.

[0014] In one embodiment, the packaged semiconductor component further comprises: a surface configured to be coupled to a printed circuit board; and a heat sink opposite the surface. Furthermore, the side source terminals provide mechanical support for the heat sink. Furthermore, the heat sink has a recess around the side source terminals. Furthermore, the heat sink has a recess around the side source terminals.

[0015] In one embodiment, each of the first side and the second side of the packaged semiconductor component comprises a lead frame. In addition, the lead frame comprises a stamped flat end portion.

[0016] In one embodiment, the gate is positioned on a third side of the packaged semiconductor component.

[0017] In one embodiment, the packaged semiconductor component further comprises a gate terminal positioned on a third side of the packaged semiconductor component.

[0018] Another aspect of the present disclosure is a circuit assembly comprising a packaged semiconductor component. The packaged semiconductor component includes a semiconductor die including a field-effect transistor having a source, a gate, and a drain; a drain terminal connected to the drain; and a source terminal connected to the source, wherein the drain terminal and the source terminal are on the same side of the packaged semiconductor component. The circuit assembly also includes a capacitor external to the packaged semiconductor component, with the capacitor electrically connected between the source terminal and the drain terminal.

[0019] In one embodiment, the circuit assembly further includes a second capacitor external to the packaged semiconductor component, and the packaged semiconductor component includes a second source terminal that is on the same side of the packaged semiconductor component as the drain terminal and the source terminal. Furthermore, the second capacitor is electrically connected between the second source terminal and the drain.

[0020] In one embodiment, the circuit assembly further comprises a printed circuit board, and the packaged semiconductor component and the capacitor are positioned on the printed circuit board. In addition, the packaged semiconductor component further comprises a heat sink opposite to the printed circuit board.

[0021] In one embodiment, the packaged semiconductor component includes a gate terminal and a Kelvin source terminal on a side opposite to the same side as the drain terminal and the source terminal.

[0022] In one embodiment, the packaged semiconductor component comprises a plurality of additional source terminals located on a side opposite to the same side where the drain terminal and the source terminal are located.

[0023] In one embodiment, the packaged semiconductor component comprises at least one additional drain terminal on the same side as the drain terminal and the source terminal, and the at least one additional drain terminal is electrically connected to a capacitor external to the packaged semiconductor component.

[0024] Another aspect of the present disclosure is a circuit assembly comprising a packaged semiconductor component. The packaged semiconductor component comprises a semiconductor die including a field effect transistor having a source, a gate, and a drain; a plurality of drain terminals on a first side of the packaged semiconductor component and connected to the drain; a side source terminal on a second side of the packaged semiconductor component and connected to the source; and a plurality of source terminals on a third side of the packaged semiconductor component and connected to the side source terminals within the packaged semiconductor component. The first side is opposite to the second side, and the third side is orthogonal to the first and second sides. The circuit assembly also comprises a printed circuit board, wherein the packaged semiconductor component is positioned on the printed circuit board, and a capacitor is on the printed circuit board. The capacitor is electrically connected between a drain terminal of the plurality of drain terminals and the side source terminal.

[0025] In one embodiment, the packaged semiconductor component further comprises a heat sink opposite the printed circuit board. In addition, the heat sink has a recess around the side source terminal. In addition, the side source terminal provides mechanical support for the heat sink.

[0026] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a lead frame, and the lead frame further includes stamped flat ends.

[0027] To summarize this disclosure, certain aspects, advantages, and novel features of the innovations are described herein. It should be understood that not all of these advantages may be achieved according to any particular embodiment. Thus, an innovation may be embodied or performed in a manner that achieves or optimizes one advantage or group of advantages taught herein without necessarily achieving other advantages taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] These and other features, aspects and advantages of the present disclosure are described with reference to the accompanying drawings of certain embodiments. It should be understood that the accompanying drawings are incorporated in and constitute a part of this specification for the purpose of illustrating the concepts disclosed herein and that the drawings are not drawn to scale.

[0029] Figure 1A An example of a circuit assembly according to some embodiments is illustrated.

[0030] Figure 1B Pictured Figure 1A An example of a schematic circuit diagram of the circuit components and external capacitors.

[0031] Figure 1C Another example of a circuit assembly according to some embodiments is illustrated.

[0032] Figure 2A Illustrated is an example of a top-side view of a semiconductor component according to an embodiment of the present disclosure.

[0033] Figure 2BPictured Figure 2A Example of a bottom side view of a semiconductor component.

[0034] Figure 3A Illustrated is an example of an exploded view of a packaged semiconductor component according to an embodiment of the present disclosure.

[0035] Figure 3B An example of an array assembly of packaged semiconductor components according to an embodiment of the present disclosure is illustrated.

[0036] Figure 4 An example of a cross-sectional view of a semiconductor component according to an embodiment of the present disclosure is illustrated.

[0037] Figure 5 An example of a circuit assembly system having two semiconductor packages according to an embodiment of the present disclosure is illustrated.

[0038] Figure 6 An example of a circuit assembly system is illustrated that implements a capacitor on top of the circuit assembly system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The following detailed description of certain embodiments provides various descriptions of specific embodiments. However, the innovations described herein may be embodied in a variety of different ways, for example, as defined and encompassed by the claims. In this description, reference is made to the accompanying drawings in which the same reference numerals and / or terms may indicate identical or functionally similar elements. It will be understood that the elements illustrated in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that certain embodiments may include more elements and / or a subset of the elements illustrated in the drawings than illustrated in the drawings. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the drawings. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

[0040] Introduction

[0041] Electronic components comprising one or more integrated circuit (IC) dies can be deployed in a variety of applications and under a variety of environmental conditions. For example, such components can form part of a power electronics system. In some cases, a power electronics system can be used to provide power for electric vehicles. In some applications, a power electronics system can be part of a fixed energy storage system, such as a system for storing solar energy, a system for delivering electricity to a destination, and the like. These are just examples, and such systems have many other applications. In some cases, the components can include diode switches, field effect transistors (FETs), such as metal oxide semiconductor FETs (MOSFETs) (e.g., silicon MOSFETs, GaN MOSFETs, etc.), insulated gate bipolar transistors (IGBTs), other bipolar transistors, and the like, or any suitable combination thereof. Such switches can be included in inverters. In certain applications, the switches in the packaged semiconductor components disclosed herein can switch voltages in the range of 1 volt (V) to 150V, such as switching voltages in the range of 12V to 150V.

[0042] Snubber capacitors may be used in certain switching components to reduce and / or eliminate voltage transients and / or ringing associated with the switches. It may be desirable to reduce and / or minimize the parasitic inductance associated with a snubber capacitor connected between the terminals of a switching device. Embodiments of the present disclosure may provide low parasitic inductance associated with a snubber capacitor connected between the terminals of a switching device and associated packaging components for connection to the snubber capacitor.

[0043] Power electronics systems can generate a lot of heat. This heat can cause serious problems. For example, overheating can lead to performance degradation, reduced reliability, shortened life, etc. For example, excessive thermal stress can weaken solder joints, damage semiconductor components, or both. In some applications, surge loads can cause temperatures to rise rapidly. High surge loads can be encountered in various applications, such as when starting portable compressors, HVAC systems, refrigeration systems, electric motors, power converters, etc. In some semiconductor package designs, a cooling solution can be implemented in the semiconductor package to dissipate heat. In some cases, the semiconductor package can be designed to dissipate heat through a printed circuit board (PCB). For example, top-side cooling can be used to cool the IC, for example, as described in U.S. Patent No. 10,658,276, entitled "Device with top-side base plate," the disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

[0044] Certain semiconductor packages (e.g., semiconductor component packages) may include die connection terminals (e.g., contact terminals), such as the source, drain, and gate of a field-effect transistor semiconductor component. The source and drain terminals may be implemented on opposite ends of the body of the semiconductor component. For example, the switch terminals of the semiconductor component may be arranged so that the source and drain are implemented opposite each other. Some semiconductor components may include an exposed heat sink facing downward toward the surface of a carrier (such as a PCB). In a top-side cooling device with an exposed heat sink at drain potential, the terminals on the side of the device adjacent to the side with the source terminal and the side with the drain terminal may not be in electrical contact with the PCB. The source and drain terminals may be electrically contacted with other components via traces embedded and / or etched on a printed circuit board (PCB). For example, these terminals may be electrically connected to a power generation component that provides a high-frequency switching input power signal (e.g., a signal for a digital-to-analog converter and / or an analog-to-digital converter) via PCB traces. However, these traces may generate parasitic effects, such as parasitic inductance. This parasitic inductance may cause signal distortion of high-speed switching signals, impedance mismatch, signal noise, etc., or any combination thereof.

[0045] The shape and height of the conductive elements of a semiconductor package can also have detrimental parasitic inductances at certain switching frequencies. Therefore, there is a need for a die package that facilitates operation with relatively low parasitic effects, such as parasitic inductances. Such a semiconductor chip package can be designed to have a low profile and fit close to internal components on a PCB when mounted.

[0046] Package Design

[0047] Various aspects of the present disclosure relate to a semiconductor chip package (e.g., a semiconductor package) having a lead frame and (multiple) electrical components that can reduce and / or minimize parasitic effects. Specifically, the semiconductor chip package can include various traces to electrically connect between the integrated components of the semiconductor chip package. Such traces can generate unwanted parasitic inductances, and (multiple) electrical components can be integrated in the semiconductor chip package to alleviate these unwanted parasitic inductances. In addition, each semiconductor component can include a lead frame and implement (multiple) electrical components. Such a lead frame can be formed to have a desired shape and can provide a heating solution for the semiconductor package. In some cases, the lead frame also provides electrical connections between the terminals of the semiconductor component. For example, the lead frame can provide electrical connections to the back of the die and the top surface of the semiconductor die. The lead frame can also be a formable shape (e.g., a preformed lead frame) and can be implemented as a conductor with a pre-positioned or arranged shape during the assembly process.

[0048] In some cases, electrical components can be implemented to reduce and / or minimize parasitic effects. For example, capacitors and connections to semiconductor packages can be arranged to achieve low parasitic inductance. When high-speed switching signals are applied to the inputs of semiconductor components, parasitic inductance can be generated between traces of a carrier (such as a PCB). To reduce and / or minimize parasitic inductance, capacitors (such as buffer capacitors) can be implemented between the traces.

[0049] In the embodiments disclosed herein, capacitors and source and drain terminals can be implemented to reduce and / or minimize parasitic inductance. The source and drain terminals of a semiconductor package can be connected via a capacitor. The placement of the source and drain leads of the semiconductor package can allow for a compact connection between the capacitor and the source and drain leads. In the present disclosure, this capacitor connected between the source and drain of a switching device may generally be referred to as a "snubber capacitor." During operation of the semiconductor component (such as high-speed switching), the source and drain leads can be connected via a snubber capacitor component via a PCB trace. The source-capacitor-drain connection influences ringing or voltage overshoot in the semiconductor switching waveform, thereby forming a tight current path and / or a "triangle" loop region. In experiments in which a snubber capacitor was implemented on the semiconductor package to directly bridge the drain and source, parasitic inductance was reduced. In some embodiments, by providing a snubber capacitor on either side of the PCB layout, two source lead frames can be extended on both sides of the semiconductor component.

[0050] In the embodiments disclosed herein, heat transfer can be concentrated on the top side of the semiconductor package. In certain applications, top side cooling may be ideal, for example due to bottom side mounting surface temperature, PCB layout and / or feature considerations. The technology disclosed herein can be applied to double-sided cooled semiconductor packages. Certain designs can have conductor elements exposed on the top and bottom, and can have design features that maintain position during assembly and mold encapsulation. This can control molding flash and resin oozing. Therefore, the need for grinding can be reduced or eliminated.

[0051] Figure 1A A circuit assembly 100A according to an embodiment of the present disclosure is illustrated. For illustrative purposes, the circuit assembly 100A is illustrated as a package having a single packaged semiconductor component 110. However, the circuit assembly 100A may include multiple packaged semiconductor components 110, and the present disclosure does not limit the number of packaged semiconductor components 110. Figure 1A As shown in FIG, the circuit assembly 100A may include a packaged semiconductor component 110, traces 120, 130, 140, and a capacitor 150. The packaged semiconductor component 110 may be implemented on a carrier, such as a PCB ( Figure 1A (not shown in the figure). Packaged semiconductor component 110 can be electrically connected to other components (such as other power components, other semiconductor components, etc.) via the PCB. For example, traces 120, 130, 140 can be etched onto the PCB and configured to provide electrical contact areas or lines between packaged semiconductor component 110 and other components. Traces 120, 130, 140 can each have any suitable shape and / or area for a particular application.

[0052] Trace 120 can provide electrical contact to a designated terminal (e.g., drain terminal 122 of packaged semiconductor component 110). Trace 130 can provide electrical contact to another set of designated terminals (e.g., source terminal 132 of packaged semiconductor component 110). Trace 140 can provide electrical contact to a designated terminal (e.g., gate terminal 142 of packaged semiconductor component 110). In some cases, trace 135 can be combined with trace 130 and provide a contact area for the source of packaged semiconductor component 110. Alternatively, terminal 134 and trace 135 can be arranged as a Kelvin source. These configurations are provided as examples, and the configurations can be modified based on the specific application.

[0053] like Figure 1A As further illustrated in FIG, capacitor 150 may have ends connected to corresponding traces. For example, trace 120 and trace 130 may be capacitively coupled via capacitor 150. Such capacitor 150 may be referred to as a buffer capacitor. Capacitor 150 may be utilized to mitigate unwanted signals, such as voltage spikes, generated by parasitic effects (e.g., parasitic inductance caused by inductive coupling of traces 120 and 130), which may occur during high-speed switching operations of circuit components. For example, parasitic inductance caused by two adjacent traces (such as between trace 120 and trace 130) may result in parasitic inductance. In embodiments of the present disclosure, these parasitic effects caused by inductive coupling between traces may be mitigated by capacitor 150. For example, capacitor 150 may absorb energy associated with voltage spikes. In some cases, capacitor 150 may be soldered to traces 120 and 130. The capacitance value of capacitor 150 may be determined based on the applied input signal (e.g., one or more of the applied voltage, frequency, or waveform) and the distance between the traces. Capacitor 150 may be any suitable capacitor specified for circuit assembly 100A.

[0054] Figure 1B Pictured Figure 1ASchematic circuit diagram of the circuit assembly 100A and the capacitor 150. The drain terminal(s) 122, source terminal(s) 132 (including 132A, 132B), gate terminal 142 and Kelvin source 134 of the packaged semiconductor component 110 may correspond to Figure 1B 122, 132, 142 and 134 of the schematic view. Figure 1A Traces 120, 130, 140, and 135 in Figure 1B The same reference numerals are used in the figures. Figure 1B As shown in FIG, the capacitor 150 may be connected between the drain terminal(s) 122 and the source terminal(s) 132 of the packaged semiconductor component 110. Figure 1A As further illustrated in FIG, the packaged semiconductor component 110 may also provide source terminals 132A, 132B on both sides of the packaged semiconductor component 110.

[0055] Figure 1C FIG. 1 illustrates a circuit assembly 100B according to an embodiment of the present disclosure. Figure 1C As shown in FIG, the circuit assembly 100B is Figure 1A The circuit assembly 100A shown in FIG. 1 includes an additional capacitor 155. Traces 120 and 130 of the circuit assembly 100B are also shaped and configured to connect the additional capacitor 155 between the source terminal 132 and the drain terminal 122 of the packaged semiconductor component 110. Similar components of the circuit assembly 100B may function similarly to Figure 1A Similar components of circuit assembly 100A function similarly or identically. For ease of illustration, circuit assembly 100B is illustrated as a package having a single packaged semiconductor component 110. However, circuit assembly 100B may include multiple packaged semiconductor components 110, and the present disclosure is not limited to the number of packaged semiconductor components 110.

[0056] like Figure 1CAs shown in FIG, each of capacitor 150 and additional capacitor 155 can have an end connected to a corresponding trace. For example, trace 120 and trace 130 can be capacitively coupled via capacitor 150 and additional capacitor 155 on opposite sides of packaged semiconductor component 110. Each of capacitor 150 and additional capacitor 155 can mitigate unwanted signals, such as voltage spikes, generated by parasitic effects (e.g., parasitic inductance caused by inductive coupling of traces 120 and 130), which may occur during high-speed switching operations of circuit assembly 100B. For example, parasitic inductance caused by two adjacent traces (such as between trace 120 and trace 130) can result in parasitic inductance. In embodiments of the present disclosure, these parasitic effects caused by inductive coupling between traces can be mitigated by capacitor 150 and additional capacitor 155. For example, each of capacitor 150 and additional capacitor 155 can absorb energy associated with the voltage spike. In some cases, each of capacitor 150 and additional capacitor 155 can be soldered to traces 120 and 130. In some applications, placing two capacitors 150 and 155 in parallel with each other can be beneficial to mitigate parasitic effects. The capacitance value of each of capacitor 150 and additional capacitor 155 can be determined based on the applied input signal (e.g., one or more of the applied voltage, frequency, or waveform) and the distance between the traces. Each of capacitor 150 and additional capacitor 155 can be any suitable capacitor for the specifications of circuit assembly 100B.

[0057] Figure 2A The diagram shows a Figure 1A 1 is a top-side view of a packaged semiconductor component 110. The packaged semiconductor component 110 may include a packaging structure 310 that may surround the packaged semiconductor component 110. The packaging structure 310 may be made of a rigid molding resin. The packaging structure 310 may be placed on top of a die paddle 320. The die paddle 320 may be referred to as a "clip." The die paddle 320 may be used as a heat sink in any suitable embodiment disclosed herein. In some cases, the heat sink may be a top-side heat sink with a relatively large area. The die paddle 320 may be used to provide an electrical connection to the top surface of the packaged semiconductor component 110 and may be used as a heat sink. In some examples, the semiconductor package assembly or manufacturing orientation may favor the die paddle 320 being assembled last on top of the die, where this may be referred to as a "clip." The package structure may also include molding material. The packaged semiconductor component 110 may include a bottom side that includes stamped leads. The stamped leads may be flat.

[0058] Figure 2B The diagram shows a Figure 1A1 is a bottom view of a packaged semiconductor component 110. The packaged semiconductor component 110 may include drain terminal(s) 122, source terminal(s) 132 (including 132A, 132B), gate terminal 142, and Kelvin source terminal 134. The packaged semiconductor component 110 may be assembled on top of a PCB, wherein the top of the PCB provides various traces, such as traces 120, 130, 140, and / or 135, as shown. Figure 1A In some embodiments, each of the drain terminal(s) 122, source terminal(s) 132 (including 132A, 132B), gate terminal 142, and Kelvin source terminal 134 can be electrically connected to one of the traces by assembling the packaged semiconductor component 110 on top of the PCB. For example, each of the drain terminal(s) 122, source terminal(s) 132 (including 132A, 132B), gate terminal 142, and Kelvin source terminal 134 can provide a contact for monitoring the packaged semiconductor component 110 (e.g., a contact for a temperature sensor such as a thermocouple), etc. by contacting its corresponding trace. In some embodiments, the drain terminal(s) 122, source terminal(s) 132 (including 132A, 132B), gate terminal 142, and Kelvin source terminal 134 can extend outside the body of the packaged semiconductor component 110 by contacting its corresponding trace. In some embodiments, drain terminal(s) 122, source terminal(s) 132 (including 132A, 132B), gate terminal 142, and Kelvin source terminal 134 can be flush with the outer surface of packaged semiconductor component 110 by contacting their corresponding traces. In some embodiments, drain terminal(s) 122, source terminal(s) 132 (including 132A, 132B), gate terminal 142, and Kelvin source terminal 134 can be recessed from the outer surface of packaged semiconductor component 110 in one or more orientations by contacting their corresponding traces. Kelvin source terminal 134 can be provided as a terminal that provides decoupling of current paths (e.g., control current path and load current path). In some embodiments, Kelvin source terminal 134 can be combined with source 132 (e.g., to form a signal pad).

[0059] Packaged semiconductor component 110 may include side source terminals 132A and 132B. These side source terminals 132A and 132B may be electrically connected to source terminal 132 within packaged semiconductor component 110 via a common trace. For example, trace 130 may be shaped to cover the area of side source terminals 132A and 132B and source terminal 132. As illustrated, side source terminals 132A and 132B are positioned on a side of packaged semiconductor component 110, while other source terminals 132 and drain terminal 122 are positioned on other corresponding sides of packaged semiconductor component 110. Molding material and die pad 320 may have corresponding recesses around side source terminals 132A and 132B. These recesses may be used to recess the terminals to make side source terminals 132A and 132B less conspicuous during handling or to reduce spacing between other components within a PCB layout. The shape and position of these notches can provide sufficient electrical surface creepage distance to mitigate and / or prevent arcing between adjacent terminals of different voltages or functions. The side source terminals 132A and 132B are each on a side of the packaged semiconductor component 110 that is adjacent to the other source terminals 132 and is also adjacent to the drain terminal 122. The side source terminals 132A and 132B are positioned closer to the nearest drain terminal 122 than to the nearest other source terminals 132. The side source terminals 132A and 132B can also provide mechanical structure for the packaged semiconductor component 110. For example, when the packaged semiconductor component 110 is assembled, these side source terminals 132A and 132B can provide mechanical support during and / or after the manufacturing process of the packaged semiconductor component 110 (including the die pad 320).

[0060] In some embodiments, the packaged semiconductor component 110 may include frames 352, 310, 230, and 240. These frames may be conductive frames, such as lead frames of the packaged semiconductor component 110. These frames may be provided with terminals (such as drain, source, and gate) that may be connected to the die. Figure 2B (not shown) electrical contact patterns are implemented. For example, drain frame 352, source frame 310, gate frame 230, and Kelvin source frame 240 can be arranged based on the drain, source, gate, and Kelvin source of the die terminals, respectively. Therefore, the (multiple) source terminals 132 (including 132A, 132B), (multiple) drain terminals 122, gate terminals 142, and Kelvin sources 134 of the packaged semiconductor component 110 can be electrically connected to drain frame 352, source frame 310, gate frame 230, and Kelvin source frame 240, respectively.

[0061] Although reference is made to source contacts, drain contacts, and gate contacts in this disclosure, this is for illustrative purposes only. Generally speaking, stamped leads can be used to provide a source terminal, a gate terminal, a drain terminal, a Kelvin source terminal, a control terminal, an input terminal, an output terminal, a sensor terminal, a base terminal, an emitter terminal, a collector terminal, a ground terminal, a reference terminal, a short circuit terminal, or any other suitable electrical terminal.

[0062] Figure 3A-3B Illustrated are example embodiments of semiconductor components and assemblies in an array structure.

[0063] Figure 3A 3. An exploded view of a packaged semiconductor component 110 according to some embodiments is shown. Each packaged semiconductor component 110 can be mounted on a frame 352 and assembled with other semiconductor components. In some embodiments, the frame 352 can provide mechanical support and electrical contact in the assembly.

[0064] like Figure 3A As shown in , the packaged semiconductor component 110 may include a bonding material layer 312, a die 314, a die attach material layer 316, and a package structure 310 and a die holder 320 (e.g., a die clip). In some examples, the bonding material layer 312 may be formed based on a pattern that may include multiple regions to provide electrical connections to corresponding die connection terminals (e.g., contact terminals) such as a source (including a Kelvin source), a drain, and a gate of the semiconductor component. For example, die attach pads 312A, 312B, 312C, and 312D may provide electrical connections to a drain terminal, a source terminal, a gate terminal, and a Kelvin source terminal of the die connection terminals, respectively. In some examples, the die attach material layer 312 may be formed of a conductive material such as solder, a conductive epoxy, and the like.

[0065] See further Figure 3AIn some examples, a field effect transistor (FET), such as a metal oxide semiconductor field effect transistor (MOSFET) (e.g., a GaN MOSFET), can be implemented on die 314. Thus, die 314 can include terminals, such as a drain, a source (and a Kelvin source), and a gate. In some cases, a die attach material layer 316 can be assembled (e.g., bonded) on top of die 314. In some examples, die attach material layer 316 can cover the top surface of die 314. Furthermore, die attach material layer 316 can be configured to bond die 314 to package structure 310. Bonding material layer 314 and die attach material layer 316 can be formed using the same type of bonding material (e.g., a conductive bonding material). In some cases, the structure of packaged semiconductor component 110 can be modified so that die pad 320 can be positioned on top of die attach material layer 316. In some assembly processes, die pad 320 can be assembled after die 314 and die attach material layer 316 are assembled. During these assembly processes, die pad 320 may be referred to as a "clip."

[0066] Figure 3B An example of an array assembly 350 that packages semiconductor components 110 is shown. Figure 3B , a die paddle or clip 320 can be mounted on each device lead frame unit 352 of the array assembly 350. In some embodiments, the packaged semiconductor components 110 can be assembled or mounted in different orientations. During the assembly process of the array assembly 350, the device lead frame unit 352 can alternatively be mounted on top of each die paddle or clip 320.

[0067] Figure 4 Pictured Figure 1A The cross section of the packaged semiconductor component 110 is shown in FIG. Figure 4 As shown in FIG, the packaged semiconductor component 110 may include a die paddle or clip 320, a die attach structure 420, a die 314, a lead attach structure 440, a drain lead frame 312A, a source lead frame 312B, a side source terminal 132A (side source terminal 132B is not shown), and a source terminal 132 ( Figure 414. The other side source terminals 132, Kelvin source terminals 134, and gate terminals 142 are not shown in FIG. 14. The die pad 320 may be used as a heat sink. The die pad 320 may also be used to provide an electrical connection to the top surface of the packaged semiconductor component 110. A die attach structure 420 may be used to attach the die 314 and the die pad 320. The die 314 may be implemented as a field effect transistor (FET), such as a metal oxide semiconductor field effect transistor (MOSFET) (e.g., a Si MOSFET or a GaN MOSFET), and thus, the die 314 may include terminals such as a drain, a source, and a gate. The lead attach structure 440 may attach the die 314 to the lead frames 312A and 312B ( Figure 4 Lead frames 312C and 312D are not shown).

[0068] In some embodiments, lead frame 312A may be connected to drain terminal 122, and lead frame 312B may be connected to source terminal 132 and side source terminals 132A and 132B ( Figure 4 The side source terminal 132 is not shown. These lead frames 312A and 312B can be connected to other semiconductor components or any electrical components by connecting to the corresponding terminals 122, 132 and 132A (drain terminal, source terminal and gate terminal) of the tube core. For example, the drain terminal of the tube core 314 can be connected to the lead frame 312A and the drain terminal 122. The drain terminal 122 can then be electrically coupled to the trace 120, as shown in FIG. Figure 1A and Figure 1B Likewise, the source terminal of die 314 can be connected to lead frame 312B and source terminal 132. Source terminal 132 can then be electrically coupled to trace 130, as described with reference to FIG. Figure 1A and Figure 1B Likewise, the gate terminal of the die 314 may also be connected via the lead frame 312D (as shown in FIG3 ), the gate terminal 135 (as shown in FIG4 ). Figure 1A ) and trace 140 (as shown in Figure 1A ) and connected to trace 140.

[0069] Figure 1A 2 are implemented in a manner close to the drain terminal 122. For example, since the drain terminal 122 and the side source terminal 132A are at a close distance to each other, the traces 120 and 130 can also be implemented in a manner close to each trace, such as Figure 1A Thus, according to embodiments disclosed herein, an electronic component 150 (such as a capacitor) may be implemented between traces 120 and 130 .

[0070] In some embodiments, drain terminal 122 and source terminal 132 can provide mechanical support points when mounting packaged semiconductor component 110 on a carrier (such as a PCB), or can support lead frames 312A and 312B at desired locations within a lead frame array during assembly. In some embodiments, side terminals 132A and 132B can provide additional mechanical support points.

[0071] Figure 5 A circuit assembly 500 is shown that incorporates two packaged semiconductor components 110A and 110B. Each of these components may be packaged in a manner similar to semiconductor package 110, such as Figure 1A and Figure 2B As shown in . Figure 5 , it is demonstrated that the semiconductor components 110A and 110B are assembled so as to be rotated 180 degrees relative to each other. For example, the semiconductor component 110A is positioned in the opposite direction, rotated 180 degrees relative to the semiconductor component 110B. For example, the drain terminal 122A of the semiconductor component 110A is positioned on the upper side (e.g., Figure 5 On the upper side), the source terminal 132AA, the Kelvin source terminal 134A and the gate terminal 142A are positioned on the lower side (e.g., Figure 5 The semiconductor component 110A may be assembled in an opposite direction relative to the semiconductor component 110A. For example, the drain terminal 122B of the semiconductor component 110B is positioned on the lower side (e.g., Figure 5 ), while the source terminal 132BB, the Kelvin source terminal 134B, and the gate terminal 142B are positioned on the upper side (e.g., Figure 5 On the upper side of Figure 5 As further shown in FIG, side source terminals 132A1 and 132B1 of semiconductor component 110A may be located on an upper side relative to side source terminals 132A2 and 132B2 of semiconductor component 110B. Therefore, capacitors 150A and 150B may be implemented while minimizing the form factor of circuit assembly 500.

[0072] Capacitor 150A is connected to the drain and source terminals of the component via traces ( Figure 5 Similarly, capacitor 150B is connected to packaged semiconductor component 110A via traces ( Figure 5 110B). The integration of capacitors 150A and 150B creates capacitor loops 514 and 524, respectively. In some designs, more than two semiconductor components may be implemented. For example, an array comprising multiple semiconductor components may be created by arranging each component rotated 180 degrees relative to adjacent components.

[0073] Figure 6 The diagram illustrates a circuit assembly system 600 formed by implementing a capacitor on top of the circuit assembly system 600 according to an embodiment of the present disclosure. Circuit assembly system 600 includes a packaged semiconductor component 650 and capacitors 680 and 690 on a PCB. Packaged semiconductor component 650 includes a source terminal and a drain terminal on a common side. Thus, buffer capacitor 680 can be electrically connected between source terminal 632A and drain terminal 622A via a trace having low parasitic inductance. Similarly, buffer capacitor 690 can be electrically connected between source terminal 632B and drain terminal 622C via a trace having low parasitic inductance. The location of the terminals on packaged semiconductor component 650 enables the buffer capacitor to be connected between the source and drain in a compact layout with low parasitic inductance.

[0074] For illustration purposes, Figure 6 The bottom view of the packaged semiconductor component 650 and two capacitors 680 and 690 is shown, wherein the PCB is not shown, but some traces on the PCB are shown. The packaged semiconductor component 650 and the capacitors 680, 690 can be implemented on the PCB, for example, similar to one or more embodiments described above. The capacitors 680 and / or 690 can be electrically connected between the source and the drain in any suitable manner. Figure 6 As shown in FIG, the PCB may include traces 660A, 660B, and 670 (e.g., Figure 6 Only a portion of the PCB trace is shown in FIG, which is shown as being connected to the source terminal 632A, the source terminal 632B and the drain terminal(s) 622A-622C, respectively. The gate terminal 642, the other source terminal 632 and the Kelvin source terminal 634 may be connected to Figure 6 6. In some embodiments, source terminal 632A and drain terminal(s) 622A-622C may be coupled by implementing capacitor 680 between trace 660A and trace 670. In some cases, source terminal 632B and drain terminal(s) 622A-622C may be coupled by implementing capacitor 690 between trace 660A and trace 670. In some embodiments, traces 660A and 660B may be formed within the same trace.

[0075] The layout of the source frame 610, the drain frame 620, the gate frame 630 and the Kelvin source frame 640 may be arranged as follows: Figure 6 In some embodiments, the layout can be determined based on the layout of the die terminals (e.g., drain, source (and Kelvin source) and gate). For example, Figure 6As shown in , source frame 610 can be patterned to cover the source terminal(s) of the die so that the source terminals of the die are electrically connected to terminals on opposite sides of packaged semiconductor component 650. In packaged semiconductor component 650, the source terminal(s) of the die are electrically connected to source terminals 632A and 632B and source terminal 632. In addition, drain frame 620 can be patterned to cover the drain terminal(s) of the die. Drain frame 620 can electrically connect the drain terminal(s) of the die to drain terminals 622A-622C, as shown in FIG. Figure 6 Furthermore, the gate frame 630 and the Kelvin source frame 640 may electrically connect the terminal(s) of the die to the gate terminal 642 and the Kelvin source terminal 634, respectively.

[0076] In some embodiments, the circuit assembly system 600 may include two capacitors 680 and 690. These capacitors 680, 690 may be connected via source traces 660A and 660B (for ease of illustration, Figure 6 Only a portion of the source trace is shown in FIG) and the drain trace 670 are implemented between the source terminal(s) and the drain terminal(s). Figure 6 As shown in FIG, source terminal 632A is electrically connected to source trace 660A, while another source terminal 632B is electrically connected to source trace 660B. In addition, drain terminals 622A-622C can be connected to drain trace 670. Therefore, capacitor 680 can be electrically connected between source terminal 632A and drain terminals 622A-622C via a short trace. In addition, capacitor 690 can be electrically connected between source terminal 632B and drain terminals 622A-622C via a short trace. Figure 6 The trace shown in may represent a portion of a trace. In some embodiments, one of capacitors 680 or 690 may be implemented in circuit assembly system 600. In other embodiments, both capacitors 680 and 690 may be implemented in circuit assembly system 600.

[0077] Additional embodiments

[0078] In the foregoing description, the present disclosure has been described with reference to specific embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

[0079] In fact, although the present disclosure is made in the context of certain embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the present invention and their equivalents. In addition, although several variations of the embodiments have been shown and described in detail, it will be readily apparent to those skilled in the art based on this disclosure that other modifications within the scope of the present disclosure are within the scope of the present disclosure. It is also envisioned that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the embodiments disclosed herein. Any method disclosed herein does not have to be performed in the order described. Therefore, the scope of the present disclosure is not intended to be limited by the specific embodiments described above.

[0080] It should be understood that the systems and methods of the present disclosure each have several innovative aspects, no single innovative aspect being solely responsible for or necessary for achieving the desired properties disclosed herein. The various features and processes described above can be used independently of one another or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of the present disclosure.

[0081] Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as functioning in certain combinations and even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination. No single feature or feature group is necessary or indispensable for every embodiment.

[0082] It should also be understood that, unless otherwise expressly stated or understood otherwise in the context of use, conditional language used herein (such as "can," "may," "perhaps," "likely," "for example," etc.) is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not include these features, elements, and / or steps. Thus, such conditional language is generally not intended to imply that features, elements, and / or steps are in any way essential to one or more embodiments, or that one or more embodiments necessarily include logic (whether input or prompted by the author) for determining whether these features, elements, and / or steps are included or performed in any particular embodiment. The terms "comprising," "including," "having," and the like are synonymous and are used inclusively in an open-ended manner and do not exclude other elements, features, actions, operations, and the like. Furthermore, the term "or" is used in an inclusive sense (rather than an exclusive sense), and thus, when used to connect a list of elements, the term "or" means one, some, or all of the elements in the list. Furthermore, unless otherwise specified, the articles "a," "an," and "the" used in this application and the appended claims should be interpreted as meaning "one or more" or "at least one." Similarly, although operations may be depicted in a particular order in the figures, it should be understood that these operations need not be performed in the particular order shown, or in sequential order, nor that all illustrated operations need be performed to achieve the desired results. Furthermore, the figures may schematically depict one or more example processes in the form of flow charts. However, other operations not depicted may be incorporated into the schematically illustrated example methods and processes. For example, one or more additional operations may be performed before, after, concurrently with, or between any illustrated operations. Furthermore, in other embodiments, the operations may be rearranged or reordered. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above-described embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the program components and systems may generally be integrated together in a single software product or packaged into multiple software products. Furthermore, other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired results.

[0083] Furthermore, while the methods and apparatus described herein may be susceptible to various modifications and alternative forms, specific examples thereof have been illustrated in the accompanying drawings and described in detail herein. However, it should be understood that the present disclosure is not limited to the specific forms or methods disclosed, but rather encompasses all modifications, equivalents, and alternatives falling within the spirit and scope of the various implementations described and the appended claims. Furthermore, any specific features, aspects, methods, characteristics, features, qualities, attributes, elements, etc. disclosed herein in connection with an implementation or embodiment may be applied to all other implementations or embodiments described herein. Any method disclosed herein does not necessarily have to be performed in the order described. The methods disclosed herein may include certain actions taken by the practitioner; however, these methods may also include any third party's direction of those actions, whether express or implied. The ranges disclosed herein also include any and all overlaps, sub-ranges, and combinations thereof. Language such as "at most," "at least," "greater than," "less than," "between," and the like encompasses the recited numbers. Numerals preceded by terms such as "about" or "approximately" are inclusive of the recited numeral and should be interpreted based on the specific circumstances (e.g., as accurate as possible under the specific circumstances, such as ±5%, ±10%, ±15%, etc.). Phrases preceded by terms such as "substantially" are inclusive of the recited phrase and should be interpreted based on the specific circumstances (e.g., as reasonable as possible under the specific circumstances). For example, "substantially constant" includes "constant." Unless otherwise noted, all measurements were made under standard conditions, including temperature and pressure.

[0084] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including individual members. For example, "at least one of A, B, or C" is intended to encompass: A, B, C, A and B, A and C, B and C, and A, B and C. Unless expressly stated otherwise, linking language such as the phrase "at least one of X, Y, and Z" should be understood, depending on the context, as generally used to convey that an item, term, or the like can be at least one of X, Y, or Z. Thus, such linking language is not generally intended to imply that certain embodiments require the presence of at least one of X, at least one of Y, and at least one of Z, respectively. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the apparatus and methods disclosed herein.

[0085] Thus, the claims are not to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

1. A circuit assembly comprising: a packaged semiconductor component comprising a semiconductor die including a field effect transistor, a side source terminal positioned on a first side of the packaged semiconductor component and connected to a source of the field effect transistor, and a drain terminal positioned on a second side of the packaged semiconductor component and connected to a drain of the field effect transistor, wherein the first side is adjacent to the second side; as well as A capacitor is external to the packaged semiconductor component, the capacitor being electrically connected between the source terminal and the drain terminal.

2. The circuit assembly of claim 1, further comprising a printed circuit board, the packaged semiconductor component and the capacitor being positioned on the printed circuit board, and the packaged semiconductor component further comprising a heat sink opposite the printed circuit board.

3. The circuit assembly of claim 2, wherein the side source terminal provides a mechanical support point for the heat sink.

4. The circuit assembly of claim 1 , wherein the packaged semiconductor component further comprises: a plurality of additional drain terminals on the second side and connected to the drain of the field effect transistor; as well as A plurality of source terminals are on a third side of the packaged semiconductor component and connected to the source of the field effect transistor, wherein the third side is opposite the second side. 5 . The circuit assembly of claim 1 , the packaged semiconductor component further comprising a second side source terminal on an opposite side of the first side. 6 . The circuit assembly of claim 1 , wherein each of the first side and the second side of the packaged semiconductor component comprises a lead frame.

7. The circuit assembly of claim 1 , further comprising a second packaged semiconductor component and a second capacitor electrically connected between lateral source and drain terminals of the second packaged semiconductor component, the second packaged semiconductor component rotated 180 degrees relative to the packaged semiconductor component.

8. The circuit assembly of claim 1 further comprising a printed circuit board, wherein the printed circuit board includes traces, and wherein the capacitor is connected to one of the traces.

9. A packaged semiconductor component comprising: a semiconductor die including a field effect transistor having a source, a gate, and a drain; a plurality of drain terminals on a first side of the packaged semiconductor component and connected to the drain; a side source terminal on a second side of the packaged semiconductor component and connected to the source; as well as a plurality of source terminals on a third side of the packaged semiconductor component and connected to the side source terminals within the packaged semiconductor component, wherein the third side is opposite the first side, wherein the second side is adjacent to both the first side and the third side, and wherein the side source terminals are positioned closer to the first side than the third side.

10. The packaged semiconductor component of claim 9, further comprising: a surface arranged to be coupled to a printed circuit board; as well as A heat sink is opposite to the surface. The packaged semiconductor component of claim 10 , wherein the side source terminal provides mechanical support for the heat sink. 12 . The packaged semiconductor component of claim 10 , wherein the heat spreader has a recess around the side source terminal. 13 . The packaged semiconductor component of claim 9 , wherein each of the first side and the second side of the packaged semiconductor component comprises a lead frame. The packaged semiconductor component of claim 13 , wherein the lead frame comprises stamped flat ends. 15 . The packaged semiconductor component of claim 9 , further comprising a gate terminal positioned on the third side of the packaged semiconductor component.

16. A circuit assembly comprising: Packaged semiconductor components, including: a semiconductor die including a field effect transistor having a source, a gate, and a drain; a drain terminal connected to the drain; and a source terminal connected to the source, wherein the drain terminal and the source terminal are on a same side of the packaged semiconductor component; and A capacitor is external to the packaged semiconductor component, the capacitor being electrically connected between the source terminal and the drain terminal.

17. The circuit assembly of claim 16 further comprising a second capacitor external to the packaged semiconductor component, wherein the packaged semiconductor component includes a second source terminal, the second source terminal being on the same side of the packaged semiconductor component as the drain terminal and the source terminal, and wherein the second capacitor is electrically connected between the second source terminal and the drain.

18. The circuit assembly of claim 16, further comprising a printed circuit board, the packaged semiconductor component and the capacitor being positioned on the printed circuit board, wherein the packaged semiconductor component further comprises a heat sink opposite the printed circuit board.

19. The circuit assembly of claim 16, wherein the packaged semiconductor component includes a plurality of additional source terminals located on a side opposite to the same side as the drain terminal and the source terminal.

20. The circuit assembly of claim 16, wherein the packaged semiconductor component includes at least one additional drain terminal on the same side as the drain terminal and the source terminal, wherein the at least one additional drain terminal is electrically connected to the capacitor external to the packaged semiconductor component.

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