Multi-channel radio frequency transceiver chip based on three-dimensional stacking process
Through a multi-channel RF transceiver chip based on the three-dimensional stacking process, using vertical interconnection and ground-hole-gold ball-ground hole shielding structure, the traditional chip's area, electromagnetic coupling and interconnect reliability problems are solved, and a compact package with high integration, high power output and high phase shifting accuracy is achieved.
Patent Information
- Application Number
- CN202510591952.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-09
- Publication Date
- 2025-08-08
AI Technical Summary
In the prior art, traditional tile phased array systems have large area and limited number of edge gold wire interconnections. Gallium arsenide chips are susceptible to electromagnetic coupling, resulting in reduced phase shift accuracy, insufficient power processing capacity of silicon-based chips, and three-dimensional stacking technology has problems such as inter-layer electromagnetic interference and low reliability of vertical interconnections.
A multi-channel RF transceiver chip based on three-dimensional stacking technology is adopted to realize innovative connections between GaAs radio frequency base plate, GaAs adapter plate and CMOS chip cover plate through a vertical interconnection structure and a ground hole-gold ball-ground hole shielding structure. It uses gold bumps and metal ground holes for electrical interconnection, and a ground hole-gold ball-ground hole shielding structure is set up between the RF circuits to improve isolation.
It realizes high power output, high phase shift accuracy and compact packaging, with an increase of more than 50% of integration, greater than 30dB between channels, increased phase shift accuracy by 40%, reduced area by 50%, and reduced interconnection loss.
Smart Images
Figure CN120453261A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of microwave integrated circuit technology, and specifically relates to a multi-channel radio frequency transceiver (TR) chip based on a three-dimensional stacking process, which is suitable for highly integrated and high-frequency application scenarios such as 5G communications, satellite communications, and millimeter-wave imaging systems. Background Art
[0002] With the development of technology, active phased array systems have been widely used in various fields, and their performance, reconfigurability, and broadband operation have attracted much attention. A typical active phased array consists of multiple antennas, each equipped with independent transmit and receive (T / R) modules. These modules need to strike a balance between high integration, compactness, light weight, and cost efficiency.
[0003] In traditional tile-type phased array systems, the multi-function chip (MFC) with a tiled architecture is difficult to meet the small size requirements of the Ka-band antenna unit due to problems such as large area occupation and limited number of edge gold wire interconnections. Gallium arsenide (GaAs) chips are susceptible to electromagnetic coupling, resulting in reduced phase shift accuracy and worsening noise coefficient, while silicon-based (CMOS) chips have insufficient power handling capabilities. Existing three-dimensional stacking technology is based on the inherent characteristics of silicon chips and uses silicon through-silicon vias to achieve vertical interconnection of three silicon chips. Although this solution can improve the integration level, it still faces challenges such as electromagnetic interference between layers, uneven thermal stress distribution, and low vertical interconnection reliability. Therefore, there is an urgent need for a high-isolation, high-reliability, and compact three-dimensional stacked RF transceiver chip design solution. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a multi-channel RF transceiver chip based on a three-dimensional stacking process. Through its innovative vertical interconnect structure and ground via-gold ball-ground via shielding structure, this invention addresses existing issues such as electromagnetic coupling and high interconnection losses, achieving high power output, high phase shift accuracy, and compact packaging.
[0005] The technical solution adopted in the present invention is as follows:
[0006] A multi-channel radio frequency transceiver chip based on a three-dimensional stacking process, comprising a GaAs radio frequency base plate, a GaAs adapter plate, and a CMOS chip cover plate arranged in sequence from bottom to top;
[0007] The GaAs radio frequency backplane is used to integrate a multi-channel radio frequency circuit; the radio frequency circuit includes a common port and multiple antenna ports, and each port is connected to one end of a corresponding first metal trace provided on the GaAs adapter board through a gold bump;
[0008] The CMOS chip cover plate has a control circuit for controlling the working state of the radio frequency circuit and a power modulation circuit for supplying power to the radio frequency circuit integrated on its lower surface; the input ports of the control circuit and the power modulation circuit are connected to one end of a corresponding second metal trace provided on the GaAs adapter plate via gold bumps, and the output ports are connected to one end of a corresponding third metal trace provided on the GaAs adapter plate via gold bumps;
[0009] The GaAs adapter plate has an area larger than that of the CMOS chip cover plate and is provided with a plurality of first metal traces, a plurality of second metal traces, and a plurality of third metal traces; wherein the first metal trace is led to the upper surface of the GaAs adapter plate through a metal ground hole, and the other end is extended to an area not covered by the CMOS chip cover plate to achieve connection with an external device; the other end of the second metal trace is extended to an area not covered by the CMOS chip cover plate to achieve connection with an external device; the third metal trace is led to the lower surface of the GaAs adapter plate through a metal ground hole, and the other end is connected to the radio frequency circuit through a gold bump.
[0010] Furthermore, a ground hole-gold ball-ground hole shielding structure is provided between each channel of the radio frequency circuit to improve the isolation between channels; the ground hole-gold ball-ground hole shielding structure includes an upper ground hole, a gold ball, and a lower ground hole, and a metal ground plane is provided on the lower surface of the GaAs radio frequency base plate and the upper surface of the GaAs adapter plate, and the upper and lower ends of the gold ball are connected to the metal ground plane through the upper ground hole and the lower ground hole respectively; multiple ground hole-gold ball-ground hole shielding structures form a short-circuit boundary condition or form a shielding cavity structure.
[0011] Furthermore, epoxy resin glue is filled between the CMOS chip cover plate and the GaAs adapter plate.
[0012] Furthermore, the GaAs radio frequency backplane and GaAs adapter plate are manufactured using a 90nm Al-GaAs / GaAs pHEMT process, and the cutoff frequency exceeds 90 GHz.
[0013] Beneficial effects of the present invention:
[0014] (1) The present invention adopts a three-dimensional stacking solution to solve the interface interconnection problems such as RF circuit power supply and control signal transmission at the chip level, achieving higher integration, improving the integration and performance of the phased array as a whole, and reducing the area by more than 50% compared with the traditional tiled architecture.
[0015] (2) The present invention can further optimize the wiring layout of the RF circuit through the ground hole-gold ball-ground hole shielding structure, and make the isolation between channels greater than 30dB and improve the phase shift accuracy by 40%.
[0016] (3) The present invention possesses the advantages of both silicon chips and gallium arsenide chips; the control circuit and the power modulation circuit utilize the advantages of silicon chips with many wiring layers, dense routing, and low power consumption, while the radio frequency circuit utilizes the advantages of gallium arsenide chips with low loss and high power. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 Exploded view of a multi-channel RF transceiver chip based on a 3D stacking process;
[0018] Figure 2 Side view of the multi-channel RF transceiver chip structure based on three-dimensional stacking process.
[0019] Explanation of the accompanying figures: 1. GaAs RF base plate, 2. GaAs adapter board, 3. Silicon control cover plate, 4. Gold bump, 5. Ground via, 6. Epoxy resin glue, 7. Ground via-gold ball-ground via shielding structure. DETAILED DESCRIPTION
[0020] To make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings. However, the present invention can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.
[0021] This embodiment provides a Ka-band multi-channel RF transceiver chip based on a three-dimensional stacking process, including a GaAs RF base plate, a GaAs adapter plate, and a CMOS chip cover plate arranged in sequence from bottom to top. The overall size is 5.8mm×5.8mm×0.4mm, and the chip integrates 4 receiving channels and 4 transmitting channels.
[0022] The GaAs radio frequency backplane is used to integrate a multi-channel radio frequency circuit; the radio frequency circuit includes a common port, four antenna ports, a power distribution network, four transmitting channels, four receiving channels and eight radio frequency single-pole double-throw switches; the transmitting and receiving states of the channels are switched via the single-pole double-throw switches; the transmitting channel includes a power amplifier, a driver amplifier and a phase shifter; the receiving channel includes two low-noise amplifiers, an attenuator and a phase shifter; the phase shifter is shared by the transmitting and receiving channels; multiple channels are connected to the common port via a power distribution network; a common port and four antenna ports are all connected to one end of a corresponding first metal trace on the GaAs adapter board via gold bumps.
[0023] Epoxy resin glue is filled between the CMOS chip cover and the GaAs adapter board to reduce stress and improve chip reliability; a control circuit for controlling the working state of the radio frequency circuit and a power modulation circuit for supplying power to the radio frequency circuit are integrated on its lower surface; the input ports of the control circuit and the power modulation circuit are connected to one end of a corresponding second metal trace on the GaAs adapter board via gold bumps, and the output ports are connected to one end of a corresponding third metal trace on the GaAs adapter board via gold bumps.
[0024] The GaAs adapter board has an area larger than that of the CMOS chip cover board and is provided with a plurality of first metal traces, a plurality of second metal traces, and a plurality of third metal traces. The first metal trace is led to the upper surface of the GaAs adapter board through a metal ground hole, and the other end is extended to an area not covered by the CMOS chip cover board to achieve connection with an external device. The other end of the second metal trace is extended to an area not covered by the CMOS chip cover board to achieve connection with an external device. The third metal trace is led to the lower surface of the GaAs adapter board through a metal ground hole, and the other end is connected to the radio frequency circuit through a gold bump. The second metal trace is provided on the upper surface of the GaAs adapter board, and the first metal trace and the third metal trace can be provided on the upper surface or the lower surface of the GaAs adapter board, or partially provided on the upper surface and partially provided on the lower surface.
[0025] While the GaAs RF backplane optimizes the wiring layout topology to achieve higher spatial efficiency, it also introduces electromagnetic coupling issues between adjacent transmission channels, particularly impacting phase shifter performance. To mitigate these coupling effects, a ground hole-gold ball-ground hole shielding structure is provided between each channel of the RF circuit to improve isolation between channels. The ground hole-gold ball-ground hole shielding structure includes an upper ground hole, a gold ball, and a lower ground hole. A metal ground plane is provided on the lower surface of the GaAs RF backplane and the upper surface of the GaAs adapter plate. The upper and lower ends of the gold ball are connected to the metal ground plane through the upper and lower ground holes, respectively. Multiple ground hole-gold ball-ground hole shielding structures form a short-circuit boundary condition or a shielding cavity structure.
[0026] The present invention arranges the control circuit and the power modulation circuit on a silicon chip, taking advantage of the silicon chip's advantages of multiple wiring layers, dense routing, and low power consumption. The radio frequency circuit is arranged on a GaAs radio frequency backplane, taking advantage of the gallium arsenide chip's advantages of low loss and high power. That is, the present invention has the advantages of both silicon chips and gallium arsenide chips.
[0027] The two layers of chips in the present invention are electrically interconnected via gold bumps, and the upper and lower metal layers of the GaAs chip are electrically interconnected via ground vias. RF signals are transmitted between layers via a two-level vertical transition between the gold bumps and the ground vias, achieving return loss >20dB and insertion loss <0.1dB. DC signals (power supply signals) and control signals are matched to the gold bumps of the GaAs adapter board via the silicon chip's redistribution layer (RDL), achieving low-loss serial-to-parallel conversion and power modulation throughout the three-dimensional stacked architecture. Furthermore, the three-dimensional stacked architecture offers a denser interconnect density and smaller footprint than chips using gold wire interconnects or other methods.
[0028] On the basis of the three-dimensional stacking architecture, the present invention utilizes the metallized ground holes and gold bumps on the gallium arsenide chip to form a ground hole-gold ball-ground hole shielding structure to connect the upper and lower metal ground planes, forming a short-circuit boundary condition to block the propagation of electromagnetic waves. At the same time, a shielding cavity structure can also be formed to completely confine the electromagnetic waves radiated by the chip circuit, greatly improving the isolation between radio frequency circuits. Unlike the semi-open space where traditional chips are located, the present invention can form a fully enclosed space (i.e., a shielding cavity structure) through the ground hole-gold ball-ground hole shielding structure, which can further improve space efficiency, and the isolation between channels is improved by more than 11dB.
Claims
1. A multi-channel radio frequency transceiver chip based on a three-dimensional stacking process, characterized in that: It includes a GaAs radio frequency base plate, a GaAs adapter plate and a CMOS chip cover plate which are arranged in sequence from bottom to top; The GaAs radio frequency backplane is used to integrate a multi-channel radio frequency circuit; the radio frequency circuit includes a common port and multiple antenna ports, and each port is connected to one end of a corresponding first metal trace provided on the GaAs adapter board through a gold bump; The CMOS chip cover plate has a control circuit for controlling the working state of the radio frequency circuit and a power modulation circuit for supplying power to the radio frequency circuit integrated on its lower surface; the input ports of the control circuit and the power modulation circuit are connected to one end of a corresponding second metal trace provided on the GaAs adapter plate via gold bumps, and the output ports are connected to one end of a corresponding third metal trace provided on the GaAs adapter plate via gold bumps; The GaAs adapter plate has an area larger than that of the CMOS chip cover plate and is provided with a plurality of first metal traces, a plurality of second metal traces, and a plurality of third metal traces; wherein the first metal trace is led to the upper surface of the GaAs adapter plate through a metal ground hole, and the other end is extended to an area not covered by the CMOS chip cover plate to achieve connection with an external device; the other end of the second metal trace is extended to an area not covered by the CMOS chip cover plate to achieve connection with an external device; the third metal trace is led to the lower surface of the GaAs adapter plate through a metal ground hole, and the other end is connected to the radio frequency circuit through a gold bump.
2. The multi-channel RF transceiver chip based on a three-dimensional stacking process according to claim 1, characterized in that: A ground hole-gold ball-ground hole shielding structure is provided between each channel of the radio frequency circuit to improve the isolation between channels; the ground hole-gold ball-ground hole shielding structure includes an upper ground hole, a gold ball, and a lower ground hole; the lower surface of the GaAs radio frequency base plate and the upper surface of the GaAs adapter plate are provided with a metal ground plane, and the upper and lower ends of the gold ball are connected to the metal ground plane through the upper ground hole and the lower ground hole respectively; multiple ground hole-gold ball-ground hole shielding structures form a short-circuit boundary condition or form a shielding cavity structure.
3. The multi-channel RF transceiver chip based on a three-dimensional stacking process according to claim 2, characterized in that: Epoxy resin glue is filled between the CMOS chip cover plate and the GaAs adapter plate.
4. The multi-channel RF transceiver chip based on a three-dimensional stacking process according to claim 3, characterized in that: The GaAs radio frequency bottom plate and the GaAs adapter plate are manufactured using a 90nm Al-GaAs / GaAs pHE MT process, and the cutoff frequency exceeds 90 GHz.