A small signal acquisition circuit for power distribution monitoring terminals

Abstract

This invention discloses a small signal acquisition circuit for a power distribution monitoring terminal, including a switching unit and a sampling unit. The sampling unit comprises several operational amplifiers, several inverters, several transistors, several resistors, a selector, a trigger, and a capacitor. Among the several operational amplifiers, the non-inverting input of operational amplifier U1 is connected to terminal 2_1, the inverting input is connected to the non-inverting input of operational amplifier U5, one end of resistor R1, one end of resistor R2, and one end of capacitor C1, and the output is connected to the input of inverter U2. The inverting input of operational amplifier U5 is connected to the output and the first input of multiplier U10; the second input of multiplier U10 is connected to terminals 1-2 and the output is connected to terminals 1-3; the O0 pin of selector U3 is connected to the base of transistor Q2, the O1 pin is connected to the base of transistor Q1, the A0 pin is connected to the output of inverter U4, the A1 pin is connected to the output of inverter U2 and the input of inverter U4, the SA pin is connected to the 1Q pin of flip-flop U6, and the SB pin is connected to the inverted 1Q pin and the 1D pin of flip-flop U6.

Description

Technical Field

[0001] This invention relates to the field of power distribution measurement and control technology, and in particular to a small signal acquisition circuit for power distribution monitoring terminals. Background Technology

[0002] The power distribution system is a crucial link in the power system responsible for power distribution. Its main function is to safely and reliably distribute the high-voltage power transmitted from the substation to various electrical devices according to user needs after the voltage is stepped down by transformers. Therefore, in order to improve the reliability of power consumption, in addition to real-time monitoring of parameters such as three-phase voltage / current / zero-sequence voltage during the power consumption process, it is also necessary to monitor various equipment and environmental parameters in the corresponding power supply area. Due to the complexity and diversity of monitoring signals and the differences in attenuation characteristics or built-in gain functions of different sensors during signal transmission, the amplitude of the final output signal may span multiple orders of magnitude from μV to V. This requires setting corresponding gain parameters for each signal level during the initial configuration of the system to ensure that they are within the same order of magnitude for centralized monitoring. However, when changes or expansions are needed, such as changing the input signal of the original monitoring port to a sensor with a different output level or adding different monitoring points during expansion, this fixed gain configuration method requires re-burning and debugging the system program. Therefore, a small signal acquisition circuit for power distribution monitoring terminals is proposed, which is easy to change the signal monitoring type and put into use, and can be quickly configured during system expansion. Summary of the Invention

[0003] To address the aforementioned technical problems, the purpose of this invention is to provide a small signal acquisition circuit for a power distribution monitoring terminal, comprising a switching unit and a sampling unit. The sampling unit includes several operational amplifiers, inverters, transistors, resistors, selectors, triggers, and capacitors. Operational amplifier U1 has its non-inverting input connected to terminal 2-1, its inverting input connected to the non-inverting input of operational amplifier U5, one end of resistor R1, one end of resistor R2, and one end of capacitor C1, and its output connected to the input of inverter U2. Operational amplifier U5's inverting input is connected to its output and the first input of multiplier U10. The second input of multiplier U10 is connected to terminal 1-2, and its output is connected to... Terminals 1-3; pin O0 of selector U3 is connected to the base of transistor Q2, pin O1 is connected to the base of transistor Q1, pin A0 is connected to the output of inverter U4, pin A1 is connected to the output of inverter U2 and the input of inverter U4, pin SA is connected to pin 1Q of trigger U6, pin SB is connected to the inverted pin 1Q and pin 1D of trigger U6; pins 1PR and 1CLR of trigger U6 and the collector of transistor Q2 are connected to the power supply; the collector of transistor Q1 is connected to the other end of resistor R2; the emitter of transistor Q2 is connected to the other end of resistor R1; the emitter of transistor Q1, pins B0 and B1 of selector U3, and the other end of capacitor C1 are grounded.

[0004] Furthermore, the sampling unit also includes several operational amplifiers, several transistors, several diodes, and several resistors. Among the several operational amplifiers, the non-inverting input of operational amplifier U7 is connected to the emitter of transistor Q3, one end of resistor R3, one end of resistor R4, and one end of resistor R5; its inverting input is connected to the inverting input of operational amplifier U8 and terminals I-5; and its output is connected to the anode of diode D2 and the other end of resistor R5. The non-inverting input of operational amplifier U8 is connected to the emitter of transistor Q4, one end of resistor R8, one end of resistor R9, and one end of resistor R10; and its output is connected to the anode of diode D1 and the other end of resistor R10. The non-inverting input of operational amplifier U9 is connected to the anodes of diode D3 and D4, and one end of resistor R13. One end of resistor R14 and one end of resistor R14 are connected to the output terminal of flip-flop U6, which is connected to the 1CLK terminal and one end of resistor R14. The collectors of transistors Q3 and Q4, the other end of resistor R3, the other end of resistor R8, and the other end of resistor R13 are connected to the power supply. The base of transistor Q3 is connected to the output terminal of inverter U4. The base of transistor Q4 is connected to the output terminal of inverter U2. The cathode of diode D1 is connected to the cathode of diode D3 and one end of resistor R11. The cathode of diode D2 is connected to the cathode of diode D4 and one end of resistor R12. The other ends of resistors R4, R9, R11, R12, and R14 are grounded.

[0005] Furthermore, one end of resistor R16 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U9 and one end of resistor R15; the other end of resistor R15 is grounded.

[0006] Furthermore, one end of resistor R6 is connected to one end of resistor R7 and terminal 1-5; the other end of resistor R7 is connected to the power supply; and the other end of resistor R6 is grounded.

[0007] Furthermore, the switching unit includes a rotary switch, S1, whose common terminal is connected to terminal 1_1 and its connecting terminal is connected to terminal 2_1.

[0008] Furthermore, the switching unit includes several relay switches and corresponding bit decoders. The coils of the relay switches are connected to the output terminals of the bit decoders, and the input control terminals of the decoders are connected to the host chip.

[0009] Furthermore, resistors R16 and R15 are sliding rheostats.

[0010] The advantages of this invention compared to the prior art are:

[0011] This invention enables rapid configuration when the monitoring type of a power distribution terminal changes or the monitoring range is expanded, without requiring reprogramming and debugging, and offers a fast response time during the configuration process. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 The circuit structure diagram of the sampling unit provided by the present invention.

[0014] Figure 2 The circuit structure diagram of the switching unit provided by the present invention. Detailed Implementation

[0015] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0016] This invention discloses a small signal acquisition circuit for a power distribution monitoring terminal, comprising a switching unit and a sampling unit. The sampling unit includes several operational amplifiers (op-amps), several inverters, several transistors, several resistors, a selector, a trigger, and a capacitor. Among the several operational amplifiers, the non-inverting input of operational amplifier U1 is connected to terminal 2-1, and its inverting input is connected to the non-inverting input of operational amplifier U5, one end of resistor R1, one end of resistor R2, and one end of capacitor C1. Its output is connected to the input of inverter U2. The inverting input of operational amplifier U5 is connected to its output and the first input of multiplier U10. The second input of multiplier U10 is connected to terminal 1-2, and its output is connected to terminal 1-3. The O0 pin of the selector U3 is connected to the base of transistor Q2, the O1 pin is connected to the base of transistor Q1, the A0 pin is connected to the output of inverter U4, the A1 pin is connected to the output of inverter U2 and the input of inverter U4, the SA pin is connected to the 1Q pin of flip-flop U6, the SB pin is connected to the 1Q inverted pin and the 1D pin of flip-flop U6; the 1PR inverted pin and 1CLR inverted pin of flip-flop U6 and the collector of transistor Q2 are connected to the power supply; the collector of transistor Q1 is connected to the other end of resistor R2; the emitter of transistor Q2 is connected to the other end of resistor R1; the emitter of transistor Q1, the B0 pin and B1 pin of selector U3, and the other end of capacitor C1 are grounded.

[0017] Specifically, the sampling unit further includes several operational amplifiers, several transistors, several diodes, and several resistors. Among the several operational amplifiers, the non-inverting input of operational amplifier U7 is connected to the emitter of transistor Q3, one end of resistor R3, one end of resistor R4, and one end of resistor R5; its inverting input is connected to the inverting input of operational amplifier U8 and its I-5 terminals; and its output terminal is connected to the anode of diode D2 and the other end of resistor R5. The non-inverting input of operational amplifier U8 is connected to the emitter of transistor Q4, one end of resistor R8, one end of resistor R9, and one end of resistor R10; and its output terminal is connected to the anode of diode D1 and the other end of resistor R10. The non-inverting input of operational amplifier U9 is connected to the anodes of diode D3 and D4, and one end of resistor R13. One end of resistor R14 and one end of resistor R14 are connected to the output terminal of flip-flop U6, which is connected to the 1CLK terminal and one end of resistor R14. The collectors of transistors Q3 and Q4, the other end of resistor R3, the other end of resistor R8, and the other end of resistor R13 are connected to the power supply. The base of transistor Q3 is connected to the output terminal of inverter U4. The base of transistor Q4 is connected to the output terminal of inverter U2. The cathode of diode D1 is connected to the cathode of diode D3 and one end of resistor R11. The cathode of diode D2 is connected to the cathode of diode D4 and one end of resistor R12. The other ends of resistors R4, R9, R11, R12, and R14 are grounded.

[0018] Specifically, one end of resistor R16 is connected to the power supply, and the other end is connected to the inverting input of operational amplifier U9 and one end of resistor R15; the other end of resistor R15 is grounded.

[0019] Specifically, one end of resistor R6 is connected to one end of resistor R7 and terminals 1-5; the other end of resistor R7 is connected to the power supply; and the other end of resistor R6 is grounded.

[0020] Specifically, the switching unit includes a rotary switch, S1, whose common terminal is connected to terminal 1_1 and its connecting terminal is connected to terminal 2_1.

[0021] Specifically, the switching unit includes several relay switches and corresponding bit decoders. The coils of the relay switches are connected to the output terminals of the bit decoders, and the input control terminals of the decoders are connected to the host chip.

[0022] Specifically, resistors R16 and R15 are sliding rheostats.

[0023] In one embodiment, the problem to be solved is that the system program needs to be re-programmed and debugged when changing the monitoring type or expanding the number of monitoring units. In the solution, 1_1 is the common gain multiple signal input terminal, 2_1 is the sampling unit gain signal multiple feedback terminal, 1_2 is the gained signal input terminal, 1_3 is the gain output terminal, 1_4 is the start signal input terminal, 1_5 is the reset signal terminal, and 1_6 is another start signal input terminal. In this embodiment, the monitoring signal output by the corresponding sensor is input to 1_2. After adjusting the common gain multiple voltage signal of 1_1, the switching unit is selected to the sampling unit connected to 1_2. The voltage of 1_1 can be input from the upper-level connected chip or voltage regulation circuit. Then, two pulse signals are input to 1_4. After configuration, the sampling unit can be reused for other monitoring types by inputting two pulse signals to 1_4 again. In the specific circuit principle, when the circuit is powered on, the 2_1 signal is input to the non-inverting input of op-amp U1. After the corresponding sampling unit to be controlled is selected by the switching unit, the signal is input to 1_4. Initially, the sampling circuit is in an interrupt standby state. After the 1_4 signal is input, the inverting input of op-amp U1 will collect the voltage at the connection point of resistor R2 and capacitor C1, compare it with the non-inverting input, and output the result signal to inverter U2. After inversion, one path of inverter U2 is input to pin A1 of selector U3, and the other path is inverted by inverter U4 and input to pin A0 of selector U3, allowing selector U3 to select and feed back to transistors Q1 and Q2. When the base voltage of transistor Q2 remains consistent, during initial power-up or in a re-regulation state, the voltage at the connection point of C1 and resistor R2 is less than the 1_1 feedback voltage. The O0 pin of selector U3 outputs a signal to the base of transistor Q2, turning on Q2. The collector voltage of transistor Q2 is fed back to capacitor C1 via the emitter and resistor R1, pulling its voltage up to approach the synchronization voltage at the non-inverting input of op-amp U1. Then, the 1_4 signal is input again to the 1clk pin of flip-flop U6. The 1Q pin and 1Q inverting pin of flip-flop U6 are reverse-biased, with the 1Q pin outputting a high potential voltage and the 1Q inverting pin outputting a low potential voltage. The O0 and O1 pins of selector U3 output potential voltages B0 and B1, respectively. During initial power-up or in a re-regulation state, assuming capacitor C1 and resistor R2 are connected, the voltage at the connection point of C1 and resistor R2 is less than the 1_1 feedback voltage. If the voltage at the connection terminal of resistor R2 is greater than the feedback voltage of 1_1, then the input signal at pin O1 of selector U3 is sent to the base of transistor Q1. The voltage at the terminal of capacitor C1 is routed through resistor R2, collector and emitter of transistor Q1 to ground. The voltage at the terminal of capacitor C1 is synchronized with 1_1 and then inputs signal 1_4 to flip-flop U6. At the same time, the voltage at the connection terminal of capacitor C1 and resistor R2 will be output to multiplier U10 via op-amp U5. After inputting 1_2, the gain will be amplified according to the voltage followed by op-amp U5 and output to 1_3, thus completing the gain. When it is necessary to change the gain factor of other sampling units again, the signal parameter of 1_1 is changed, and after the switching unit is selected to the corresponding sampling unit, a pulse signal is input to 1_4. The above process is repeated until all sampling units are controlled.

[0024] In one embodiment, considering the uncertainty of the gain multiplier span before and after the sampling unit, to ensure that no gain interruption occurs during automatic adjustment, it is necessary to set the interval period of the two pulse signals 1_4 according to the maximum and minimum values ​​of the time constant curves between capacitor C1 and resistor R1 and between capacitor C1 and resistor R2 each time the gain multiplier of the sampling unit is adjusted. In the case of multiple sampling units, this will increase the overall control response time. Therefore, based on the above scheme, a faster response control scheme is proposed. In this scheme, the method of external input for 1_4 is changed to the first selection of the input start signal by 1_6, and the second time the interval period is automatically controlled according to the size of the gain span before and after. In the specific scheme, inverters U2 and U4 are first set to... The output terminals are respectively input to the bases of transistors Q4 and Q3. When 1_6 is input for the first time, the high or low potential voltage signal output by op-amp U1 is inverted by inverter U2 and input to the base of transistor Q4 to turn on, or inverted by inverter U4 and input to the base of transistor Q3 to turn on. Assuming that the output of selector U3 is first output from pin O0 to pin O1, transistor Q3 turns on. The collector power supply signal of transistor Q3 is fed back to the non-inverting input of op-amp U7 through transistor Q3. When powered on, the non-inverting input of op-amp U7 is set with a low potential reference voltage by resistors R3 and R4, and the inverting input of op-amp U7 is set with a high potential reference voltage. After the power supply is input to the non-inverting input of op-amp U7 through transistor Q3, the high potential signal output by op-amp U7 is fed back to the non-inverting input closed loop through resistor R5. The signal is pulled up to the non-inverting input of op-amp U7. Simultaneously, the signal passes through diode D2 and resistor R12. Diode D4 is reverse-biased and cut off during the first signal input (1_6). The 1_6 signal is routed in two ways: one through diode D3 and resistor R11, and the other through resistor R14. The potential at the junction of resistor R14 and the anode of diode D3 is greater than the initial low output potential of op-amp U7 but less than the reference voltage potential at the inverting input of op-amp U9. When the gain is adjusted, switching the outputs O0 and O1 of selector U3 causes a change in the outputs of inverters U2 and U4, turning on transistor Q4 and cutting off transistor Q3. Op-amp U7 is fed back to its non-inverting input via resistor R5 for a closed-loop high output potential. Meanwhile, the collector power supply of transistor Q4 is fed back via transistor Q4's reverse bias. The voltage is fed to the non-inverting input of op-amp U8, where a low-potential reference voltage is set, and the inverting input of op-amp U8, where a high-potential reference voltage is set. When transistor Q4 is turned on, the potential at the non-inverting input of op-amp U8 is greater than that at the inverting input. The high-potential output of op-amp U8 is fed back to the non-inverting input of op-amp U8 via resistor R10 in a closed loop. Simultaneously, the output of op-amp U8 also passes through diode D1 and resistor R11. Diode D3 is reverse-biased and cut off, which again pulls up the potential of the anode connection of resistor R13 and diode D3 and feeds it back to the non-inverting input of op-amp U9. The non-inverting input voltage of op-amp U9 is greater than the input signal voltage at the inverting input of op-amp U9. The reference voltage parameter at the inverting input of op-amp U9 is greater than the potential of either diode D4 or diode D3 when biased, but less than the potential voltages of both diode D4 and diode D3 when biased.The output signal of operational amplifier U9 is sent to the 1clk pin of trigger U6 for self-control, and the self-control interval is mapped to the gain span. Conversely, if selector U3 first switches from O1 to O0, then transistor Q4 is turned on first during the high level of the first input signal 1_6. When the first signal cycle ends and returns to low level, the closed loop output of operational amplifier U8 feeds back to the cathode of diode D3, pulls up the voltage potential of pull-up resistor R13 and the anode of diode D3, and then the output of operational amplifier U7 is pulled up again to complete the self-control of operational amplifier U9.

[0025] In one embodiment, the first input of the 1_6 signal, besides the example shown in the attached figure, can also be input via the inverting input of operational amplifier U9. The connection method involves removing the voltage divider signal or the power supply provided to the inverting input of operational amplifier U9. The upper-level chip enables the pull-up resistor to set the constant voltage at the inverting input of operational amplifier U9 to be greater than the voltage at the anode connection of resistor R13 and diode D3 when either diode D3 or D4 is biased. During startup, enabling the pull-down resistor completes the first input, or resistors R16 and R15 can be set as adjustable rheostats and started via a sliding knob. The upper-level chip is not shown in the attached figure. 1_5 is the reset signal. During the sampling unit's control, in the second... During regulation, input signal 1_5 is applied; or during parallel control, input signal 1_5 is applied after the first round of regulation is completed, causing all sampling units to re-enter standby mode. During standby, the input parameter 2_1 is maintained. The high-potential reference voltage set at the inverting terminals of operational amplifiers U7 and U8 can be set by the power supply or voltage divider. In addition to rotary switch S1, the switching unit can also control the conduction of independent relay switches through decoding. The connection method is to connect the relay switch coil corresponding to each sampling unit to the output terminal of the decoder. According to the selected number of bits, the upper chip controls the coil to be energized and conduct, feeding back the current 1_1 signal to 2_1. The relay switch and decoder are not shown in the attached diagram.

[0026] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. A small signal acquisition circuit for use in a power distribution monitoring terminal, characterized in that, The system includes a switching unit and a sampling unit. There are several sampling units, each comprising several operational amplifiers (op-amps), several inverters, several transistors, several resistors, a selector, a trigger, and a capacitor. Among the several operational amplifiers, the non-inverting input of operational amplifier U1 is connected to the gain signal feedback terminal 2_1 of the sampling unit, and its inverting input is connected to the non-inverting input of operational amplifier U5, one end of resistor R1, one end of resistor R2, and one end of capacitor C1. Its output terminal is connected to the input terminal of inverter U2. The inverting input of operational amplifier U5 is connected to its output terminal and the first input terminal of multiplier U10. The second input terminal of multiplier U10 is connected to the input terminal 1_2 of the signal being gained, and its output terminal is connected to the gain output terminal 1_3. The O0 pin of selector U3 is connected to the base of transistor Q2, and its O1 pin is also connected to the base of transistor Q1. A0... Pin A1 is connected to the output of inverter U4, pin A1 is connected to the output of inverter U2 and the input of inverter U4, pin SA is connected to pin 1Q of flip-flop U6, pin SB is connected to the inverted pin 1Q and pin 1D of flip-flop U6; pins 1PR and 1CLR of flip-flop U6 and the collector of transistor Q2 are connected to the power supply; pin 1CLK of U6 is connected to the start signal input terminal 1_4; the collector of transistor Q1 is connected to the other end of resistor R2; the emitter of transistor Q2 is connected to the other end of resistor R1; the emitter of transistor Q1, pins B0 and B1 of selector U3, and the other end of capacitor C1 are grounded; one end of the switching unit is connected to the common gain multiple signal input terminal 1_1, and the other end is connected to the sampling unit gain signal multiple feedback terminal 2_1; During operation, input the monitoring signal output from the corresponding sensor to 1_2. After adjusting the common gain multiple voltage signal of 1_1, select the corresponding sampling unit connected to 2_1 using the switching unit. Then, input two pulse signals to 1_4 to complete the configuration. When the sampling unit is reused for other monitoring types, input two pulse signals to 1_4 again. When the circuit is powered on, the signal from 2_1 is input to the non-inverting input of operational amplifier U1. After selecting the corresponding sampling unit to be controlled through the switching unit, input a signal to 1_4. Initially, the sampling circuit is in an interrupt standby state. After the signal is input to 1_4, operational amplifier U1 inverts. The input terminal collects the voltage at the connection point of resistor R2 and capacitor C1, compares it with the non-inverting input, and outputs the result signal to inverter U2. After inversion, inverter U2 outputs one signal to pin A1 of selector U3, and the other signal is inverted by inverter U4 and output to pin A0 of selector U3. This ensures that the voltage at the bases of transistors Q1 and Q2 remains consistent when selector U3 selects and provides feedback. During initial power-on or in a re-adjustment state, the voltage at the connection point of C1 and resistor R2 is less than the 1-1 feedback voltage. In this case, pin O0 of selector U3 outputs a signal to the base of transistor Q2, turning on transistor Q2 and causing the collector of transistor Q2 to... The voltage is fed back to capacitor C1 through the emitter and resistor R1, pulling its voltage up to approach the voltage at the non-inverting input of op-amp U1. Then, the 1_4 signal is input again to the 1clk pin of flip-flop U6. The 1Q and 1Q inverting pins of flip-flop U6 are reverse-biased, with the 1Q pin outputting a high potential voltage and the 1Q inverting pin outputting a low potential voltage. The O0 and O1 pins of selector U3 output potential voltages B0 and B1, respectively. During initial power-up or in a re-adjustment state, assuming the voltage at the connection point of capacitor C1 and resistor R2 is greater than the 1_1 feedback voltage, the input signal at the O1 pin of selector U3 is sent to the base of transistor Q1, and capacitor C1... The terminal voltage is routed through resistor R2, the collector and emitter of transistor Q1, and ground. The terminal voltage of capacitor C1 is synchronized with 1_1 and inputs signal 1_4 to flip-flop U6. At the same time, the voltage at the connection between capacitor C1 and resistor R2 is output to multiplier op-amp U10 via op-amp U5. After inputting to 1_2, the gain is amplified according to the voltage followed by op-amp U5 and output to 1_3, thus completing the gain. When it is necessary to change the gain factor of other sampling units again, the signal parameters of 1_1 are changed, and after the switching unit is selected to the corresponding sampling unit, a pulse signal is input to 1_4. The above process is repeated until all sampling units are controlled.

2. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 1, characterized in that, The sampling unit also includes several operational amplifiers, several transistors, several diodes, and several resistors. Operational amplifier U7's non-inverting input is connected to the emitter of transistor Q3, one end of resistor R3, one end of resistor R4, and one end of resistor R5; its inverting input is connected to the inverting input of operational amplifier U8 and the reset signal terminal 1-5; its output terminal is connected to the anode of diode D2 and the other end of resistor R5. Operational amplifier U8's non-inverting input is connected to the emitter of transistor Q4, one end of resistor R8, one end of resistor R9, and one end of resistor R10; its output terminal is connected to the anode of diode D1 and the other end of resistor R10. Operational amplifier U9's non-inverting input is connected to the anodes of diodes D3 and D4, one end of resistor R13, one end of resistor R14, and the start signal input terminal 1-6. The output terminal is connected to the 1CLK terminal of flip-flop U6; the collectors of transistors Q3 and Q4, the other end of resistors R3, R8, and R13 are connected to the power supply; the base of transistor Q3 is connected to the output terminal of inverter U4; the base of transistor Q4 is connected to the output terminal of inverter U2; the cathode of diode D1 is connected to the cathode of diode D3 and one end of resistor R11; the cathode of diode D2 is connected to the cathode of diode D4 and one end of resistor R12; one end of resistor R16 is connected to the power supply, and the other end is connected to the inverting terminal of op-amp U9 and one end of resistor R15; the other ends of resistors R4, R9, R11, R12, R14, and R15 are grounded.

3. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 2, characterized in that, One end of resistor R6 is connected to one end of resistor R7 and terminals 1-5; the other end of resistor R7 is connected to the power supply; and the other end of resistor R6 is grounded.

4. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 1, characterized in that, The switching unit includes a rotary switch, S1, whose common terminal is connected to terminal 1_1 and its connecting terminal is connected to terminal 2_1.

5. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 1, characterized in that, The switching unit includes several relay switches and corresponding bit decoders. The coils of the relay switches are connected to the output terminals of the bit decoders, and the input control terminals of the decoders are connected to the host chip.

6. The small signal acquisition circuit for a power distribution monitoring terminal according to claim 2, characterized in that, The resistors R16 and R15 are sliding rheostats.

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