Compensation method, compensation device and switching power supply

Abstract

The invention provides a compensation method, a compensation device and a switching power supply, and the compensation method comprises the following steps: generating a sine reference voltage, the frequency of which is twice the real-time voltage frequency of an AC power grid; filtering the voltage at the two ends of the output bus capacitor by using a wave trap to obtain a first voltage, performing subtraction operation on the first voltage and the reference voltage, and then performing PI adjustment to obtain a second voltage; carrying out multiplication operation on the sine reference voltage and a first set calculation coefficient, or carrying out multiplication operation on the sine reference voltage, the second voltage and a second set calculation coefficient to obtain a compensation voltage; and compensating the conduction time of the synchronous switch tube according to the real-time voltage of the alternating-current power grid, the first voltage, the second voltage and the compensation voltage, thereby controlling the boost inductive current and realizing compensation for the total harmonic distortion of the PFC converter current. According to the invention, the symmetry of inductive current can be improved, the distortion of input current is reduced, and thus the iTHD is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electric energy conversion, and in particular to a compensation method, a compensation device and a switching power supply. Background Art

[0002] Research on single-phase medium-power PFC rectification technology is developing towards high efficiency and high power density. In order to achieve high efficiency, the bridgeless PFC topology has been proposed to follow this trend. Compared with the traditional bridge-type Boost PFC converter, the bridgeless PFC uses switches to replace the bridge arm diodes, reducing the loss of the open-path switching devices, thereby improving efficiency.

[0003] Among various bridgeless PFC topologies, the totem pole bridgeless PFC has become the mainstream due to its advantages such as fewer components and less common-mode noise. Figure 1 The figure shows a circuit diagram of a well-known totem pole bridgeless PFC, including a boost inductor L, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a fourth switch tube Q4. The first switch tube Q1 and the second switch tube Q2 are high-frequency switches, and the third switch tube Q3 and the fourth switch tube Q4 are power-frequency switches. The power-frequency switches can be replaced by diodes.

[0004] Specifically: in the positive half-cycle of the power frequency AC of the PFC converter, the first switch tube Q1 serves as a synchronous switch tube, the second switch tube Q2 serves as a main switch tube, the third switch tube Q3 serves as a power frequency switch tube and remains off, and the fourth switch tube Q4 serves as a power frequency switch tube and remains on; in the negative half-cycle of the power frequency AC of the PFC converter, the first switch tube Q1 serves as the main switch tube, the second switch tube Q2 serves as a synchronous switch tube, the third switch tube Q3 serves as a power frequency switch tube and remains on, and the fourth switch tube Q4 serves as a power frequency switch tube and remains off; its working principle takes the positive half-cycle of the input voltage as an example. When the second switch tube Q2 is driven to turn on, the input voltage of the PFC converter (i.e., the voltage across the boost inductor L) is recorded as V in The output voltage of the PFC converter is recorded as V out The inductance of the boost inductor L is recorded as L, the boost inductor L is excited, and the current of the boost inductor L is expressed as V in / L slope rises, and when the second switch Q2 is turned off, the first switch Q1 continues to flow, the boost inductor L is demagnetized, and the voltage across the boost inductor L is V out- V in ,, where V out is the output voltage of the PFC converter, the current of the boost inductor L is (V out -Vi n ) / L slope decreases.

[0005] Totem-pole bridgeless PFC circuits require GaN or SiC devices in continuous conduction mode (CCM) to achieve efficiency advantages. Due to hard switching, the switching frequency is typically low. However, in critical conduction mode (CRM), zero voltage switching (ZVS) can be achieved by controlling the negative inductor current, further increasing the PFC switching frequency and achieving higher power density. As the switching frequency increases, the boost inductor L becomes smaller, reducing the inductor size. However, as the inductance decreases, the magnetizing and demagnetizing slopes of the inductor current also increase exponentially.

[0006] like Figure 2 Shown Figure 1 The waveform diagram of the circuit. Based on the waveform diagram, the inventor of this application conducted an in-depth study on the totem pole bridgeless PFC circuit and found that due to the power characteristics of the PFC converter, the output voltage V out The voltage fluctuates in a sinusoidal manner at twice the power frequency. At low switching frequency, the boost inductor L is large, and V out The demagnetization slope of the boost inductor is less affected, but when the boost inductor L decreases, the demagnetization slope of the boost inductor L current (V out -V in ) / L will also present a sinusoidal voltage fluctuation of twice the power frequency, causing asymmetry in the boost inductor current. The smaller the boost inductor L, the more serious the asymmetry, which will seriously affect the total harmonics of the PFC converter current.

[0007] For switching power supplies, reducing the total harmonic distortion (iTHD) of the input current is the most direct and effective means of reducing power pollution. iTHD is defined as the ratio of the effective value of the total harmonic current to the effective value of the fundamental current. Currently, most literature on the total harmonic compensation of current in PFC converters focuses on compensating for the zero crossings on both sides of the industrial frequency input voltage, or compensating for the negative current of the inductor to increase the average value of the zero crossings on both sides of the input voltage. Since current products on the market and research on high switching frequency PFC converters of MHz and above are still in the early stages, there is no solution for how to reduce the total harmonic distortion of the input current of PFC converters at high switching frequencies.

[0008] In summary, further increasing the switching frequency to achieve higher power density is the future development trend, and it is very necessary to propose a compensation scheme for the total harmonic distortion of the input current under high switching frequency.

[0009] It should be noted that the information disclosed in the background technology section above is only intended to deepen the understanding of the overall background technology of this application, and should not be regarded as an admission or in any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0010] In view of this, the technical problem to be solved by the present invention is to provide a power factor correction soft switch control device and method, which can at least to a certain extent solve the deficiencies of the above-mentioned prior art problems.

[0011] As a first aspect of the present invention, the embodiment and technical solution of the compensation method provided are as follows:

[0012] A compensation method for compensating for total harmonic distortion of a PFC converter current, wherein the PFC converter includes a boost inductor, an output bus capacitor, a main switch tube, and a synchronous switch tube, wherein the compensation method comprises the following steps:

[0013] Generate a sinusoidal reference voltage, wherein the frequency of the sinusoidal reference voltage is twice the real-time voltage frequency of the AC power grid;

[0014] The voltage across the output bus capacitor is filtered using a notch filter to obtain a first voltage, and the first voltage is subtracted from a reference voltage and then PI-regulated to obtain a second voltage;

[0015] multiplying the sinusoidal reference voltage by a first set calculation coefficient, or multiplying the sinusoidal reference voltage, the second voltage, and a second set calculation coefficient to obtain a compensation voltage;

[0016] The conduction time of the synchronous switch tube is compensated according to the real-time voltage of the AC grid, the first voltage, the second voltage, and the compensation voltage, thereby controlling the boost inductor current and compensating for the total harmonic distortion of the PFC converter current.

[0017] Furthermore, the compensation voltage is obtained according to the formula Va=k1×sin2θ or Va=k2×Vc×sin2θ; wherein: V a is the compensation voltage, k1 is the first setting calculation coefficient, k2 is the second setting calculation coefficient, sin2θ is the sinusoidal reference voltage, V c is the second voltage.

[0018] Furthermore, the conduction time T of the synchronous switch tube is calculated according to the following formula: off :

[0019]

[0020] Where: V c For the second voltage, V ofilt is the first voltage, V a is the compensation voltage, V in is the real-time voltage of the AC grid.

[0021] As a second aspect of the present invention, the technical solution of the compensation device provided is as follows:

[0022] A compensation device for compensating for total harmonic distortion of a PFC converter current, wherein the PFC converter includes a boost inductor, an output bus capacitor, a main switch tube, and a synchronous switch tube, wherein the compensation device includes:

[0023] a phase-locked loop configured to generate a sinusoidal reference voltage, wherein the frequency of the sinusoidal reference voltage is twice the frequency of the real-time voltage of the AC power grid;

[0024] a voltage loop configured to filter the voltage across the output bus capacitor using a notch filter to obtain a first voltage, subtract the first voltage from a reference voltage, and then perform PI regulation to obtain a second voltage;

[0025] a multiplier configured to multiply the sinusoidal reference voltage by a set calculation coefficient, or to multiply the sinusoidal reference voltage, the second voltage, and a second set calculation coefficient to obtain a compensation voltage;

[0026] The time compensation module is configured to compensate the on-time of the synchronous switch tube according to the real-time voltage of the AC grid, the first voltage, the second voltage, and the compensation voltage, thereby controlling the boost inductor current and compensating for the total harmonic distortion of the PFC converter current.

[0027] Preferably, the phase-locked loop comprises:

[0028] A phase detector for detecting a phase difference between the real-time voltage of the AC grid and a voltage signal obtained by frequency division of the sinusoidal reference voltage, and converting the detected phase difference into a voltage signal for output;

[0029] A low-pass filter, used to smooth the voltage signal output by the phase detector;

[0030] a voltage-controlled oscillator, configured to generate the sinusoidal reference voltage under the control of the voltage signal output by the low-pass filter;

[0031] The frequency divider is used to divide the sinusoidal reference voltage by a frequency division coefficient of 2, and then input the divided voltage into the phase detector.

[0032] Preferably, the voltage loop includes:

[0033] A sampling module, configured to obtain a voltage across an output bus capacitor of the PFC converter;

[0034] a notch filter, for filtering out ripples in the output voltage of the PFC converter;

[0035] a subtractor, configured to perform a subtraction operation on the output voltage of the notch filter and a reference voltage;

[0036] A PI controller is used to perform PI regulation on the result of the subtractor operation.

[0037] Furthermore, according to formula V a =k1×sin2θ or V a =k2×V c × sin2θ to obtain the compensation voltage; where: V a is the compensation voltage, k1 is the first setting calculation coefficient, k2 is the second setting calculation coefficient, sin2θ is the sinusoidal reference voltage, V c is the second voltage.

[0038] Furthermore, the conduction time T of the synchronous switch tube is calculated according to the following formula: off :

[0039]

[0040] Where: V c For the second voltage, V ofilt is the first voltage, V a is the compensation voltage, V in is the real-time voltage of the AC grid.

[0041] As a third aspect of the present invention, the technical solution of the embodiment of the switching power supply provided is as follows:

[0042] A switching power supply includes a PFC converter, wherein the PFC converter includes a boost inductor, an output bus capacitor, a main switch tube and a synchronous switch tube, wherein: the switching power supply further includes the compensation device described in any one of the second aspects above.

[0043] The inventors of this application first discovered that the inherent ripple of the PFC output voltage at twice the frequency of the input voltage causes inductor current asymmetry, resulting in poor input current total harmonic distortion (iTHD). They therefore proposed a solution. The embodiments of the present invention have the following beneficial effects:

[0044] The embodiments of the present invention construct a sinusoidal compensation value at twice the input voltage frequency and superimpose it on the synchronous tube conduction time. This eliminates the need for additional hardware detection circuitry and compensates for the negative current flowing through the inductor simply by compensating the synchronous tube conduction time. This significantly reduces the asymmetry of the inductor current, mitigates the impact of the PFC converter's output voltage ripple at twice the power frequency on the input current total harmonic distortion (THD), and reduces the iTHD value. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1A circuit diagram of a known PFC converter;

[0046] Figure 2 for Figure 1 Schematic diagram of the circuit waveform;

[0047] Figure 3 This is a schematic structural diagram of a compensation device according to a second embodiment of the present invention;

[0048] Figure 4 A specific schematic diagram of a phase-locked loop;

[0049] Figure 5 A more specific structural diagram of the compensation device according to the second embodiment of the present invention;

[0050] Figure 6 1 is a main waveform diagram of the switching power supply according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0051] Typical embodiments embodying the features and advantages of the present disclosure will be described in detail in the following description with reference to the accompanying drawings. It should be understood that the present disclosure is capable of various variations in different embodiments without departing from the scope of the present disclosure, and the description and drawings are essentially illustrative of these variations and are not intended to limit the present disclosure.

[0052] In addition, the figures of this disclosure are merely schematic diagrams of the present disclosure and are not necessarily drawn to scale. Identical reference numbers in the figures denote identical or similar parts, and therefore repeated descriptions thereof will be omitted. Some of the blocks shown in the figures are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented using software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0053] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0055] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0056] It should be understood that, in the specification, claims and drawings, when a step is described as being connected to another step, the step may be directly connected to the other step, or be connected to the other step through a third step; when an element / unit is described as being "connected" to another element / unit, the element / unit may be "directly connected" to the other element / unit, or be "connected" to the other element / unit through a third element / unit.

[0057] In existing PFC circuit systems, based on the analysis of background technology, as power supplies develop towards higher power density and higher switching frequencies, it is necessary to consider the impact of the twice-frequency ripple of the PFC converter's output voltage on the total harmonic distortion (THD) of the PFC current. This impact of the twice-frequency ripple on iTHD must be reduced to enable the power supply to meet more stringent iTHD requirements.

[0058] In order to solve the above problems, the embodiments of the present invention provide a PFC converter current total harmonic distortion compensation method, compensation device and switching power supply. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other in any way.

[0059] First embodiment

[0060] This embodiment provides a compensation method for compensating the total harmonic distortion of the PFC converter current. Figure 1 As shown in FIG, the PFC converter includes a boost inductor L, an output bus capacitor Co, a main switch Q2, and a synchronous switch Q1. Each time the PFC converter enters the next power frequency half-cycle, the roles of the main switch Q2 and the synchronous switch Q1 are swapped. In the positive power frequency half-cycle, Q2 acts as the main switch and Q1 acts as the synchronous switch. In the negative power frequency half-cycle, Q1 acts as the main switch and Q2 acts as the synchronous switch.

[0061] The compensation method of this embodiment includes the following steps:

[0062] Generate a sinusoidal reference voltage whose frequency is twice the real-time voltage frequency of the AC grid;

[0063] The voltage across the output bus capacitor is filtered using a notch filter to obtain a first voltage, the first voltage is subtracted from a reference voltage, and then PI regulation is performed to obtain a second voltage;

[0064] Multiplying the sinusoidal reference voltage by the first set calculation coefficient, or multiplying the sinusoidal reference voltage, the second voltage, and the second set calculation coefficient to obtain a compensation voltage;

[0065] The conduction time of the synchronous switch tube is compensated according to the real-time voltage of the AC grid, the first voltage, the second voltage and the compensation voltage, thereby controlling the boost inductor current and compensating the total harmonic distortion of the PFC converter current.

[0066] The compensation method provided in this embodiment compensates for the negative current flowing through the inductor by compensating the conduction time of the synchronous tube, thereby significantly reducing the asymmetry of the inductor current, reducing the impact of the twice-power frequency ripple of the PFC converter output voltage on the input current distortion, and lowering the iTHD value.

[0067] As a specific implementation method, the calculation formula of the compensation voltage is V a =k1×sin2θ, V a is the compensation voltage, k1 is the first set calculation coefficient, and at this time the compensation voltage has nothing to do with the output load of the PFC converter.

[0068] Furthermore, the calculation formula of the compensation voltage is V a =k2×V c ×sin2θ, k2 is the first setting calculation coefficient, V c The second voltage is the compensation voltage associated with the voltage loop output. The compensation voltage changes with the load to achieve minimal iTHD at full load.

[0069] As a specific implementation method, the conduction time T of the synchronous switch tube is calculated according to the following formula: off :

[0070]

[0071] Where: V c is the second voltage, V ofilt is the first voltage, V a is the compensation voltage, V in is the real-time voltage of the AC grid.

[0072] Second embodiment

[0073] This embodiment provides a compensation device for compensating the total harmonic distortion of the PFC converter current, such as Figure 1 As shown in FIG, the PFC converter includes a boost inductor L, an output bus capacitor Co, a main switch Q2, and a synchronous switch Q1. Each time the PFC converter enters the next power frequency half-cycle, the roles of the main switch Q2 and the synchronous switch Q1 are swapped. In the positive power frequency half-cycle, Q2 acts as the main switch and Q1 acts as the synchronous switch. In the negative power frequency half-cycle, Q1 acts as the main switch and Q2 acts as the synchronous switch.

[0074] Figure 3 Schematic diagram of the structure of a compensation device according to a second embodiment of the present invention, wherein the compensation device includes:

[0075] a phase-locked loop configured to generate a sinusoidal reference voltage having a frequency twice that of a real-time voltage frequency of an AC power grid;

[0076] a voltage loop configured to filter the voltage across the output bus capacitor using a notch filter to obtain a first voltage, subtract the first voltage from a reference voltage, and then perform PI regulation to obtain a second voltage;

[0077] a multiplier configured to multiply the sinusoidal reference voltage by a set calculation coefficient, or to multiply the sinusoidal reference voltage, the second voltage, and a second set calculation coefficient to obtain a compensation voltage;

[0078] The time compensation module is configured to compensate the on-time of the synchronous switch tube according to the real-time voltage of the AC grid, the first voltage, the second voltage and the compensation voltage, thereby controlling the boost inductor current and compensating the total harmonic distortion of the PFC converter current.

[0079] Specifically, the sinusoidal reference voltage can be generated by using a digital phase-locked loop constructed based on a PI control algorithm using digital control, or by using a second-order generalized integrator to generate a first signal that is in phase with the input voltage signal and a second signal that is orthogonal to the input voltage signal, and performing Park transform on the first signal and the second signal to obtain a d-axis component and a q-axis component, and then adjusting the q-axis component to 0 through a PI controller. In specific implementation, technicians in this field can select a specific acquisition method according to needs, and this embodiment does not limit the specific acquisition method.

[0080] Figure 4 A specific schematic diagram of a phase-locked loop is shown in Figure 1. Figure 4As shown, the phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator and a frequency divider. The specific working principle of the phase-locked loop is as follows: the phase detector PD generates a rectangular wave voltage signal by taking the difference between the phase of the real-time voltage of the AC power grid and the phase of the signal fed back by the frequency divider after the sinusoidal reference voltage is divided. The rectangular wave voltage signal is then converted into a smooth continuous signal by the low-pass filter. Under the control of the signal, the voltage-controlled oscillator generates a frequency signal output (i.e., the sinusoidal reference voltage) that is proportional to the output voltage of the low-pass filter. The output of the voltage-controlled oscillator is divided by the frequency divider and then fed back to the phase detector. Since the present invention requires that the frequency of the sinusoidal reference voltage is twice the frequency of the real-time voltage of the AC power grid, the frequency division coefficient of the frequency divider is set to 2, so that the voltage-controlled oscillator can output a signal with a frequency twice the frequency of the real-time voltage of the AC power grid.

[0081] The real-time voltage of the AC grid represents the instantaneous magnitude and phase of the AC voltage at the power frequency input of the PFC converter, and can be obtained by sampling. During specific implementation, those skilled in the art can select a specific method for obtaining each parameter as required. This embodiment does not limit the specific method for obtaining these parameters.

[0082] It should be noted that, in a specific implementation, the amplitude of the sinusoidal reference voltage is 1.

[0083] Figure 5 FIG. 1 is a more specific structural diagram of the compensation device according to the second embodiment of the present invention, wherein the voltage loop includes:

[0084] The sampling module is used to obtain the voltage across the output bus capacitor of the PFC converter (i.e. Figure 1 The voltage across the capacitor Co can be obtained by sampling;

[0085] The notch filter is used to filter out the twice power frequency ripple of the PFC converter output voltage. The initial notch frequency is generally set to 100Hz and can be adjusted in real time according to the power input frequency.

[0086] The subtractor is used to subtract the output voltage of the PFC converter from a reference voltage. The reference voltage is determined based on circuit parameters and can be set to 410V, for example. This embodiment does not limit the preset voltage reference value; those skilled in the art can select it based on actual circumstances.

[0087] The PI controller is used to perform PI regulation on the result of the subtractor operation.

[0088] The PI controller is mainly used to adjust the voltage loop. The PI controller can also be constructed using a digital proportional integrator or an operational amplifier circuit, which is not limited in this embodiment.

[0089] As a specific implementation method, the calculation formula of the compensation voltage is V a =k1×sin2θ, V a is the compensation voltage, k1 is the first set calculation coefficient, and at this time the compensation voltage has nothing to do with the output load of the PFC converter.

[0090] Figure 5 The calculation formula of compensation voltage is V a =k2×V c × sin2θ, k2 is the second setting calculation coefficient, V c The second voltage is the compensation voltage associated with the voltage loop output. The compensation voltage changes with the load to achieve minimal iTHD at full load.

[0091] It should be noted that the above θ is the phase of the real-time voltage of the AC grid, θ=2×π×f, where f is the frequency of the real-time voltage of the AC grid. Therefore, sin2θ=sin(2×π×(2×f)), and the frequency represented by sin2θ is twice the frequency of the AC grid.

[0092] As a specific implementation method, the conduction time T of the synchronous switch tube is calculated according to the following formula: off :

[0093]

[0094] Where: V c is the second voltage, V ofilt is the first voltage, V a is the compensation voltage, V in is the real-time voltage of the AC grid.

[0095] Specifically, the demagnetization current of the PFC converter is the demagnetization slope multiplied by the demagnetization time, where the demagnetization slope is (Vout-Vin) / L. Since the input voltage and input current of the PFC converter are in phase, the input power has twice the power frequency power. This power is transmitted to the output end of the PFC converter, which will cause the output voltage Vout to have twice the power frequency ripple, such as Figure 2 As shown, Vout has twice the power frequency ripple, which causes the current magnitude to show twice the power frequency waveform at the end of the demagnetization current, resulting in serious asymmetry. This embodiment superimposes a voltage Va with a frequency twice the real-time voltage of the AC grid on the DC voltage Vofilt after the output voltage of the PFC converter is filtered by the notch filter, thereby changing the on-time Toff of the synchronous switch tube and compensating the current magnitude at the end of the demagnetization current, so that the magnitude is close to the same during the entire power frequency cycle. Where Vc is the output voltage of the voltage loop, which represents the load size of the PFC converter. Since the output voltage ripple of the PFC converter is positively correlated with the load size, if the above formula V is selected a =k2×V c× sin2θ is used for compensation. As mentioned above, the conduction time of the synchronous switch tube can be compensated according to the load size, so that the total harmonic distortion of the full load current can be well compensated.

[0096] Third embodiment

[0097] This embodiment provides a switching power supply including a PFC converter. The PFC converter includes a boost inductor, an output bus capacitor, a main switch tube, and a synchronous switch tube. The switching power supply further includes any compensation device in the second embodiment described above.

[0098] Figure 6 The main waveform diagram of the switching power supply according to the third embodiment of the present invention is shown in FIG. Figure 6 As shown, after compensation by the compensation device in the second embodiment, the simulation shows that the entire inductor current has good symmetry, indicating that the switching power supply of this embodiment can well compensate for the total harmonic distortion of the current.

[0099] The PFC converter was selected as an actual prototype of an interleaved totem bridgeless PFC for testing. Taking 230VAC input as an example, the iTHD test results of the switching power supply of the prior art and the present embodiment are compared as shown in Table 1 below:

[0100] Output power Existing technology This embodiment technology 150W (5% load) 35.42％ 14.04％ 300W (10% load) 27.85％ 3.83％ 900W (30% load) 15.29％ 4.34％ 1500W (50% load) 16.44％ 3.09％ 2100W (70% load) 11.76％ 3.06％ 3000W (100% load) 9.45％ 3.17％

[0101] Table 1 Comparison of iTHD test results of switching power supplies between prior art and this embodiment

[0102] As can be seen from Table 1, the iTHD value of the present invention is significantly lower than that of the prior art, and the iTHD value fluctuates smoothly, showing a significant improvement. The compensation device of the present invention can be applied in actual production, and its compensated iTHD can meet the stringent THD requirements of server power supplies, communication power supplies, etc.

[0103] The terms used in the above embodiments are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in various forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope of the appended claims. Therefore, all changes and modifications that fall within the scope of the claims or their equivalents are intended to be covered by the appended claims.

Claims

1. A compensation method for compensating total harmonic distortion of a PFC converter current, wherein the PFC converter includes a boost inductor, an output bus capacitor, a main switch tube, and a synchronous switch tube, characterized in that: The compensation method comprises the following steps: Generate a sinusoidal reference voltage, wherein the frequency of the sinusoidal reference voltage is twice the real-time voltage frequency of the AC power grid; The voltage across the output bus capacitor is filtered using a notch filter to obtain a first voltage, and the first voltage is subtracted from a reference voltage and then PI-regulated to obtain a second voltage; multiplying the sinusoidal reference voltage by a first set calculation coefficient, or multiplying the sinusoidal reference voltage, the second voltage, and a second set calculation coefficient to obtain a compensation voltage; The conduction time of the synchronous switch tube is compensated according to the real-time voltage of the AC grid, the first voltage, the second voltage, and the compensation voltage, thereby controlling the boost inductor current and compensating for the total harmonic distortion of the PFC converter current.

2. The compensation method according to claim 1, characterized in that: The compensation voltage is obtained according to the formula Va=k1×sin2θ or Va=k2×Vc×sin2θ; wherein: V a is the compensation voltage, k1 is the first setting calculation coefficient, k2 is the second setting calculation coefficient, sin2θ is the sinusoidal reference voltage, V c is the second voltage.

3. The compensation method according to claim 1, characterized in that: The conduction time T of the synchronous switch tube is calculated according to the following formula: off : Where: V c For the second voltage, V ofilt is the first voltage, V a is the compensation voltage, V in is the real-time voltage of the AC grid.

4. A compensation device for compensating for total harmonic distortion of a PFC converter current, wherein the PFC converter comprises a boost inductor, an output bus capacitor, a main switch tube, and a synchronous switch tube, characterized in that: The compensation device comprises: a phase-locked loop configured to generate a sinusoidal reference voltage, wherein the frequency of the sinusoidal reference voltage is twice the frequency of the real-time voltage of the AC power grid; a voltage loop configured to filter the voltage across the output bus capacitor using a notch filter to obtain a first voltage, subtract the first voltage from a reference voltage, and then perform PI regulation to obtain a second voltage; a multiplier configured to multiply the sinusoidal reference voltage by a set calculation coefficient, or to multiply the sinusoidal reference voltage, the second voltage, and a second set calculation coefficient to obtain a compensation voltage; The time compensation module is configured to compensate the on-time of the synchronous switch tube according to the real-time voltage of the AC grid, the first voltage, the second voltage, and the compensation voltage, thereby controlling the boost inductor current and compensating for the total harmonic distortion of the PFC converter current.

5. The compensation device according to claim 4, characterized in that: The phase-locked loop comprises: A phase detector for detecting a phase difference between the real-time voltage of the AC grid and a voltage signal obtained by frequency division of the sinusoidal reference voltage, and converting the detected phase difference into a voltage signal for output; A low-pass filter, used to smooth the voltage signal output by the phase detector; a voltage-controlled oscillator, configured to generate the sinusoidal reference voltage under the control of the voltage signal output by the low-pass filter; The frequency divider is used to divide the sinusoidal reference voltage by a frequency division coefficient of 2, and then input the divided voltage into the phase detector.

6. The compensation device according to claim 4, characterized in that: The voltage loop includes: A sampling module, configured to obtain a voltage across an output bus capacitor of the PFC converter; a notch filter, for filtering out ripples in the output voltage of the PFC converter; a subtractor, configured to perform a subtraction operation on the output voltage of the notch filter and a reference voltage; A PI controller is used to perform PI regulation on the result of the subtractor operation.

7. The compensation method according to claim 4, characterized in that: According to the formula V a =k1×sin2θ or V a =k2×V c × sin2θ to obtain the compensation voltage; where: V a is the compensation voltage, k1 is the first setting calculation coefficient, k2 is the second setting calculation coefficient, sin2θ is the sinusoidal reference voltage, V c is the second voltage.

8. The compensation method according to claim 4, characterized in that: The conduction time T of the synchronous switch tube is calculated according to the following formula: off : Where: V c For the second voltage, V ofilt is the first voltage, V a is the compensation voltage, V in is the real-time voltage of the AC grid.

9. A switching power supply comprising a PFC converter, wherein the PFC converter comprises a boost inductor, an output bus capacitor, a main switch tube, and a synchronous switch tube, characterized in that: The switching power supply further comprises the compensation device according to any one of claims 4 to 8.

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