Multi-loop control DC-DC conversion circuit and chip

Abstract

The invention discloses a multi-loop control DC-DC conversion circuit and a chip, relates to the field of integrated circuit design, and can greatly increase the amplification factor of a capacitor while reducing the area of the capacitor on the chip. The multi-loop control DC-DC conversion circuit comprises a first voltage dividing module and a second voltage dividing module which are used for dividing a target voltage; one end of the energy storage module is connected with the second voltage division module and the other end is grounded; the two input ends of the first amplification module are connected with the two ends of the first voltage division module respectively, and the output end is connected with target voltage; two input ends of the second amplification module are respectively connected with two ends of the second voltage division module, and an output end of the second amplification module is connected with one end of the second voltage division module; wherein the amplification factor of the energy storage module is determined by the transconductance of the first amplification module, the transconductance of the second amplification module, the resistance value of the first voltage division module and the resistance value of the second voltage division module.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a multi-loop controlled DC-DC conversion circuit and chip. Background Art

[0002] Capacitors are used in many circuit designs to ensure loop stability. For example, pulse-width-modulated DC-DC converters, LED drivers, and low-frequency phase-locked loops (PLLs) all employ capacitors. Larger capacitors occupy a larger area within the chip. Currently, capacitor multiplication circuits can be used to increase capacitance while reducing chip area, thus saving chip costs.

[0003] In related technologies, DC-DC conversion circuits often use a single-stage transconductance amplifier or operational amplifier to achieve capacitance amplification. Although this reduces the area of the capacitor, the amplification factor of such a circuit is generally small. Summary of the Invention

[0004] The present invention provides a multi-loop controlled DC-DC conversion circuit and chip, which can greatly increase the capacitance amplification factor while reducing the capacitance area on the chip.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a multi-loop controlled DC-DC conversion circuit, the multi-loop controlled DC-DC conversion circuit comprising: A first voltage dividing module and a second voltage dividing module are used to divide the target voltage; An energy storage module, one end of which is connected to the second voltage divider module and the other end of which is grounded; A first amplifying module, wherein two input terminals are respectively connected to two ends of the first voltage dividing module, and an output terminal is connected to a target voltage; The second amplifying module has two input ends connected to the two ends of the second voltage dividing module respectively, and an output end connected to one end of the second voltage dividing module; The amplification factor of the energy storage module is determined by the transconductance of the first amplifying module, the transconductance of the second amplifying module, the resistance of the first voltage dividing module, and the resistance of the second voltage dividing module.

[0006] In one possible implementation, the energy storage module includes a capacitor; One end of the capacitor is connected to the other end of the second voltage divider module, and the other end is grounded.

[0007] In a possible implementation, the first voltage dividing module includes a first resistor, and the second voltage dividing module includes a second resistor; One end of the first resistor is connected to the target voltage, and the other end is connected to one end of the second resistor. The other end of the second resistor is connected to one end of the capacitor.

[0008] In one possible implementation, the magnification factor is expressed by the following formula: ; Wherein, K is the amplification factor, gm1 is the transconductance of the first amplifying module, gm2 is the transconductance of the second amplifying module, R1 is the resistance value of the first resistor, and R2 is the resistance value of the second resistor.

[0009] In a possible implementation, the multi-loop controlled DC-DC conversion circuit further includes: a transient enhancement module; a transient enhancement module, connected to the first amplification module and the second amplification module, receiving a feedback voltage and a reference voltage, and configured to provide a first bias current to the first amplification module and the second amplification module according to an error signal between the feedback voltage and the reference voltage; The first amplifying module and the second amplifying module are used to increase the changing speed of the target voltage according to the first bias current.

[0010] In one possible implementation, the transient enhancement module includes: a bias circuit, a differential circuit, and a conversion circuit; a bias circuit connected to the differential circuit and configured to provide a second bias current to the differential circuit; A differential circuit is connected to the reference voltage and the feedback voltage to generate an error signal according to the reference voltage and the feedback voltage; The conversion circuit is connected to the differential circuit, the first amplifying module and the second amplifying module, and is used to convert the error signal into a first bias current and provide the first bias current to the first amplifying module and the second amplifying module.

[0011] In one possible implementation, the bias circuit includes PMOS 15, PMOS 14, and a current source; One end of the current source is grounded, and the other end is connected to the drain of the PMOS 15; The gate of the PMOS 15 is connected to the drain of the PMOS 15 and the gate of the PMOS 14 . The source of the PMOS 15 and the source of the PMOS 14 are connected to the power supply voltage. The drain of the PMOS 14 is connected to the differential circuit.

[0012] In one possible implementation, the differential circuit includes PMOS 8 and PMOS 9; The gate of PMOS 8 is connected to the reference voltage, the gate of PMOS 9 is connected to the feedback voltage, the source of PMOS 8 and the source of PMOS 9 are connected to the drain of PMOS 14, and the drain of PMOS 8 and the drain of PMOS 9 are connected to the conversion circuit.

[0013] In one possible implementation, the conversion circuit includes NMOS 10, NMOS 11, and NMOS 12; The drain of NMOS 10 is connected to the drain of PMOS 8 and the gate of NMOS 10, and the drain of NMOS 11 is connected to the drain of PMOS 9, the gate of NMOS 11, and the gate of NMOS 12; The drain of the NMOS 12 is connected to the first amplifying module and the second amplifying module; The source of the NMOS 10 , the source of the NMOS 11 , and the source of the NMOS 12 are grounded.

[0014] In a second aspect, the present invention provides a chip, which may include the multi-loop controlled DC-DC conversion circuit of the first aspect and any possible implementation thereof.

[0015] The multi-loop controlled DC-DC conversion circuit provided by the present invention achieves capacitor amplification by adopting a two-stage transconductance amplifier. Compared with the use of a single-stage transconductance amplifier in the related art, the capacitor capacitance can be increased by a square factor, thereby greatly increasing the capacitor amplification factor while reducing the capacitor area on the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit principle block diagram of a multi-loop controlled DC-DC conversion circuit provided by an embodiment of the present invention; Figure 2 A circuit schematic diagram of a multi-loop controlled DC-DC conversion circuit provided by an embodiment of the present invention; Figure 3 A schematic diagram of an equivalent circuit diagram provided by an embodiment of the present invention; Figure 4 A schematic diagram of another equivalent circuit diagram provided by an embodiment of the present invention; Figure 5 A circuit schematic diagram of another multi-loop controlled DC-DC conversion circuit provided by an embodiment of the present invention; Figure 6 A circuit timing diagram of a transient enhancement module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0018] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values may be based on additional conditions or values beyond the stated in practice.

[0019] Figure 1 The circuit principle block diagram of a multi-loop controlled DC-DC conversion circuit provided by an embodiment of the present invention. Figure 1 As shown, the multi-loop controlled DC-DC conversion circuit may include: a first voltage dividing module 11 , a second voltage dividing module 12 , an energy storage module 13 , a first amplifying module 14 and a second amplifying module 15 .

[0020] The first voltage divider module 11 and the second voltage divider module 12 are used to divide the target voltage VA. It is understood that the target voltage VA can be any voltage required in any scenario where the capacitance value needs to be amplified. For example, the target voltage VA can be the voltage at the output of an amplifier in a DC-DC converter, or the voltage in a phase-locked loop circuit, or the voltage in other application scenarios, which are not limited in this embodiment of the present invention.

[0021] The energy storage module has one end connected to the second voltage divider module 12 and the other end grounded. The energy storage module can be a capacitor.

[0022] The first amplifying module 14 has two input terminals connected to the two ends of the first voltage dividing module 11 respectively, and an output terminal connected to the target voltage VA.

[0023] The second amplifying module 15 has two input terminals connected to the two ends of the second voltage dividing module 12 respectively, and an output terminal connected to one end of the second voltage dividing module 12 , that is, the output terminal is connected to the middle node between the first voltage dividing module 11 and the second voltage dividing module 12 .

[0024] The amplification factor of the energy storage module 13 is determined by the transconductance of the first amplifying module 14 , the transconductance of the second amplifying module 15 , the resistance of the first voltage dividing module 11 , and the resistance of the second voltage dividing module 12 .

[0025] The multi-loop controlled DC-DC conversion circuit in the embodiment of the present invention achieves capacitor amplification by using a two-stage transconductance amplifier. Compared with the use of a single-stage transconductance amplifier in the related art, the capacitor capacitance can be increased by a square factor, thereby greatly increasing the capacitor amplification factor while reducing the capacitor area on the chip.

[0026] Optional, Figure 2 The circuit principle diagram of a multi-loop controlled DC-DC conversion circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the energy storage module 13 may include: a capacitor C1.

[0027] One end of the capacitor C1 is connected to the other end of the second voltage divider module 12 , and the other end is grounded.

[0028] Optional, such as Figure 2 As shown, the first voltage dividing module 11 may include a first resistor R1 , and the second voltage dividing module 12 may include a second resistor R2 .

[0029] One end of the first resistor R1 is connected to the target voltage VA, and the other end is connected to one end of the second resistor R2 . The other end of the second resistor R2 is connected to the capacitor C1 .

[0030] In the specific implementation, Figure 2 As shown, assuming that the nodes on either side of the first resistor R1 are A and B, and the nodes on either side of the second resistor R2 are C and D, the currents flowing out of node C are I1 and I2, and the current flowing into node C is I3. Then, the current relationship at node C is: I1 + I2 = I3. The currents flowing out of node A are I3 and I4, and the current flowing into node A is I5. Then, the current relationship at node A is: I3 + I4 = I5. Furthermore, assuming that the transconductance of the first amplifier module is gm1, and the transconductance of the second amplifier module is gm2.

[0031] It is worth noting that the voltages of the aforementioned nodes B and C are the same.

[0032] Since the voltage across the second resistor R2 is I1*R2 and the transconductance of the second amplifying module is gm2, I2 can be expressed by the following formula (1).

[0033] (1) Substituting formula (1) into I3=I1+I2, we can obtain the following formula (2).

[0034] (2) Assuming that the voltage of node C is VC, VC can be expressed by the following formula (3).

[0035] (3) Among them, ZC1, Both are used to represent the impedance of capacitor C1.

[0036] According to formula (2) and formula (3), the equivalent input resistance RCin of node C to ground can be obtained. RCin can be expressed by the following formula (4).

[0037] (4) Figure 3 A schematic diagram of an equivalent circuit diagram provided by an embodiment of the present invention is shown as follows: Figure 3 As shown in the figure, it is the equivalent circuit diagram after simplifying the impedance RCin of node C to ground. Figure 3 , we can get the ground impedance Rin of node A.

[0038] Since the voltage across the first resistor R1 is I3*R1 and the transconductance of the first amplifying module is gm1, I4 can be expressed by the following formula (5).

[0039] (5) Substituting formula (5) into I5=I3+I4, we can obtain the following formula (6).

[0040] (6) like Figure 3 As shown, assuming that the voltage of node A is VA, VA can be expressed by the following formula (7).

[0041] (7) According to formula (6) and formula (7), the equivalent input resistance Rin of node A to ground can be obtained. Rin can be expressed by the following formula (8).

[0042] (8) Substituting formula (4) of RCin into formula (8), we can obtain the following formula (9).

[0043] (9) After simplifying the above formula (9), we can get Rin=R1'+R2'+ZC1', Figure 4 To simplify the equivalent circuit diagram of node A to ground impedance Rin. Figure 4 As shown, R1', R2', and C1' can be expressed by the following formulas respectively.

[0044]

[0045]

[0046]

[0047] That is to say, the multi-loop controlled DC-DC converter circuit in the embodiment of the present invention can expand the capacitance of the capacitor C1 to K times of the original capacitance, that is, If the two resistors have the same resistance and transconductance, the capacitance can be increased to the square of (1+gm1*R1) the original capacitance, which greatly increases the capacitance without increasing the area of the capacitor on the chip, thus reducing chip cost.

[0048] Furthermore, the multi-loop controlled DC-DC converter circuit provided by the embodiments of the present invention not only increases the capacitance gain but also improves the response speed to load transients, thereby increasing the adjustment speed of the feedback loop and reducing output voltage variations. Specifically, the multi-loop controlled DC-DC converter circuit provided by the embodiments of the present invention may also include a transient enhancement module.

[0049] The transient enhancement module is connected to the first amplification module and the second amplification module, and is connected to the feedback voltage and the reference voltage, and is used to provide the first bias current for the first amplification module and the second amplification module according to the error signal between the feedback voltage and the reference voltage.

[0050] The first amplifying module and the second amplifying module are used to increase the changing speed of the target voltage according to the first bias current.

[0051] It is understood that the first amplifying module is specifically configured to directly increase the rate of change of the target voltage (the voltage at node A) based on the first bias current. The second amplifying module is specifically configured to directly increase the rate of change of the voltage at its output terminal, i.e., one end of the second resistor R2 (node C), based on the first bias current, thereby indirectly increasing the rate of change of the target voltage and, therefore, improving the response speed of the entire loop.

[0052] Furthermore, in embodiments of the present invention, the transient enhancement module can generate a first bias current based on the error signal between the feedback voltage and the reference voltage, providing bias current to the first and second amplifier modules. This allows the drive capabilities of the first and second amplifier modules to change in real time based on load variations. Consequently, when a large load transient occurs, the drive capabilities of the first and second amplifier modules do not affect the rapid rise of the output signal, thereby preventing any impact on the response speed to the load transient. Compared to related art designs in which the drive capability of the error amplifier is fixed, embodiments of the present invention can significantly improve the response speed to load transients, thereby increasing the adjustment speed of the feedback loop and reducing output voltage variations.

[0053] Optional, Figure 5The circuit principle diagram of another multi-loop controlled DC-DC conversion circuit provided by the embodiment of the present invention. Figure 5 As shown, the transient enhancement module may include: a bias circuit, a differential circuit and a conversion circuit.

[0054] The bias circuit is connected to the differential circuit and is used to provide a second bias current to the differential circuit.

[0055] The differential circuit is connected to the reference voltage and the feedback voltage and is used to generate an error signal according to the reference voltage and the feedback voltage.

[0056] The conversion circuit is connected to the differential circuit, the first amplifying module and the second amplifying module, and is used to convert the error signal into a first bias current and provide the first bias current to the first amplifying module and the second amplifying module.

[0057] Optional, such as Figure 5 As shown, the bias circuit includes a PMOS Q15, a PMOS Q14 and a current source.

[0058] One end of the current source is grounded, and the other end is connected to the drain of the PMOS Q15.

[0059] The gate of the PMOS Q15 is connected to the drain of the PMOS Q15 and the gate of the PMOS Q14. The source of the PMOS Q15 and the source of the PMOS Q14 are connected to the power supply voltage. The drain of the PMOS Q14 is connected to the differential circuit.

[0060] Optional, such as Figure 5 As shown, the differential circuit includes PMOS Q8 and PMOS Q9.

[0061] The gate of PMOS Q8 is connected to the reference voltage BG, the gate of PMOS Q9 is connected to the feedback voltage FB, the source of PMOS Q8 and the source of PMOS Q9 are connected to the drain of PMOS Q14, and the drain of PMOS Q8 and the drain of PMOS Q9 are connected to the conversion circuit.

[0062] Optional, such as Figure 5 As shown, the conversion circuit includes NMOS Q10, NMOS Q11 and NMOS Q12.

[0063] The drain of NMOS Q10 is connected to the drain of PMOS Q8 and the gate of NMOS Q10 , and the drain of NMOS Q11 is connected to the drain of PMOS Q9 , the gate of NMOS Q11 , and the gate of NMOS Q12 .

[0064] The drain of the NMOS Q12 is connected to the first amplifying module and the second amplifying module.

[0065] The source of the NMOS Q10 , the source of the NMOS Q11 , and the source of the NMOS Q12 are grounded.

[0066] Optional, such as Figure 5 As shown, the first amplifying module may include: PMOS Q1, PMOS Q2, PMOS Q3, NMOS Q4, NMOS Q5, NMOS Q6, PMOS Q7, PMOS Q13, and capacitor C2.

[0067] The gate of Q13 is connected to the drain of Q13 , the drain of Q12 , the gate of Q3 , the gate of Q7 , and the second amplification module.

[0068] The source of Q13, the source of Q3, and the source of Q7 are connected to the power supply voltage.

[0069] The drain of Q3 is connected to the source of Q1 and the source of Q2, the gate of Q1 is connected to the other end of the first resistor R1, and the gate of Q2 is connected to one end of the first resistor R1, that is, the target voltage is connected. Figure 5 As shown, it is assumed that the target voltage is the COMP voltage.

[0070] The drain of Q1 is connected to the drain of Q5 and the gate of Q6, the drain of Q2 is connected to the drain of Q4, the gate of Q4 is connected to the drain of Q4 and the gate of Q5, and the source of Q4 and the source of Q5 are grounded.

[0071] The source of Q6 is grounded, and the drain of Q6 is connected to the drain of Q7.

[0072] Capacitor C2 is connected between the gate of Q6 and the drain of Q6 , and C2 is the Miller compensation capacitor of the first amplification module.

[0073] Optional, such as Figure 5 As shown, the second amplifying module may include: PMOS Q1', PMOS Q2', PMOS Q3', NMOS Q4', NMOS Q5', NMOS Q6', PMOS Q7', and capacitor C2'.

[0074] The gates of Q3 ′, Q7 ′ and Q13 are connected.

[0075] The source of Q3 ′ and the source of Q7 ′ are connected to the power supply voltage.

[0076] The drain of Q3 ′ is connected to the source of Q1 ′ and the source of Q2 ′, the gate of Q1 ′ is connected to the other end of the second resistor R2 , and the gate of Q2 ′ is connected to one end of the second resistor R2 .

[0077] The drain of Q1' is connected to the drain of Q5' and the gate of Q6', the drain of Q2' is connected to the drain of Q4', the gate of Q4' is connected to the drain of Q4' and the gate of Q5', and the source of Q4' and the source of Q5' are grounded.

[0078] The source of Q6 ′ is grounded, and the drain of Q6 ′ is connected to the drain of Q7 ′.

[0079] Capacitor C2 ′ is connected between the gate of Q6 ′ and the drain of Q6 ′. C2 ′ is a Miller compensation capacitor of the second amplification module.

[0080] Figure 5 The circuit principle is as follows: Through the transient enhancement module, when the load changes, the differential pair Q8 and Q9 can identify the error voltage between the feedback voltage FB and the reference voltage BG, convert the error voltage into an error current, and mirror it to Q12 through the current mirror Q11, thereby changing the current in Q13. Q13 provides the first bias current for the first and second amplifier modules. If the current mirror ratio of Q7, Q3, Q7', Q3', and Q13 is 1:1:1:1:1, the current in Q13 will affect the currents in Q7 and Q7', thereby increasing the speed of change of the voltage at the COMP node when the load changes, thereby improving the response speed of the entire loop.

[0081] Figure 6 A circuit timing diagram of a transient enhancement module provided by an embodiment of the present invention, referring to Figure 5 ,like Figure 6 As shown, when the output current iL increases in a step at time T0, the charge of the output capacitor will decrease, the output voltage VOUT will decrease, the voltage of FB will decrease linearly with VOUT, and the COMP signal will increase. If there is no transient enhancement module, the COMP signal will rise to its maximum value after time t2, and the undershoot voltage of the FB signal will be V1. Through the transient enhancement module of the embodiment of the present invention, when a transient change occurs, the current I11 flowing through Q11 will increase through the action of the differential pair Q8 and Q9. Through the replication of the current mirror, the current I7 flowing through Q7 and the current I7' flowing through Q7' will increase. Then, the rise time of the COMP signal will be shortened to t1, and the undershoot voltage of the FB signal will be reduced to V2. It can be seen that the response speed of the load transient is significantly improved.

[0082] The embodiment of the present invention further provides a chip, which may include: Figure 1-Figure 5 Any multi-loop controlled DC-DC conversion circuit in.

[0083] In a possible implementation, the chip may be a power management chip. Of course, it may also be other types of chips, which are not specifically limited here.

[0084] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention shall be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A multi-loop controlled DC-DC conversion circuit, characterized in that: include: A first voltage dividing module and a second voltage dividing module are used to divide the target voltage; an energy storage module, one end of which is connected to the second voltage divider module and the other end of which is grounded; a first amplifying module, wherein two input terminals are respectively connected to two ends of the first voltage dividing module, and an output terminal is connected to the target voltage; a second amplifying module, wherein two input ends are respectively connected to two ends of the second voltage dividing module, and an output end is connected to one end of the second voltage dividing module; The amplification factor of the energy storage module is determined by the transconductance of the first amplifying module, the transconductance of the second amplifying module, the resistance of the first voltage dividing module, and the resistance of the second voltage dividing module.

2. The multi-loop controlled DC-DC conversion circuit according to claim 1, characterized in that: The energy storage module includes a capacitor; One end of the capacitor is connected to the other end of the second voltage divider module, and the other end is grounded.

3. The multi-loop controlled DC-DC conversion circuit according to claim 2, characterized in that: The first voltage dividing module includes a first resistor, and the second voltage dividing module includes a second resistor; One end of the first resistor is connected to the target voltage, and the other end of the first resistor is connected to one end of the second resistor. The other end of the second resistor is connected to one end of the capacitor.

4. The multi-loop controlled DC-DC conversion circuit according to claim 3, characterized in that: The magnification is expressed by the following formula: ; Wherein, K is the amplification factor, gm1 is the transconductance of the first amplifying module, gm2 is the transconductance of the second amplifying module, R1 is the resistance value of the first resistor, and R2 is the resistance value of the second resistor.

5. The multi-loop controlled DC-DC conversion circuit according to any one of claims 1 to 4, characterized in that: The multi-loop controlled DC-DC conversion circuit further includes: a transient enhancement module; The transient enhancement module is connected to the first amplification module and the second amplification module, is connected to the feedback voltage and the reference voltage, and is used to provide a first bias current for the first amplification module and the second amplification module according to an error signal between the feedback voltage and the reference voltage; The first amplifying module and the second amplifying module are configured to increase a changing speed of the target voltage according to the first bias current.

6. The multi-loop controlled DC-DC conversion circuit according to claim 5, characterized in that: The transient enhancement module includes: a bias circuit, a differential circuit and a conversion circuit; The bias circuit is connected to the differential circuit and is used to provide a second bias current to the differential circuit; The differential circuit is connected to the reference voltage and the feedback voltage, and is used to generate the error signal according to the reference voltage and the feedback voltage; The conversion circuit is connected to the differential circuit, the first amplifying module and the second amplifying module, and is configured to convert the error signal into the first bias current and provide the first bias current to the first amplifying module and the second amplifying module.

7. The multi-loop controlled DC-DC conversion circuit according to claim 6, characterized in that: The bias circuit includes a PMOS 15, a PMOS 14 and a current source; One end of the current source is grounded, and the other end is connected to the drain of the PMOS 15; The gate of the PMOS 15 is connected to the drain of the PMOS 15 and the gate of the PMOS 14 . The source of the PMOS 15 and the source of the PMOS 14 are connected to the power supply voltage. The drain of the PMOS 14 is connected to the differential circuit.

8. The multi-loop controlled DC-DC conversion circuit according to claim 7, characterized in that: The differential circuit includes PMOS 8 and PMOS 9; The gate of PMOS 8 is connected to the reference voltage, the gate of PMOS 9 is connected to the feedback voltage, the source of PMOS 8 and the source of PMOS 9 are connected to the drain of PMOS 14, and the drain of PMOS 8 and the drain of PMOS 9 are connected to the conversion circuit.

9. The multi-loop controlled DC-DC conversion circuit according to claim 8, characterized in that: The conversion circuit includes NMOS 10, NMOS 11 and NMOS 12; The drain of NMOS 10 is connected to the drain of PMOS 8 and the gate of NMOS 10, and the drain of NMOS 11 is connected to the drain of PMOS 9, the gate of NMOS 11, and the gate of NMOS 12; The drain of the NMOS 12 is connected to the first amplifying module and the second amplifying module; The source of the NMOS 10 , the source of the NMOS 11 , and the source of the NMOS 12 are grounded.

10. A chip, characterized in that: The chip includes the multi-loop controlled DC-DC conversion circuit according to any one of claims 1 to 9.

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