Buck converter with fast response output voltage switching

Abstract

The application relates to the technical field of power management integrated circuits, and discloses a Buck converter capable of quickly responding to output voltage switching. The converter comprises a Buck control module, a BUCK driving module, a power tube, an auxiliary charging low-dropout linear regulator and an auxiliary discharging low-dropout linear regulator; the target output value of the auxiliary charging low-dropout linear regulator is lower than the target output value of the Buck converter by a first deviation value, and the target output value of the auxiliary discharging low-dropout linear regulator is higher than the target output value of the Buck converter by a second deviation value; when the reference voltage rises, the auxiliary charging low-dropout linear regulator injects a large current to accelerate the rise of the output voltage; and when the reference voltage falls, the auxiliary discharging low-dropout linear regulator absorbs a large current to accelerate the fall of the output voltage. The application significantly improves the switching speed and transient response capability of the output voltage without affecting the overall efficiency of the Buck converter, and is suitable for application scenarios requiring frequent and fast switching of voltage domains.

Description

Technical Field

[0001] This application relates to the field of power management circuits, and in particular to switching power supply control technology. Background Technology

[0002] With the development of mobile communication technology, the integration and functional complexity of RF transceiver chips are constantly increasing. In RF transceiver chips, the RF amplifier is one of the important functional modules, and its power supply voltage needs to be switched rapidly according to different operating modes. For example, under the GSM standard, a higher power supply voltage is required for the RF amplifier to achieve better power efficiency; while under the WCDMA standard, a lower power supply voltage is required to achieve better linearity. Therefore, the power management circuit supplying the RF amplifier needs to have the ability to quickly switch the output voltage.

[0003] Currently, Buck converters are widely used in the power supply circuits of RF amplifiers due to their high conversion efficiency. However, traditional Buck converters suffer from slow response speed. This is because the output of the Buck converter is connected to an external inductor L0, and the current in the inductor cannot change abruptly. When a rapid increase in output voltage is required, even if the loop compensator rapidly increases the PWM duty cycle, the rise rate of the output voltage will be limited due to the limited rise rate of the inductor current. Similarly, when a rapid decrease in output voltage is required, the decrease rate of the inductor current will also limit the decrease rate of the output voltage.

[0004] This slow response time can lead to the following problems when switching operating modes: when switching from low to high voltage, the slow voltage rise rate may cause insufficient output power of the RF amplifier during the transition; when switching from high to low voltage, the slow voltage fall rate may cause a deterioration in the linearity of the RF amplifier during the transition. These problems will affect the overall performance of the RF transceiver chip.

[0005] Therefore, how to improve the switching speed of the output voltage while maintaining the high efficiency of the Buck converter is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The purpose of this application is to provide a Buck converter with fast response to output voltage switching, so as to solve the problems mentioned in the background art.

[0007] This application discloses a Buck converter with fast response to output voltage switching, comprising:

[0008] The Buck control module is used to monitor the output voltage of the Buck converter, output a pulse width modulation signal, and generate bias current and reference voltage.

[0009] The BUCK driver module and power transistors are provided. The input terminal of the BUCK driver module is connected to the pulse width modulation signal, and the output terminal outputs the drive signal. The power transistors include an upper P-type power transistor and a lower N-type power transistor. The source of the P-type power transistor is connected to the external input power supply voltage, and the gate is connected to the drive signal. The drain of the P-type power transistor is shorted to the drain of the N-type power transistor and outputs to the external circuit. The source of the N-type power transistor is connected to the ground terminal of the chip, and the gate is connected to the drive signal.

[0010] The auxiliary charging low-dropout linear regulator has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminals connected to the first reference voltage, the fourth bias current and the first bias current respectively, its adjustment control terminal connected to the first mismatch adjustment signal, and its output terminal connected to the output voltage.

[0011] The auxiliary discharge low-dropout linear regulator has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminals connected to the first reference voltage, the fifth bias current, the second bias current, and the third bias current, respectively, its adjustment control terminal connected to the second mismatch adjustment signal, and its output terminal connected to the output voltage.

[0012] External inductors and load capacitors are used to stabilize the output voltage.

[0013] In a preferred embodiment, the target output value of the auxiliary charging low-dropout linear regulator is lower than the target output value of the Buck converter by a first deviation value. When the reference voltage rises rapidly, the Buck converter controls the output voltage to gradually increase through a pulse width modulation signal. At the same time, the auxiliary charging low-dropout linear regulator responds quickly by injecting current into the output terminal to make the output voltage rise rapidly. When the output voltage reaches the preset output voltage of the auxiliary charging low-dropout linear regulator, the loop of the auxiliary charging low-dropout linear regulator is automatically shut down.

[0014] The target output value of the auxiliary discharge low-dropout linear regulator is higher than the target output value of the Buck converter by a second deviation value. When the reference voltage drops rapidly, the Buck converter gradually reduces the output voltage through pulse width modulation signal control. At the same time, the auxiliary discharge low-dropout linear regulator responds quickly, drawing current from the output terminal to make the output voltage drop rapidly. When the output voltage reaches the preset output voltage of the auxiliary discharge low-dropout linear regulator, the loop of the auxiliary discharge low-dropout linear regulator is automatically shut down, so that the auxiliary charging low-dropout linear regulator and the auxiliary discharge low-dropout linear regulator only work briefly when the reference voltage is rapidly rising and falling. After the switching is completed, the auxiliary charging low-dropout linear regulator and the auxiliary discharge low-dropout linear regulator are in the off state, which does not affect the overall efficiency of the Buck converter.

[0015] In a preferred embodiment, the Buck control module includes:

[0016] A first level converter and a second level converter, wherein the input of the first level converter is connected to a first digital mismatch adjustment signal, and the output of the first mismatch adjustment signal is output; the input of the second level converter is connected to a second digital mismatch adjustment signal, and the output of the second mismatch adjustment signal is output.

[0017] A low-pass filter whose input is connected to a reference voltage and outputs a first reference voltage after filtering out high-frequency noise;

[0018] The loop compensator has a reference voltage input terminal connected to a first reference voltage, a feedback input terminal connected to the output voltage, and an output signal from the loop compensator.

[0019] A PWM generator whose input is connected to the output signal of a loop compensator, and outputs a pulse width modulation signal.

[0020] The bias current generator has its input terminal connected to the first reference voltage and its output terminal outputting a first bias current, a second bias current, a third bias current, a fourth bias current, and a fifth bias current.

[0021] In a preferred embodiment, the auxiliary charging low-dropout linear regulator further includes a first amplifier, whose power supply terminal is connected to an analog power supply voltage, its ground terminal is connected to an analog ground, its non-inverting input terminal is connected to a first reference voltage, its inverting input terminal is connected to a first feedback voltage, and its output terminal outputs the first amplifier output voltage.

[0022] In a preferred embodiment, the auxiliary charging low-dropout linear regulator further includes:

[0023] The first output current limiting module has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminal connected to the fourth bias current, and its output terminal connected to the output voltage of the first amplifier.

[0024] A first N-type transistor, a first P-type transistor, and a second P-type transistor, wherein the source of the first N-type transistor is connected to the analog ground, the gate is connected to the output voltage of the first amplifier, and the drain is connected to the drain of the first P-type transistor to form a first current mirror junction voltage; the drain and gate of the first P-type transistor are shorted, and the source is connected to the analog power supply voltage; the source of the second P-type transistor is connected to the analog power supply voltage, the gate is shorted to the gate of the first P-type transistor, and the drain is connected to the output voltage;

[0025] The first voltage divider feedback module has its input terminal connected to the output voltage, its bias current terminal connected to the first bias current, its adjustment control terminal connected to the first mismatch adjustment signal, and its ground terminal connected to the analog ground.

[0026] In a preferred embodiment, the first voltage divider feedback module further includes:

[0027] The first group of resistors includes the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor;

[0028] First capacitor;

[0029] The first group of N-type switching transistors includes the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor;

[0030] First decoder;

[0031] The second, third, fourth, fifth, sixth, and seventh resistors are connected in series. One end of the second resistor is connected to the output voltage, and the voltage signal between the other end and the third resistor in series serves as the first feedback voltage. The first capacitor and the first resistor are connected in series between the output voltage and the first feedback voltage. The voltage signal between the third, fourth, fifth, sixth, and seventh resistors in series is connected to the sources of the third, fourth, fifth, and sixth N-type transistors, respectively. The drains of the third, fourth, fifth, and sixth N-type transistors are shorted together and connected to the first bias current. The input of the first decoder is connected to the first mismatch adjustment signal, and the output outputs a first set of switch control signals, including a first switch control signal, a second switch control signal, a third switch control signal, and a fourth switch control signal, which are connected in series to the gates of the third, fourth, fifth, and sixth N-type transistors.

[0032] In a preferred embodiment, the auxiliary discharge low-dropout linear regulator further includes:

[0033] The second amplifier has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its inverting input terminal connected to the first reference voltage, its non-inverting input terminal connected to the second feedback voltage, and its output terminal outputting the second amplifier output voltage.

[0034] The second output current limiting module has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminal connected to the fifth bias current, and its output terminal connected to the output voltage of the second amplifier.

[0035] The system comprises a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a third P-type transistor, and a fourth P-type transistor, as well as an eighth resistor. The source of the seventh N-type transistor is connected to the analog ground, its gate is connected to the output voltage of the second amplifier, and its drain is connected to the drain of the third P-type transistor to form a second current mirror connection point voltage. The drain and gate of the third P-type transistor are shorted, and its source is connected to the analog power supply voltage. The source of the fourth P-type transistor is connected to the analog power supply voltage, its gate is shorted to the gate of the third P-type transistor, and its drain is connected to the gate and drain of the eighth N-type transistor to form a third current mirror connection point voltage. The source of the eighth N-type transistor is connected to the analog ground, and its gate and drain are shorted to form the third current mirror connection point voltage and connected to the gate of the ninth N-type transistor. The drain of the ninth N-type transistor is connected to the output voltage and one end of the eighth resistor. The other end of the eighth resistor is connected to the third bias current.

[0036] The second voltage divider feedback module has its input terminal connected to the output voltage, its bias current terminal connected to the second bias current, its adjustment control terminal connected to the second mismatch adjustment signal, and its ground terminal connected to the analog ground.

[0037] In a preferred embodiment, the second voltage divider feedback module further includes:

[0038] The second group of resistors includes the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth resistors;

[0039] The second capacitor and the third capacitor;

[0040] The second group of N-type switching transistors includes the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor;

[0041] Second decoder;

[0042] The tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth resistors are connected in series. One end of the tenth resistor is connected to the analog ground, and the voltage signal between the other end and the eleventh resistor serves as the second feedback voltage. The second capacitor and the ninth resistor are connected in series between the output voltage and the second feedback voltage. The voltage signal between the tenth, eleventh, twelfth, thirteenth, and fourteenth resistors is connected to the source of the tenth, eleventh, twelfth, and thirteenth N-type transistors, respectively. The drains of the tenth, eleventh, twelfth, and thirteenth N-type transistors are shorted together and connected to the second bias current. The input of the second decoder is connected to the second mismatch adjustment signal, and the output outputs a second set of switch control signals, including a fifth, sixth, seventh, and eighth switch control signal, which are connected in series to the gate of the tenth, eleventh, twelfth, and thirteenth N-type transistors.

[0043] This application achieves the following technical effects by introducing an auxiliary charging low-dropout linear regulator and an auxiliary discharging low-dropout linear regulator into a traditional Buck converter:

[0044] First, it allows for rapid output voltage switching and improves the circuit's transient response. In traditional Buck converters, when the reference voltage suddenly rises (falls), the output signal of the loop compensator rises (falls), the duty cycle of the pulse width modulation signal increases (decreases), the power transistor's on-time increases (decreases), and the current in the external inductor increases (falls). Since the current in the external inductor cannot change abruptly, the output voltage cannot rise (fall) rapidly, making it unsuitable for applications requiring rapid output voltage switching. By introducing an auxiliary charging low-dropout linear regulator and an auxiliary discharging low-dropout linear regulator, when the reference voltage suddenly rises, the output of the auxiliary charging low-dropout linear regulator does not pass through the external inductor. Therefore, the internal loop of the auxiliary charging low-dropout linear regulator further activates the second P-type transistor, injecting a large current into the output terminal to increase the output voltage, significantly improving the output voltage rise speed. When the reference voltage suddenly drops, the output of the auxiliary discharge low-dropout linear regulator does not pass through the external inductor. Therefore, the internal loop of the auxiliary discharge low-dropout linear regulator will further open the ninth N-type transistor, draw a large current from the output terminal to reduce the output voltage, which greatly improves the speed at which the output voltage drops.

[0045] Second, it will not affect the overall efficiency of the Buck converter. By adjusting the first mismatch adjustment signal and the second mismatch adjustment signal, the target output value of the auxiliary charging low-dropout linear regulator is made to be lower than the target output value of the Buck converter by a first deviation value, while the target output value of the auxiliary discharging low-dropout linear regulator is higher than the target output value of the Buck converter by a second deviation value. Therefore, the auxiliary charging low-dropout linear regulator and the auxiliary discharging low-dropout linear regulator only operate briefly when the reference voltage is rapidly rising and falling, respectively. After the switching is completed, the auxiliary charging low-dropout linear regulator and the auxiliary discharging low-dropout linear regulator are in the off state, which will not affect the overall efficiency of the Buck converter.

[0046] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the overall structure of a Buck converter with fast-response output voltage switching according to an embodiment of this application.

[0048] Figure 2 This is a schematic diagram of the structure of existing technology that adds a compensation module to the constant conduction time control.

[0049] Figure 3 This is a schematic diagram of a design scheme where the reference voltage can be selected in the existing technology.

[0050] Figure 4 This is a schematic diagram of the Buck control module of a Buck converter with fast-response output voltage switching according to an embodiment of this application.

[0051] Figure 5This is a circuit diagram of an auxiliary charging low-dropout linear regulator for a Buck converter with fast-response output voltage switching according to an embodiment of this application.

[0052] Figure 6 This is a circuit diagram of the first voltage divider feedback module of a Buck converter with fast-response output voltage switching according to an embodiment of this application.

[0053] Figure 7 This is a waveform diagram of the auxiliary charging low-dropout linear regulator of the Buck converter with fast-response output voltage switching according to an embodiment of this application during operation, wherein... Figure 7 (a) shows the waveform of the output voltage variation without the assistance of an auxiliary charging low-dropout linear regulator. Figure 7 (b) shows the waveform of the output voltage change when assisted by an auxiliary charging low-dropout linear regulator.

[0054] Figure 8 This is a circuit diagram of an auxiliary discharge low-dropout linear regulator for a Buck converter with fast-response output voltage switching according to an embodiment of this application.

[0055] Figure 9 This is a circuit diagram of the second voltage divider feedback module of a Buck converter with fast-response output voltage switching according to an embodiment of this application.

[0056] Figure 10 This is a waveform diagram of the auxiliary discharge low-dropout linear regulator of the Buck converter with fast-response output voltage switching according to an embodiment of this application during operation, wherein... Figure 10 (a) shows the waveform of the output voltage change without the assistance of the low-dropout linear regulator. Figure 10 (b) shows the waveform of the output voltage change when assisted by an auxiliary discharge low-dropout linear regulator. Detailed Implementation

[0057] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0058] Explanation of some concepts:

[0059] Buck converter (hereinafter referred to as "BUCK"): A type of switching power supply that converts a higher input DC voltage into a lower stable output DC voltage by periodically turning a switching transistor on and off.

[0060] Pulse Width Modulation (PWM): A technique that modulates the duty cycle of a pulse signal. In Buck converters, it is used to control the on-time ratio of the switching transistor, thereby regulating the output voltage.

[0061] Low-dropout linear regulator (LDO): A type of linear regulator with a small input-output voltage difference, enabling rapid voltage regulation, but with relatively low efficiency. The auxiliary charging LDO1 and auxiliary discharging LDO2 described in this application both belong to this category.

[0062] Constant On-Time (COT) control: A control method that stabilizes the output voltage by fixing the on-time of the switching transistor.

[0063] P-type metal-oxide-semiconductor field-effect transistors (PMOS) and N-type metal-oxide-semiconductor field-effect transistors (NMOS) are two complementary types of field-effect transistors and are fundamental components of circuits. The first P-type power transistor (PMOS0) and the first N-type power transistor (NMOS0) are the main switching transistors in a Buck converter.

[0064] External inductor L0: A key component in the output filter circuit of the Buck converter. Together with the load capacitor CL, it forms an LC filter network to filter out switching ripple.

[0065] The first mismatch adjustment signal offset1_tune<1:0> and the second mismatch adjustment signal offset2_tune<1:0> are used to adjust the deviation of the expected output voltage of the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 from the output voltage of the Buck converter. In this specification, "first mismatch adjustment signal offset1_tune<1:0>" and "second mismatch adjustment signal offset2_tune<1:0>" are, in some places, exemplarily written as "2-bit mismatch adjustment signal offset1_tune<1:0>" and "2-bit mismatch adjustment signal offset2_tune<1:0>".

[0066] The following is a brief summary of some of the innovative aspects of this application:

[0067] In summary, this application creatively proposes a unique technical solution for applications where the RF amplifier in an RF transceiver module needs to rapidly switch voltage domains to adapt to different operating modes. It cleverly introduces two auxiliary low-dropout linear regulators (auxiliary charging low-dropout linear regulator LDO1 and auxiliary discharging low-dropout linear regulator LDO2) into the traditional Buck converter architecture. Through a carefully designed mismatch adjustment mechanism, these regulators operate effectively only during voltage switching transients. Specifically, the first mismatch adjustment signal offset1_tune<1:0> controls the target output value of the auxiliary charging low-dropout linear regulator LDO1 to be lower than the first deviation value Voffset1 of the Buck converter's target output value. The second mismatch adjustment signal offset2_tune<1:0> controls the target output value of the auxiliary discharging low-dropout linear regulator LDO2 to be higher than the second deviation value Voffset2 of the Buck converter's target output value. This allows these two auxiliary low-dropout linear regulators to overcome the dynamic response limitations of traditional Buck converters caused by the continuity of the external inductor L0 current without affecting the steady-state efficiency of the Buck converter. When the reference voltage Vref rises rapidly, the auxiliary charging low-dropout linear regulator LDO1 injects a large current through the second P-type transistor PMOS12; when the reference voltage Vref drops rapidly, the auxiliary discharging low-dropout linear regulator LDO2 absorbs a large current through the ninth N-type transistor NMOS23. This collaborative working mechanism based on a preset deviation value not only solves the problems of slow response and large fluctuations in output voltage Vout of traditional Buck converters when there are sudden load changes or when the output voltage Vout needs to be switched quickly, but also ensures that the system can smoothly transition to a high-efficiency steady-state working state after a rapid response through the automatic adjustment characteristics of the first voltage divider feedback module (13) and the second voltage divider feedback module (23), demonstrating the uniqueness of the technical concept and the outstanding technical effect of this application.

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0069] In this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as those represented by their corresponding Chinese names plus letter codes. For example, "BUCK" and "Buck converter" refer to the same technical feature, "PWM" and "pulse width modulation PWM" refer to the same technical feature, and other similar technical features represented by English letter codes are equivalent to their corresponding Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to:

[0070] Buck converter;

[0071] Pulse Width Modulation (PWM)

[0072] Low dropout linear regulator (LDO);

[0073] Auxiliary charging low dropout linear regulator LDO1;

[0074] Auxiliary discharge low-dropout linear regulator LDO2;

[0075] Output voltage Vout;

[0076] Reference voltage Vref;

[0077] First reference voltage Vref1;

[0078] First feedback voltage Vfb1;

[0079] Second feedback voltage Vfb2;

[0080] Input power supply voltage Vin;

[0081] Constant on-time control (COT);

[0082] Simulated power supply voltage VDD;

[0083] Simulated VSS;

[0084] The first amplifier output voltage Vg1;

[0085] The output voltage of the second amplifier is Vg2;

[0086] The voltage at the connection point of the first current mirror is Vbp1;

[0087] The voltage at the connection point of the second current mirror is Vbn2;

[0088] First deviation value Voffset1;

[0089] The second deviation value is Voffset2;

[0090] The expected output value of the first low-dropout linear regulator is Vout_LDO1;

[0091] The expected output value of the second low-dropout linear regulator is Vout_LDO2;

[0092] First bias current Ibn1;

[0093] Second bias current Ibn2;

[0094] The third bias current is Ibn10u;

[0095] Fourth bias current Ibp1;

[0096] Fifth bias current Ibp2;

[0097] P-type metal-oxide-semiconductor field-effect transistor (PMOS);

[0098] N-type metal-oxide-semiconductor field-effect transistor (NMOS);

[0099] First P-type power transistor PMOS0;

[0100] The first N-type power transistor is NMOS0;

[0101] First drive signal HS;

[0102] Second drive signal LS;

[0103] First amplifier AMP1;

[0104] Second amplifier AMP2;

[0105] External inductor L0;

[0106] Load capacitance CL;

[0107] The loop compensator outputs the signal Verr.

[0108] The first mismatch adjustment signal is offset1_tune<1:0>.

[0109] The second mismatch adjustment signal is offset2_tune<1:0>.

[0110] The first set of switch control signals SC11-SC14;

[0111] The second set of switch control signals SC21-SC24;

[0112] The first group of resistors is R10-R16;

[0113] The second set of resistors is R20-R28;

[0114] First capacitor C10;

[0115] Second capacitor C20;

[0116] Third capacitor C21;

[0117] The first group of transistors are NMOS11, PMOS11, and PMOS12;

[0118] The second group of transistors are NMOS21-23 and PMOS21-22;

[0119] The first group of NMOS switches is SMN11-14;

[0120] The second group of NMOS switches is SMN21-24.

[0121] Furthermore, in all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0122] 11: First output current limiting module;

[0123] 21: Second output current limiting module;

[0124] 13: First voltage divider feedback module;

[0125] 23: Second voltage divider feedback module;

[0126] 12: First decoder;

[0127] 22: Second decoder.

[0128] To make this specification clearer and more concise, the same technical feature may be described using different Chinese terms in different contexts. For example, "low dropout linear regulator (LDO)" and "LDO regulator" refer to the same technical feature. For ease of expression and to avoid repetition, different terms are used for the same technical feature in this specification, such as letter codes, English abbreviations, and Chinese names.

[0129] It should be noted that although different expressions may be used for the same technical features in the specification of this application, as long as the letter codes or English abbreviations are the same, they refer to the same technical features. The correspondence between different terms can be determined based on the specific description and drawings in the specification. Those skilled in the art can clearly understand the technical features referred to by the same letter codes or English abbreviations based on the content of the specification, and will not have difficulty understanding the content of the invention.

[0130] In this specification, to maintain brevity, the same technical feature is presented in the form of "Chinese name + English code" when it first appears, and may be presented in the form of only its English code when it appears thereafter. These different forms of expression refer to the same technical feature.

[0131] To make this specification clearer and more concise, the same technical feature may be described using different Chinese terms in different contexts. For example, "low dropout linear regulator (LDO)" and "LDO regulator" refer to the same technical feature. For ease of expression and to avoid repetition, different terms are used for the same technical feature in this specification, such as letter codes, English abbreviations, and Chinese names.

[0132] It should be noted that although different expressions may be used for the same technical features in the specification of this application, as long as the letter codes or English abbreviations are the same, they refer to the same technical features. The correspondence between different terms can be determined based on the specific description and drawings in the specification. Those skilled in the art can clearly understand the technical features referred to by the same letter codes or English abbreviations based on the content of the specification, and will not have difficulty understanding the content of the invention.

[0133] The first embodiment of this application relates to a Buck converter with fast response to output voltage switching, such as... Figure 1 , Figures 4 to 6 ,as well as Figure 8 and Figure 9 As shown, it includes:

[0134] The Buck control module is used to monitor the output voltage Vout of the Buck converter, output a pulse width modulation (PWM) signal, and generate bias current and reference voltage Vref.

[0135] The BUCK driver module and power transistors are provided. The input of the BUCK driver module is connected to the pulse width modulation (PWM) signal, and the output of the BUCK driver module is the drive signal HS and LS. The power transistors include an upper P-type power transistor PMOS0 and a lower N-type power transistor NMOS0. The source of the P-type power transistor PMOS0 is connected to the external input power supply voltage Vin, the gate is connected to the drive signal HS, and the drain of the P-type power transistor PMOS0 is shorted to the drain of the N-type power transistor NMOS0 and output to the external circuit. The source of the N-type power transistor NMOS0 is connected to the ground of the chip, and the gate is connected to the drive signal LS.

[0136] The auxiliary charging low-dropout linear regulator LDO1 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminals connected to the first reference voltage Vref1, the fourth bias current Ibp1 and the first bias current Ibn1 respectively, its adjustment control terminal connected to the first mismatch adjustment signal offset1_tune<1:0>, and its output terminal connected to the output voltage Vout.

[0137] The auxiliary discharge low-dropout linear regulator LDO2 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminals connected to the first reference voltage Vref1, the fifth bias current Ibp2, the second bias current Ibn2 and the third bias current Ibn10u respectively, its adjustment control terminal connected to the second mismatch adjustment signal offset2_tune<1:0>, and its output terminal connected to the output voltage Vout.

[0138] Optionally, the target output value of the auxiliary charging low-dropout linear regulator LDO1 is lower than the target output value of the Buck converter by a first deviation value Voffset1. When the reference voltage Vref rises rapidly, the Buck converter gradually increases the output voltage Vout through pulse width modulation (PWM) signal control. At the same time, the auxiliary charging low-dropout linear regulator LDO1 responds quickly by injecting current into the output terminal to make the output voltage Vout rise rapidly. When the output voltage Vout reaches the preset output voltage of the auxiliary charging low-dropout linear regulator LDO1, the loop of the auxiliary charging low-dropout linear regulator LDO1 is automatically shut down.

[0139] The target output value of the auxiliary discharge low-dropout linear regulator LDO2 is higher than the target output value of the Buck converter by a second deviation value Voffset2. When the reference voltage Vref drops rapidly, the Buck converter gradually reduces the output voltage Vout through pulse width modulation (PWM) signal control. At the same time, the auxiliary discharge low-dropout linear regulator LDO2 responds quickly, drawing current from the output terminal to make the output voltage Vout drop rapidly. When the output voltage Vout reaches the preset output voltage of the auxiliary discharge low-dropout linear regulator LDO2, the loop of the auxiliary discharge low-dropout linear regulator LDO2 is automatically shut down. This means that the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharge low-dropout linear regulator LDO2 only work briefly when the reference voltage Vref is rapidly rising and falling. After the switching is completed, the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharge low-dropout linear regulator LDO2 are in the off state, which does not affect the overall efficiency of the Buck converter.

[0140] Optionally, the Buck control module includes:

[0141] A first level converter and a second level converter, wherein the input of the first level converter is connected to a first digital mismatch adjustment signal offset1_tune_dig<1:0>, and the output of the first mismatch adjustment signal offset1_tune<1:0> is output; the input of the second level converter is connected to a second digital mismatch adjustment signal offset2_tune_dig<1:0>, and the output of the second mismatch adjustment signal offset2_tune<1:0> is output.

[0142] A low-pass filter, whose input is connected to a reference voltage Vref, and outputs a first reference voltage Vref1 after filtering out high-frequency noise;

[0143] The loop compensator has its reference voltage input terminal connected to the first reference voltage Vref1, its feedback input terminal connected to the output voltage Vout, and its output loop compensator output signal Verr.

[0144] The PWM generator has its input terminal connected to the output signal Verr of the loop compensator, and outputs a pulse width modulation (PWM) signal.

[0145] The bias current generator has its input terminal connected to the first reference voltage Vref1, and its output terminal outputting a first bias current Ibn1, a second bias current Ibn2, a third bias current Ibn10u, a fourth bias current Ibp1, and a fifth bias current Ibp2.

[0146] Optionally, the auxiliary charging low-dropout linear regulator LDO1 further includes a first amplifier AMP1, whose power supply terminal is connected to the analog power supply voltage VDD, its ground terminal is connected to the analog ground VSS, its non-inverting input terminal is connected to the first reference voltage Vref1, its inverting input terminal is connected to the first feedback voltage Vfb1, and its output terminal outputs the first amplifier output voltage Vg1.

[0147] Optionally, the auxiliary charging low-dropout linear regulator LDO1 further includes:

[0148] The first output current limiting module 11 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminal connected to the fourth bias current Ibp1, and its output terminal connected to the first amplifier output voltage Vg1.

[0149] A first N-type transistor NMOS11, a first P-type transistor PMOS11, and a second P-type transistor PMOS12 are wherein the source of the first N-type transistor NMOS11 is connected to the analog ground VSS, the gate is connected to the first amplifier output voltage Vg1, and the drain is connected to the drain of the first P-type transistor PMOS11 to form a first current mirror connection point voltage Vbp1; the drain and gate of the first P-type transistor PMOS11 are shorted, and the source is connected to the analog power supply voltage VDD; the source of the second P-type transistor PMOS12 is connected to the analog power supply voltage VDD, the gate is shorted to the gate of the first P-type transistor PMOS11, and the drain is connected to the output voltage Vout.

[0150] The first voltage divider feedback module 13 has its input terminal connected to the output voltage Vout, its bias current terminal connected to the first bias current Ibn1, its adjustment control terminal connected to the first mismatch adjustment signal offset1_tune<1:0>, and its ground terminal connected to the analog ground VSS.

[0151] Optionally, the first voltage divider feedback module 13 further includes:

[0152] The first group of resistors includes the first resistor R10, the second resistor R11, the third resistor R12, the fourth resistor R13, the fifth resistor R14, the sixth resistor R15, and the seventh resistor R16.

[0153] First capacitor C10;

[0154] The first group of N-type switching transistors includes the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14;

[0155] First decoder 12;

[0156] The second resistor R11, the third resistor R12, the fourth resistor R13, the fifth resistor R14, the sixth resistor R15, and the seventh resistor R16 are connected in series. One end of the second resistor R11 is connected to the output voltage Vout, and the voltage signal between the other end of the second resistor R11 and the third resistor R12 in series serves as the first feedback voltage Vfb1. The first capacitor C10 and the first resistor R10 are connected in series between the output voltage Vout and the first feedback voltage Vfb1. The voltage signal between the third resistor R12, the fourth resistor R13, the fifth resistor R14, the sixth resistor R15, and the seventh resistor R16 in series is respectively connected to the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the seventh resistor R16. The source of the sixth N-type transistor SWN14, and the drains of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14 are shorted together and connected to the first bias current Ibn1. The input terminal of the first decoder 12 is connected to the first mismatch adjustment signal offset1_tune<1:0>, and the output terminal outputs the first set of switch control signals, including the first switch control signal SC11, the second switch control signal SC12, the third switch control signal SC13, and the fourth switch control signal SC14, which are sequentially connected to the gates of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14.

[0157] Optionally, the auxiliary discharge low-dropout linear regulator LDO2 further includes:

[0158] The second amplifier AMP2 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its inverting input terminal connected to the first reference voltage Vref1, its non-inverting input terminal connected to the second feedback voltage Vfb2, and its output terminal outputting the second amplifier output voltage Vg2.

[0159] The second output current limiting module 21 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminal connected to the fifth bias current Ibp2, and its output terminal connected to the second amplifier output voltage Vg2.

[0160] The seventh N-type transistor NMOS21, the eighth N-type transistor NMOS22, the ninth N-type transistor NMOS23, the third P-type transistor PMOS21, and the fourth P-type transistor PMOS22, along with the eighth resistor R28, wherein the source of the seventh N-type transistor NMOS21 is connected to the analog ground VSS, the gate is connected to the second amplifier output voltage Vg2, and the drain is connected to the drain of the third P-type transistor PMOS21 to form the second current mirror connection point voltage Vbp2; the drain and gate of the third P-type transistor PMOS21 are shorted, and the source is connected to the analog power supply voltage VDD; the source of the fourth P-type transistor PMOS22 is connected to... The analog power supply voltage VDD has its gate shorted to the gate of the third P-type transistor PMOS21, and its drain connected to the gate and drain of the eighth N-type transistor NMOS22 to form the third current mirror connection point voltage Vbn2; the source of the eighth N-type transistor NMOS22 is connected to the analog ground VSS, and its gate and drain are shorted to form the third current mirror connection point voltage Vbn2, which is also connected to the gate of the ninth N-type transistor NMOS23; the drain of the ninth N-type transistor NMOS23 is connected to the output voltage Vout and one end of the eighth resistor R28; the other end of the eighth resistor R28 is connected to the third bias current Ibn10u;

[0161] The second voltage divider feedback module 23 has its input terminal connected to the output voltage Vout, its bias current terminal connected to the second bias current Ibn2, its adjustment control terminal connected to the second mismatch adjustment signal offset2_tune<1:0>, and its ground terminal connected to the analog ground VSS.

[0162] Optionally, the second voltage divider feedback module 23 further includes:

[0163] The second group of resistors includes the ninth resistor R20, the tenth resistor R21, the eleventh resistor R22, the twelfth resistor R23, the thirteenth resistor R24, the fourteenth resistor R25, and the fifteenth resistor R26;

[0164] The second capacitor C20 and the third capacitor C21;

[0165] The second group of N-type switching transistors includes the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23, and the thirteenth N-type transistor SWN24;

[0166] Second decoder 22;

[0167] The tenth resistor R21, eleventh resistor R22, twelfth resistor R23, thirteenth resistor R24, fourteenth resistor R25, and fifteenth resistor R26 are connected in series. One end of the tenth resistor R21 is connected to the analog ground VSS, and the voltage signal between the other end and the eleventh resistor R22 in series serves as the second feedback voltage Vfb2. The second capacitor C20 and the ninth resistor R20 are connected in series between the output voltage Vout and the second feedback voltage Vfb2. The voltage signal between the tenth resistor R21, eleventh resistor R22, twelfth resistor R23, thirteenth resistor R24, and fourteenth resistor R25 in series is respectively connected to the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, and the twelfth N-type transistor SWN23. The source of the thirteenth N-type transistor SWN24, the drains of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23, and the thirteenth N-type transistor SWN24 are shorted together and connected to the second bias current Ibn2. The input terminal of the second decoder 22 is connected to the second mismatch adjustment signal offset2_tune<1:0>, and the output terminal outputs the second set of switch control signals, including the fifth switch control signal SC21, the sixth switch control signal SC22, the seventh switch control signal SC23, and the eighth switch control signal SC24, which are sequentially connected to the gates of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23, and the thirteenth N-type transistor SWN24.

[0168] To make the technical solution of this application clearer and more understandable, the following is combined with Figures 1 to 9 Preferred embodiments of this application are described in detail, but it should be understood that the described embodiments are merely exemplary and not restrictive.

[0169] Figure 1 This is a structural diagram of the Buck converter (hereinafter referred to as "Buck converter") with fast response output voltage switching according to this application. Figure 1 As shown, the Buck converter includes a Buck control module, a Buck drive module, a power transistor, an auxiliary charging low-dropout linear regulator (hereinafter referred to as "Auxiliary Charging LDO1" or "LDO1") and an auxiliary discharging low-dropout linear regulator (hereinafter referred to as "Auxiliary Discharging LDO2" or "LDO2"), as well as an external inductor L0 and a load capacitor CL.

[0170] Specifically, the Buck control module monitors the output voltage Vout of the Buck converter, outputs a pulse width modulation signal (PWM signal), and generates a bias current and a reference voltage Vref. The input of the Buck drive module is connected to the PWM signal, and the output of the drive signal is HS and LS. The power transistors include an upper P-type power transistor PMOS0 and a lower N-type power transistor NMOS0. The source of PMOS0 is connected to the external input power supply voltage Vin, the gate is connected to the drive signal HS, the drain is shorted to the drain of NMOS0 and output to the external circuit, the source of NMOS0 is connected to the chip ground, and the gate is connected to the drive signal LS.

[0171] The auxiliary charging LDO1 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminals connected to the first reference voltage Vref1 and the bias currents Ibp1 and Ibn1 respectively, its adjustment control terminal connected to the 2-bit mismatch adjustment signal offset1_tune<1:0>, and its output terminal connected to the output voltage Vout. The auxiliary charging LDO1 is used to assist the Buck converter in rapidly increasing its output voltage.

[0172] The auxiliary discharge LDO2 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminals connected to the first reference voltage Vref1 and the bias currents Ibp2, Ibn2 and Ibn10u respectively, its adjustment control terminal connected to the 2-bit mismatch adjustment signal offset2_tune<1:0>, and its output terminal connected to the output voltage Vout. The auxiliary discharge LDO2 is used to assist the Buck converter output voltage to drop rapidly.

[0173] The external inductor L0 and load capacitor CL are used to stabilize the output voltage Vout.

[0174] When a rapid rise in output voltage Vout is required, the Buck converter gradually increases the output voltage under PWM signal control, while the auxiliary charging LDO1 responds quickly to replenish the output current and reduce the voltage rise time. When a rapid drop in output voltage Vout is required, the auxiliary discharging LDO2 quickly absorbs excess current to reduce the output voltage, while the Buck converter gradually reduces the output voltage under PWM signal control. Through the coordinated operation of auxiliary charging LDO1 and auxiliary discharging LDO2, the Buck converter achieves rapid switching of output voltage, improving the circuit's dynamic response capability.

[0175] Figure 2 This is a schematic diagram of an existing constant on-time control (COT) system with an added compensation module. (See diagram below.) Figure 2As shown, this structure is a Buck converter with fast dynamic response. By adding a compensation module to the COT (Constant Voltage Regulator) architecture, the dynamic response performance is improved. While this design improves the transient response of the Buck converter, it cannot meet the requirement of rapid output voltage switching when the reference voltage changes rapidly. The figure shows the existing Buck converter circuit structure with COT control, which includes the input power supply Vin, driver, switching transistor, inductor L, load capacitor CO, sense resistor network, and control loop circuit. This structure regulates the output voltage through duty cycle control, but due to the continuity limitation of the inductor current, its response speed is slow when rapid output voltage switching is required, failing to meet the requirements of high-performance power systems for fast voltage switching.

[0176] Figure 3 This is a schematic diagram of the existing design options for the reference voltage. For example... Figure 3 As shown, this structure is a voltage-mode Buck converter that achieves reference voltage switching through a reference voltage selection circuit and a threshold control circuit. The figure illustrates the input power supply Vin, a high-side P-type transistor, a low-side N-type transistor MN, an inductor L, an output capacitor CL, a load current Iload, load resistors RFB1 and RFB2, and the control circuitry. The control circuitry includes a COT control circuit, a ramp generator, a reference voltage selection circuit, and a voltage controller. This design accelerates duty cycle changes and improves transient performance through the reference voltage selection circuit and threshold control circuit, but it still cannot meet the requirement of fast output voltage switching. Although this existing structure can achieve reference voltage selection, its response speed is still slow when fast output voltage switching is required due to the continuous characteristics of the inductor current.

[0177] Figure 4 This is a structural diagram of the Buck control module of this application. Figure 4As shown, the Buck control module includes a level shifter, a low-pass filter, a loop compensator, a PWM generator, and a bias current generator. The level shifter converts the digital voltage domain signal into the desired analog voltage domain signal. Its inputs are connected to two sets of 2-bit digital mismatch adjustment signals offset1_tune_dig<1:0> and offset2_tune_dig<1:0>, and its outputs are the same 2-bit mismatch adjustment signals offset1_tune<1:0> and offset2_tune<1:0>. The low-pass filter removes high-frequency noise from the reference voltage Vref. Its input is connected to the reference voltage Vref, and after filtering out high-frequency noise, it outputs the first reference voltage Vref1. The loop compensator, by adding poles and zeros to the loop, can offset... The LC filter eliminates phase lag or lead, while simultaneously increasing the DC gain of the Buck system to enhance its ability to adjust to changes in input voltage and load. Its reference voltage input is connected to the first reference voltage Vref1, its feedback input is connected to the output voltage Vout, and its output loop compensator output signal Verr. The PWM generator generates PWM signals; its input is connected to the loop compensator output signal Verr, and it outputs PWM signals. The bias current generator generates various bias currents required by other modules; its input is connected to the first reference voltage Vref1, and it outputs bias currents Ibn1, Ibn2, Ibn10u, Ibp1, and Ibp2.

[0178] Figure 5 This is a circuit diagram of the auxiliary charging LDO1 of this application. Figure 5As shown, the auxiliary charging LDO1 includes a first amplifier AMP1, a first output current limiting module 11, transistors NMOS11, PMOS11, PMOS12, and a first voltage divider feedback module 13. AMP1 is used to amplify the difference between the first feedback voltage Vfb1 and the first reference voltage Vref1, and outputs the first amplifier output voltage Vg1. The output voltage Vout is adjusted through the negative feedback loop of the auxiliary charging LDO1. Its power supply terminal is connected to the analog power supply VDD, its ground terminal is connected to the analog ground VSS, its non-inverting input terminal is connected to the first reference voltage Vref1, its inverting input terminal is connected to the first feedback voltage Vfb1, and its output terminal outputs the first amplifier output voltage Vg1. The first output current limiting module 11 is used to limit the gate voltage Vg1 of NMOS11, so that the voltage difference Vgs between the gate and source of NMOS11 is limited to the expected range. Its power supply terminal is connected to the analog power supply VDD, its ground terminal is connected to the analog ground VSS, its input terminal is connected to the bias current Ibp1, and its output terminal is connected to the first amplifier output voltage Vg1; the source of transistor NMOS11 is connected to the analog ground VSS, its gate is connected to the first amplifier output voltage Vg1, and its drain is connected to the drain of transistor PMOS11 to form the first current mirror connection point voltage Vbp1; the drain and gate of transistor PMOS11 are shorted, and its source is connected to the analog power supply VDD; the source of transistor PMOS12 is connected to the analog power supply VDD, its gate is shorted to the gate of transistor PMOS11, and its drain is connected to the output voltage Vout; the first voltage divider feedback module 13 has its input terminal connected to the output voltage Vout, its bias current terminal connected to the bias current Ibn1, its adjustment control terminal connected to the 2-bit mismatch adjustment signal offset1_tune<1:0>, and its ground terminal connected to the analog ground VSS.

[0179] Figure 6 This is a circuit diagram of the first voltage divider feedback module 13 of this application. (See diagram for example.) Figure 6As shown, the first voltage divider feedback module 13 includes resistors R10-R16, capacitor C10, NMOS switches SMN11, SWN12, SWN13, and SWN14, and a first decoder 12. Resistors R11-R16 are connected in series. One end of resistor R11 is connected to the output voltage Vout, and the voltage signal between the other end of resistor R11 and resistor R12 is used as the first feedback voltage Vfb1. A capacitor C10 and resistor R10 are connected in series between the output voltage Vout and the first feedback voltage Vfb1. The voltage signal between resistors R12-R16 is connected to the source of NMOS switches SMN11-SWN14 respectively. The drains of these NMOS switches are shorted together and connected to the bias current Ibn1. The input of the first decoder 12 is connected to a 2-bit mismatch adjustment signal offset1_tune<1:0>, and the output output outputs four sets of switch control signals SC11-SC14, which are connected in series to the gate of NMOS switches SMN11-SWN14. The voltage divider resistor feedback module injects current Ibn1 into the series resistors of different poles by adjusting the mismatch adjustment signal offset1_tune<1:0>, which causes the LDO output voltage to deviate from the Buck target voltage.

[0180] Figure 7 This is a waveform diagram of the auxiliary charging LDO1 during operation. For example... Figure 7 As shown, Figure 7 (a) is the waveform when the reference voltage Vref is switched from low to high without the assistance of an LDO. Figure 7 (b) shows the waveform when Vref switches from low to high with the assistance of the auxiliary LDO. It is clear from the waveform that with the assistance of the auxiliary charging LDO1, the output voltage Vout rises to the target value more quickly when the reference voltage Vref switches from low to high. It can be seen that... Figure 7 In (b), the ILDO1 signal indicates that the auxiliary charging LDO1 is activated during the rise of the reference voltage Vref, providing additional current to accelerate the rise of the output voltage Vout, significantly shortening the voltage rise time. Figure 7 In (a), due to the lack of auxiliary LDO support, the output voltage Vout rises slowly and takes longer to reach a stable state.

[0181] Figure 8 This is the circuit diagram of the auxiliary discharge LDO2 of this application. Figure 8As shown, the auxiliary discharge LDO2 includes a second amplifier AMP2, a second output current limiting module 21, transistors NMOS21, NMOS22, NMOS23, PMOS21, PMOS22, resistor R28, and a second voltage divider feedback module 23. AMP2 is used to amplify the difference between the feedback voltage Vfb2 and the first reference voltage Vref1 and output signal Vg2. It also adjusts the output voltage Vout through the negative feedback loop of the auxiliary discharge LDO2. Its power supply terminal is connected to the analog power supply VDD, its ground terminal is connected to the analog ground VSS, its inverting input terminal is connected to the first reference voltage Vref1, its non-inverting input terminal is connected to the feedback voltage Vfb2, and its output terminal outputs voltage Vg2. The second output current limiting module 21 is used to limit the gate voltage Vg2 of NMOS21, so that the voltage difference Vgs between the gate and source of NMOS21 is limited to the expected range. Its power supply terminal is connected to the analog power supply VDD, its ground terminal is connected to the analog ground VSS, its input terminal is connected to the bias current Ibp2, and its output terminal is connected to voltage Vg2. The source of transistor NMOS21 is connected to analog ground VSS, its gate is connected to voltage Vg2, and its drain is connected to the drain of transistor PMOS21 to form the second current mirror connection point voltage Vbp2; the drain and gate of transistor PMOS21 are shorted, and its source is connected to analog power supply VDD; the source of transistor PMOS22 is connected to analog power supply VDD, its gate is shorted to the gate of transistor PMOS21, and its drain is connected to the gate and drain of transistor NMOS22 to form the third current mirror connection point voltage Vbn2; the source of transistor NMOS22... The gate and drain of transistor NMOS23 are connected to analog ground VSS, and the gate and drain are shorted to Vbn2 and connected to the gate of transistor NMOS23. The drain of transistor NMOS23 is connected to the output voltage Vout and one end of resistor R28. The other end of resistor R28 is connected to the bias current Ibn10u. The second voltage divider feedback module 23 has its input terminal connected to the output voltage Vout, its bias current terminal connected to the bias current Ibn2, its adjustment control terminal connected to the 2-bit mismatch adjustment signal offset2_tune<1:0>, and its ground terminal connected to analog ground VSS.

[0182] Figure 9 This is a circuit diagram of the second voltage divider feedback module 23 of this application. (See diagram for example.) Figure 9As shown, the second voltage divider feedback module 23 includes resistors R20-R26, capacitors C20 and C21, NMOS switches SMN21, SWN22, SWN23, and SWN24, and a second decoder 22. Resistors R21-R26 are connected in series. One end of resistor R21 is connected to the power supply ground VSS, and the voltage signal between the other end and resistor R22 in series serves as the feedback signal Vfb2. A capacitor C20 and resistor R20 are connected in series between the output voltage Vout and the feedback signal Vfb2. The voltage signal between resistors R21-R25 in series is connected to the source of NMOS switches SMN21-SWN24 respectively. The drains of these NMOS switches are shorted together and connected to the bias current Ibn2. The input of the second decoder 22 is connected to a 2-bit mismatch adjustment signal offset2_tune<1:0>, and the output outputs four sets of switch control signals SC21-SC24, which are connected in series to the gate of NMOS switches SMN21-SWN24. The voltage divider resistor feedback module can draw current Ibn2 from the different series resistors by adjusting the mismatch adjustment signal offset2_tune<1:0>, which can cause the LDO's expected output voltage to deviate from the Buck target voltage.

[0183] Figure 10 This is a waveform diagram of the auxiliary discharge LDO2 during operation, as described in this application. Figure 10 As shown, Figure 10 (a) is the waveform when the reference voltage Vref is switched from high to low without the assistance of an LDO. Figure 10 (b) shows the waveform when Vref switches from high to low with the assistance of the auxiliary LDO. It is clear from the waveform that with the assistance of the auxiliary discharge LDO2, the output voltage Vout drops to the target value more quickly when the reference voltage Vref switches from high to low. It can be seen that... Figure 10 In (b), the ILDO2 signal indicates that the auxiliary discharge LDO2 is activated during the drop of the reference voltage Vref, accelerating the drop of the output voltage Vout by absorbing excess current, thus significantly shortening the voltage drop time. Figure 10 In (a), due to the lack of auxiliary LDO support, the output voltage Vout decreases more slowly and takes longer to reach a stable state.

[0184] Working principle:

[0185] The Buck converter with fast-response output voltage switching of this application includes the following main functional modules: a Buck control module, used to monitor the output voltage Vout state and generate a PWM signal to adjust the duty cycle of the power transistor to ensure that the output voltage Vout is stable at the expected value, while providing a reference voltage Vref and bias current for other modules; a Buck drive module, which converts the PWM signal to the drive voltage domain and improves the signal's driving capability to drive the power transistor; an auxiliary charging low-dropout linear regulator LDO1, which, when a rapid increase in output voltage is required, gradually increases the output voltage through PWM control, while the auxiliary charging low-dropout linear regulator LDO1 responds quickly to supplement the output current and reduce the voltage rise time; and an auxiliary discharging low-dropout linear regulator LDO2, which, when a rapid decrease in output voltage is required, quickly absorbs excess current to reduce the output voltage, while the Buck converter gradually decreases the output voltage through PWM control.

[0186] Buck control module, such as Figure 4 As shown, the system includes a level shifter, a low-pass filter, a loop compensator, a PWM generator, and a bias current generator. The level shifter converts the digital voltage domain signal into the desired analog voltage domain signal; the low-pass filter filters out high-frequency noise on the reference voltage Vref and outputs a first reference voltage Vref1; the loop compensator, by adding poles and zeros to the loop, cancels the phase lag or lead caused by the LC filter, while simultaneously increasing the DC gain of the Buck system to enhance its ability to adjust to changes in input voltage and load, ensuring stable output voltage under various operating conditions; the PWM generator generates PWM signals; and the bias current generator generates various bias currents required by other modules.

[0187] The operating steps of the auxiliary charging low-dropout linear regulator LDO1 are as follows:

[0188] Step 1: When the Buck converter is first started or when the Buck converter has started but the output voltage needs to be increased to a higher level, the output voltage Vout is at a low level. At this time, the Buck converter gradually increases the output voltage through PWM control. At the same time, the first voltage divider feedback module 13 of the auxiliary charging low dropout linear regulator LDO1 samples the output voltage Vout and outputs the first feedback voltage Vfb1. At this time, the first feedback voltage Vfb1 is less than the first reference voltage Vref1. After passing through the first amplifier AMP1, the output voltage Vg1 of the first amplifier increases, the current of the transistor NMOS11 increases, and the pull-up current of the output transistor PMOS12 increases synchronously to supplement the output current and reduce the voltage rise time.

[0189] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary charging low dropout linear regulator LDO1, due to the continuous operation of the Buck system, the output voltage Vout will continue to rise towards the preset output voltage of the Buck converter. At this time, the sampling voltage of the first voltage divider feedback module 13, the first feedback voltage Vfb1, gradually exceeds the first reference voltage Vref1. After passing through the first amplifier AMP1, the output voltage Vg1 of the first amplifier gradually decreases, the current of transistor NMOS11 gradually decreases, and the pull-up current of the output transistor PMOS12 decreases synchronously. When the first feedback voltage Vfb1 exceeds the first reference voltage Vref1 by a certain value, the output voltage Vg1 of the first amplifier drops to the limit, and transistors NMOS11 and PMOS12 are all turned off, so that the loop of the auxiliary charging low dropout linear regulator LDO1 is completely disconnected from the Buck system, thus not affecting the overall efficiency of the Buck converter.

[0190] The operating steps of the auxiliary discharge low-dropout linear regulator LDO2 are as follows:

[0191] Step 1: When the input reference voltage of Buck is switched from high to low, and the output voltage needs to be reduced to a lower level, the output voltage Vout is still at a relatively high level. At this time, the Buck converter gradually reduces the output voltage through PWM control. At the same time, the second voltage divider feedback module 23 of the auxiliary discharge low dropout linear regulator LDO2 samples the output voltage Vout and outputs the second feedback voltage Vfb2. At this time, the second feedback voltage Vfb2 is greater than the first reference voltage Vref1. After passing through the second amplifier AMP2, the output voltage Vg2 of the second amplifier increases, and the current of the transistor NMOS21 increases, which causes the pull-down current of the output transistor NMOS23 to increase synchronously to draw a large current from the output terminal and reduce the voltage drop time.

[0192] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary discharge low-dropout linear regulator LDO2, due to the continuous operation of the Buck system, the output voltage Vout will continue to decrease towards the preset output voltage of the Buck converter. At this time, the sampling voltage of the second voltage divider feedback module 23, the second feedback voltage Vfb2, gradually becomes less than the first reference voltage Vref1. After passing through the second amplifier AMP2, the output voltage Vg2 of the second amplifier gradually decreases, the current of transistor NMOS21 gradually decreases, and the pull-down current of the output transistor NMOS23 decreases synchronously. When the second feedback voltage Vfb2 is less than a certain value of the first reference voltage Vref1, the output voltage Vg2 of the second amplifier drops to its limit, and transistors NMOS21 and NMOS23 are all turned off, so that the loop of the auxiliary discharge low-dropout linear regulator LDO2 is completely disconnected from the Buck system, thus not affecting the overall efficiency of the Buck converter.

[0193] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0194] This example presents a Buck converter with fast response to output voltage switching, including:

[0195] The Buck control module is used to monitor the output voltage Vout of the Buck converter, output a pulse width modulation (PWM) signal, and generate bias current and reference voltage Vref.

[0196] The BUCK driver module and power transistor are used to enhance the driving capability of the pulse width modulation (PWM) signal and output the corresponding driving voltage to drive the power transistor.

[0197] The auxiliary charging low-dropout linear regulator LDO1 is used to assist the Buck converter output voltage to rise rapidly.

[0198] The auxiliary discharge low-dropout linear regulator LDO2 is used to assist the Buck converter output voltage to drop rapidly.

[0199] The external inductor L0 and load capacitor CL are used to stabilize the output voltage Vout.

[0200] Preferably, the Buck control module includes: a first level converter and a second level converter, wherein the input of the first level converter is connected to a first digital mismatch adjustment signal offset1_tune_dig<1:0>, and the output of the first mismatch adjustment signal offset1_tune<1:0> is output; the input of the second level converter is connected to a second digital mismatch adjustment signal offset2_tune_dig<1:0>, and the output of the second mismatch adjustment signal offset2_tune<1:0> is output; and a low-pass filter, the input of which is connected to a reference voltage Vref, and After filtering out high-frequency noise, the first reference voltage Vref1 is output; the loop compensator has its reference voltage input connected to the first reference voltage Vref1, its feedback input connected to the output voltage Vout, and outputs the loop compensator output signal Verr; the PWM generator has its input connected to the loop compensator output signal Verr, and outputs a pulse width modulation (PWM) signal; the bias current generator has its input connected to the first reference voltage Vref1, and outputs the first bias current Ibn1, the second bias current Ibn2, the third bias current Ibn10u, the fourth bias current Ibp1, and the fifth bias current Ibp2.

[0201] Preferably, the input terminal of the BUCK drive module is connected to the pulse width modulation (PWM) signal, and the output terminal outputs drive signals HS and LS; the power transistors include an upper P-type power transistor PMOS0 and a lower N-type power transistor NMOS0, wherein the source of the P-type power transistor PMOS0 is connected to the external input power supply voltage Vin, the gate is connected to the drive signal HS, the drain is shorted to the drain of the N-type power transistor NMOS0 and output to the external circuit, the source of the N-type power transistor NMOS0 is connected to the chip ground, and the gate is connected to the drive signal LS.

[0202] Preferably, the auxiliary charging low-dropout linear regulator LDO1 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminals connected to the first reference voltage Vref1, the fourth bias current Ibp1 and the first bias current Ibn1 respectively, its adjustment control terminal connected to the first mismatch adjustment signal offset1_tune<1:0>, and its output terminal connected to the output voltage Vout.

[0203] Preferably, the auxiliary charging low-dropout linear regulator LDO1 further includes a first amplifier AMP1, whose power supply terminal is connected to the analog power supply voltage VDD, its ground terminal is connected to the analog ground VSS, its non-inverting input terminal is connected to the first reference voltage Vref1, its inverting input terminal is connected to the first feedback voltage Vfb1, and its output terminal outputs the first amplifier output voltage Vg1.

[0204] Preferably, the auxiliary charging low-dropout linear regulator LDO1 further includes: a first output current limiting module 11, whose power supply terminal is connected to the analog power supply voltage VDD, ground terminal is connected to the analog ground VSS, input terminal is connected to the fourth bias current Ibp1, and output terminal is connected to the first amplifier output voltage Vg1.

[0205] Preferably, the auxiliary charging low-dropout linear regulator LDO1 further includes a first N-type transistor NMOS11, a first P-type transistor PMOS11, and a second P-type transistor PMOS12. The source of the first N-type transistor NMOS11 is connected to the analog ground VSS, its gate is connected to the first amplifier output voltage Vg1, and its drain is connected to the drain of the first P-type transistor PMOS11 to form a first current mirror connection point voltage Vbp1. The drain and gate of the first P-type transistor PMOS11 are shorted, and its source is connected to the analog power supply voltage VDD. The source of the second P-type transistor PMOS12 is connected to the analog power supply voltage VDD, its gate is shorted to the gate of the first P-type transistor PMOS11, and its drain is connected to the output voltage Vout. The first voltage divider feedback module 13 has its input connected to the output voltage Vout, its bias current connected to the first bias current Ibn1, its adjustment control connected to the first mismatch adjustment signal offset1_tune<1:0>, and its ground connected to the analog ground VSS.

[0206] Preferably, the first voltage divider feedback module 13 is used to adjust the first deviation value Voffset1 between the expected output voltage of the auxiliary charging low dropout linear regulator LDO1 and the output voltage of the Buck converter. Its input terminal is connected to the output voltage Vout, the bias current terminal is connected to the first bias current Ibn1, the adjustment control terminal is connected to the first mismatch adjustment signal offset1_tune<1:0>, the ground terminal is connected to the analog ground VSS, and the output terminal outputs the first feedback voltage Vfb1.

[0207] Preferably, the first voltage divider feedback module 13 further includes: a first group of resistors, including a first resistor R10, a second resistor R11, a third resistor R12, a fourth resistor R13, a fifth resistor R14, a sixth resistor R15, and a seventh resistor R16; a first capacitor C10; a first group of N-type switching transistors, including a third N-type transistor SMN11, a fourth N-type transistor SWN12, a fifth N-type transistor SWN13, and a sixth N-type transistor SWN14; and a first decoder 12; wherein the second resistor R11, the third resistor R12, the fourth resistor R13, the fifth resistor R14, the sixth resistor R15, and the seventh resistor R16 are connected in series, one end of the second resistor R11 is connected to the output voltage Vout, and the voltage signal between the other end and the third resistor R12 is used as the first feedback voltage Vfb1. The first capacitor C10 and the first resistor R10 are connected in series between the output voltage Vout and the first feedback voltage Vfb1. The third resistor R12, the fourth resistor R15, the fifth resistor R16, the fifth resistor R16, the sixth resistor R16, and the seventh resistor R16 are connected in series. 13. The voltage signal between the fifth resistor R14, the sixth resistor R15, and the seventh resistor R16 connected in series is respectively connected to the source of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14. The drains of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14 are shorted together and connected to the first bias current Ibn1. The input terminal of the first decoder 12 is connected to the first mismatch adjustment signal offset1_tune<1:0>, and the output terminal outputs the first set of switch control signals, including the first switch control signal SC11, the second switch control signal SC12, the third switch control signal SC13, and the fourth switch control signal SC14, which are sequentially connected to the gate of the third N-type transistor SMN11, the fourth N-type transistor SWN12, the fifth N-type transistor SWN13, and the sixth N-type transistor SWN14.

[0208] The first voltage divider feedback module 13 is used to adjust the expected output value Vout_LDO1 of the auxiliary charging low-dropout linear regulator LDO1. Assuming the first mismatch adjustment signal offset1_tune<1:0>=0b00, after being decoded by the first decoder 12, the first switch control signal SC11 is pulled high, and the third N-type transistor SMN11 is turned on. At this time, the derivation formula of the relationship between the expected output value Vout_LDO1 of the auxiliary charging low-dropout linear regulator LDO1 and the first feedback voltage Vfb1 is as follows:

[0209] V out_ldo1 =(R 11 +R 12 +R 13 +R14 +R 15 +R 16 )×Vfb1 / (R 12 +R 13 +R 14 +R 15 +R 16 )-Ibn1*R 11 *(R 13 +R 14 +R 15 +R 16 ) / (R 12 +R 13 +R 14 +R 15 +R 16 (1)

[0210] The resistor divider is configured to ensure that the Buck converter's output voltage Vout satisfies the formula: V out =(R 11 +R 12 +R 13 +R 14 +R 15 +R 16 )Vref / (R 12 +R 13 +R 14 +R 15 +R 16 (2)

[0211] When the auxiliary charging low-dropout linear regulator LDO1 is working normally, since Vfb1 = Vref, we have:

[0212] V out_ldo1 =V out -Ibn1*R 11 *(R 13 +R 14 +R 15 +R 16 ) / (R 12 +R 13 +R 14 +R 15 +R 16 (3)

[0213] Among them, V out_ldo1 This indicates the preset output voltage value of the auxiliary charging low-dropout linear regulator, which is the target output voltage that the auxiliary charging low-dropout linear regulator stabilizes when it is working.

[0214] Then V offset1 =Ibn1*R 11 *(R 13 +R 14 +R15 +R 16 ) / (R 12 +R 13 +R 14 +R 15 +R 16 (4)

[0215] Among them, V offset1 This represents the first deviation value, which is the voltage difference between the target output voltage of the auxiliary charging low-dropout linear regulator and the target output voltage of the Buck converter.

[0216] Preferably, the auxiliary discharge low-dropout linear regulator LDO2 has its power supply terminal connected to the analog power supply voltage VDD, its ground terminal connected to the analog ground VSS, its input terminals connected to the first reference voltage Vref1, the fifth bias current Ibp2, the second bias current Ibn2 and the third bias current Ibn10u respectively, its adjustment control terminal connected to the second mismatch adjustment signal offset2_tune<1:0>, and its output terminal connected to the output voltage Vout.

[0217] Preferably, the auxiliary discharge low-dropout linear regulator LDO2 further includes: a second amplifier AMP2, whose power supply terminal is connected to the analog power supply voltage VDD, its ground terminal is connected to the analog ground VSS, its inverting input terminal is connected to the first reference voltage Vref1, its non-inverting input terminal is connected to the second feedback voltage Vfb2, and its output terminal outputs the second amplifier output voltage Vg2.

[0218] Preferably, the auxiliary discharge low-dropout linear regulator LDO2 further includes a second output current limiting module 21, whose power supply terminal is connected to the analog power supply voltage VDD, ground terminal is connected to the analog ground VSS, input terminal is connected to the fifth bias current Ibp2, and output terminal is connected to the second amplifier output voltage Vg2.

[0219] Preferably, the auxiliary discharge low-dropout linear regulator LDO2 further includes a seventh N-type transistor NMOS21, an eighth N-type transistor NMOS22, a ninth N-type transistor NMOS23, a third P-type transistor PMOS21, and a fourth P-type transistor PMOS22, as well as an eighth resistor R28. The source of the seventh N-type transistor NMOS21 is connected to the analog ground VSS, its gate is connected to the second amplifier output voltage Vg2, and its drain is connected to the drain of the third P-type transistor PMOS21 to form the second current mirror connection point voltage Vbp2. The drain and gate of the third P-type transistor PMOS21 are shorted, and its source is connected to the analog power supply voltage VDD. The source of the fourth P-type transistor PMOS22 is connected to the analog power supply voltage VDD, and its gate is shorted to the gate of the third P-type transistor PMOS21. The drain is connected to the gate of the eighth N-type transistor NMOS22, and the drain forms the third current mirror connection point voltage Vbn2; the source of the eighth N-type transistor NMOS22 is connected to the analog ground VSS, and the gate and drain are shorted to form the third current mirror connection point voltage Vbn2 and connected to the gate of the ninth N-type transistor NMOS23; the drain of the ninth N-type transistor NMOS23 is connected to the output voltage Vout and one end of the eighth resistor R28; the other end of the eighth resistor R28 is connected to the third bias current Ibn10u; the second voltage divider feedback module 23 has its input terminal connected to the output voltage Vout, its bias current terminal connected to the second bias current Ibn2, its adjustment control terminal connected to the second mismatch adjustment signal offset2_tune<1:0>, and its ground terminal connected to the analog ground VSS.

[0220] Preferably, the second voltage divider feedback module 23 is used to adjust the second deviation value Voffset2 between the expected output voltage of the auxiliary discharge low-dropout linear regulator LDO2 and the output voltage of the Buck converter. Its input terminal is connected to the output voltage Vout, its bias current terminal is connected to the second bias current Ibn2, its adjustment control terminal is connected to the second mismatch adjustment signal offset2_tune<1:0>, its ground terminal is connected to the analog ground VSS, and its output terminal outputs the second feedback voltage Vfb2.

[0221] Preferably, the second voltage divider feedback module 23 further includes: a second group of resistors, including a ninth resistor R20, a tenth resistor R21, an eleventh resistor R22, a twelfth resistor R23, a thirteenth resistor R24, a fourteenth resistor R25, and a fifteenth resistor R26; a second capacitor C20 and a third capacitor C21; a second group of N-type switching transistors, including a tenth N-type transistor SMN21, an eleventh N-type transistor SWN22, a twelfth N-type transistor SWN23, and a thirteenth N-type transistor SWN24; and a second decoder 22; wherein... The tenth resistor R21, the eleventh resistor R22, the twelfth resistor R23, the thirteenth resistor R24, the fourteenth resistor R25, and the fifteenth resistor R26 are connected in series. One end of the tenth resistor R21 is connected to the analog ground VSS, and the voltage signal between the other end and the eleventh resistor R22 in series serves as the second feedback voltage Vfb2. The second capacitor C20 and the ninth resistor R20 are connected in series between the output voltage Vout and the second feedback voltage Vfb2. The tenth resistor R21, the eleventh resistor R22, the twelfth resistor R23, the thirteenth resistor R24, the fourteenth resistor R25, and the fifteenth resistor R26 are connected in series. The voltage signal between resistors R22, R23, R24, and R25, which are connected in series, is connected to the sources of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23, and the thirteenth N-type transistor SWN24, respectively. The drains of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23, and the thirteenth N-type transistor SWN24 are shorted together and connected to the second bias current. Ibn2, the input terminal of the second decoder 22 is connected to the second mismatch adjustment signal offset2_tune<1:0>, and the output terminal outputs the second set of switch control signals, including the fifth switch control signal SC21, the sixth switch control signal SC22, the seventh switch control signal SC23 and the eighth switch control signal SC24, which are sequentially connected to the gates of the tenth N-type transistor SMN21, the eleventh N-type transistor SWN22, the twelfth N-type transistor SWN23 and the thirteenth N-type transistor SWN24.

[0222] The second voltage divider feedback module 23 is used to adjust the expected output value Vout_LDO2 of the auxiliary discharge low-dropout linear regulator LDO2. Assuming the second mismatch adjustment signal offset2_tune<1:0>=0b00, after being decoded by the second decoder 22, the fifth switch control signal SC21 is pulled high, the tenth N-type transistor SMN21 is turned on, and all other switches are turned off. At this time, the derivation formula of the relationship between the expected output value Vout_LDO2 of the auxiliary discharge low-dropout linear regulator LDO2 and the second feedback voltage Vfb2 is as follows:

[0223] V out_ldo2 =(R 21+R 22 +R 23 +R 24 +R 25 +R 26 )×Vfb2 / (R 21 )-Ibn2*(R 23 +R 24 +R 25 +R 26 (5)

[0224] The resistor value is set so that the output voltage Vout of the Buck converter satisfies the formula:

[0225] V out =(R 21 +R 22 +R 23 +R 24 +R 25 +R 26 )Vref / (R 21 (6)

[0226] When the auxiliary discharge low-dropout linear regulator LDO2 is working normally, since Vfb2 = Vref, we have:

[0227] V out_ldo2 =V out -Ibn2*(R 23 +R 24 +R 25 +R 26 (7)

[0228] Then V offset2 =Ibn2*(R 23 +R 24 +R 25 +R 26 (8)

[0229] More specifically, the Buck converter with fast-response output voltage switching of this application includes the following main functional modules: a Buck control module, used to monitor the output voltage Vout state of the Buck converter and generate a pulse width modulation (PWM) signal to adjust the duty cycle of the power transistor to ensure that the output voltage Vout is stable at the expected value, while providing a reference voltage Vref and bias current for other modules; a Buck drive module, which converts the PWM signal to the drive voltage domain and improves the driving capability of the signal to drive the power transistor; an auxiliary charging low-dropout linear regulator (LDO1), which, when a rapid increase in output voltage is required, gradually increases the output voltage Vout through PWM signal control, while the auxiliary charging LDO1 responds quickly to supplement the output current and reduce the voltage rise time; and an auxiliary discharging LDO2, which, when a rapid decrease in output voltage is required, quickly absorbs excess current to reduce the output voltage Vout, while the Buck converter gradually decreases the output voltage Vout through PWM signal control.

[0230] Buck control module, such as Figure 4 As shown, the system includes a level shifter, a low-pass filter, a loop compensator, a PWM generator, and a bias current generator. The level shifter converts digital voltage domain signals into the desired analog voltage domain signals; the low-pass filter filters out high-frequency noise on the reference voltage Vref, outputting a first reference voltage Vref1; the loop compensator, by adding poles and zeros to the loop, cancels the phase lag or lead caused by the LC filter, while simultaneously increasing the DC gain of the Buck system to enhance its ability to adjust to input voltage and load changes, ensuring stable output voltage under various operating conditions; the PWM generator generates pulse width modulation (PWM) signals; and the bias current generator generates various bias currents required by other modules.

[0231] The BUCK driver module is used to convert the PWM signal into two sets of signals with a certain dead time, ensuring that there is a non-overlapping time period between the high-side power transistor PMOS0 and the low-side power transistor NMOS0, that is, the time period during which both power transistors are in the off state at a certain moment, thereby avoiding shoot-through between the upper and lower transistors, and improving the driving capability of the signal, outputting the drive signals HS and LS that can drive the power transistors.

[0232] Auxiliary charging low dropout linear regulator LDO1, such as Figure 5As shown, it includes a first amplifier AMP1, a first output current limiting module 11, transistors NMOS11, PMOS11, PMOS12 and a first voltage divider feedback module 13. The first amplifier AMP1 amplifies the difference between the first feedback voltage Vfb1 and the first reference voltage Vref1, and outputs the first amplifier output voltage Vg1. The output voltage Vout is adjusted through the negative feedback loop of the auxiliary charging low-dropout linear regulator LDO1. The difference between the first feedback voltage Vfb1 and the first reference voltage Vref1 gradually decreases, causing the output voltage Vout to eventually stabilize at the expected value. The first output current limiting module 11 limits the gate voltage Vg1 of the first N-type transistor NMOS11, limiting the voltage difference Vgs between the gate and source of the first N-type transistor NMOS11 to within the expected range. According to the characteristics of saturated transistors, when Vgs is limited, its current is also limited. Then, through the mirroring effect of the current mirrors of the first P-type transistor PMOS11 and the second P-type transistor PMOS12 according to a preset ratio, the pull-up current at the output terminal of the auxiliary charging low-dropout linear regulator LDO1 is limited to within the expected value. The first voltage divider feedback module 13... Figure 6 As shown, the output voltage of the auxiliary charging low dropout linear regulator LDO1 is sampled according to a certain ratio to obtain voltage Vfb1 and fed back to the inverting input terminal of the first amplifier AMP1. At the same time, by adjusting the first mismatch adjustment signal offset1_tune<1:0>, current Ibn1 is injected into the series resistors of different poles, so that the output voltage of the auxiliary charging low dropout linear regulator LDO1 deviates from the target voltage of the Buck converter.

[0233] The operating steps of the auxiliary charging low-dropout linear regulator LDO1 are as follows:

[0234] Step 1: When the Buck converter is first started, or when the Buck converter has already started but the output voltage needs to be increased to a higher level, the output voltage Vout is at a low level. At this time, the Buck converter gradually increases the output voltage Vout through PWM signal control. Simultaneously, the first voltage divider feedback module 13 of the auxiliary charging low dropout linear regulator LDO1 samples the output voltage Vout and outputs the first feedback voltage Vfb1. At this time, the first feedback voltage Vfb1 is less than the first reference voltage Vref1. After passing through the first amplifier AMP1, the output voltage Vg1 of the first amplifier increases, and the current of the first N-type transistor NMOS11 increases, causing the pull-up current of the second P-type transistor PMOS12 to increase synchronously to supplement the output current and reduce the voltage rise time. The waveform diagram is as follows. Figure 7 As shown, where Figure 7 (a) is the waveform when the reference voltage Vref is switched from low to high without the assistance of the low-dropout linear regulator LDO1. Figure 7(b) is the waveform when the reference voltage Vref is switched from low to high with the assistance of the low dropout linear regulator LDO1.

[0235] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary charging low-dropout linear regulator LDO1, due to the continuous operation of the Buck converter, the output voltage Vout will continue to rise towards the preset output voltage of the Buck converter. At this time, the first voltage divider feedback module 13 samples the first feedback voltage Vfb1, which gradually exceeds the first reference voltage Vref1. After passing through the first amplifier AMP1, the output voltage Vg1 of the first amplifier gradually decreases, the current of the first N-type transistor NMOS11 gradually decreases, and the pull-up current of the second P-type transistor PMOS12 decreases synchronously. When the first feedback voltage Vfb1 is greater than the first reference voltage Vref1 by a certain value, the output voltage Vg1 of the first amplifier drops to the limit, and the first N-type transistor NMOS11 and the second P-type transistor PMOS12 are all turned off, so that the loop of the auxiliary charging low-dropout linear regulator LDO1 is completely disconnected from the Buck system, thus not affecting the overall efficiency of the Buck converter.

[0236] Auxiliary discharge low dropout linear regulator LDO2, such as Figure 8 As shown, it includes a second amplifier AMP2, a second output current limiting module 21, transistors NMOS21, NMOS22, NMOS23, PMOS21, PMOS22, an eighth resistor R28, and a second voltage divider feedback module 23. The second amplifier AMP2 amplifies the difference between the second feedback voltage Vfb2 and the first reference voltage Vref1, and outputs the second amplifier output voltage Vg2. The output voltage Vout is adjusted through the negative feedback loop of the auxiliary discharge low-dropout linear regulator LDO2. The difference between the second feedback voltage Vfb2 and the first reference voltage Vref1 gradually decreases, causing the output voltage Vout to eventually stabilize at the expected value. The second output current limiting module 21 limits the gate voltage Vg2 of the seventh N-type transistor NMOS21, ensuring that the voltage difference Vgs between the gate and source of the seventh N-type transistor NMOS21 is limited to the expected range. Through the current mirror composed of the third P-type transistor PMOS21, the fourth P-type transistor PMOS22, the eighth N-type transistor NMOS22, and the ninth N-type transistor NMOS23, the pull-down current at the output of the auxiliary discharge low-dropout linear regulator LDO2 is limited to the expected value. The second voltage divider feedback module 23, as... Figure 9As shown, the output voltage of the auxiliary discharge low-dropout linear regulator LDO2 is sampled according to a certain ratio to obtain the second feedback voltage Vfb2 and fed back to the inverting input of the second amplifier AMP2. At the same time, by adjusting the second mismatch adjustment signal offset2_tune<1:0>, the current Ibn2 is drawn from the series resistors of different poles, so that the expected output voltage of the auxiliary discharge low-dropout linear regulator LDO2 deviates from the target voltage of the Buck converter.

[0237] The operating steps of the auxiliary discharge low-dropout linear regulator LDO2 are as follows:

[0238] Step 1: When the input reference voltage Vref of the Buck converter switches from high to low, and the output voltage Vout needs to be reduced to a lower level, the output voltage Vout is still at a relatively high level. At this time, the Buck converter gradually reduces the output voltage Vout through PWM signal control. Simultaneously, the second voltage divider feedback module 23 of the auxiliary discharge low-dropout linear regulator LDO2 samples the output voltage Vout and outputs the second feedback voltage Vfb2. At this time, the second feedback voltage Vfb2 is greater than the first reference voltage Vref1. After passing through the second amplifier AMP2, the output voltage Vg2 of the second amplifier increases, and the current of the seventh N-type transistor NMOS21 increases, causing the pull-down current of the ninth N-type transistor NMOS23 to increase synchronously to draw a large current from the output terminal and reduce the voltage drop time. The waveform diagram is as follows. Figure 10 As shown, where Figure 10 (a) is the waveform when the reference voltage Vref is switched from high to low without the assistance of the low-dropout linear regulator LDO2. Figure 10 (b) is the waveform when the reference voltage Vref is switched from high to low with the assistance of the low dropout linear regulator LDO2.

[0239] Step 2: After the output voltage Vout reaches the preset output voltage of the auxiliary discharge low-dropout linear regulator LDO2, due to the continuous operation of the Buck converter, the output voltage Vout will continue to decrease towards the preset output voltage of the Buck converter. At this time, the second voltage divider feedback module 23 samples the second feedback voltage Vfb2, which gradually becomes less than the first reference voltage Vref1. After passing through the second amplifier AMP2, the output voltage Vg2 of the second amplifier gradually decreases, the current of the seventh N-type transistor NMOS21 gradually decreases, and the pull-down current of the ninth N-type transistor NMOS23 decreases synchronously. When the second feedback voltage Vfb2 is less than a certain value of the first reference voltage Vref1, the output voltage Vg2 of the second amplifier drops to its limit, and both the seventh N-type transistor NMOS21 and the ninth N-type transistor NMOS23 are turned off, so that the loop of the auxiliary discharge low-dropout linear regulator LDO2 is completely disconnected from the Buck system, thus not affecting the overall efficiency of the Buck converter.

[0240] Compared with the prior art, the beneficial effects of this application are as follows:

[0241] Benefit 1: It can quickly switch the output voltage and improve the transient response capability of the circuit.

[0242] In a traditional Buck converter, when the reference voltage Vref suddenly rises (falls), the output signal Verr of the loop compensator rises (falls), the duty cycle of the pulse width modulation (PWM) signal increases (decreases), the on-time of the power transistor increases (decreases), and the current of the external inductor L0 increases (falls). Since the current on the external inductor L0 cannot change abruptly, the output voltage Vout cannot rise (fall) rapidly. Therefore, it is not suitable for some applications that require rapid switching of the output voltage.

[0243] By introducing the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2, when the reference voltage Vref suddenly rises, the output of the auxiliary charging low-dropout linear regulator LDO1 does not pass through the external inductor L0. Therefore, the internal loop of the auxiliary charging low-dropout linear regulator LDO1 will further open the second P-type transistor PMOS12, injecting a large current into the output terminal to make the output voltage Vout rise, greatly improving the rise speed of the output voltage Vout. When the reference voltage Vref suddenly drops, the output of the auxiliary discharging low-dropout linear regulator LDO2 does not pass through the external inductor L0. Therefore, the internal loop of the auxiliary discharging low-dropout linear regulator LDO2 will further open the ninth N-type transistor NMOS23, drawing a large current from the output terminal to make the output voltage Vout drop, greatly improving the drop speed of the output voltage Vout.

[0244] Benefit 2: It will not affect the overall efficiency of the Buck converter.

[0245] By adjusting the first mismatch adjustment signal offset1_tune<1:0> and the second mismatch adjustment signal offset2_tune<1:0>, the target output value of the auxiliary charging low-dropout linear regulator LDO1 is made to be lower than the target output value of the Buck converter by a first deviation value Voffset1, while the target output value of the auxiliary discharging low-dropout linear regulator LDO2 is higher than the target output value of the Buck converter by a second deviation value Voffset2. Therefore, the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 only operate briefly when the reference voltage Vref is rapidly rising and falling. After the switching is completed, the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 are in the off state and will not affect the overall efficiency of the Buck converter.

[0246] The above embodiments have the following technical effects:

[0247] First, it allows for rapid output voltage switching and improves the circuit's transient response. In traditional Buck converters, when the reference voltage Vref suddenly rises (falls), the output signal Verr of the loop compensator rises (falls), the duty cycle of the pulse width modulation (PWM) signal increases (decreases), the on-time of the power transistor increases (decreases), and the current in the external inductor L0 increases (falls). Since the current in the external inductor L0 cannot change abruptly, the output voltage Vout cannot rise (fall) rapidly, making it unsuitable for applications requiring rapid output voltage switching. By introducing the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2, when the reference voltage Vref suddenly rises, the output of the auxiliary charging low-dropout linear regulator LDO1 does not pass through the external inductor L0. Therefore, the internal loop of the auxiliary charging low-dropout linear regulator LDO1 further activates the second P-type transistor PMOS12, injecting a large current into the output terminal to cause the output voltage Vout to rise, greatly improving the rise speed of the output voltage Vout. When the reference voltage Vref suddenly drops, the output of the auxiliary discharge low dropout linear regulator LDO2 does not pass through the external inductor L0. Therefore, the internal loop of the auxiliary discharge low dropout linear regulator LDO2 will further open the ninth N-type transistor NMOS23, draw a large current from the output terminal to make the output voltage Vout drop, which greatly improves the drop speed of the output voltage Vout.

[0248] Second, it will not affect the overall efficiency of the Buck converter. By adjusting the first mismatch adjustment signal offset1_tune<1:0> and the second mismatch adjustment signal offset2_tune<1:0>, the target output value of the auxiliary charging low-dropout linear regulator LDO1 is made to be lower than the target output value of the Buck converter by a first deviation value Voffset1, while the target output value of the auxiliary discharging low-dropout linear regulator LDO2 is higher than the target output value of the Buck converter by a second deviation value Voffset2. Therefore, the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 only operate briefly when the reference voltage Vref is rapidly rising and falling. After the switching is completed, the auxiliary charging low-dropout linear regulator LDO1 and the auxiliary discharging low-dropout linear regulator LDO2 are in the off state, which will not affect the overall efficiency of the Buck converter.

[0249] It should be noted that in the application documents of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In the application documents of this application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0250] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A BUCK converter with fast response to output voltage switching, characterized in that, include: The BUCK control module is used to monitor the output voltage of the BUCK converter, output a pulse width modulation signal, and generate bias current and reference voltage. The BUCK driver module and power transistors are provided. The input terminal of the BUCK driver module is connected to the pulse width modulation signal, and the output terminal outputs the drive signal. The power transistors include an upper P-type power transistor and a lower N-type power transistor. The source of the P-type power transistor is connected to the external input power supply voltage, and the gate is connected to the drive signal. The drain of the P-type power transistor is shorted to the drain of the N-type power transistor and outputs to the external circuit. The source of the N-type power transistor is connected to the ground terminal of the chip, and the gate is connected to the drive signal. The auxiliary charging low-dropout linear regulator has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminals connected to the first reference voltage, the fourth bias current and the first bias current respectively, its adjustment control terminal connected to the first mismatch adjustment signal, and its output terminal connected to the output voltage. The auxiliary discharge low-dropout linear regulator has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminals connected to the first reference voltage, the fifth bias current, the second bias current and the third bias current respectively, its adjustment control terminal connected to the second mismatch adjustment signal, and its output terminal connected to the output voltage. External inductors and load capacitors are used to stabilize the output voltage; The target output value of the auxiliary charging low-dropout linear regulator is lower than the target output value of the BUCK converter by a first deviation value. When the reference voltage rises rapidly, the BUCK converter gradually increases the output voltage through pulse width modulation signal control. At the same time, the auxiliary charging low-dropout linear regulator responds quickly and injects current into the output terminal to make the output voltage rise rapidly. When the output voltage reaches the preset output voltage of the auxiliary charging low-dropout linear regulator, the loop of the auxiliary charging low-dropout linear regulator is automatically closed. The target output value of the auxiliary discharge low-dropout linear regulator is higher than the target output value of the BUCK converter by a second deviation value. When the reference voltage drops rapidly, the BUCK converter gradually reduces the output voltage through pulse width modulation signal control. At the same time, the auxiliary discharge low-dropout linear regulator responds quickly, drawing current from the output terminal to make the output voltage drop rapidly. When the output voltage reaches the preset output voltage of the auxiliary discharge low-dropout linear regulator, the loop of the auxiliary discharge low-dropout linear regulator is automatically shut down, so that the auxiliary charging low-dropout linear regulator and the auxiliary discharge low-dropout linear regulator only work briefly when the reference voltage is rapidly rising and falling. After the switching is completed, the auxiliary charging low-dropout linear regulator and the auxiliary discharge low-dropout linear regulator are in the off state, which does not affect the overall efficiency of the BUCK converter.

2. The BUCK converter according to claim 1, characterized in that, The BUCK control module includes: A first level converter and a second level converter, wherein the input of the first level converter is connected to a first digital mismatch adjustment signal, and the output of the first mismatch adjustment signal is output; the input of the second level converter is connected to a second digital mismatch adjustment signal, and the output of the second mismatch adjustment signal is output. A low-pass filter whose input is connected to a reference voltage and outputs a first reference voltage after filtering out high-frequency noise; The loop compensator has a reference voltage input terminal connected to a first reference voltage, a feedback input terminal connected to the output voltage, and an output signal from the loop compensator. A PWM generator whose input is connected to the output signal of a loop compensator, and outputs a pulse width modulation signal. The bias current generator has its input terminal connected to the first reference voltage and its output terminal outputting a first bias current, a second bias current, a third bias current, a fourth bias current, and a fifth bias current.

3. The BUCK converter according to claim 1, characterized in that, The auxiliary charging low-dropout linear regulator also includes a first amplifier, whose power supply terminal is connected to an analog power supply voltage, its ground terminal is connected to an analog ground, its non-inverting input terminal is connected to a first reference voltage, its inverting input terminal is connected to a first feedback voltage, and its output terminal outputs the first amplifier output voltage.

4. The BUCK converter according to claim 3, characterized in that, The auxiliary charging low-dropout linear regulator also includes: The first output current limiting module has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminal connected to the fourth bias current, and its output terminal connected to the output voltage of the first amplifier. A first N-type transistor, a first P-type transistor, and a second P-type transistor, wherein the source of the first N-type transistor is connected to the analog ground, the gate is connected to the output voltage of the first amplifier, and the drain is connected to the drain of the first P-type transistor to form a first current mirror junction voltage; the drain and gate of the first P-type transistor are shorted, and the source is connected to the analog power supply voltage; the source of the second P-type transistor is connected to the analog power supply voltage, the gate is shorted to the gate of the first P-type transistor, and the drain is connected to the output voltage; The first voltage divider feedback module has its input terminal connected to the output voltage, its bias current terminal connected to the first bias current, its adjustment control terminal connected to the first mismatch adjustment signal, and its ground terminal connected to the analog ground.

5. The BUCK converter according to claim 4, characterized in that, The first voltage divider feedback module further includes: The first group of resistors includes the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor; First capacitor; The first group of N-type switching transistors includes the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor, and the sixth N-type transistor; First decoder; The second, third, fourth, fifth, sixth, and seventh resistors are connected in series. One end of the second resistor is connected to the output voltage, and the voltage signal between the other end and the third resistor in series serves as the first feedback voltage. The first capacitor and the first resistor are connected in series between the output voltage and the first feedback voltage. The voltage signal between the third, fourth, fifth, sixth, and seventh resistors in series is connected to the sources of the third, fourth, fifth, and sixth N-type transistors, respectively. The drains of the third, fourth, fifth, and sixth N-type transistors are shorted together and connected to the first bias current. The input of the first decoder is connected to the first mismatch adjustment signal, and the output outputs a first set of switch control signals, including a first switch control signal, a second switch control signal, a third switch control signal, and a fourth switch control signal, which are connected in series to the gates of the third, fourth, fifth, and sixth N-type transistors.

6. The BUCK converter according to claim 1, characterized in that, The auxiliary discharge low-dropout linear regulator also includes: The second amplifier has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its inverting input terminal connected to the first reference voltage, its non-inverting input terminal connected to the second feedback voltage, and its output terminal outputting the second amplifier output voltage. The second output current limiting module has its power supply terminal connected to the analog power supply voltage, its ground terminal connected to the analog ground, its input terminal connected to the fifth bias current, and its output terminal connected to the output voltage of the second amplifier. The system comprises a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a third P-type transistor, and a fourth P-type transistor, as well as an eighth resistor. The source of the seventh N-type transistor is connected to the analog ground, its gate is connected to the output voltage of the second amplifier, and its drain is connected to the drain of the third P-type transistor to form a second current mirror connection point voltage. The drain and gate of the third P-type transistor are shorted, and its source is connected to the analog power supply voltage. The source of the fourth P-type transistor is connected to the analog power supply voltage, its gate is shorted to the gate of the third P-type transistor, and its drain is connected to the gate and drain of the eighth N-type transistor to form a third current mirror connection point voltage. The source of the eighth N-type transistor is connected to the analog ground, and its gate and drain are shorted to form the third current mirror connection point voltage and connected to the gate of the ninth N-type transistor. The drain of the ninth N-type transistor is connected to the output voltage and one end of the eighth resistor. The other end of the eighth resistor is connected to the third bias current. The second voltage divider feedback module has its input terminal connected to the output voltage, its bias current terminal connected to the second bias current, its adjustment control terminal connected to the second mismatch adjustment signal, and its ground terminal connected to the analog ground.

7. The BUCK converter according to claim 6, characterized in that, The second voltage divider feedback module also includes: The second group of resistors includes the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth resistors; The second capacitor and the third capacitor; The second group of N-type switching transistors includes the tenth N-type transistor, the eleventh N-type transistor, the twelfth N-type transistor, and the thirteenth N-type transistor; Second decoder; The tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth resistors are connected in series. One end of the tenth resistor is connected to the analog ground, and the voltage signal between the other end and the eleventh resistor in series serves as the second feedback voltage. The second capacitor and the ninth resistor are connected in series between the output voltage and the second feedback voltage. The voltage signal between the tenth, eleventh, twelfth, thirteenth, and fourteenth resistors in series is connected to the source of the tenth, eleventh, twelfth, and thirteenth N-type transistors, respectively. The drains of the tenth, eleventh, twelfth, and thirteenth N-type transistors are shorted together and connected to the second bias current. The input of the second decoder is connected to the second mismatch adjustment signal, and the output outputs a second set of switch control signals, including a fifth, sixth, seventh, and eighth switch control signal, which are connected in series to the gate of the tenth, eleventh, twelfth, and thirteenth N-type transistors.

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