Switching circuit to improve the dynamic range of CMOS image sensors in extreme environments

Abstract

The present invention discloses a switching circuit for improving the dynamic range of a CMOS image sensor under extreme environments. The switching circuit comprises a sampling tube, a bootstrap capacitor, a control module, an inverter, a parasitic capacitance release module, a fully differential module, and a sampling path switch module. The sampling tube is an NMOS tube, a source terminal of which is an input terminal of the switching circuit, a drain terminal of which is an output terminal of the switching circuit, a gate terminal of which is connected to the control module and is controlled by the charging voltage of the bootstrap capacitor, an inverter inverts a clock signal and introduces it into the control module, so that the working timing of the control module is controlled by a pair of complementary clock signals, the parasitic capacitance release module is turned on after the switching circuit completes sampling to release the gate charge of the sampling tube, the fully differential module introduces another input terminal into the switching circuit, so that the switching circuit forms a fully differential input structure, and the sampling path switch module forms a low-resistance conduction path for the path from the input signal to the output terminal of the switching circuit. Advantages of the switching circuit include high linearity and fast switching speed.

Description

Technical Field

[0001] The present invention relates to a switching circuit, and in particular to a switching circuit for improving the dynamic range of a CMOS image sensor under extreme conditions. Background Art

[0002] As a core component of modern photoelectric conversion, CMOS image sensors have become a key growth driver for the global semiconductor industry. This growth is primarily driven by strong demand from multi-camera systems in smartphones, automotive electronic vision, industrial automated inspection, and security surveillance networks. CMOS image sensors are rapidly evolving along a multi-dimensional performance optimization path. On the one hand, pixel technology continues to advance, with back-illuminated and stacked structures gradually replacing traditional front-illuminated designs, improving quantum efficiency and full-well electron capacity. On the other hand, performance in specialized applications continues to improve. Harsh industrial environments, such as high temperatures and dust, require ultra-high frame rates exceeding 240 fps. Automobiles operating in tunnels must cope with extreme dynamic ranges exceeding 150 dB. Security surveillance systems require clear images in low-light conditions as low as 0.01 lux. These technological advancements converge towards a common goal: obtaining higher-quality image information under these extreme conditions.

[0003] With the rapid development of applications in various extreme environments, CMOS image sensors are required to have higher pixel resolution, higher frame rate, and wider dynamic range. Correspondingly, the readout circuits used to read out the sensor data also need to be faster and more accurate.

[0004] The readout circuitry of existing CMOS image sensors typically consists of three components: a preamplifier circuit, a sampling circuit, and an ADC circuit. The preamplifier circuit amplifies the weak voltage signal (i.e., the sensed data) output by the CMOS image sensor, generating an amplified voltage signal to meet subsequent processing requirements. The sampling circuit performs discrete time sampling on the amplified voltage signal to generate a sampled voltage (analog voltage). The ADC circuit converts the sampled voltage into a digital code for subsequent image processing. To obtain high-precision light intensity signals and support a wide dynamic range (HDR), the sampling circuit is the core link for reliable conversion of analog signals to digital signals. This sampling circuit typically achieves sampling by sequentially switching on and off switches within a switching structure. The linearity of the switches within this structure is a key factor in determining the performance of the sampling circuit.

[0005] Traditional sampling switches use a CMOS switch structure. Due to the source-follower effect of CMOS transistors and the limited voltage difference between the gate and the source, there is obvious nonlinear distortion, which is particularly serious under high signal input or high temperature environments. It is increasingly difficult to meet the readout circuit requirements of CMOS image sensors.

[0006] In order to reduce the adverse effects caused by the nonlinear distortion of the sampling switch, researchers have proposed the following in recent years: Figure 1 The gate voltage bootstrap switch shown in the figure. MS is the sampling transistor, and when it is turned on, the gate voltage bootstrap switch enables signal transmission. C1 is a bootstrap capacitor, which stores the gate drive voltage of the sampling transistor, enabling the sampling transistor's gate voltage to follow the input signal. M1 to M7 are auxiliary switching transistors, forming a control module that controls the charge and discharge paths of bootstrap capacitor C1. This gate voltage bootstrap switch is widely used in the readout circuits of CMOS image sensors, particularly for accurately sampling analog signals in high dynamic range (HDR) imaging. The basic principle behind its improved linearity is that when the sampling transistor MS is turned on, the bootstrap capacitor C1 boosts the gate voltage of the sampling transistor MS to a value higher than its source voltage, thereby enhancing the conduction capability of the sampling transistor MS, reducing the on-resistance, and improving linearity.

[0007] While the aforementioned gate-voltage bootstrap switch offers improved linearity compared to traditional sampling switches, it still suffers from the following issues: 1. Low linearity: During the on-state phase of the sampling tube MS, although the bootstrap capacitor C1 boosts the gate voltage of the sampling tube MS, the gate voltage boost is insufficient due to the parasitic capacitance of the sampling tube MS. This causes the source voltage of the sampling tube MS to vary with the input signal, ultimately manifesting as nonlinear on-resistance, negatively impacting signal fidelity. Distortion is particularly pronounced under high dynamic range inputs. 2. Slow switching speed: During high-speed switching, the parasitic capacitance on the sampling tube MS must be frequently charged and discharged, consuming additional energy and increasing transient time. Furthermore, the parasitic capacitance of the bootstrap capacitor plates also shunts the charging current, slowing the charging process. Furthermore, these parasitic capacitances can lead to charge injection and clock feedthrough in the circuit, reducing the transient response speed of the gate-voltage bootstrap switch. Summary of the Invention

[0008] The technical problem to be solved by this invention is to provide a switching circuit with high linearity and fast switching speed to enhance the dynamic range of CMOS image sensors under extreme conditions. When used as a sampling switch in the readout circuit of a CMOS image sensor, this switching circuit can significantly enhance the dynamic range of the CMOS image sensor operating under extreme conditions.

[0009] The technical solution adopted by the present invention to solve the above technical problems is: a switching circuit for improving the dynamic range of a CMOS image sensor under extreme environments, which realizes switching between an on state and an off state under the control of a clock signal CLK1, and includes a sampling tube, a bootstrap capacitor for storing the gate drive voltage of the sampling tube, and a control module for controlling the charging and discharging path of the bootstrap capacitor. The sampling tube is an NMOS tube, whose source is the input end of the switching circuit, the drain is the output end of the switching circuit, the gate is connected to the control module, and is controlled by the charging voltage of the bootstrap capacitor. The switching circuit also includes an inverter, a parasitic capacitance release module, a fully differential module and a sampling path switch module; the input end of the inverter is connected to the clock signal CLK1, which is used to invert the clock signal CLK1 and then introduce it into the control module, so that the working timing of the control module is controlled by a pair of complementary clock signals; the parasitic capacitance release module is used to be turned on after the sampling of the switching circuit is completed to release the gate charge of the sampling tube; the fully differential module is used to introduce another input end other than the source of the sampling tube to the switching circuit, so that the switching circuit forms a fully differential input structure; the sampling path switch module is used to form a low-resistance conduction path for the path from the input signal to the output end of the switching circuit.

[0010] Compared with the prior art, the advantages of the present invention are that by adding an inverter, a parasitic capacitance release module, a fully differential module and a sampling path switch module, the inverter inverts the clock signal CLK1 and then introduces it into the control module, so that the working timing of the control module is controlled by a pair of complementary clock signals, thereby achieving precise control of the bootstrap capacitor charging and discharging path, avoiding switching shock and timing drift, and the parasitic capacitance release module is turned on after the switching circuit sampling is completed, which can release the gate charge of the sampling tube, thereby reducing the residual parasitic capacitance of the gate of the sampling tube and improving linearity. The fully differential module introduces another input to the switching circuit in addition to the source of the sampling tube. The sampling path switch module forms a low-resistance conduction path for the input signal to the output end of the switching circuit, thereby reducing the on-resistance and parasitic capacitance of the input signal in the process of passing to the output end of the switching circuit, effectively enhancing the driving capability and improving the switching speed. Therefore, the present invention has high linearity and fast switching speed. When used as a sampling switch in the readout circuit of a CMOS image sensor, it can significantly improve the dynamic range of the CMOS image sensor operating in extreme environments.

[0011] Furthermore, the control module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor; the first MOS transistor, the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are all NMOS transistors, and the third MOS transistor, the fourth MOS transistor, the seventh MOS transistor, and the ninth MOS transistor are all PMOS transistors; the gates of the first MOS transistor, the third MOS transistor, and the ninth MOS transistor, and the drains of the fourth MOS transistor and the fifth MOS transistor are all connected to the gate of the sampling tube, the source of the first MOS tube is connected to the source of the sampling tube, and the first MOS transistor, the second MOS transistor, and the ninth MOS transistor are all connected to the gate of the sampling tube. The drain of the OS transistor and the source of the eighth MOS transistor are both connected to one end of the bootstrap capacitor, the gate of the second MOS transistor is connected to the output end of the inverter, the source of the second MOS transistor is grounded, the sources of the third MOS transistor and the fourth MOS transistor are both connected to the other end of the bootstrap capacitor, the drain of the third MOS transistor, the source of the seventh MOS transistor, and the gate of the fifth MOS transistor are all connected to the power supply voltage VDD, the gate of the fourth MOS transistor, the source of the ninth MOS transistor, the drains of the seventh MOS transistor, and the eighth MOS transistor are connected, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, the gates of the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are connected, the gates of the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are connected to the clock signal CLK1, and the source of the sixth MOS transistor is connected to the ground.

[0012] Furthermore, the parasitic capacitance release module includes a tenth MOS transistor, which is a PMOS transistor; the gate of the tenth MOS transistor is connected to the clock signal CLK1, the source is connected to the power supply voltage VDD, and the drain is connected to the connection end of the drain of the sixth MOS transistor and the source of the fifth MOS transistor.

[0013] Furthermore, the sampling path switch module includes an eleventh MOS transistor and a twelfth MOS transistor, the eleventh MOS transistor being an NMOS transistor and the twelfth MOS transistor being a PMOS transistor; the gates of the eleventh MOS transistor and the twelfth MOS transistor are both connected to a clock signal CLK1; the source of the eleventh MOS transistor and the drain of the twelfth MOS transistor are connected to the drains of the first MOS transistor, the second MOS transistor, and the ninth MOS transistor, the source of the eighth MOS transistor, and a connecting end of one end of the bootstrap capacitor; the drain of the eleventh MOS transistor is connected to the gate of the sampling transistor, and the source of the twelfth MOS transistor is connected to the source of the sampling transistor.

[0014] Furthermore, the fully differential module includes a thirteenth MOS transistor, which is an NMOS transistor; the gate of the thirteenth MOS transistor is grounded, the source serves as another input end of the switch circuit, and the drain is connected to the drain of the sampling tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A circuit diagram of an existing gate voltage bootstrap switch;

[0016] Figure 2 A circuit diagram of a switch circuit for improving the dynamic range of a CMOS image sensor under extreme conditions of the present invention;

[0017] Figure 3 The figure is the FFT simulation result of the existing gate voltage bootstrap switch;

[0018] Figure 4 This is a diagram showing the FFT simulation results of the switching circuit for improving the dynamic range of a CMOS image sensor under extreme conditions of the present invention;

[0019] Figure 5 The figure is a simulation result diagram of the establishment time of the existing gate voltage bootstrap switch;

[0020] Figure 6 This is a diagram showing the simulation results of the settling time of the switching circuit for improving the dynamic range of the CMOS image sensor under extreme conditions of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0022] Example 1: A switching circuit for improving the dynamic range of a CMOS image sensor under extreme environments, which switches between an on state and an off state under the control of a clock signal CLK1, includes a sampling tube MS, a bootstrap capacitor C1 for storing a gate drive voltage of the sampling tube MS, and a control module for controlling the charge and discharge path of the bootstrap capacitor C1. The sampling tube MS is an NMOS tube, whose source is the input end of the switching circuit, the drain is the output end of the switching circuit, and the gate is connected to the control module and is controlled by the charging voltage of the bootstrap capacitor C1. The switching circuit also includes an inverter N1, a parasitic capacitance release module, and a fully differential module and a sampling path switch module; the input end of the inverter N1 is connected to the clock signal CLK1, which is used to invert the clock signal CLK1 and then introduce it into the control module, so that the working timing of the control module is controlled by a pair of complementary clock signals; the parasitic capacitance release module is used to be turned on after the switching circuit sampling is completed to release the gate charge of the sampling tube MS; the full differential module is used to introduce another input end other than the source of the sampling tube MS to the switching circuit, so that the switching circuit forms a full differential input structure; the sampling path switch module is used to form a low-resistance conduction path for the path from the input signal to the output end of the switching circuit.

[0023] In this embodiment, the inverter N1 inverts the clock signal CLK1 and introduces it into the control module, so that the operating timing of the control module is controlled by a pair of complementary clock signals, thereby achieving precise control of the charging and discharging paths of the bootstrap capacitor C1, avoiding switching shock and timing drift. The parasitic capacitance release module is turned on after the switching circuit completes sampling, and can release the gate charge of the sampling tube MS, thereby reducing the residual parasitic capacitance of the gate of the sampling tube MS and improving linearity. The fully differential module introduces another input terminal in addition to the source terminal of the sampling tube MS to the switching circuit, so that the switching circuit forms a fully differential input structure. The fully differential input structure can subtract input noise, effectively suppress common-mode input noise, and improve the linearity of the switching circuit. The sampling path switch module forms a low-resistance conduction path for the input signal to the output terminal of the switching circuit, reducing the on-resistance and parasitic capacitance of the input signal in the process of passing to the output terminal of the switching circuit, effectively enhancing the driving capability and improving the switching speed.

[0024] Example 2: This example is basically the same as Example 1, except that: Figure 2As shown, in this embodiment, the control module includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8 and a ninth MOS transistor M9; the first MOS transistor M1, the second MOS transistor M2, the fifth MOS transistor M5, the sixth MOS transistor M6 and the eighth MOS transistor M8 are all NMOS transistors, and the third MOS transistor M3, the fourth MOS transistor M4, the seventh MOS transistor M7 and the ninth MOS transistor M9 are all PMOS transistors; the gates of the first MOS transistor M1, the third MOS transistor M3 and the ninth MOS transistor M9, and the drains of the fourth MOS transistor M4 and the fifth MOS transistor M5 are all connected to the gate of the sampling transistor MS, the source of the first MOS transistor M1 is connected to the source of the sampling transistor MS, and the first MOS transistor M1, the second MOS transistor M2, the fifth MOS transistor M5, the sixth MOS transistor M6 and the eighth MOS transistor M8 are all NMOS transistors. The drains of the S transistor M2 and the ninth MOS transistor M9, and the source of the eighth MOS transistor M8 are all connected to one end of the bootstrap capacitor C1. The gate of the second MOS transistor M2 is connected to the output end of the inverter N1. The source of the second MOS transistor M2 is grounded. The sources of the third MOS transistor M3 and the fourth MOS transistor M4 are all connected to the other end of the bootstrap capacitor C1. The drain of the third MOS transistor M3, the source of the seventh MOS transistor M7, and the gate of the fifth MOS transistor M5 are all connected to the power supply voltage VDD. The gate of the fourth MOS transistor M4, the source of the ninth MOS transistor M9, and the drains of the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected. The source of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6. The gates of the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 are connected to the clock signal CLK1. The source of the sixth MOS transistor M6 is connected to the ground.

[0025] In this embodiment, the third MOS transistor M3, the fourth MOS transistor M4, the seventh MOS transistor M7, and the eighth MOS transistor M8 form a bootstrap charging path. When the clock signal CLK1 is at a high level, the seventh MOS transistor M7 and the eighth MOS transistor M8 are turned on, and the two ends of the bootstrap capacitor C1 are connected to ground and the power supply voltage VDD, respectively, through the second MOS transistor M2 and the third MOS transistor M3, thereby charging the bootstrap capacitor C1. The fourth MOS transistor M4 and the ninth MOS transistor M9 are turned on during the on-phase of the switching circuit, increasing the voltage at the end of the bootstrap capacitor C1 connected to the source of the third MOS transistor M3 and transmitting it to the gate of the sampling transistor MS through the ninth MOS transistor M9. The fifth MOS transistor M5 and the sixth MOS transistor M6 serve as protection transistors connected between the gate of the sampling transistor MS and ground, limiting the maximum voltage difference between the gate and source of the sampling transistor MS, preventing overvoltage in the sampling transistor MS and ensuring safe operation of the switching circuit during the bootstrap process. When the first MOS transistor M1 is turned on, it can clamp the gate voltage of the sampling transistor MS at a high potential, thereby enhancing the conduction capability of the sampling transistor MS. The second MOS transistor M2 is an auxiliary clock control switch, which is controlled by the inverted clock signal CLK2 of the clock signal CLK1, and controls the on and off of the first MOS transistor M1 to realize the switching between the on state and the off state of the switch circuit.

[0026] Example 3: This example is basically the same as Example 2, except that: Figure 2 As shown, in this embodiment, the parasitic capacitance release module includes a tenth MOS transistor M10, which is a PMOS transistor; the gate of the tenth MOS transistor M10 is connected to the clock signal CLK1, the source is connected to the power supply voltage VDD, and the drain is connected to the drain of the sixth MOS transistor M6 and the connection terminal of the source of the fifth MOS transistor M5.

[0027] In this embodiment, after the switch circuit completes sampling, the tenth MOS transistor M10 is turned on, connecting the gate of the sampling transistor MS to the power supply voltage VDD, thereby effectively releasing the gate charge of the sampling transistor MS and reducing the residual parasitic capacitance of the gate of the sampling transistor MS. This significantly improves the voltage linearity in the on-state of the switch circuit, reduces the drift of the on-resistance with changes in the input signal, improves linearity, and can fundamentally optimize the linearity performance of CMOS image sensor sampling.

[0028] Example 4: This example is basically the same as Example 3, except that: Figure 2As shown, in this embodiment, the sampling path switch module includes an eleventh MOS transistor M11 and a twelfth MOS transistor M12. The eleventh MOS transistor M11 is an NMOS transistor, and the twelfth MOS transistor M12 is a PMOS transistor. The gates of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are both connected to the clock signal CLK1. The source of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12 are connected to the drains of the first MOS transistor M1, the second MOS transistor M2, and the ninth MOS transistor M9, the source of the eighth MOS transistor M8, and the connecting end of one end of the bootstrap capacitor C1. The drain of the eleventh MOS transistor M11 is connected to the gate of the sampling transistor MS, and the source of the twelfth MOS transistor M12 is connected to the source of the sampling transistor MS.

[0029] In this embodiment, the sampling path switch module is formed by the eleventh MOS transistor M11 and the twelfth MOS transistor M12. The eleventh MOS transistor M11 is turned on during the off phase of the switch circuit, rapidly pulling the gate of the sampling transistor MS to its source potential, quickly shutting down the sampling transistor MS and placing the switch circuit in a deep off state. This reduces turn-off delay and transient current, improving turn-off speed. This is particularly suitable for high-speed image sampling scenarios and significantly improves the speed performance and dynamic response capability of the switch circuit. The twelfth MOS transistor M12 is connected in parallel with the first MOS transistor M1 to form a low-resistance conduction path, effectively reducing the on-resistance and parasitic capacitance effects of the input signal on its way to the output of the switch circuit. This further enhances drive capability, reduces parasitic resistance, and increases the charge and discharge speed of the switch circuit, thereby improving signal transmission fidelity and response bandwidth.

[0030] Example 5: This example is basically the same as Example 4, except that: Figure 2 As shown, in this embodiment, the fully differential module includes a thirteenth MOS transistor M13, which is an NMOS transistor; the gate of the thirteenth MOS transistor M13 is grounded, the source serves as another input end of the switch circuit, and the drain is connected to the drain of the sampling transistor MS.

[0031] In this embodiment, a new input terminal is introduced by adding the thirteenth MOS transistor M13. The thirteenth MOS transistor M13 and the sampling transistor MS form a fully differential input structure, so that the switch circuit becomes a fully differential input structure. The fully differential input structure performs subtraction processing on the input noise, thereby effectively suppressing the common-mode input noise, thereby reducing the charge injection effect and improving the switching linearity.

[0032] like Figure 2As shown, the specific operating process of the switching circuit for improving the dynamic range of a CMOS image sensor under extreme environments of the present invention is as follows: the source of the sampling transistor MS is connected to the input signal Vin, and the source of the thirteenth MOS transistor M13 is connected to the input signal Vip, where the input signal Vip is the complementary signal of the input signal Vin. When the clock signal CLK1 is at a low level, the second MOS transistor M2 and the third MOS transistor M3 are turned on, the first MOS transistor M1 is turned off, and the two ends of the bootstrap capacitor C1 are connected to ground and the power supply voltage VDD through the second MOS transistor M2 and the third MOS transistor M3, respectively. At this time, the power supply voltage VDD charges the bootstrap capacitor C1, the fifth MOS transistor M5 and the sixth MOS transistor M6 are turned on, and the gate of the sampling transistor MS is connected to the ground GND through the fifth MOS transistor M5 and the sixth MOS transistor M6. The gate of the ninth MOS transistor M9 is at a low level, and the gate of the fourth MOS transistor M4 is at a high level. Therefore, the fourth MOS transistor M4 and the ninth MOS transistor M9 are turned off, isolating the two ends of the bootstrap capacitor C1 from the sampling transistor MS, and the switching circuit is in a closed state. When the clock signal CLK1 is at a high level, the sampling tube MS is in the on state. At this time, the eighth MOS tube M8 pulls the gate of the fourth MOS tube M4 to a low level, so that the voltage on the bootstrap capacitor C1 is charged to the gate of the sampling tube MS. The first MOS tube M1 and the sampling tube MS are turned on at the same time. At this time, the switch circuit is in the on state, the input signal Vin is transmitted to the output terminal Vout of the switch circuit through the sampling tube MS, and the input signal Vip is transmitted to the output terminal Vout of the switch circuit through the thirteenth MOS tube M13. The second MOS tube M2 and the third MOS tube M3 are turned off. At this time, the sampling The source voltage of the sampling transistor MS is the input signal Vin, while the gate voltage is the source voltage plus the power supply voltage VDD pre-stored by the bootstrap capacitor C1. Therefore, the voltage difference between the gate and source of the sampling transistor MS is the power supply voltage VDD stored in the bootstrap capacitor C1, which is a constant value. Since the gate voltage of the sampling transistor MS is higher than the power supply voltage VDD during the sampling period, the fifth and sixth MOS transistors M5 and M6 are required to ensure that the voltage difference between the drain and source of the sampling transistor MS does not exceed the power supply voltage VDD during the charge discharge process, maintaining a safe operating state for the switching circuit. The seventh and eighth MOS transistors M7 and M8 complement each other in controlling the switching path, forming a clock-controlled switch. The tenth MOS transistor M10 turns on after the switching circuit completes sampling, connecting the gate of the sampling transistor MS to the power supply voltage VDD, effectively releasing the gate charge of the sampling transistor MS and reducing the residual parasitic capacitance of the sampling transistor MS gate. The eleventh MOS transistor M11 turns on during the switching circuit's shutdown phase, pulling the gate of the sampling transistor MS to its source potential, quickly shutting down the sampling transistor MS and improving shutdown speed. The twelfth MOS transistor M12 is connected in parallel with the first MOS transistor M1 , which reduces the on-resistance and parasitic capacitance in the process of the input signal passing through the output end of the switch circuit, further enhances the driving capability, and reduces the parasitic resistance.

[0033] In order to verify the performance of the switch circuit for improving the dynamic range of the CMOS image sensor under extreme conditions of the present invention, Figure 2 The switch circuit and the circuit for improving the dynamic range of CMOS image sensor under extreme environment of the present invention are shown. Figure 1 The gate voltage bootstrap switch shown in the figure is subjected to FFT simulation and settling time simulation respectively. Among them, the FFT simulation results of the existing gate voltage bootstrap switch are shown in the figure Figure 3 As shown in FIG. 1 , the FFT simulation results of the switching circuit for improving the dynamic range of the CMOS image sensor under extreme conditions of the present invention are shown in FIG. Figure 4 As shown in the figure, the simulation of the establishment time of the existing gate voltage bootstrap switch is as follows Figure 5 As shown in FIG. 1 , the simulation of the settling time of the switch circuit for improving the dynamic range of the CMOS image sensor under extreme conditions of the present invention is as follows: Figure 6 shown.

[0034] analyze Figure 3 It can be seen that the effective number of bits (ENOB) of the existing gate voltage bootstrap switch is 10.12 bits. Figure 4 The effective number of bits (ENOB) of the switch circuit for improving the dynamic range of CMOS image sensors under extreme conditions is 12.07 bits. This indicates that the switch circuit for improving the dynamic range of CMOS image sensors under extreme conditions has a 19.2% improvement in linearity compared to conventional gate voltage bootstrap switches.

[0035] analyze Figure 5 It can be seen that the time required for the existing gate voltage bootstrap switch to stabilize the output voltage at 1.5956V is 26.8566ns. Figure 6 It can be seen that the switching circuit of the present invention, which improves the dynamic range of CMOS image sensors under extreme environments, takes 24.7952ns to stabilize the output voltage at 1.5956V. Compared with the existing gate voltage bootstrap switch, the settling time is shortened by 2.0614ns, and the switching speed is increased by approximately 7.68%.

[0036] In summary, the switching circuit of the present invention for improving the dynamic range of CMOS image sensors under extreme environments has advantages such as high linearity and high speed compared to existing gate voltage bootstrap switches. It can be widely used in CMOS image sensor readout circuits, analog front-end circuits, column-level sample-and-hold modules, etc., and has broad application prospects.

Claims

1. A switching circuit for improving the dynamic range of a CMOS image sensor under extreme conditions. The circuit switches between on and off states under the control of a clock signal CLK1. The circuit comprises a sampling tube, a bootstrap capacitor for storing the gate drive voltage of the sampling tube, and a control module for controlling the charge and discharge paths of the bootstrap capacitor. The sampling tube is an NMOS tube, with its source serving as the input of the switching circuit and its drain serving as the output of the switching circuit. The gate is connected to the control module and is controlled by the charging voltage of the bootstrap capacitor. The circuit is characterized in that The system also includes an inverter, a parasitic capacitance release module, a full differential module and a sampling path switch module; the input end of the inverter is connected to the clock signal CLK1, which is used to invert the clock signal CLK1 and then introduce it into the control module, so that the working timing of the control module is controlled by a pair of complementary clock signals; the parasitic capacitance release module is used to be turned on after the switching circuit sampling is completed to release the gate charge of the sampling tube; the full differential module is used to introduce another input end other than the source of the sampling tube to the switching circuit, so that the switching circuit forms a full differential input structure; the sampling path switch module is used to form a low-resistance conduction path for the path from the input signal to the output end of the switching circuit; the control module includes the first MOS tube to the ninth MOS tube. MOS tube; the first MOS tube, the second MOS tube, the fifth MOS tube, the sixth MOS tube and the eighth MOS tube are all NMOS tubes, and the third MOS tube, the fourth MOS tube, the seventh MOS tube and the ninth MOS tube are all PMOS tubes; the gates of the first MOS tube, the third MOS tube and the ninth MOS tube, and the drains of the fourth MOS tube and the fifth MOS tube are all connected to the gate of the sampling tube, the source of the first MOS tube is connected to the source of the sampling tube, the drains of the first MOS tube, the second MOS tube and the ninth MOS tube, and the source of the eighth MOS tube are all connected to one end of the bootstrap capacitor, the gate of the second MOS tube is connected to the output end of the inverter, the source of the second MOS tube is grounded, and the third MOS tube is grounded. The sources of the OS transistor and the fourth MOS transistor are connected to the other end of the bootstrap capacitor, the drain of the third MOS transistor, the source of the seventh MOS transistor and the gate of the fifth MOS transistor are all connected to the power supply voltage VDD, the gate of the fourth MOS transistor, the source of the ninth MOS transistor, the drains of the seventh MOS transistor and the eighth MOS transistor are connected, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, the gates of the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are connected, the source of the sixth MOS transistor is connected to the ground, the gates of the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are connected to the clock signal CLK1, and the source of the sixth MOS transistor is connected to the ground; the parasitic capacitance release module includes a tenth MOS transistor, which is a PMOS transistor, the gate of the tenth MOS transistor is connected to the clock signal CLK1, and the source is connected to the power supply voltage VDD. The voltage VDD is applied, and the drain is connected to the connecting end of the drain of the sixth MOS transistor and the source of the fifth MOS transistor. The sampling path switch module includes an eleventh MOS transistor and a twelfth MOS transistor, the eleventh MOS transistor is an NMOS transistor, and the twelfth MOS transistor is a PMOS transistor. The gates of the eleventh MOS transistor and the gates of the twelfth MOS transistor are both connected to the clock signal CLK1. The source of the eleventh MOS transistor and the drain of the twelfth MOS transistor are connected to the connecting end of the first MOS transistor, the second MOS transistor, and the ninth MOS transistor, the source of the eighth MOS transistor, and one end of the bootstrap capacitor. The drain of the eleventh MOS transistor is connected to the gate of the sampling transistor, and the source of the twelfth MOS transistor is connected to the source of the sampling transistor.

2. The switching circuit for improving the dynamic range of a CMOS image sensor under extreme conditions according to claim 1, characterized in that The fully differential module includes a thirteenth MOS tube, which is an NMOS tube. The gate of the thirteenth MOS tube is grounded, the source serves as another input end of the switch circuit, and the drain is connected to the drain of the sampling tube.

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