Level conversion circuit and switching power supply chip

Abstract

The embodiment of the invention provides a level conversion circuit and a switching power supply chip. The level conversion circuit comprises a control module, a protection module and a conversion module, the control module generates a control signal according to an input signal, and when positive grounding rebound noise is triggered and the grounding rebound noise voltage is greater than a preset voltage, the protection module suspends one of the positive output end and the negative output end of the conversion module, so that the conversion module outputs the positive output end and the negative output end of the conversion module. The conversion module generates a positive output voltage signal and a negative output voltage signal according to the control signal, the steady-state power supply voltage and the grounding rebound noise voltage, and outputs the positive output voltage signal and the negative output voltage signal to the suspended output end. The absolute value of the gate-source voltage of a part of transistors connected with the suspended output end can be limited to be smaller than or equal to the sum of the steady-state power supply voltage and a smaller voltage, and the damage risk caused by the overvoltage of the gate of the transistor can be reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a level conversion circuit and a switching power supply chip. Background Art

[0002] Printed circuit board (PCB) traces and packages have parasitic inductance. When a switching power supply chip (such as a buck or boost) switches on and off, the current change causes a corresponding change in magnetic flux, which in turn generates ground bounce noise at both ends of the parasitic inductance. The positive and negative terminals of the PCB decoupling capacitors are typically treated as ideal power and ground. This ground bounce noise affects the chip-side power and ground. For on-chip circuits, the equivalent superposition of ground bounce noise on the chip-side power and ground can degrade critical performance, resulting in unstable internal power supply voltages, reference voltage offsets, loss of feedback loop control, and potential damage to low-voltage circuits.

[0003] When ground bounce noise is triggered, the voltage difference between the chip-side power supply and the chip-side ground will momentarily oscillate within the range of the steady-state power supply voltage plus or minus the ground bounce noise voltage. For conventional level converters, the gate-source voltage of some MOS transistors will be biased to the steady-state power supply voltage plus the ground bounce noise voltage, causing the MOS transistors to be damaged by gate overvoltage. Summary of the Invention

[0004] The present disclosure provides a level conversion circuit and a switching power supply chip, which can reduce the risk of damage caused by transistor gate overvoltage when ground bounce noise is triggered.

[0005] In a first aspect, the present disclosure provides a level conversion circuit, including a control module, a protection module, and a conversion module.

[0006] The protection module is configured to, when positive ground bounce noise is triggered and the ground bounce noise voltage is greater than a preset voltage, suspend one of the positive output terminal and the negative output terminal of the conversion module so that the absolute value of the gate-source voltage of some transistors connected to the suspended output terminal follows the ground bounce noise voltage.

[0007] The control module is configured to generate a control signal according to an input signal. The conversion module is configured to generate a positive output voltage signal and a negative output voltage signal according to the control signal, a steady-state power supply voltage, and the ground bounce noise voltage when ground bounce noise is triggered.

[0008] In some embodiments of the present disclosure, the conversion module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first load transistor and a second load transistor, and the protection module includes a suspension control unit.

[0009] The gate of the first transistor is connected to the first output terminal of the control module, the gate of the second transistor is connected to the second output terminal of the control module, the source of the first transistor, the source of the second transistor, the drain of the first load transistor, and the drain of the second load transistor are grounded, and the source of the third transistor, the source of the fourth transistor, the source of the fifth transistor, the source of the sixth transistor, the source of the first load transistor, and the source of the second load transistor are connected to the power input terminal.

[0010] The gate of the third transistor is connected to the drain of the fourth transistor, the drain of the second transistor, the gate of the fifth transistor, the gate of the seventh transistor and the first control end of the suspension control unit; the gate of the fourth transistor is connected to the drain of the third transistor, the drain of the first transistor, the gate of the sixth transistor, the gate of the eighth transistor and the second control end of the suspension control unit; the first input end of the suspension control unit is connected to the drain of the seventh transistor; the second input end of the suspension control unit is connected to the drain of the eighth transistor; the output of the suspension control unit is grounded; and the third control end of the suspension control unit is connected to the third output end of the control module.

[0011] The drain of the fifth transistor is connected to the source of the seventh transistor, the body of the seventh transistor, the gate of the first load transistor and the positive output terminal, and the drain of the sixth transistor is connected to the source of the eighth transistor, the body of the eighth transistor, the gate of the second load transistor and the negative output terminal.

[0012] The suspension control unit is configured to, when the positive ground bounce noise is triggered and the ground bounce noise voltage is greater than the preset voltage, disconnect the seventh transistor from the ground when the input signal is at a low level so that the positive output terminal is suspended, and disconnect the eighth transistor from the ground so that the negative output terminal is suspended when the input signal is at a high level.

[0013] In some embodiments of the present disclosure, the protection module also includes a voltage stabilizing unit, the drain of the first transistor is connected to the first end of the voltage stabilizing unit and the second control end of the suspension control unit, the drain of the second transistor is connected to the second end of the voltage stabilizing unit and the first control end of the suspension control unit, and the third end of the voltage stabilizing unit is connected to the power input end.

[0014] The gate of the third transistor is connected to the fourth end of the voltage stabilizing unit, the gate of the fifth transistor and the gate of the seventh transistor, the gate of the fourth transistor is connected to the fifth end of the voltage stabilizing unit, the gate of the sixth transistor and the gate of the eighth transistor, the drain of the third transistor is connected to the sixth end of the voltage stabilizing unit, and the drain of the fourth transistor is connected to the seventh end of the voltage stabilizing unit.

[0015] The voltage stabilizing unit is configured to, in the case of triggering the ground bounce noise, when the input signal is at a low level, stabilize the absolute values of the gate-source voltages of the fourth transistor, the sixth transistor, and the eighth transistor to the steady-state power supply voltage; and when the input signal is at a high level, stabilize the absolute values of the gate-source voltages of the third transistor, the fifth transistor, and the seventh transistor to the steady-state power supply voltage.

[0016] In some embodiments of the present disclosure, the voltage stabilizing unit includes a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor. The upper plate of the first capacitor and the upper plate of the second capacitor are connected to the power input terminal, the lower plate of the first capacitor is connected to the gate of the fifth transistor, the gate of the third transistor, the gate of the seventh transistor, the first end of the second resistor, and the first end of the fourth resistor, the second end of the second resistor is connected to the drain of the second transistor, the second end of the fourth resistor is connected to the drain of the fourth transistor, the lower plate of the second capacitor is connected to the gate of the sixth transistor, the gate of the fourth transistor, the gate of the eighth transistor, the first end of the first resistor, and the first end of the third resistor, the second end of the first resistor is connected to the drain of the first transistor, and the second end of the third resistor is connected to the drain of the third transistor.

[0017] In some embodiments of the present disclosure, the floating control unit includes a ninth transistor, a tenth transistor, a fifth resistor, a sixth resistor, a first pull-down tube and a second pull-down tube, the source of the ninth transistor, the source of the tenth transistor, the source of the first pull-down tube and the source of the second pull-down tube are grounded, the gate of the ninth transistor is connected to the first end of the fifth resistor and the drain of the first pull-down tube, the drain of the ninth transistor is connected to the drain of the seventh transistor, the gate of the tenth transistor is connected to the first end of the sixth resistor and the drain of the second pull-down tube, and the drain of the tenth transistor is connected to the drain of the eighth transistor.

[0018] The second end of the fifth resistor is connected to the drain of the second transistor, the second end of the sixth resistor is connected to the drain of the first transistor, and the gates of the first pull-down transistor and the second pull-down transistor are connected to the third output end of the control module.

[0019] In some embodiments of the present disclosure, the control module includes a first inverter, a second inverter, a third capacitor, a seventh resistor, an eighth resistor and a voltage regulator diode, the input end of the first inverter is connected to the input signal, the output end of the first inverter is connected to the gate of the first transistor and the input end of the second inverter, and the output end of the second inverter is connected to the gate of the second transistor.

[0020] The upper plate of the third capacitor is connected to the power input terminal, the lower plate of the third capacitor is connected to the first end of the seventh resistor and the first end of the eighth resistor, the second end of the eighth resistor is connected to the negative electrode of the voltage regulator diode and the third control terminal of the suspension control unit, and the second end of the seventh resistor and the positive electrode of the voltage regulator diode are grounded.

[0021] In some embodiments of the present disclosure, the protection module also includes a pull-down unit, the first input end of the pull-down unit is connected to the drain of the seventh transistor through the floating control unit, the second input end of the pull-down unit is connected to the drain of the eighth transistor through the floating control unit, the output end of the pull-down unit is grounded, and the control end of the pull-down unit is connected to the fourth output end of the control module.

[0022] The pull-down unit is configured to disconnect the suspension control unit from the ground within a preset time period from the flipping moment of the input signal to the flipping moment, so as to disconnect the seventh transistor and the eighth transistor from the ground.

[0023] In some embodiments of the present disclosure, the pull-down unit includes a third pull-down tube and a fourth pull-down tube, the source of the third pull-down tube and the source of the fourth pull-down tube are grounded, the drain of the third pull-down tube is connected to the drain of the seventh transistor through the suspension control unit, the drain of the fourth pull-down tube is connected to the drain of the eighth transistor through the suspension control unit, and the gate of the third pull-down tube and the gate of the fourth pull-down tube are connected to the fourth output end of the control module.

[0024] In some embodiments of the present disclosure, the control module includes a delay device, an XOR gate, a switch tube, a ninth resistor and a fourth capacitor, the input end of the delay device and the first input end of the XOR gate are connected to the input signal, the output end of the delay device is connected to the second input end of the XOR gate, the output end of the XOR gate is connected to the gate of the switch tube, the source of the switch tube and the lower plate of the fourth capacitor are grounded, the drain of the switch tube is connected to the first end of the ninth resistor, the upper plate of the fourth capacitor, the gate of the third pull-down tube and the gate of the fourth pull-down tube, and the second end of the ninth resistor is connected to the power input end.

[0025] In a second aspect, the present disclosure provides a switching power supply chip, comprising any level conversion circuit provided in the first aspect.

[0026] The technical solution disclosed herein provides a level conversion circuit, including a control module, a protection module, and a conversion module. The control module generates a control signal based on an input signal. When positive ground bounce noise is triggered and the ground bounce noise voltage is greater than a preset voltage, the protection module suspends one of the positive output terminal and the negative output terminal of the conversion module so that the absolute value of the gate-source voltage of the part of the transistors connected to the suspended output terminal follows the ground bounce noise voltage. The conversion module generates a positive output voltage signal and a negative output voltage signal based on the control signal, a steady-state power supply voltage, and the ground bounce noise voltage. This can limit the absolute value of the gate-source voltage of the part of the transistors connected to the suspended output terminal to be less than or equal to the sum of the steady-state power supply voltage and a smaller voltage, thereby reducing the risk of damage caused by transistor gate overvoltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0028] Figure 1 The following is a circuit diagram of a level converter provided in the prior art.

[0029] Figure 2 A schematic diagram of the structure of a level conversion circuit provided in an embodiment of the present disclosure.

[0030] Figure 3 A circuit diagram of a level conversion circuit provided by an embodiment of the present disclosure.

[0031] Figure 4 A circuit diagram of another level conversion circuit provided by an embodiment of the present disclosure.

[0032] Figure 5 This is a timing diagram of the operation of the level conversion circuit provided by an embodiment of the present disclosure when the input signal is reversed.

[0033] Figure 6 and Figure 7 This is a timing diagram of the operation of the level conversion circuit provided by an embodiment of the present disclosure when ground bounce noise is triggered. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0036] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0037] In addition, the terms "first", "second", etc. in the description and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0038] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0039] In the description of the present disclosure, unless otherwise specified, "multiple" and "at least two" mean more than two (including two). Similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0040] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0041] Figure 1 A circuit diagram of a level converter provided by the prior art is shown in FIG. Figure 1 As shown, the level converter 10 includes a first MOS transistor PM1, a second MOS transistor PM2, a third MOS transistor PM3, a fourth MOS transistor PM4, a fifth MOS transistor PM5, a sixth MOS transistor PM6, a seventh MOS transistor NM1, an eighth MOS transistor NM2, a ninth MOS transistor NM3, a tenth MOS transistor NM4 and an inverter INV.

[0042] The source of the first MOS transistor PM1, the source of the second MOS transistor PM2, the source of the third MOS transistor PM3, the source of the fourth MOS transistor PM4, the source of the fifth MOS transistor PM5, and the source of the sixth MOS transistor PM6 are connected to the power input terminal; the gate of the first MOS transistor PM1 is connected to the drain of the second MOS transistor PM2, the gate of the third MOS transistor PM3, the gate of the ninth MOS transistor NM3, and the drain of the eighth MOS transistor NM2; the gate of the second MOS transistor PM2 is connected to the drain of the first MOS transistor PM1 and the drain of the seventh MOS transistor NM1; the gate of the seventh MOS transistor NM1 is connected to the input terminal of the inverter INV and the input signal IN; and the gate of the eighth MOS transistor NM2 is connected to the output terminal of the inverter INV.

[0043] The drain of the third MOS transistor PM3 is connected to the drain of the ninth MOS transistor NM3, the negative output signal terminal, the gates of the fourth MOS transistor PM4, the gates of the tenth MOS transistor NM4, and the gate of the sixth MOS transistor PM6. The drain of the fourth MOS transistor PM4 is connected to the drain of the tenth MOS transistor NM4, the gate of the fifth MOS transistor PM5, and the positive output signal terminal. The source of the seventh MOS transistor NM1, the source of the eighth MOS transistor NM2, the source of the ninth MOS transistor NM3, and the source of the tenth MOS transistor NM4 are grounded to AGND. The drains of the fifth MOS transistor PM5 and the sixth MOS transistor PM6 are both grounded to AGND through the load.

[0044] In a steady state, when the input signal IN is at a high level, the seventh MOS transistor NM1, the ninth MOS transistor NM3, the second MOS transistor PM2, and the fourth MOS transistor PM4 are turned on, and the eighth MOS transistor NM2, the tenth MOS transistor NM4, the first MOS transistor PM1, and the third MOS transistor PM3 are turned off. The positive output voltage signal OUTP is the power supply voltage VCC, and the negative output voltage signal OUTN is the ground potential VAGND. Then, VSG_PM2=VSG_PM4=VGS_NM3=VCC-VAGND, where VSG_PM2 is the source-gate voltage of the second MOS transistor PM2, VSG_PM4 is the source-gate voltage of the fourth MOS transistor PM4, and VGS_NM3 is the gate-source voltage of the ninth MOS transistor NM3.

[0045] When the input signal IN is at a low level, the seventh MOS transistor NM1, the ninth MOS transistor NM3, the second MOS transistor PM2, and the fourth MOS transistor PM4 are turned off, and the eighth MOS transistor NM2, the tenth MOS transistor NM4, the first MOS transistor PM1, and the third MOS transistor PM3 are turned on. The positive output voltage signal OUTP is the ground potential VAGND, and the negative output voltage signal OUTN is the power supply voltage VCC. Then, VSG_PM1=VSG_PM3=VGS_NM4=VCC-VAGND, where VSG_PM1 is the source-gate voltage of the first MOS transistor PM1, VSG_PM3 is the source-gate voltage of the third MOS transistor PM3, and VGS_NM4 is the gate-source voltage of the tenth MOS transistor NM4.

[0046] When ground bounce noise is triggered, the instantaneous voltage of VCC-VAGND is VCC_DC ± VNOISE - VAGND_DC, where VCC_DC is the steady-state power supply voltage, VAGND_DC is the steady-state ground potential, and VNOISE is the amplitude of the ground bounce noise voltage. If each of the ninth MOS transistor NM3, the tenth MOS transistor NM4, the first MOS transistor PM1, the second MOS transistor PM2, the third MOS transistor PM3, and the fourth MOS transistor PM4 turns on when ground bounce noise is triggered, the gate-source voltage of each MOS transistor will be pulled up to VCC_DC ± VNOISE - VAGND_DC due to the limited withstand voltage between the gate and source of each MOS transistor. This may cause the MOS transistor to be damaged by the high voltage.

[0047] In order to solve the above technical problems, the present disclosure provides a level conversion circuit, including a control module, a protection module and a conversion module. The control module generates a control signal based on an input signal. When positive ground bounce noise is triggered and the ground bounce noise voltage is greater than a preset voltage, the protection module suspends one of the positive output terminal and the negative output terminal of the conversion module so that the absolute value of the gate-source voltage of the part of the transistors connected to the suspended output terminal follows the ground bounce noise voltage. The conversion module generates a positive output voltage signal and a negative output voltage signal based on the control signal, the steady-state power supply voltage and the ground bounce noise voltage. The absolute value of the gate-source voltage of the part of the transistors connected to the suspended output terminal can be limited to be less than or equal to the sum of the steady-state power supply voltage and a smaller voltage, thereby reducing the risk of damage caused by transistor gate overvoltage.

[0048] The technical solutions provided by the present disclosure are described in detail below with reference to several specific embodiments.

[0049] Figure 2 A schematic diagram of a level conversion circuit according to an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the level conversion circuit 100 includes a control module 110, a protection module 120, and a conversion module 130. The input terminal of the control module 110 receives an input signal IN, the output terminal of the control module 110 is connected to the control terminal of the conversion module 130, the conversion module 130 is grounded through the protection module 120, the input terminal of the conversion module 130 is connected to the power input terminal of the level conversion circuit 100, the positive output terminal of the conversion module 130 outputs a positive output voltage signal OUTP, and the negative output terminal of the conversion module 130 outputs a negative output voltage signal OUTN.

[0050] The control module 110 is configured to generate a control signal according to an input signal IN. The conversion module 130 is configured to generate a positive output voltage signal OUTP and a negative output voltage signal OUTN according to the control signal, a steady-state power supply voltage VCC_DC, and a ground bounce noise voltage when ground bounce noise is triggered.

[0051] The protection module 120 is configured to, when positive ground bounce noise is triggered and the ground bounce noise voltage is greater than a preset voltage Vpre, float one of the positive output terminal and the negative output terminal of the conversion module 130 so that the absolute value of the gate-source voltage of some transistors connected to the floating output terminal follows the ground bounce noise voltage.

[0052] For example, Figure 3 A circuit diagram of a level conversion circuit provided by an embodiment of the present disclosure, combined with Figure 2 and Figure 3 As shown, the conversion module 130 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first load transistor LM1 and a second load transistor LM2, and the protection module 120 includes a suspension control unit 121.

[0053] Among them, the gate of the first transistor M1 is connected to the first output end of the control module 110, the gate of the second transistor M2 is connected to the second output end of the control module 110, the source of the first transistor M1, the source of the second transistor M2, the drain of the first load transistor LM1 and the drain of the second load transistor LM2 are grounded AGND, and the source of the third transistor M3, the source of the fourth transistor M4, the source of the fifth transistor M5, the source of the sixth transistor M6, the source of the first load transistor LM1 and the source of the second load transistor LM2 are connected to the power input end.

[0054] The gate of the third transistor M3 is connected to the drain of the fourth transistor M4, the drain of the second transistor M2, the gate of the fifth transistor M5, the gate of the seventh transistor M7, and the first control terminal of the floating control unit 121. The gate of the fourth transistor M4 is connected to the drain of the third transistor M3, the drain of the first transistor M1, the gate of the sixth transistor M6, the gate of the eighth transistor M8, and the second control terminal of the floating control unit 121. A first input terminal of the floating control unit 121 is connected to the drain of the seventh transistor M7, a second input terminal of the floating control unit 121 is connected to the drain of the eighth transistor M8, an output terminal of the floating control unit 121 is grounded AGND, and a third control terminal of the floating control unit 121 is connected to the third output terminal of the control module 110.

[0055] The drain of the fifth transistor M5 is connected to the source of the seventh transistor M7, the body of the seventh transistor M7, the gate of the first load transistor LM1 and the positive output terminal, and the drain of the sixth transistor M6 is connected to the source of the eighth transistor M8, the body of the eighth transistor M8, the gate of the second load transistor LM2 and the negative voltage output terminal.

[0056] Continue to see Figure 3 The protection module 120 also includes a voltage stabilizing unit 122, the drain of the first transistor M1 is connected to the first end of the voltage stabilizing unit 122 and the second control end of the suspension control unit 121, the drain of the second transistor M2 is connected to the second end of the voltage stabilizing unit 122 and the first control end of the suspension control unit 121, and the third end of the voltage stabilizing unit 122 is connected to the power input end.

[0057] The gate of the third transistor M3 is connected to the fourth terminal of the voltage stabilizing unit 122, the gate of the fifth transistor M5, and the gate of the seventh transistor M7. The gate of the fourth transistor M4 is connected to the fifth terminal of the voltage stabilizing unit 122, the gate of the sixth transistor M6, and the gate of the eighth transistor M8. The drain of the third transistor M3 is connected to the sixth terminal of the voltage stabilizing unit 122, and the drain of the fourth transistor M4 is connected to the seventh terminal of the voltage stabilizing unit 122.

[0058] Specifically, such as Figure 3 As shown, the voltage stabilizing unit 122 includes a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, the upper plate of the first capacitor C1 and the upper plate of the second capacitor C2 are connected to the power input terminal, the lower plate of the first capacitor C1 is connected to the gate of the fifth transistor M5, the gate of the third transistor M3, the gate of the seventh transistor M7, the first end of the second resistor R2 and the first end of the fourth resistor R4, and the lower plate of the second capacitor C2 is connected to the gate of the sixth transistor M6, the gate of the fourth transistor M4, the gate of the eighth transistor M8, the first end of the first resistor R1 and the first end of the third resistor R3.

[0059] The second end of the first resistor R1 is connected to the drain of the first transistor M1, the second end of the second resistor R2 is connected to the drain of the second transistor M2, the second end of the third resistor R3 is connected to the drain of the third transistor M3, and the second end of the fourth resistor R4 is connected to the drain of the fourth transistor M4.

[0060] The floating control unit 121 includes a ninth transistor M9, a tenth transistor M10, a fifth resistor R5, a sixth resistor R6, a first pull-down transistor DM1, and a second pull-down transistor DM2. The source of the ninth transistor M9, the source of the tenth transistor M10, the source of the first pull-down transistor DM1, and the source of the second pull-down transistor DM2 are grounded AGND. The gate of the ninth transistor M9 is connected to the first end of the fifth resistor R5 and the drain of the first pull-down transistor DM1. The drain of the ninth transistor M9 is connected to the drain of the seventh transistor M7.

[0061] The gate of the tenth transistor M10 is connected to the first end of the sixth resistor R6 and the drain of the second pull-down transistor DM2. The drain of the tenth transistor M10 is connected to the drain of the eighth transistor M8. The second end of the fifth resistor R5 is connected to the drain of the second transistor M2. The second end of the sixth resistor R6 is connected to the drain of the first transistor M1. The gates of the first pull-down transistor DM1 and the second pull-down transistor DM2 are connected to the third output terminal of the control module 110.

[0062] Continue to see Figure 3 The control module 110 includes a first inverter INV1, a second inverter INV2, a third capacitor C3, a seventh resistor R7, an eighth resistor R8 and a Zener diode D. The input end of the first inverter INV1 receives the input signal IN, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and the gate of the first transistor M1, and the output end of the second inverter INV2 is connected to the gate of the second transistor M2.

[0063] The upper plate of the third capacitor C3 is connected to the power input terminal, the lower plate of the third capacitor C3 is connected to the first end of the seventh resistor R7 and the first end of the eighth resistor R8, the second end of the eighth resistor R8 is connected to the cathode of the voltage regulator diode D and the third control terminal of the suspension control unit 121, and the second end of the seventh resistor R7 and the anode of the voltage regulator diode D are grounded.

[0064] For example, in the present disclosure, ground AGND is taken as an ideal ground, and the ground potential VAGND=0. When all ground bounce noises are equivalently superimposed on the power input terminal, the instantaneous voltage of the power supply voltage VCC received by the power input terminal is VCC_DC±VNOISE, that is, VCC=VCC_DC±VNOISE.

[0065] In the steady state case where the input signal IN is at a high level, the first control signal output by the first inverter INV1 is at a low level, and the second control signal output by the second inverter INV2 is at a high level. The first control signal can pull down the gate voltage of the first transistor M1, and the second control signal can pull up the gate voltage of the second transistor M2, so as to turn off the first transistor M1 and turn on the second transistor M2, thereby turning off the fourth transistor M4 and turning on the third transistor M3.

[0066] At this time, the gate of the fifth transistor M5 and the gate of the seventh transistor M7 are biased to the ground AGND, and the gate of the sixth transistor M6 and the gate of the eighth transistor M8 are biased to the power input terminal, then the fifth transistor M5 and the eighth transistor M8 are turned on, the seventh transistor M7 and the sixth transistor M6 are turned off, the positive output voltage signal OUTP is biased to the power supply voltage VCC, and the negative output voltage signal OUTN is biased to 0.

[0067] The lower plate of the third capacitor C3 is biased to the ground AGND by the seventh resistor R7. Since the second transistor M2 and the third transistor M3 are turned on, the first transistor M1 and the fourth transistor M4 are turned off, the gate of the ninth transistor M9 is biased to the ground AGND, and the gate of the tenth transistor M10 is biased to the power input terminal, the ninth transistor M9 is turned off and the tenth transistor M10 is turned on.

[0068] When ground bounce noise is triggered, the second resistor R2 and the fourth resistor R4 limit the current capacity of the lower plate of the first capacitor C1. The charge on the first capacitor C1 does not rapidly charge or discharge during the ground bounce noise triggering period, and the voltage across the first capacitor C1 remains stable. At this time, the source-gate voltage VSG_M3 of the third transistor M3 and the source-gate voltage VSG_M5 of the fifth transistor M5 are at the steady-state power supply voltage VCC_DC. The gate voltage of the seventh transistor M7 remains at 0±VNOISE, the positive output voltage signal OUTP is VCC_DC±VNOISE, and the gate-source voltage VGS_M7 of the seventh transistor M7 is -VCC_DC.

[0069] Because the steady-state power supply voltage VCC_DC is lower than the maximum withstand voltage of the third transistor M3, the fifth transistor M5, and the seventh transistor M7, the absolute value of the gate-source voltage |VGS_M3| of the third transistor M3 is lower than the maximum withstand voltage of the third transistor M3, the absolute value of the gate-source voltage |VGS_M5| of the fifth transistor M5 is lower than the maximum withstand voltage of the fifth transistor M5, and the absolute value of the gate-source voltage |VGS_M7| of the seventh transistor M7 is lower than the maximum withstand voltage of the seventh transistor M7. In this way, when the input signal IN is at a high level and ground bounce noise is triggered, the voltage stabilization unit 122 can stabilize the absolute values of the gate-source voltages of the third transistor M3, the fifth transistor M5, and the seventh transistor M7 at the steady-state power supply voltage VCC_DC, thereby preventing damage to the third transistor M3, the fifth transistor M5, and the seventh transistor M7 due to gate overvoltage.

[0070] Furthermore, when the input signal IN is at a high level and ground bounce noise is triggered, even if the positive output voltage signal OUTP is biased below the ground potential VAGND by the ground bounce noise, the body diode of the seventh transistor M7 remains in an off state, and thus a through current in the branch where the fifth transistor M5 and the seventh transistor M7 are located is not triggered, thereby improving the stability of the level shifter circuit 100.

[0071] The gate voltage of the first load transistor LM1 is VCC_DC±VNOISE, the source voltage of the first load transistor LM1 is VCC_DC±VNOISE, and the source-gate voltage of the first load transistor LM1 is 0. The first load transistor LM1 remains in an off state. Therefore, when the input signal IN is at a high level and ground bounce noise is triggered, the first load transistor LM1 will not be damaged by gate overvoltage.

[0072] The first resistor R1 and the third resistor R3 limit the current capacity of the lower plate of the second capacitor C2. The charge on the second capacitor C2 does not rapidly charge or discharge during the ground bounce noise triggering period, and the voltage across the second capacitor C2 remains stable. At this time, the source-gate voltage VSG_M4 of the fourth transistor M4 and the source-gate voltage VSG_M6 of the sixth transistor M6 are 0. Therefore, when the input signal IN is at a high level and the ground bounce noise is triggered, the fourth transistor M4 and the sixth transistor M6 will not be damaged by gate overvoltage.

[0073] In addition, when the input signal IN is high and ground bounce noise is triggered, the sixth transistor M6 is continuously in the off state, so the through current of the branch where the sixth transistor M6 and the eighth transistor M8 are located is not triggered, thereby improving the stability of the level conversion circuit 100.

[0074] The seventh resistor R7 limits the current capacity of the branch containing the third capacitor C3. Therefore, before the eighth resistor R8 and the branch containing the Zener diode D are turned on, the voltage across the third capacitor C3 remains stable, and the voltage across the lower plate of the third capacitor C3 is 0±VNOISE. If the voltage across the lower plate of the third capacitor C3 is neither too high to cause reverse breakdown of the Zener diode D nor too low to cause forward conduction of the Zener diode D, the gate of the first pull-down transistor DM1 and the gate of the second pull-down transistor DM2 are coupled by the third capacitor C3, and the gate-source voltage VGS_DM1 of the first pull-down transistor DM1 and the gate-source voltage VGS_DM2 of the second pull-down transistor DM2 are 0±VNOISE.

[0075] When the Zener diode D is not conducting, if the ground bounce noise is forward noise, the ground bounce noise voltage is VNOISE, the gate-source voltage VGS_DM1 of the first pull-down transistor DM1 and the gate-source voltage VGS_DM2 of the second pull-down transistor DM2 are both VNOISE, and the gate voltage of the eighth transistor M8 and the source voltage of the second load transistor LM2 are both VCC_DC+VNOISE. When the ground bounce noise voltage VNOISE is greater than the threshold voltages of the first and second pull-down transistors DM1 and DM2, that is, the preset voltage Vpre, the first and second pull-down transistors DM1 and DM2 are turned on. Since the fifth resistor R5 and the sixth resistor R6 limit the current capacity of their respective branches, the first pull-down transistor DM1 can pull the gate of the ninth transistor M9 to the ground AGND, and the second pull-down transistor DM2 can pull the gate of the tenth transistor M10 to the ground AGND. Then, the gate-source voltage VGS_M9 of the ninth transistor M9 and the gate-source voltage VGS_M10 of the tenth transistor M10 are 0, and the ninth transistor M9 and the tenth transistor M10 are in the off state, thereby disconnecting the seventh transistor M7 from the ground and disconnecting the eighth transistor M8 from the ground.

[0076] At this time, the negative output terminal is in a floating state, and the negative output voltage signal OUTN is coupled by the parasitic capacitance to follow the ground bounce noise voltage VNOISE. Therefore, the source voltage of the eighth transistor M8 and the gate voltage of the second load transistor LM2 follow the ground bounce noise voltage VNOISE. The gate-source voltage VGS_M8 of the eighth transistor M8 and the source-gate voltage VSG_LM2 of the second load transistor LM2 can be, for example, VCC_DC+Vpre. Since the preset voltage Vpre is generally small, VCC_DC+Vpre is less than the maximum withstand voltage of the eighth transistor M8 and the second load transistor LM2.

[0077] When the ground bounce noise voltage VNOISE drops below the preset voltage Vpre, the first and second pull-down transistors DM1 and DM2 are turned off, the gate-source voltage VGS_M9 of the ninth transistor M9 is biased to 0 by the branch containing the fifth resistor R5, and the tenth transistor M10 is turned back on. At this point, the negative output voltage signal OUTN is biased to the ground potential VAGND, i.e., the source voltage of the eighth transistor M8 and the gate voltage of the second load transistor LM2 are 0, the gate-source voltage VGS_M8 of the eighth transistor M8 and the source-gate voltage VSG_LM2 of the second load transistor LM2 are VCC_DC + VNOISE, and VCC_DC + VNOISE ≤ VCC_DC + Vpre.

[0078] In this way, when positive ground bounce noise is triggered and the ground bounce noise voltage is greater than the preset voltage Vpre, when the input signal IN is at a high level, the floating control unit 121 disconnects the eighth transistor M8 from the ground, so that the negative output terminal is floating. Since the negative output voltage signal OUTN follows the ground bounce noise voltage VNOISE, the absolute value of the gate-source voltage |VGS_M8| of the eighth transistor M8 is less than the maximum withstand voltage of the eighth transistor M8, and the absolute value of the gate-source voltage |VGS_LM2| of the second load transistor LM2 is less than the maximum withstand voltage of the second load transistor LM2, thereby preventing damage to the eighth transistor M8 and the second load transistor LM2 due to gate overvoltage.

[0079] If the ground bounce noise is negative, the ground bounce noise voltage is -VNOISE, the gate-source voltage VGS_DM1 of the first pull-down transistor DM1 and the gate-source voltage VGS_DM2 of the second pull-down transistor DM2 are -VNOISE, the first pull-down transistor DM1 and the second pull-down transistor DM2 are turned off, the gate voltage of the ninth transistor M9 is biased to 0 by the branch including the fifth resistor R5, and the tenth transistor M10 remains on.

[0080] At the same time, the gate voltage of the eighth transistor M8 is VCC_DC-VNOISE. When VCC_DC-VNOISE can maintain the channel of the eighth transistor M8, the negative output voltage signal OUTN is biased to the ground potential VAGND, the gate-source voltage VGS_M8 of the eighth transistor M8 and the source-gate voltage VSG_LM2 of the second load transistor LM2 are VCC_DC-VNOISE, and VCC_DC-VNOISE≤VCC_DC.

[0081] When VCC_DC-VNOISE decreases to a level insufficient to maintain the channel voltage of the eighth transistor M8, the negative output terminal is in a floating state, and the negative output voltage signal OUTN follows the ground bounce noise voltage VNOISE. At this time, the gate-source voltage VGS_M8 of the eighth transistor M8 and the source-gate voltage VSG_LM2 of the second load transistor LM2 maintain the voltage when the channel of the eighth transistor M8 is turned on.

[0082] In this way, when the input signal IN is at a high level and negative ground bounce noise is triggered, the absolute value of the gate-source voltage |VGS_M8| of the eighth transistor M8 is less than the maximum withstand voltage of the eighth transistor M8, and the absolute value of the gate-source voltage |VGS_LM2| of the second load transistor LM2 is less than the maximum withstand voltage of the second load transistor LM2, thereby preventing damage to the eighth transistor M8 and the second load transistor LM2 due to gate overvoltage.

[0083] Furthermore, when the input signal IN is at a high level and ground bounce noise is triggered, the channel of the second load transistor LM2 may be momentarily turned off. However, as the ground bounce noise decreases, the conductive state of the second load transistor LM2 is quickly restored. Therefore, even if the load connected to the drain of the second load transistor LM2 has current capability, a through current in the branch where the second load transistor LM2 is located will not be triggered, thereby improving the stability of the level shifter circuit 100.

[0084] In other embodiments, the input signal IN is at a low level. In a steady state where the input signal IN is at a low level, the first control signal output by the first inverter INV1 is at a high level, and the second control signal output by the second inverter INV2 is at a low level. The first control signal can pull up the gate voltage of the first transistor M1, and the second control signal can pull down the gate voltage of the second transistor M2, so as to turn on the first transistor M1 and turn off the second transistor M2, thereby turning on the fourth transistor M4 and turning off the third transistor M3.

[0085] At this time, the gate of the fifth transistor M5 and the gate of the seventh transistor M7 are biased to the power input terminal, and the gate of the sixth transistor M6 and the gate of the eighth transistor M8 are biased to the ground AGND, then the fifth transistor M5 and the eighth transistor M8 are turned off, the seventh transistor M7 and the sixth transistor M6 are turned on, the positive output voltage signal OUTP is biased to 0, and the negative output voltage signal OUTN is biased to the power supply voltage VCC.

[0086] The lower plate of the third capacitor C3 is biased to the ground AGND by the seventh resistor R7. Since the first transistor M1 and the fourth transistor M4 are turned on, the second transistor M2 and the third transistor M3 are turned off, the gate of the ninth transistor M9 is biased to the power input terminal, and the gate of the tenth transistor M10 is biased to the ground AGND, the ninth transistor M9 is turned on and the tenth transistor M10 is turned off.

[0087] When ground bounce noise is triggered, the source-gate voltage VSG_M3 of the third transistor M3 and the source-gate voltage VSG_M5 of the fifth transistor M5 are 0. Therefore, when the input signal IN is at a high level and ground bounce noise is triggered, the third transistor M3 and the fifth transistor M5 will not be damaged by gate overvoltage. In addition, when the input signal IN is at a low level and ground bounce noise is triggered, the fifth transistor M5 remains in the off state, so the through current of the branch containing the fifth transistor M5 and the seventh transistor M7 is not triggered, which can improve the stability of the level shifter circuit 100.

[0088] The gate voltage of the second load transistor LM2 is VCC_DC±VNOISE, the source voltage of the second load transistor LM2 is VCC_DC±VNOISE, and the source-gate voltage of the second load transistor LM2 is 0. The second load transistor LM2 remains in the off state. Therefore, when the input signal IN is at a low level and ground bounce noise is triggered, the second load transistor LM2 will not be damaged by gate overvoltage.

[0089] The source-gate voltage VSG_M4 of the fourth transistor M4 and the source-gate voltage VSG_M6 of the sixth transistor M6 are the steady-state power supply voltage VCC_DC, the gate voltage of the eighth transistor M8 is maintained at 0±VNOISE, the negative output voltage signal OUTN is VCC_DC±VNOISE, and the gate-source voltage VGS_M8 of the eighth transistor M8 is -VCC_DC. In this way, when the input signal IN is at a low level and ground bounce noise is triggered, the voltage stabilization unit 122 can stabilize the absolute values of the gate-source voltages of the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 at the steady-state power supply voltage VCC_DC, thereby preventing damage to the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 due to gate overvoltage.

[0090] The first resistor R1 and the third resistor R3 limit the current capacity of the lower plate of the second capacitor C2. The charge on the second capacitor C2 does not rapidly charge or discharge during the ground bounce noise triggering period, and the voltage across the second capacitor C2 remains stable. At this time, the source-gate voltage VSG_M4 of the fourth transistor M4 and the source-gate voltage VSG_M6 of the sixth transistor M6 are 0. Therefore, when the input signal IN is at a high level and the ground bounce noise is triggered, the fourth transistor M4 and the sixth transistor M6 will not be damaged by gate overvoltage.

[0091] Furthermore, when the input signal IN is at a low level and ground bounce noise is triggered, even if the negative output voltage signal OUTN is biased below the ground potential VAGND by the ground bounce noise, the body diode of the eighth transistor M8 remains in the off state, and thus the through current in the branch where the sixth transistor M6 and the eighth transistor M8 are located will not be triggered.

[0092] When the Zener diode D is not conducting, if the ground bounce noise is forward noise, the gate voltage of the seventh transistor M7 and the source voltage of the first load transistor LM1 are both VCC_DC+VNOISE. When the ground bounce noise voltage VNOISE is greater than the preset voltage Vpre, the first pull-down transistor DM1 and the second pull-down transistor DM2 are turned on, the gate-source voltage VGS_M9 of the ninth transistor M9 and the gate-source voltage VGS_M10 of the tenth transistor M10 are 0, and the ninth transistor M9 and the tenth transistor M10 are in the off state, thereby disconnecting the seventh transistor M7 from the ground and disconnecting the eighth transistor M8 from the ground.

[0093] At this time, the positive output terminal is in a floating state, and the positive output voltage signal OUTP is coupled by parasitic capacitance to follow the ground bounce noise voltage VNOISE. Consequently, the source voltage of the seventh transistor M7 and the gate voltage of the first load transistor LM1 follow the ground bounce noise voltage VNOISE. The gate-source voltage VGS_M7 of the seventh transistor M7 and the source-gate voltage VSG_LM1 of the first load transistor LM1 can be, for example, VCC_DC+Vpre, where VCC_DC+Vpre is less than the maximum withstand voltage of the seventh transistor M7 and the first load transistor LM1.

[0094] When the ground bounce noise voltage VNOISE decreases to less than the preset voltage Vpre, the gate-source voltage VGS_M10 of the tenth transistor M10 is biased to 0 by the branch including the sixth resistor R6, the ninth transistor M9 is turned on again, the positive output voltage signal OUTP is biased to the ground potential VAGND, and the gate-source voltage VGS_M7 of the seventh transistor M7 and the source-gate voltage VSG_LM1 of the first load transistor LM1 are VCC_DC+VNOISE, which are less than or equal to VCC_DC+Vpre.

[0095] In this way, when positive ground bounce noise is triggered and the ground bounce noise voltage is greater than the preset voltage Vpre, when the input signal IN is at a low level, the floating control unit 121 disconnects the seventh transistor M7 from the ground, so that the positive output terminal is floating. Since the positive output voltage signal OUTP follows the ground bounce noise voltage VNOISE, the absolute value of the gate-source voltage |VGS_M7| of the seventh transistor M7 is less than the maximum withstand voltage of the seventh transistor M7, and the absolute value of the gate-source voltage |VGS_LM1| of the first load transistor LM1 is less than the maximum withstand voltage of the first load transistor LM1, thereby preventing damage to the seventh transistor M7 and the first load transistor LM1 due to gate overvoltage.

[0096] If the ground bounce noise is negative, the gate-source voltage VGS_M10 of the tenth transistor M10 is biased to 0 by the branch including the sixth resistor R6, the ninth transistor M9 remains on again, and the gate voltage of the seventh transistor M7 is VCC_DC-VNOISE. When VCC_DC-VNOISE can maintain the channel of the seventh transistor M7, the positive output voltage signal OUTP is biased to the ground potential VAGND, the gate-source voltage VGS_M2 of the seventh transistor M7 and the source-gate voltage VSG_LM1 of the first load transistor LM1 are VCC_DC-VNOISE, and VCC_DC-VNOISE≤VCC_DC.

[0097] When VCC_DC-VNOISE decreases to a level insufficient to maintain the channel of the seventh transistor M7, the positive output terminal is in a floating state, the positive output voltage signal OUTP follows the ground bounce noise voltage VNOISE, and the gate-source voltage VGS_M7 of the seventh transistor M7 and the source-gate voltage VSG_LM1 of the first load transistor LM1 maintain the voltage when the channel of the seventh transistor M7 is turned on.

[0098] In this way, when the input signal IN is at a low level and negative ground bounce noise is triggered, the absolute value of the gate-source voltage |VGS_M7| of the seventh transistor M7 is less than the maximum withstand voltage of the seventh transistor M7, and the absolute value of the gate-source voltage |VGS_LM1| of the first load transistor LM1 is less than the maximum withstand voltage of the first load transistor LM1, thereby preventing damage to the seventh transistor M7 and the first load transistor LM1 due to gate overvoltage.

[0099] Furthermore, when the input signal IN is at a low level and ground bounce noise is triggered, the channel of the first load transistor LM1 may be momentarily turned off. However, as the ground bounce noise decreases, the conductive state of the first load transistor LM1 is quickly restored. Therefore, even if the load connected to the drain of the first load transistor LM1 has current capability, a through current in the branch where the first load transistor LM1 is located will not be triggered, thereby improving the stability of the level shifter circuit 100.

[0100] In summary, when ground bounce noise is triggered, the absolute values of the gate-source voltages of the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, and the tenth transistor are less than or equal to the steady-state power supply voltage VCC_DC. The absolute values of the gate-source voltages of the seventh transistor M7, the eighth transistor M8, the first load transistor LM1, and the second load transistor LM2 follow the ground bounce noise voltage to be less than or equal to the sum of the steady-state power supply voltage VCC_DC and a small voltage. Therefore, when ground bounce noise is triggered, the absolute values of the gate-source voltages of the transistors in the level shifter circuit can be limited to less than the maximum withstand voltage of the transistors, thereby reducing the risk of damage caused by gate overvoltage.

[0101] In addition, when ground bounce noise is triggered, the through-current of the branch where the fifth transistor M5 and the seventh transistor M7 are located, the through-current of the branch where the sixth transistor M6 and the eighth transistor M8 are located, the through-current of the branch where the first and second load transistors LM1 are located, and the through-current of the branch where the second load transistor LM2 is located are not triggered, thereby improving the stability of the level conversion circuit 100.

[0102] In some embodiments, if the lower plate voltage of the third capacitor C3 is too high and causes the Zener diode D to reversely break down, the Zener diode D can clamp the gate-source voltage VGS_DM1 of the first pull-down transistor DM1 and the gate-source voltage VGS_DM2 of the second pull-down transistor DM2 to the reverse conduction voltage of the Zener diode D.

[0103] If the lower plate voltage of the third capacitor C3 is too low to cause the Zener diode D to conduct forward, the Zener diode D can clamp the gate-source voltage VGS_DM1 of the first pull-down transistor DM1 and the gate-source voltage VGS_DM2 of the second pull-down transistor DM2 to the forward conduction voltage of the Zener diode D.

[0104] Because the reverse conduction voltage and forward conduction voltage of the Zener diode D are relatively small, the gate-source voltage VGS_DM1 of the first pull-down transistor DM1 and the gate-source voltage VGS_DM2 of the second pull-down transistor DM2 are relatively small. Therefore, the absolute value |VGS_DM1| of the gate-source voltage of the first pull-down transistor DM1 is less than the maximum withstand voltage of the first pull-down transistor DM1, and the absolute value |VGS_DM2| of the gate-source voltage of the second pull-down transistor DM2 is less than the maximum withstand voltage of the second pull-down transistor DM2. As a result, the first pull-down transistor DM1 and the second pull-down transistor DM2 are not damaged by gate overvoltage.

[0105] The eighth resistor R8 can limit the magnitude of the current passing through the Zener diode D, ensuring that the instantaneously coupled ground bounce noise current does not exceed the current capability of the Zener diode D, thereby protecting the Zener diode D.

[0106] In this way, the magnitude of the current passing through the Zener diode D can be limited, thereby protecting the Zener diode D and improving the stability of the level conversion circuit 100 .

[0107] In some embodiments, Figure 4 This is a circuit diagram of another level conversion circuit provided by an embodiment of the present disclosure. Based on the above embodiment, the protection module 120 further includes a pull-down unit 123, such as Figure 4 shown.

[0108] The first input end of the pull-down unit 123 is connected to the drain of the seventh transistor M7 through the floating control unit 121, the second input end of the pull-down unit 123 is connected to the drain of the eighth transistor M8 through the floating control unit 121, the output end of the pull-down unit 123 is grounded AGND, and the control end of the pull-down unit 123 is connected to the fourth output end of the control module 130.

[0109] The pull-down unit 123 is configured to disconnect the floating control unit 121 from the ground AGND within a preset time period Tpre from the inversion moment of the input signal IN to the inversion moment, so as to disconnect the seventh transistor M7 and the eighth transistor M8 from the ground AGND.

[0110] Exemplarily, the pull-down unit 123 includes a third pull-down tube DM3 and a fourth pull-down tube DM4, the source of the third pull-down tube DM3 and the source of the fourth pull-down tube DM4 are grounded AGND, the drain of the third pull-down tube DM3 is connected to the drain of the seventh transistor M7 through the suspension control unit 121, the drain of the fourth pull-down tube DM4 is connected to the drain of the eighth transistor M8 through the suspension control unit 121, and the gate of the third pull-down tube DM3 and the gate of the fourth pull-down tube DM4 are connected to the fourth output end of the control module 110.

[0111] For example, Figure 4 As shown, the drain of the third pull-down transistor DM3 is connected to the drain of the seventh transistor M7 through the ninth transistor M9 , and the drain of the fourth pull-down transistor DM4 is connected to the drain of the eighth transistor M8 through the tenth transistor M10 .

[0112] The control module 110 includes a delay device DLY, an XOR gate XOR, a switch tube K, a ninth resistor R9, and a fourth capacitor C4. The drain of the switch tube K is the fourth output terminal of the control module 110. The input terminal of the delay device DLY and the first input terminal of the XOR gate XOR are connected to the input signal IN, the output terminal of the delay device DLY is connected to the second input terminal of the XOR gate XOR, the output terminal of the XOR gate XOR is connected to the gate of the switch tube K, the source of the switch tube K and the lower plate of the fourth capacitor C4 are grounded to AGND, the drain of the switch tube K is connected to the first terminal of the ninth resistor R9, the upper plate of the fourth capacitor C4, the gate of the third pull-down tube DM3, and the gate of the fourth pull-down tube DM4, and the second terminal of the ninth resistor R9 is connected to the power input terminal.

[0113] Due to the presence of the first capacitor C1, the second capacitor C2, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, the switching speed of the gate-source voltages of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 is slowed down when the input signal IN is switched. Therefore, during the switching process of the input signal IN, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may be turned on at the same time.

[0114] A preset duration Tpre is set within the delay device DLY. During the period Tpre between the inversion moment of the input signal IN and the inversion moment of the input signal IN, the level shifter circuit 100 is in an unstable state. The XOR gate XOR outputs a high level, turning on the switch tube K to generate a pull-down control signal and provide it to the gates of the third pull-down tube DM3 and the fourth pull-down tube DM4. The preset duration Tpre can be equal to or slightly greater than the duration of the unstable state of the level shifter circuit 100.

[0115] Under the action of the pull-down control signal, the third pull-down transistor DM3 and the fourth pull-down transistor DM4 are in the off state, which can disconnect the ninth transistor M9 and the tenth transistor M10 from the ground AGND, thereby disconnecting the seventh transistor M7 and the eighth transistor M8 from the ground AGND, thereby avoiding triggering the through-current of the branch where the fifth transistor M5 and the seventh transistor M7 are located, and the through-current of the branch where the sixth transistor M6 and the eighth transistor M8 are located, thereby improving the stability of the level conversion circuit 100.

[0116] After a preset time Tpre after the flip moment of the input signal IN, the level conversion circuit 100 is in a steady state, the XOR gate XOR outputs a low level, the switch tube K is turned off, the upper plate of the fourth capacitor C4 is biased to the power input terminal by the ninth resistor R9, and the third pull-down tube DM3 and the fourth pull-down tube DM4 are turned on.

[0117] For example, Figure 5 This is a timing diagram of the operation of the level conversion circuit provided by the embodiment of the present disclosure when the input signal is reversed, as shown in FIG. Figure 5 As shown, when the input signal IN flips from a low level to a high level, the gate-source voltage VGS_DM3 of the third pull-down tube DM3 and the gate-source voltage VGS_DM4 of the fourth pull-down tube DM4 are quickly pulled down to quickly turn off the third pull-down tube DM3 and the fourth pull-down tube DM4, thereby preventing the triggering of a through current.

[0118] At this time, the source-gate voltage VSG_M5 of the fifth transistor M5, the source-gate voltage VSG_M6 of the sixth transistor M6, the gate-source voltage VGS_M7 of the seventh transistor M7, the gate-source voltage VGS_M8 of the eighth transistor M8, the gate-source voltage VGS_M9 of the ninth transistor M9 and the gate-source voltage VGS_M10 of the tenth transistor M10 begin to flip, and the source-gate voltage VSG_LM1 of the first load transistor LM1 begins to flip.

[0119] like Figure 5 As shown, after the gate-source voltage VSG_M5 of the fifth transistor M5, the gate-source voltage VSG_M6 of the sixth transistor M6, the gate-source voltage VGS_M7 of the seventh transistor M7, the gate-source voltage VGS_M8 of the eighth transistor M8, the gate-source voltage VGS_M9 of the ninth transistor M9, and the gate-source voltage VGS_M10 of the tenth transistor M10 are reversed, the gate-source voltage VGS_DM3 of the third pull-down transistor DM3 and the gate-source voltage VGS_DM4 of the fourth pull-down transistor DM4 are pulled high again, and the source-gate voltage VSG_LM2 of the second load transistor LM2 begins to reverse.

[0120] When ground bounce noise is triggered, the ninth resistor R9 limits the current capacity of the top plate of the fourth capacitor C4, and the voltage across the fourth capacitor C4 remains stable. At this time, the gate-source voltage VGS_DM3 of the third pull-down transistor DM3 and the gate-source voltage VGS_M4 of the fourth pull-down transistor DM4 are at the steady-state power supply voltage VCC_DC, and the third pull-down transistor DM3 and the fourth pull-down transistor DM4 are not damaged by gate overvoltage.

[0121] For example, Figure 6 and Figure 7 This is a timing diagram of the operation of the level conversion circuit provided by the embodiment of the present disclosure when ground bounce noise is triggered, as shown in FIG. Figure 6 As shown in FIG. 1 , when negative ground bounce noise is triggered first, the power supply voltage VCC oscillates within the range of VCC_DC±VNOISE, the source-gate voltage VSG_LM2 of the second load transistor LM2 is at most VCC_DC, and the source-gate voltage VSG_LM1 of the first load transistor LM1 is zero.

[0122] The gate-source voltage VGS_DM3 of the third pull-down transistor DM3 and the gate-source voltage VGS_M5 of the fifth transistor M5 maintain VCC_DC. The source-gate voltage VGS_M9 of the ninth transistor M9 oscillates around 0V. The gate-source voltage VGS_M7 of the seventh transistor M7 maintains -VCC_DC. The gate-source voltage VGS_DM4 of the fourth pull-down transistor DM4 maintains VCC_DC. The gate-source voltage VGS_M8 of the eighth transistor M8 reaches a maximum of VCC_DC. The gate-source voltage VGS_M10 of the tenth transistor M10 oscillates around 0V. The source-gate voltage VSG_M6 of the sixth transistor M6 is 0.

[0123] like Figure 7 As shown, when the positive ground bounce noise is triggered first, the power supply voltage VCC oscillates within the range of VCC_DC±VNOISE, the source-gate voltage VSG_LM2 of the second load transistor LM2 is at most VCC_DC+Vth_DM2, where Vth_DM2 is the threshold voltage of the second pull-down transistor DM2, and the source-gate voltage VSG_LM1 of the first load transistor LM1 is 0.

[0124] The gate-source voltage VGS_DM3 of the third pull-down transistor DM3 and the gate-source voltage VGS_M5 of the fifth transistor M5 maintain VCC_DC. The source-gate voltage VGS_M9 of the ninth transistor M9 oscillates around 0V. The gate-source voltage VGS_M7 of the seventh transistor M7 maintains -VCC_DC. The gate-source voltage VGS_DM4 of the fourth pull-down transistor DM4 maintains VCC_DC. The gate-source voltage VGS_M8 of the eighth transistor M8 is a maximum of VCC_DC + Vth_DM2. The gate-source voltage VGS_M10 of the tenth transistor M10 oscillates around 0V. The source-gate voltage VSG_M6 of the sixth transistor M6 is 0.

[0125] In summary, when ground bounce noise is triggered, the absolute values of the gate-source voltages of the third pull-down transistor DM3 and the fourth pull-down transistor DM4 can be limited to the steady-state power supply voltage VCC_DC. This can further limit the gate-source voltages of the transistors in the level shifter circuit when ground bounce noise is triggered, thereby further reducing the risk of gate overvoltage damage to the transistors.

[0126] Furthermore, during the preset time period Tpre from the inversion moment of the input signal IN to the inversion moment after the input signal IN, the third pull-down transistor DM3 and the fourth pull-down transistor DM4 are turned off to avoid triggering a shoot-through current and improve the stability of the level shifting circuit 100 .

[0127] The present disclosure further provides a switching power supply chip, comprising the level conversion circuit 100 provided in any one of the above embodiments.

[0128] The switching power supply chip provided in the embodiment of the present disclosure includes the level conversion circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the voltage leveling circuit 100, which will not be repeated here.

[0129] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0130] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A level conversion circuit, characterized in that: include: Control module, protection module and conversion module; The control module is configured to generate a control signal according to an input signal; The protection module is configured to, when positive ground bounce noise is triggered and the ground bounce noise voltage is greater than a preset voltage, suspend one of the positive output terminal and the negative output terminal of the conversion module so that the absolute value of the gate-source voltage of some transistors connected to the suspended output terminal follows the ground bounce noise voltage; The conversion module is configured to generate a positive output voltage signal and a negative output voltage signal according to the control signal, a steady-state power supply voltage, and the ground bounce noise voltage when ground bounce noise is triggered.

2. The level conversion circuit according to claim 1, wherein: The conversion module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first load transistor and a second load transistor, and the protection module includes a suspension control unit; The gate of the first transistor is connected to the first output terminal of the control module, the gate of the second transistor is connected to the second output terminal of the control module, the source of the first transistor, the source of the second transistor, the drain of the first load transistor, and the drain of the second load transistor are grounded, and the source of the third transistor, the source of the fourth transistor, the source of the fifth transistor, the source of the sixth transistor, the source of the first load transistor, and the source of the second load transistor are connected to the power input terminal; The gate of the third transistor is connected to the drain of the fourth transistor, the drain of the second transistor, the gate of the fifth transistor, the gate of the seventh transistor, and the first control terminal of the suspension control unit; the gate of the fourth transistor is connected to the drain of the third transistor, the drain of the first transistor, the gate of the sixth transistor, the gate of the eighth transistor, and the second control terminal of the suspension control unit; the first input terminal of the suspension control unit is connected to the drain of the seventh transistor; the second input terminal of the suspension control unit is connected to the drain of the eighth transistor; the output of the suspension control unit is grounded; and the third control terminal of the suspension control unit is connected to the third output terminal of the control module; The drain of the fifth transistor is connected to the source of the seventh transistor, the body of the seventh transistor, the gate of the first load transistor and the positive output terminal, and the drain of the sixth transistor is connected to the source of the eighth transistor, the body of the eighth transistor, the gate of the second load transistor and the negative output terminal; The suspension control unit is configured to, when the positive ground bounce noise is triggered and the ground bounce noise voltage is greater than the preset voltage, disconnect the seventh transistor from the ground when the input signal is at a low level so that the positive output terminal is suspended, and disconnect the eighth transistor from the ground so that the negative output terminal is suspended when the input signal is at a high level.

3. The level conversion circuit according to claim 2, wherein: The protection module also includes a voltage stabilizing unit; The drain of the first transistor is connected to the first end of the voltage stabilizing unit and the second control end of the suspension control unit, the drain of the second transistor is connected to the second end of the voltage stabilizing unit and the first control end of the suspension control unit, and the third end of the voltage stabilizing unit is connected to the power input end; The gate of the third transistor is connected to the fourth terminal of the voltage stabilizing unit, the gate of the fifth transistor, and the gate of the seventh transistor; the gate of the fourth transistor is connected to the fifth terminal of the voltage stabilizing unit, the gate of the sixth transistor, and the gate of the eighth transistor; the drain of the third transistor is connected to the sixth terminal of the voltage stabilizing unit; and the drain of the fourth transistor is connected to the seventh terminal of the voltage stabilizing unit; The voltage stabilizing unit is configured to, in the case of triggering the ground bounce noise, when the input signal is at a low level, stabilize the absolute values of the gate-source voltages of the fourth transistor, the sixth transistor, and the eighth transistor to the steady-state power supply voltage; and when the input signal is at a high level, stabilize the absolute values of the gate-source voltages of the third transistor, the fifth transistor, and the seventh transistor to the steady-state power supply voltage.

4. The level conversion circuit according to claim 3, wherein: The voltage stabilizing unit includes a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor and a fourth resistor; The upper plate of the first capacitor and the upper plate of the second capacitor are connected to the power input terminal, the lower plate of the first capacitor is connected to the gate of the fifth transistor, the gate of the third transistor, the gate of the seventh transistor, the first end of the second resistor and the first end of the fourth resistor, the second end of the second resistor is connected to the drain of the second transistor, the second end of the fourth resistor is connected to the drain of the fourth transistor, the lower plate of the second capacitor is connected to the gate of the sixth transistor, the gate of the fourth transistor, the gate of the eighth transistor, the first end of the first resistor and the first end of the third resistor, the second end of the first resistor is connected to the drain of the first transistor, and the second end of the third resistor is connected to the drain of the third transistor.

5. The level conversion circuit according to claim 2, wherein: The suspension control unit includes a ninth transistor, a tenth transistor, a fifth resistor, a sixth resistor, a first pull-down transistor and a second pull-down transistor; The source of the ninth transistor, the source of the tenth transistor, the source of the first pull-down transistor, and the source of the second pull-down transistor are grounded; the gate of the ninth transistor is connected to the first end of the fifth resistor and the drain of the first pull-down transistor; the drain of the ninth transistor is connected to the drain of the seventh transistor; the gate of the tenth transistor is connected to the first end of the sixth resistor and the drain of the second pull-down transistor; and the drain of the tenth transistor is connected to the drain of the eighth transistor; The second end of the fifth resistor is connected to the drain of the second transistor, the second end of the sixth resistor is connected to the drain of the first transistor, and the gates of the first pull-down transistor and the second pull-down transistor are connected to the third output end of the control module.

6. The level conversion circuit according to claim 2, wherein: The control module includes a first inverter, a second inverter, a third capacitor, a seventh resistor, an eighth resistor and a voltage stabilizing diode. The input terminal of the first inverter is connected to the input signal, the output terminal of the first inverter is connected to the gate of the first transistor and the input terminal of the second inverter, and the output terminal of the second inverter is connected to the gate of the second transistor; The upper plate of the third capacitor is connected to the power input terminal, the lower plate of the third capacitor is connected to the first end of the seventh resistor and the first end of the eighth resistor, the second end of the eighth resistor is connected to the negative electrode of the voltage regulator diode and the third control terminal of the suspension control unit, and the second end of the seventh resistor and the positive electrode of the voltage regulator diode are grounded.

7. The level conversion circuit according to claim 6, wherein: The protection module further includes a pull-down unit; The first input terminal of the pull-down unit is connected to the drain of the seventh transistor through the suspension control unit, the second input terminal of the pull-down unit is connected to the drain of the eighth transistor through the suspension control unit, the output terminal of the pull-down unit is grounded, and the control terminal of the pull-down unit is connected to the fourth output terminal of the control module; The pull-down unit is configured to disconnect the suspension control unit from the ground within a preset time period from the flipping moment of the input signal to the flipping moment, so as to disconnect the seventh transistor and the eighth transistor from the ground.

8. The level conversion circuit according to claim 7, wherein: The pull-down unit includes a third pull-down tube and a fourth pull-down tube; The source of the third pull-down tube and the source of the fourth pull-down tube are grounded, the drain of the third pull-down tube is connected to the drain of the seventh transistor through the suspension control unit, the drain of the fourth pull-down tube is connected to the drain of the eighth transistor through the suspension control unit, and the gate of the third pull-down tube and the gate of the fourth pull-down tube are connected to the fourth output end of the control module.

9. The level conversion circuit according to claim 8, wherein: The control module includes a delay device, an XOR gate, a switch tube, a ninth resistor and a fourth capacitor; The input end of the delay device and the first input end of the XOR gate are connected to the input signal, the output end of the delay device is connected to the second input end of the XOR gate, the output end of the XOR gate is connected to the gate of the switching tube, the source of the switching tube and the lower plate of the fourth capacitor are grounded, the drain of the switching tube is connected to the first end of the ninth resistor, the upper plate of the fourth capacitor, the gate of the third pull-down tube and the gate of the fourth pull-down tube, and the second end of the ninth resistor is connected to the power input end.

10. A switching power supply chip, characterized in that: The level conversion circuit comprises the level conversion circuit according to any one of claims 1 to 9.

Images