Digital logic circuit input and output device and system thereof
By adopting the input stage of the back-to-back MOS tube structure and the output stage of the single-signal control line structure in the digital logic circuit, the problem that traditional chips can only receive 0V~VCC signals is solved, and signal reception in the full voltage range is realized, cost and PCB area are reduced, and reliability is improved.
Patent Information
- Application Number
- CN202510544800.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-08
AI Technical Summary
Traditional digital logic circuit chips can only receive digital signals from 0V to VCC, which have problems such as poor reliability, high cost, and large PCB area. Especially when the system voltage is inconsistent, special level conversion chips are needed.
The input stage of the back-to-back MOS tube structure and the output stage of the single signal control line structure are adopted. The input stage provides anti-static function and the output stage provides anti-leakage function, so that the digital logic circuit can receive signals in the full voltage range.
The input and output of the digital logic circuit can receive signals from negative voltage to exceed the power supply voltage, alleviating the problems of high cost, large PCB area, and poor reliability of traditional chips.
Smart Images
Figure CN120454713A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a digital logic circuit input and output device and a system thereof. Background Art
[0002] Currently, traditional digital logic circuit chips can generally only receive digital signals from 0V to VCC at the front end, resulting in poor reliability and inconvenience. In particular, when the voltages of various systems are inconsistent, dedicated level conversion chips are often required. As a result, traditional digital logic circuit chips have problems such as high cost and large PCB (Printed Circuit Board) area. Summary of the Invention
[0003] In view of this, the purpose of the present invention is to provide a digital logic circuit input and output device and its system, so that the input and output of the digital logic circuit can receive signals ranging from negative voltage to exceeding the power supply voltage, so as to alleviate the problems of high cost and large PCB area existing in traditional digital logic circuit chips.
[0004] In a first aspect, the present invention provides a digital logic circuit input-output device comprising: an input stage, a digital logic circuit, and an output stage electrically connected in sequence;
[0005] The input stage uses a back-to-back MOS tube structure; the input stage is used to provide anti-static function when receiving the operating voltage of the full voltage range and transmit the operating voltage to the digital logic circuit;
[0006] The output stage adopts a single-signal control circuit structure, which includes multiple PMOS transistors, multiple NMOS transistors, and substrate diodes. The substrates of each PMOS transistor are interconnected and isolated from the power supply through the substrate diode, and the substrate of each NMOS transistor is grounded. The output stage is used to provide leakage protection when receiving the full voltage range output by the digital logic circuit.
[0007] The upper limit of the full voltage range is higher than the power supply voltage and the lower limit is lower than 0V.
[0008] In one embodiment, the output stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a substrate diode;
[0009] The substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are connected to each other and isolated from the power supply through substrate diodes;
[0010] The substrates of the first NMOS transistor and the second NMOS transistor are grounded.
[0011] In one embodiment, the source of the first PMOS transistor and the drain of the sixth PMOS transistor are connected to form an output;
[0012] The gate of the second NMOS transistor is connected to the gate of the third PMOS transistor to form an output.
[0013] In one embodiment, the source of the second PMOS transistor and the source of the sixth PMOS transistor are connected to a power supply to provide power to the circuit;
[0014] The gates of the first PMOS tube, the first NMOS tube, the fourth PMOS tube and the fifth PMOS tube are connected to a power supply and are used to control the on and off states of the second PMOS tube and the sixth PMOS tube.
[0015] In one embodiment, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor to form an inverter, and is connected to the gate of the second PMOS transistor;
[0016] The drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube to form an inverter, and is also connected to the drain of the sixth PMOS tube.
[0017] In one embodiment, the gate of the second NMOS transistor is connected to the input port of the output stage, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the drain of the third PMOS transistor and the gate of the sixth PMOS transistor;
[0018] The drain of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor.
[0019] In one embodiment, the input stage includes a resistor, and an input port of the input stage is connected to the digital logic circuit via the resistor, so as to prevent electrostatic signals and surge signals from being transmitted to the digital logic circuit;
[0020] The input stage also includes a third NMOS tube and a seventh PMOS tube. The gate and drain of the third NMOS tube are connected and connected to the power supply. The gate and source of the seventh PMOS tube are connected and connected to the digital logic circuit. The source of the third NMOS tube and the drain of the seventh PMOS tube are connected to form a back-to-back relationship, which is used to provide anti-static function when receiving the operating voltage of the full voltage range.
[0021] In one embodiment, the input stage further includes a fourth NMOS transistor, wherein the gate and source of the fourth NMOS transistor are connected and grounded, and the drain of the fourth NMOS transistor is connected to the digital logic circuit;
[0022] The resistor and the fourth NMOS transistor form a voltage-dividing relationship, which is used to reduce the signal amplitude of the operating voltage entering the digital logic circuit.
[0023] In one embodiment, the input stage further includes a diode, and the input port of the input stage is connected to the ground via the diode, so as to allow the electrostatic signal and the surge signal to break through the diode to discharge the voltage.
[0024] In a second aspect, the present invention further provides a digital logic circuit input-output system, comprising any one of the digital logic circuit input-output devices provided in the first aspect.
[0025] The present invention provides a digital logic circuit input / output device and system thereof, comprising: an input stage, a digital logic circuit, and an output stage electrically connected in sequence; the input stage employing a back-to-back MOS transistor structure; the input stage being configured to provide anti-static protection when receiving an operating voltage within a full voltage range and transmit the operating voltage to the digital logic circuit; the output stage employing a single-signal control circuit structure comprising a plurality of PMOS transistors, a plurality of NMOS transistors, and a substrate diode, wherein the substrates of each PMOS transistor are interconnected and isolated from a power supply via a substrate diode, and the substrate of each NMOS transistor is grounded; the output stage being configured to provide leakage protection when receiving an output voltage within a full voltage range output by the digital logic circuit; wherein the upper limit of the full voltage range is higher than the power supply voltage and the lower limit is lower than 0V. The digital logic circuit input / output device provides anti-static protection when receiving an operating voltage within the full voltage range and provides leakage protection when outputting an output voltage within the full voltage range, thereby enabling the input and output of the digital logic circuit to receive signals ranging from negative voltage to signals exceeding the power supply voltage, thereby alleviating the problems of high cost and large PCB area associated with traditional digital logic circuit chips.
[0026] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.
[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0029] Figure 1 A block diagram of a digital logic chip structure provided by an embodiment of the present invention;
[0030] Figure 2 A schematic structural diagram of a digital logic circuit input and output device provided by an embodiment of the present invention;
[0031] Figure 3 An output circuit diagram of a digital logic chip provided by an embodiment of the present invention;
[0032] Figure 4 A digital logic chip output circuit layout provided by an embodiment of the present invention;
[0033] Figure 5 This is a digital logic chip input circuit diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0035] When designing a CMOS digital logic signal system, Figure 1 The block diagram of a digital logic chip structure is shown. Traditional digital logic chips have problems such as the input voltage signal cannot exceed the power supply voltage, or when the power is off, the output terminal cannot be connected to other ports, allowing the introduction of voltage signals, and cannot be used for dual system backup. This requires the addition of a level conversion chip in the design of the digital logic chip and the need to prevent leakage at the output terminal. This will lead to the following problems: increased PCB board area, increased design and debugging difficulty, poor reliability, and high failure rate.
[0036] Based on this, the present invention provides a digital logic circuit input and output device and system thereof, so that the input and output of the digital logic circuit can receive signals ranging from negative voltage to signals exceeding the power supply voltage, thereby alleviating the problems of high cost, large PCB area, poor reliability, and high failure rate existing in traditional digital logic circuit chips.
[0037] To facilitate understanding of this embodiment, we first introduce in detail a digital logic circuit input and output device disclosed in an embodiment of the present invention. The input and output circuits in the device and the corresponding layout of the output circuits can be used in various CMOS digital logic integrated circuit chips. Figure 2The structure diagram of a digital logic circuit input and output device shown in the figure includes: an input stage 1, a digital logic circuit 2 and an output stage 3 electrically connected in sequence, and the core of the device is an output current backflow prevention circuit.
[0038] In one example, the input stage 1 adopts a back-to-back MOS tube structure; the input stage 1 is used to provide an anti-static function when receiving an operating voltage within a full voltage range and transmit the operating voltage to the digital logic circuit 2.
[0039] In one example, the output stage 3 adopts a single-signal control circuit structure, which includes multiple PMOS transistors, multiple NMOS transistors, and substrate diodes. The substrates of each PMOS transistor are interconnected and isolated from the power supply via the substrate diode, and the substrate of each NMOS transistor is grounded. The output stage 3 is used to provide leakage protection when receiving the output voltage of the full voltage range output by the digital logic circuit 2.
[0040] The upper limit of the full voltage range is higher than the power supply voltage and the lower limit is lower than 0V.
[0041] The digital logic circuit input / output device provided in an embodiment of the present invention provides an anti-static function when receiving an operating voltage within the full voltage range, and provides an anti-leakage function when outputting an output voltage within the full voltage range. This allows the input and output of the digital logic circuit to receive signals ranging from negative voltage to signals exceeding the power supply voltage, thereby alleviating the problems of traditional digital logic circuit chips such as high cost, large PCB area, poor reliability, and high failure rate.
[0042] To facilitate understanding, the present invention provides a specific structure for a digital logic circuit input / output device. The output stage utilizes a substrate diode and a single-signal control circuit structure, including a single-signal control circuit consisting of six PMOS transistors and two NMOS transistors, and an isolation / shutdown diode. Back-to-back MOS transistors are used in the input stage.
[0043] In one example, the output stage is explained in the embodiment of the present invention, see Figure 3 A digital logic chip output circuit diagram is shown.
[0044] The core of the output stage is a PMOS transistor. When the output PMOS transistor is off, a turn-off diode is added between the substrate of the output PMOS transistor and VCC. The function of the turn-off diode is to block the output path to VCC, allowing the output of the integrated circuit chip to reach a voltage higher than VCC. Furthermore, when the output PMOS transistor is on, a large current flows through the output PMOS transistor to the power supply, and the turn-off diode is ineffective. Therefore, a circuit consisting of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NMOS transistor N1, and a second NMOS transistor N2 is required.
[0045] Furthermore, the substrates of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 are connected to each other and isolated from the power supply through the substrate diode D1; the substrates of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded.
[0046] Furthermore, the source of the first PMOS transistor P1 is connected to the drain of the sixth PMOS transistor P6 to form an output; the gate of the second NMOS transistor P2 is connected to the gate of the third PMOS transistor P3 to form an output.
[0047] Furthermore, the source of the second PMOS transistor P2 and the source of the sixth PMOS transistor P6 are connected to the power supply to provide power for the circuit; the gates of the first PMOS transistor P1, the first NMOS transistor N1, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 are connected to the power supply to control the on and off states of the second PMOS transistor P2 and the sixth PMOS transistor P6.
[0048] Furthermore, the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 to form an inverter, and is also connected to the gate of the second PMOS transistor P2.
[0049] Furthermore, the drain of the fourth PMOS transistor P4 is connected to the source of the fifth PMOS transistor P5 to form an inverter, and is also connected to the drain of the sixth PMOS transistor P6.
[0050] Furthermore, the gate of the second NMOS transistor N2 is connected to the input port of the output stage, the source of the second NMOS transistor N2 is grounded, and the drain of the second NMOS transistor N2 is connected to the drain of the third PMOS transistor P3 and the gate of the sixth PMOS transistor P6;
[0051] Furthermore, the drain of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6.
[0052] As described above, the third PMOS transistor P3, the fifth PMOS transistor P5, and the second NMOS transistor N2 connected to the gate of the sixth PMOS transistor P6 jointly control the shutdown of the sixth PMOS transistor P6, allowing current under various external voltage conditions to enter the chip, thereby ensuring that the chip output is leak-free when the output stage of the CMOS digital logic integrated circuit chip is operating normally or abnormally, and when the voltage exceeds the power supply voltage.
[0053] In the first case, when the output voltage is greater than the power supply voltage, in this case, when the device is powered off, the current of the interface signal flows back to the power supply pin, damaging the device. Therefore, the off-state output current Ioff characteristic is added. The Ioff parameter refers to when the device is powered off, that is, VCC = 0, such as Figure 2 As shown in FIG. 1 , the PMOS transistor P6 and the parasitic diode of the output port are in the cut-off state, blocking the leakage channel from the output to the power supply (VCC=0). The maximum current Ioff that can flow into the VCC pin at the output end is within the required range. Thus, when the output voltage is higher than the power supply voltage, the current cannot flow to the power supply end, that is, the Ioff parameter reaches the microampere level.
[0054] The solution is to add a turn-off diode between the substrate of the output PMOS tube (the sixth PMOS tube P6) and VCC. The function of the turn-off diode (D1) is to block the output to VCC path.
[0055] If the sixth PMOS transistor P6 is turned on, a large current flows through it to the power supply (VCC = 0), creating a leakage path for the output to the power supply (VCC = 0), rendering the cutoff diode ineffective. To ensure the design works, the sixth PMOS transistor P6 must be turned off, requiring the addition of the circuit consisting of P1N1, P2P3, and P4P5.
[0056] Function of the fifth PMOS transistor P5: When VCC=0, the fifth PMOS transistor P5 is turned on, the potential of point A is high and level, and the sixth PMOS transistor P6 is turned off.
[0057] The fourth PMOS transistor P4 functions to increase the substrate potentials of the first PMOS transistor P1 , the second PMOS transistor P2 , the third PMOS transistor P3 , the fifth PMOS transistor P5 , and the sixth PMOS transistor P6 .
[0058] Function of the first PMOS transistor P1: When VCC=0, the fifth PMOS transistor P5 is turned on, the potential at point B is high and level, and the second PMOS transistor P2 is turned off.
[0059] The function of the second PMOS transistor P2 is to limit the current, so that the potential of point A is the output voltage, and block the path of the output to VCC through the third PMOS transistor P3.
[0060] In the second case, Line 1: Under normal working conditions, it is in the cut-off state, and the output port PMOS source is connected to VCC, which does not affect the output and therefore has no effect on VOH; Line 2: Under normal working conditions, the inverter is in the normal output state, so the subsequent output terminal PMOS is determined by the inverter; Line 3: The diode controls the substrate potential of the PMOS tube in different states.
[0061] Furthermore, in order to enable the output of a CMOS digital logic integrated circuit chip to receive a signal exceeding the power supply voltage, an embodiment of the present invention provides a layout corresponding to the output circuit of a CMOS digital logic integrated circuit chip. For low-frequency circuit chips, L does not need to be particularly small, and for low-power circuits, W / L cannot be too large, otherwise the power consumption will not meet the parameters.
[0062] Furthermore, the layout is based on a P-substrate N-well CMOS process, and the layout device arrangement follows the principle of close and shortest connections.
[0063] See also Figure 4 The output circuit layout of a digital logic chip shown in the figure includes six PMOS transistors, two NMOS transistors, and one diode. The first PMOS transistor P1 is a small single transistor, and the first NMOS transistor N1 is a small single transistor. The second PMOS transistor P2 uses 16 transistors in parallel with a width-to-length ratio of 400-500. The third PMOS transistor P3 uses 14 transistors in parallel with a width-to-length ratio of 350-450. The fifth PMOS transistor P5 uses 42 transistors in parallel with a width-to-length ratio of 1200-1300. The second NMOS transistor N2 uses two transistors in parallel with a width-to-length ratio of 80-100.
[0064] The diode D1 is a P+N well structure, with P+ as the positive electrode and N well as the negative electrode, and is connected through the N+ contact.
[0065] The drain of the fifth PMOS transistor P4 is connected to the source of the fifth PMOS transistor and has the same size, so the two transistors share an active area. The sixth PMOS transistor P6 is used for output driving and carries a large current. The width of the metal connection must meet the current capacity, including the connection to the output connection and the connection to the cathode terminal of the diode. Because the source of the sixth PMOS transistor P6 is connected to the power supply through a diode, the connection between the two ends of the diode must meet the same current capacity.
[0066] All PMOS tube substrates are connected to the power supply through diodes, so they are all in the same N-well. The N-well contacts between the sixth PMOS tube P6 and other devices, taking all devices into consideration and isolating the sixth PMOS tube P6 from all other devices, thereby reducing the impact on the output end.
[0067] The layout IP is based on the P-substrate N-well CMOS process, and the gate length L takes the minimum size of the process, which can reduce both the layout area and the parasitic resistance and capacitance. The drain-connected NMOS and PMOS tubes are adjacent and maintain a certain distance, which can effectively prevent latch-up.
[0068] In one example, the embodiment of the present invention explains the input stage, see Figure 5 A digital logic chip input circuit diagram is shown.
[0069] At the input stage of the CMOS digital logic integrated circuit chip, it has the functions of anti-static and can input a voltage higher than the power supply voltage. The main structure is that a back-to-back MOS tube structure is used at the input stage of the CMOS digital logic integrated circuit chip to act as an anti-static device. This can prevent the traditional anti-static diode from being forward-conducted when the power supply voltage is lower than the input voltage, thereby causing input leakage.
[0070] Furthermore, the input stage includes a resistor R, and the input port of the input stage is connected to the digital logic circuit via the resistor R, thereby preventing static electricity and surge signals from being transmitted to the digital logic circuit. By connecting a resistor R in series between the input and the internal circuit, the embodiment of the present invention can prevent static electricity, surge, and other signals from entering the chip.
[0071] Furthermore, the input stage also includes a third NMOS transistor N3 and a seventh PMOS transistor P7. The gate and drain of the third NMOS transistor N3 are connected and connected to the power supply, the gate and source of the seventh PMOS transistor P7 are connected and connected to the digital logic circuit, and the source of the third NMOS transistor N3 and the drain of the seventh PMOS transistor P7 are connected to form a back-to-back relationship, which is used to provide an anti-static function when receiving an operating voltage within the full voltage range.
[0072] Furthermore, the input stage also includes a fourth NMOS transistor N4, the gate and source of the fourth NMOS transistor N4 are connected and grounded, and the drain of the fourth NMOS transistor N4 is connected to the digital logic circuit; the resistor R and the fourth NMOS transistor N4 form a voltage divider relationship for reducing the signal amplitude of the operating voltage entering the digital logic circuit, especially the reflected signal.
[0073] Furthermore, the input stage also includes a diode D2. The input port of the input stage is connected to ground with diode D2, which is used to allow static electricity and surge signals to break through diode D2, thereby dissipating the voltage. In this embodiment of the present invention, by connecting diode D2 to ground at the input, normal voltage signals can enter the chip normally due to the reverse cutoff function of diode D2. However, static electricity and surge signals to ground will break through diode D2, causing a momentary short circuit to ground, thereby dissipating the voltage and protecting the chip.
[0074] Furthermore, the drain of the third NMOS transistor N3 is connected to the power supply. Regardless of whether the power supply voltage is higher or lower than the input voltage, one of the above MOS transistors is always in the cut-off state, so that the input stage of the CMOS digital logic integrated circuit chip can receive the full voltage range.
[0075] In summary, the digital logic circuit input and output device provided by the embodiment of the present invention can be used at the front end of various digital logic circuits, so that the input and output of the CMOS digital logic integrated circuit chip can receive signals ranging from negative voltage to exceeding the power supply voltage.
[0076] Based on the aforementioned embodiments, an embodiment of the present invention provides a digital logic circuit input / output system, including the aforementioned digital logic circuit input / output device, which provides an anti-static function when receiving an operating voltage within the full voltage range, and provides an anti-leakage function when outputting an output voltage within the full voltage range, thereby enabling the input and output of the digital logic circuit to receive signals ranging from negative voltage to exceeding the power supply voltage, thereby alleviating the problems of high cost, large PCB area, poor reliability, and high failure rate existing in traditional digital logic circuit chips.
[0077] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working process of the digital logic circuit input and output system described above can refer to the corresponding process in the aforementioned embodiment and will not be repeated here.
[0078] In the description of the embodiments of the present invention, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.
[0079] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0080] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.
Claims
1. A digital logic circuit input and output device, characterized in that: include: An input stage, a digital logic circuit, and an output stage electrically connected in sequence; The input stage adopts a back-to-back MOS tube structure; the input stage is used to provide an anti-static function when receiving an operating voltage within a full voltage range, and transmit the operating voltage to the digital logic circuit; The output stage adopts a single-signal control circuit structure, which includes multiple PMOS transistors, multiple NMOS transistors and substrate diodes. The substrates of each PMOS transistor are interconnected and isolated from the power supply by the substrate diode, and the substrate of each NMOS transistor is grounded. The output stage is used to provide leakage protection when receiving an output voltage within the full voltage range output by the digital logic circuit; The upper limit of the full voltage range is higher than the power supply voltage and the lower limit is lower than 0V.
2. The digital logic circuit input / output device according to claim 1, wherein: The output stage includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor and a substrate diode; The substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are connected to each other and isolated from the power supply through the substrate diode; Substrates of the first NMOS transistor and the second NMOS transistor are grounded.
3. The digital logic circuit input / output device according to claim 2, wherein: The source of the first PMOS transistor is connected to the drain of the sixth PMOS transistor to form an output; The gate of the second NMOS transistor is connected to the gate of the third PMOS transistor to form an output.
4. The digital logic circuit input / output device according to claim 3, wherein: The source of the second PMOS transistor and the source of the sixth PMOS transistor are connected to a power supply for providing power to the circuit; The gates of the first PMOS transistor, the first NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are connected to a power supply and are used to control the on and off states of the second PMOS transistor and the sixth PMOS transistor.
5. The digital logic circuit input / output device according to claim 4, wherein: The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor to form an inverter, and is also connected to the gate of the second PMOS transistor; The drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube to form an inverter, and is also connected to the drain of the sixth PMOS tube.
6. The digital logic circuit input / output device according to claim 5, wherein: The gate of the second NMOS transistor is connected to the input port of the output stage, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the drain of the third PMOS transistor and the gate of the sixth PMOS transistor; The drain of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor.
7. The digital logic circuit input / output device according to claim 1, wherein: The input stage includes a resistor, and an input port of the input stage is connected to the digital logic circuit via the resistor, so as to prevent electrostatic signals and surge signals from being transmitted to the digital logic circuit; The input stage also includes a third NMOS transistor and a seventh PMOS transistor. The gate and drain of the third NMOS transistor are connected and connected to the power supply. The gate and source of the seventh PMOS transistor are connected and connected to the digital logic circuit. The source of the third NMOS transistor and the drain of the seventh PMOS transistor are connected to form a back-to-back relationship, which is used to provide anti-static function when receiving an operating voltage within the full voltage range.
8. The digital logic circuit input / output device according to claim 7, wherein: The input stage further includes a fourth NMOS transistor, wherein the gate and source of the fourth NMOS transistor are connected and grounded, and the drain of the fourth NMOS transistor is connected to the digital logic circuit; The resistor and the fourth NMOS transistor form a voltage-dividing relationship, which is used to reduce the signal amplitude of the operating voltage entering the digital logic circuit.
9. The digital logic circuit input / output device according to claim 7, wherein: The input stage further includes a diode, and an input port of the input stage is connected to the ground to allow an electrostatic signal or a surge signal to break through the diode to discharge the voltage.
10. A digital logic circuit input and output system, characterized in that: A digital logic circuit input-output device comprising the digital logic circuit input-output device according to any one of claims 1-9.