Frequency divider

Abstract

The invention provides a frequency divider, which comprises a master latch and a slave latch, and is characterized in that each of the master latch and the slave latch comprises a pseudo-differential clock tube, a sampling differential pair tube, a latch differential pair tube, a dynamic load or clock pair tube and a duty ratio selection tube; when the duty ratio selection tube is in an on state, the drain electrode and the source electrode of the pseudo-differential clock tube are forcibly grounded, the dynamic load or the clock pair tube is used as the clock pair tube, the frequency divider can generate an output signal with the duty ratio of 25%, and when the duty ratio selection tube is in an off state, the frequency divider can generate an output signal with the duty ratio of 25%. The pseudo-differential clock tube in the master latch and the pseudo-differential clock tube in the slave latch form a clock differential geminate transistor, the dynamic load or clock geminate transistor is used as a dynamic load geminate transistor, and the frequency divider can generate an output signal with a 50% duty ratio.

Description

Technical Field

[0001] The present invention generally relates to the field of circuits, and more particularly to a frequency divider. Background Art

[0002] Frequency dividers are widely used in transceivers. Especially when high quality, high linearity, and low noise are key performance requirements, a 25% duty cycle frequency divider is the preferred structure for driving passive mixers in the transceiver's transmit and receive paths. Meanwhile, the transceiver's phase-locked loop (PLL) requires a 50% duty cycle frequency divider. To address this, the current approach of designing the transmit and receive paths and the PLL separately increases design complexity and limits process portability and replicability. Summary of the Invention

[0003] According to an embodiment of the present invention, a frequency divider includes a master latch and a slave latch, wherein: each latch in the master latch and the slave latch includes a pseudo-differential clock tube, a sampling differential pair tube, a latching differential pair tube, a dynamic load or clock pair tube, and a duty cycle selection tube; when the duty cycle selection tube is in the on state, the drain and source of the pseudo-differential clock tube are forced to be grounded, the dynamic load or clock pair tube is used as a clock pair tube, and the frequency divider can generate an output signal with a 25% duty cycle, and when the duty cycle selection tube is in the off state, the pseudo-differential clock tube in the master latch and the pseudo-differential clock tube in the slave latch constitute a clock differential pair tube, the dynamic load or clock pair tube is used as a dynamic load pair tube, and the frequency divider can generate an output signal with a 50% duty cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a schematic diagram showing the circuit topology of a source-coupled logic (SCL) latch used in a frequency divider.

[0006] Figure 2 Schematic diagram showing the circuit topology of a Wang structure frequency divider.

[0007] Figure 3 Schematic diagram showing the circuit topology of a Razavi structure frequency divider.

[0008] Figure 4 FIG. 1 is a schematic diagram showing a circuit topology structure of a frequency divider according to an embodiment of the present invention.

[0009] Figure 5 is a schematic diagram showing a clock bias circuit for providing a bias for an input clock signal and an input clock inverse signal. DETAILED DESCRIPTION

[0010] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of the present invention. In the accompanying drawings and the following description, well-known structures and technologies are not shown in order to avoid unnecessary ambiguity in the present invention. In addition, it should be noted that the term "A is connected to B" used herein can mean "A is directly connected to B" or "A is indirectly connected to B via one or more other elements."

[0011] Figure 1 FIG is a schematic diagram showing the circuit topology of a source coupled logic (SCL) latch used in a frequency divider. Figure 1 As shown, the SCL latch 100 used in the frequency divider includes a clock differential pair consisting of switch transistors M1 and M2, a sampling differential pair consisting of switch transistors M3 and M4, a latch differential pair consisting of switch transistors M5 and M6, a tail current transistor M0, and a resistor load pair consisting of two resistors RL. The gate of the switch transistor M1 is used as the positive clock input terminal of the SCL latch 100, the gate of the switch transistor M2 is used as the negative clock input terminal of the SCL latch 100, the gate of the switch transistor M3 is used as the positive signal input terminal D of the SCL latch 100, and the gate of the switch transistor M4 is used as the negative signal input terminal Dn of the SCL latch 100. The drains of the switch transistors M3 and M6 and the gate of the switch transistor M5 are connected to the negative signal output terminal Qn of the SCL latch 100. The drains of the switch transistors M4 and M5 and the gate of the switch transistor M6 are connected to the positive signal output terminal Q of the SCL latch 100.

[0012] like Figure 1 As shown, the working process of the SCL latch 100 used in the frequency divider includes:

[0013] 1) When the input clock signal CK input to the positive clock input terminal of the SCL latch 100 is at a high level and the input clock inverse signal CKn input to the negative clock input terminal of the SCL latch 100 (i.e., the inverse signal of the input clock signal CK) is at a low level, the switch tube M1 is in the on state and the switch tube M2 is in the off state. The entire tail current Iss flows through the switch tube M1 branch and the sampling differential pair branch. The sampling differential pair works and the latching differential pair does not work. When the input signal input to the positive phase signal input terminal D of the SCL latch 100 is at a high level and the input inverse signal input to the negative phase signal input terminal Dn of the SCL latch 100 (i.e., the inverse signal of the input signal input to the positive phase signal input terminal D) is at a low level, the switch tube M3 is in the on state and the switch tube M4 is in the off state. , the entire tail current Iss flows through the switch tube M3 and the resistor RL, the voltage at the inverting signal output terminal Qn of the SCL latch 100 is VDD-Iss*RL (low level), and the voltage at the positive phase signal output terminal Q of the SCL latch 100 is VDD (high level); when the input signal input to the positive phase signal input terminal D of the SCL latch 100 is low level and the input inverting signal input to the inverting signal input terminal Dn of the SCL latch 100 is high level, the switch tube M3 is in the off state and the switch tube M4 is in the on state, the entire tail current Iss flows through the switch tube M4 and the resistor RL, the voltage at the inverting signal output terminal Qn of the SCL latch 100 is VDD (high level), and the voltage at the positive phase signal output terminal Q of the SCL latch 100 is VDD-Iss*RL (low level).

[0014] 2) When the input clock signal CK input to the positive clock input terminal of the SCL latch 100 is at a low level and the input clock inverse signal CKn input to the negative clock input terminal of the SCL latch 100 is at a high level, the switch tube M1 is in the off state and the switch tube M2 is in the on state. The entire tail current Iss flows through the switch tube M2 branch and the latch differential pair branch. The latch differential pair works and the sampling differential pair does not work. When the voltage at the negative signal output terminal Qn of the SCL latch 100 is VDD (high level) and the voltage at the positive signal output terminal Q of the SCL latch 100 is VDD-Iss*RL (low level), the switch tube M5 is in the on state and the switch tube M6 is in the off state. The entire tail current Iss flows through the switch tube M5, forming a positive feedback system, which promotes the SCL The voltage at the positive phase signal output terminal Q of the latch 100 is maintained at VDD-Iss*RL (low level), and the voltage at the negative phase signal output terminal Qn of the SCL latch 100 is maintained at VDD (high level); when the voltage at the negative phase signal output terminal Qn of the SCL latch 100 is VDD-Iss*RL (low level) and the voltage at the positive phase signal output terminal Q of the SCL latch 100 is VDD (high level), the switch tube M5 is in the off state and the switch tube M6 is in the on state. The entire tail current Iss flows through the switch tube M6, forming a positive feedback system, causing the voltage at the positive phase signal output terminal Q of the SCL latch 100 to be maintained at VDD (high level) and the voltage at the negative phase signal output terminal Qn of the SCL latch 100 to be maintained at VDD-Iss*RL (low level).

[0015] Two SCL latches 100 can be connected end-to-end as a master latch and a slave latch to form a frequency divider, wherein the latching time difference between the two SCL latches 100 is half a cycle of the input clock signal CK. Since the signal output terminal of the master latch is coupled to the signal input terminal of the slave latch, each signal received by the master latch needs to go through two complete clock cycles from the master latch's sampling differential pair transistors → latching differential pair transistors to the slave latch's sampling differential pair transistors → latching differential pair transistors before it can be output. That is, the period of the output signal of the frequency divider is twice the period of the input clock signal, achieving a divide-by-two frequency division.

[0016] like Figure 1 As shown, the SCL latch 100 comprises four stacked components from power to ground: a resistor load pair, a sampling differential pair / latch differential pair, a clock differential pair, and a tail current source. To reduce the stacking layer to better accommodate low power supply voltages and / or achieve high speed and large output swing requirements, the tail current source can be removed to reduce the stacking layer and / or a dynamic load can be used instead of the resistor load to achieve high speed and large swing.

[0017] Figure 2Schematic diagram showing the circuit topology of the Wang structure frequency divider. Figure 2 As shown, the Wang structure frequency divider 200 includes a master latch 202 and a slave latch 204, wherein: the master latch 202 includes a switch tube M10 used as a pseudo differential clock tube, a sampling differential pair tube composed of switch tubes M11 and M12, a latch differential pair tube composed of switch tubes M13 and M14, and a dynamic load pair tube composed of switch tubes M15 and M16; the slave latch 204 includes a switch tube M20 used as a pseudo differential clock tube, a sampling differential pair tube composed of switch tubes M21 and M22, a latch differential pair tube composed of switch tubes M23 and M24, and a dynamic load pair tube composed of switch tubes M25 and M26; the switch tubes M10 and M20 constitute a clock differential pair tube, and the gate of the switch tube M10 serves as the Wang structure frequency divider. The inverting clock input terminal of the master latch 202 and the gate of the switch tube M20 are used as the positive clock input terminal of the Wang structure divider 200; the inverting signal input terminal of the master latch 202 and the positive signal output terminal of the slave latch 204 are connected to the output signal line P1 of the Wang structure divider 200; the positive signal input terminal of the master latch 202 and the inverting signal output terminal of the slave latch 204 are connected to the output signal line P3 of the Wang structure divider 200; the positive signal output terminal of the master latch 202 and the positive signal input terminal of the slave latch 204 are connected to the output signal line P4 of the Wang structure divider 200; the inverting signal output terminal of the master latch 202 and the inverting signal input terminal of the slave latch 204 are connected to the output signal line P2 of the Wang structure divider 200.

[0018] like Figure 2As shown, the working process of the Wang structure frequency divider 200 includes: when the input clock signal CK input to the positive phase clock input terminal of the Wang structure frequency divider 200 and the gate of the dynamic load pair tubes M15 and M16 is high, and the input clock inverse signal CKn input to the negative phase clock input terminal of the Wang structure frequency divider 200 and the gate of the dynamic load pair tubes M25 and M26 is low, the pseudo differential clock tube M20 and the dynamic load pair tubes M25 and M26 are in the on state, the pseudo differential clock tube M10 and the dynamic load pair tubes M15 and M16 are in the off state, the master latch 202 operates in the latch holding mode, and the slave latch 204 operates in the sampling mode; when the input clock signal CK input to the positive phase clock input terminal of the Wang structure frequency divider 200 and the gate of the dynamic load pair tubes M15 and M16 is low, the input clock inverse signal CKn input to the negative phase clock input terminal of the Wang structure frequency divider 200 and the gate of the dynamic load pair tubes M25 and M26 is low, the pseudo differential clock tube M20 and the dynamic load pair tubes M25 and M26 are in the on state, the pseudo differential clock tube M10 and the dynamic load pair tubes M15 and M16 are in the off state, the master latch 202 operates in the latch holding mode, and the slave latch 204 operates in the sampling mode; When the input clock inversion signal CKn of the gates of the load pair transistors M25 and M26 is at a high level, the pseudo-differential clock transistor M20 and the dynamic load pair transistors M25 and M26 are in the off state, the pseudo-differential clock transistor M10 and the dynamic load pair transistors M15 and M16 are in the on state, the master latch 202 operates in the sampling mode, and the slave latch 204 operates in the latch hold mode. The latch time difference between the master latch 202 and the slave latch 204 is half a cycle of the input clock signal. The period of the output signal of the Wang structure frequency divider 200 is twice the period of the input clock signal. Therefore, there is a time difference of 1 / 4 cycle between the output signals of the master latch 202 and the slave latch 204, that is, a phase difference of 90°, thereby achieving orthogonal output signals. The latch differential pair transistors in each latch maintain the output signal of the previous clock cycle unchanged until the next clock cycle arrives, thereby achieving an output signal with a 50% duty cycle.

[0019] like Figure 2As shown, the output signal of the Wang structure frequency divider 200 jumps according to the following pattern: during the first half clock cycle, the master latch 202 operates in the latch hold mode, the slave latch 204 operates in the sampling mode, and the output signals on the output signal lines P1 and P3 are the inverted signals of the output signals on the output signal lines P4 and P2 respectively; during the second half clock cycle, the master latch 202 operates in the sampling mode, the slave latch 204 operates in the latch hold mode, the output signals on the output signal lines P1 and P3 remain unchanged relative to the first half clock cycle, and the output signals on the output signal lines P2 and P4 are inverted relative to the first half clock cycle; during the third half clock cycle, the master latch 202 operates in the sampling mode, the slave latch 204 operates in the latch hold mode, the output signals on the output signal lines P1 and P3 remain unchanged relative to the first half clock cycle, and the output signals on the output signal lines P2 and P4 are inverted relative to the first half clock cycle; The master latch 202 operates in the latch hold mode, the slave latch 204 operates in the sampling mode, the output signals on the output signal lines P2 and P4 remain unchanged relative to the second half clock cycle, and the output signals on the output signal lines P1 and P3 are inverted relative to the second half clock cycle; during the fourth half clock cycle, the master latch 202 operates in the sampling mode, the slave latch 204 operates in the latch hold mode, the output signals on the output signal lines P1 and P3 remain unchanged relative to the third half clock cycle, and the output signals on the output signal lines P2 and P4 are inverted relative to the third half clock cycle; the output signals on the output signal lines P1 to P4 cycle back and forth according to the above pattern to form a periodicity.

[0020] Table 1 shows an example operating timing relationship between the input clock signal, the inverted input clock signal, and each output signal of the Wang structure frequency divider 200, where logic 1 represents a high level and logic 0 represents a low level. As can be seen from Table 1, each output signal of the Wang structure frequency divider 200 has a 50% duty cycle.

[0021] Table 1

[0022]

[0023] In Wang-structure frequency divider 200, the dynamic load transistor pair is controlled by the input clock signal or its inverse, and can be considered to have a clock function. Therefore, the clock differential transistor pair below can be omitted. For more information about Wang-structure frequency dividers, see "A 1.8V 3mW 16.8GHz Frequency Dividers in 0.25um CMOS," presented by Wang Hongmo at the International Solid-State Circuits Conference (ISSCC) 2000.

[0024] Figure 3 Schematic diagram showing the circuit topology of the Razavi structure divider. Figure 3As shown, the Razavi structure frequency divider 300 includes a master latch 302 and a slave latch 304, wherein: the master latch 302 includes a sampling differential pair of switches consisting of switch transistors M11 and M12, a latch differential pair of switches consisting of switch transistors M13 and M14, and a clock differential pair of switches consisting of switch transistors M15 and M16; the slave latch 304 includes a sampling differential pair of switches consisting of switch transistors M21 and M22, a latch differential pair of switches consisting of switch transistors M23 and M24, and a clock differential pair of switches consisting of switch transistors M25 and M26; the gates of the sampling differential pair of transistors M15 and M16 serve as the positive phase clock input terminal of the Razavi structure frequency divider 300, and the gates of the sampling differential pair of transistors M25 and M26 serve as the positive phase clock input terminal of the Razavi structure frequency divider 300. Used as the inverting clock input terminal of the Razavi structure divider 300; the inverting signal input terminal of the master latch 302 and the positive phase signal output terminal of the slave latch 304 are connected to the output signal line P1 of the Razavi structure divider 300; the positive phase signal input terminal of the master latch 302 and the inverting signal output terminal of the slave latch 204 are connected to the output signal line P3 of the Razavi structure divider 300; the positive phase signal output terminal of the master latch 302 and the positive phase signal input terminal of the slave latch 304 are connected to the output signal line P4 of the Razavi structure divider 300; the inverting signal output terminal of the master latch 302 and the inverting signal input terminal of the slave latch 204 are connected to the output signal line P2 of the Razavi structure divider 300.

[0025] like Figure 3 As shown, in the Razavi structure frequency divider 300, when the input clock signal CK input to the gates of the clock differential pair transistors M15 and M16 is at a high level and the input clock inversion signal CKn input to the gates of the clock differential pair transistors M25 and M26 is at a low level, the clock differential pair transistors M15 and M16 are in the off state, the clock differential pair transistors M25 and M26 are in the on state, the master latch 302 operates in the latch hold mode, and the slave latch 304 operates in the sampling mode; when the input clock signal CK input to the gates of the clock differential pair transistors M15 and M16 is at a low level and the input clock inversion signal CKn input to the gates of the clock differential pair transistors M25 and M26 is at a high level, the clock differential pair transistors M15 and M16 are in the on state, the clock differential pair transistors M25 and M26 are in the off state, the master latch 302 operates in the sampling mode, and the slave latch 304 operates in the latch hold mode.

[0026] and Figure 2Unlike the Wang structure frequency divider 200 shown in FIG, at any moment, only one of the signal output lines P1 to P4 of the Razavi structure frequency divider 300 has an output signal at a high level, and the output signals on the other three signal output lines are all at a low level. For example, the output signal of the Razavi structure frequency divider 300 jumps according to the following pattern: during the first half of the clock cycle, the master latch 302 operates in the latch hold mode, the slave latch 304 operates in the sampling mode, the output signals on the output signal lines P1, P2, and P4 are at a low level, and the output signal on the output signal line P3 is at a high level; during the second half of the clock cycle, the master latch 302 operates in the sampling mode, the slave latch 304 operates in the latch hold mode, the output signals on the output signal lines P1 to P3 are at a low level, and the output signal on the output signal line P4 is at a high level; during the third half of the clock cycle, the master latch 302 operates in the sampling mode, the slave latch 304 operates in the latch hold mode, the output signals on the output signal lines P1 to P3 are at a low level, and the output signal on the output signal line P4 is at a high level; During half a clock cycle, the master latch 302 operates in a latch hold mode, the slave latch 304 operates in a sampling mode, the output signal on the output signal line P1 is high, and the output signals on the output signal lines P2 to P4 are low; during the fourth half clock cycle, the master latch 302 operates in a sampling mode, the slave latch 304 operates in a latch hold mode, the output signal on the output signal line P2 is high, and the output signals on the output signal lines P1, P3, and P4 are low; the output signals on the output signal lines P1 to P4 cycle back and forth according to the above pattern, forming a periodicity.

[0027] Table 2 shows an example operating timing relationship between the input clock signal, the inverted input clock signal, and each output signal of the Razavi architecture frequency divider 300, where a logic 1 represents a high level and a logic 0 represents a low level. As can be seen from Table 2, each output signal of the Razavi architecture frequency divider 300 has a 25% duty cycle.

[0028] Table 2 shows the relationship between the sampling input clock and the output of the divider. After four consecutive sampling clocks, the output is repeated to show a 25% duty cycle.

[0029] Table 2

[0030]

[0031] For more information about the Razavi structure divider, please refer to "Design of High-Speed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS" published by Razavi in the IEEE Journal of Solid State Circuits (JSCC) in 1995.

[0032] A 25% duty cycle local oscillator signal is beneficial for driving the passive mixer in a transceiver. It effectively prevents crossover conduction of the switching transistors driving the passive mixer, thereby improving the transceiver's signal gain and reducing signal noise. However, the frequency divider in the phase-locked loop requires a 50% duty cycle local oscillator signal. Therefore, if a circuit can meet both requirements, reusing this circuit can significantly reduce the design difficulty.

[0033] Considering the above situation, a frequency divider according to an embodiment of the present invention is proposed, including a master latch and a slave latch, each latch including a pseudo-differential clock tube, a sampling differential pair tube, a latching differential pair tube, a dynamic load or clock pair tube, and a duty cycle selection tube, wherein: when the duty cycle selection tube is in the on state, the drain and source of the pseudo-differential clock tube are forced to be grounded, the dynamic load or clock pair tube is used as a clock pair tube, and the frequency divider can generate an output signal with a 25% duty cycle, and when the duty cycle selection tube is in the off state, the pseudo-differential clock tube in the master latch and the pseudo-differential clock tube in the slave latch constitute a clock differential pair tube, the dynamic load or clock pair tube is used as a dynamic load pair tube, and the frequency divider can generate an output signal with a 50% duty cycle.

[0034] Figure 4 Schematic diagram showing the circuit topology of a frequency divider according to an embodiment of the present invention. Figure 4As shown, the frequency divider 400 includes a master latch 402 and a slave latch 404, wherein: the master latch 402 includes a switch tube M10 used as a pseudo differential clock tube, a sampling differential pair tube composed of switch tubes M11 and M12, a latch differential pair tube composed of switch tubes M13 and M14, a dynamic load or clock pair tube composed of switch tubes M15 and M16, and a switch tube M17 used as a duty cycle selection tube; the slave latch 404 includes a switch tube M20 used as a pseudo differential clock tube, a sampling differential pair tube composed of switch tubes M21 and M22, a latch differential pair tube composed of switch tubes M23 and M24, a dynamic load or clock pair tube composed of switch tubes M25 and M26, and a switch tube M27 used as a duty cycle selection tube; the switch tubes M10 and M20 constitute a clock differential pair tube, and the gate of the switch tube M10 and The gates of the dynamic load or clock pair tubes M25 and M26 are used as the inverting clock input terminals of the frequency divider 400, and the gates of the switch tube M20 and the gates of the dynamic load or clock pair tubes M15 and M26 are used as the positive clock input terminals of the frequency divider 400; the inverting signal input terminal of the master latch 402 and the positive signal output terminal of the slave latch 404 are connected to the output signal line P1 of the frequency divider 400; the positive signal input terminal of the master latch 402 and the inverting signal output terminal of the slave latch 404 are connected to the output signal line P3 of the frequency divider 400; the positive signal output terminal of the master latch 402 and the positive signal input terminal of the slave latch 404 are connected to the output signal line P4 of the frequency divider 400; the inverting signal output terminal of the master latch 402 and the inverting signal input terminal of the slave latch 404 are connected to the output signal line P2 of the frequency divider 400.

[0035] It can be seen that in each of the master latch 402 and the slave latch 404, three components are stacked from the power supply VDD to the ground: a dynamic load / clock pair, a sampling differential pair / latch differential pair, and a clock differential pair / duty cycle selection transistor. That is, in each of the master latch 402 and the slave latch 404, the dynamic load or clock pair is connected between the power supply VDD and the sampling differential pair, and the pseudo-differential clock transistor and duty cycle selection transistor are connected in parallel between the sampling differential pair and the ground.

[0036] like Figure 4 As shown, the dynamic load or clock pair tube of the master latch 402 and the pseudo differential clock tube of the slave latch 404 switch between the on state and the off state under the control of the input clock signal CK, and the pseudo differential clock tube of the master latch 402 and the dynamic load or clock pair tube of the slave latch 404 switch between the on state and the off state under the control of the input clock inversion signal CKn, and the input clock inversion signal CKn is the inversion signal of the input clock signal CK.

[0037] like Figure 4As shown, when the duty cycle selection signal SEL input to the gate of the duty cycle selection tubes M17 and M27 is at a high level (i.e., SEL=1), the source and drain of the clock differential pair tubes M10 and M20 are forced to be grounded and therefore do not work. The switch tubes M15 and M16 constitute the clock pair tubes in the master latch 402, and the switch tubes M26 and M27 constitute the clock pair tubes in the slave latch 404. The frequency divider 400 becomes Figure 3 The Razavi structure frequency divider 300 shown is a divide-by-two frequency divider with an output signal having a duty cycle of 25%. When the duty cycle selection signal SEL input to the gates of the duty cycle selection transistors M17 and M27 is at a low level (i.e., SEL=0), the clock differential pair of transistors M10 and M20 are active, the switch transistors M15 and M16 form a dynamic load pair of transistors in the master latch 402, and the switch transistors M26 and M27 form a dynamic load pair of transistors in the slave latch 404. The frequency divider 400 becomes Figure 2 The illustrated Wang-structure frequency divider 300 is a divide-by-two frequency divider whose output signal has a 50% duty cycle.

[0038] Figure 5 1 is a schematic diagram showing a clock bias circuit for providing a bias for an input clock signal and an input clock inverse signal. Figure 5 As shown, clock bias circuit 500 can use a DC blocking capacitor to AC couple a high-frequency sinusoidal signal from a voltage-controlled oscillator and a predetermined resistor to DC couple a bias voltage from a resistor divider string, thereby providing a bias for the input clock signal and the input clock inverse signal for frequency divider 400. It should be noted that clock bias circuit 500 can be included in frequency divider 400 as part of frequency divider 400.

[0039] like Figure 5 As shown, in some embodiments, the clock bias circuit 500 includes a first bias transistor M1 with a gate and drain short-circuited, a resistor divider string, a second bias transistor M2 with a gate and drain short-circuited, and a duty cycle selection transistor Msel, wherein the first bias transistor M1 is connected between the power supply VDD of the divider 400 and the resistor divider string, and the second bias transistor M2 and the duty cycle selection transistor Msel are connected in parallel between the resistor divider string and ground.

[0040] like Figure 5As shown, in some embodiments, the first bias transistor M1 is a switch transistor of the same type as the dynamic load or clock pair transistor in the divider 400 (for example, a P-type metal oxide semiconductor transistor, i.e., a PMOS transistor), and the second bias transistor M2 is a switch transistor of the same type as the clock differential pair transistors M10 and M20 in the divider 400 (for example, an N-type metal oxide field effect transistor, i.e., an NMOS transistor), and the sizes of the first bias transistor M1 and the second bias transistor M2 are mirrored to the sizes of the dynamic load or clock pair transistor and the clock differential pair transistor in the divider 400 to synchronize the changes in the conduction threshold voltages of these switch transistors, so that when the divider circuit experiences changes in process voltage and temperature, their operating states are consistent with the changes in the conduction threshold voltage. Specifically, when the duty cycle selection signal SEL=1 input to the gate of the duty cycle selection tube Msel, the source and drain of the second bias tube M2 are short-circuited, and the bias voltage Vbias from the resistor divider string is at a level proportional to the temperature to adapt the divider 400 to the 25% duty cycle mode of the Razavi structure divider 300; when the duty cycle selection signal SEL=0, the second bias tube M2 is connected in series between the resistor divider string and the ground, and the bias voltage Vbias from the resistor divider string is at a level inversely proportional to the temperature to adapt the divider 400 to the 50% duty cycle mode of the Wang structure divider 200.

[0041] like Figure 5 As shown, in some embodiments, the clock bias circuit 500 further includes a decoder and a group of multiple switch tubes Msw, wherein these switch tubes are turned on or off under the control of the decoder, and the resistor divider string can output different bias voltages Vbias as these switch tubes are turned on or off to adapt to input clock signals with a wide range of frequencies, thereby reducing the power consumption of the divider 400.

[0042] The present invention may be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the present invention. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive, and the scope of the present invention is defined by the appended claims rather than the foregoing description. All modifications that come within the meaning and scope of the claims and equivalents are intended to be included within the scope of the present invention.

Claims

1. A frequency divider comprising a master latch and a slave latch, wherein: Each latch in the master latch and the slave latch includes a pseudo differential clock tube, a sampling differential pair tube, a latch differential pair tube, a dynamic load or clock pair tube, and a duty cycle selection tube. When the duty cycle selection tube is in the on state, the drain and source of the pseudo differential clock tube are forced to be grounded, the dynamic load or clock pair tube is used as a clock pair tube, and the frequency divider can generate an output signal with a 25% duty cycle, and When the duty cycle selection tube is in the off state, the pseudo differential clock tube in the master latch and the pseudo differential clock tube in the slave latch constitute a clock differential pair tube, the dynamic load or clock pair tube is used as a dynamic load pair tube, and the divider can generate an output signal with a 50% duty cycle.

2. The frequency divider according to claim 1, wherein When the duty cycle selection tube is in the on state, the frequency divider becomes a Razavi structure frequency divider.

3. The frequency divider according to claim 1, wherein When the duty cycle selection tube is in the off state, the frequency divider becomes a king structure frequency divider.

4. The frequency divider according to claim 1, wherein In each of the master latch and the slave latch, the dynamic load or clock pair is connected between the power supply of the frequency divider and the sampling differential pair, and the pseudo differential clock and duty cycle selection tubes are connected in parallel between the sampling differential pair and ground.

5. The frequency divider according to claim 1, wherein The dynamic load or clock pair tube of the master latch and the pseudo differential clock tube of the slave latch switch between the on state and the off state under the control of the input clock signal, and the pseudo differential clock tube of the master latch and the dynamic load or clock pair tube of the slave latch switch between the on state and the off state under the control of the input clock inversion signal, and the input clock inversion signal is the inversion signal of the input clock signal. The frequency divider according to claim 1 , wherein: In each of the master latch and the slave latch, when the duty cycle selection tube is in the off state: When the pseudo differential clock tube is in the on state, the dynamic load pair tube is in the on state, and When the pseudo differential clock signal is in an off state, the dynamic load pair is in an off state.

7. The frequency divider according to claim 6, wherein: When the pseudo differential clock tube and the dynamic load pair of the master latch are in the on state and the pseudo differential clock tube and the dynamic load pair of the slave latch are in the off state, the master latch operates in the sampling mode and the slave latch operates in the latch holding mode, and When the pseudo differential clock tube and the dynamic load pair tube of the master latch are in the off state and the pseudo differential clock tube and the dynamic load pair tube of the slave latch are in the on state, the master latch operates in the latch holding mode and the slave latch operates in the sampling mode.

8. The frequency divider according to claim 1, wherein When the duty cycle selection tube is in the on state: When the clock differential pair of the master latch is in the off state and the clock differential pair of the slave latch is in the on state, the master latch operates in the latch holding mode and the slave latch operates in the sampling mode, and When the clock differential pair transistors of the master latch are in the on state and the clock differential pair transistors of the slave latch are in the off state, the master latch operates in a sampling mode and the slave latch operates in a latch holding mode.

9. The frequency divider according to claim 7 or 8, further comprising: The clock signal bias circuit is configured to use a DC blocking capacitor to AC couple a high-frequency sinusoidal signal from a voltage-controlled oscillator and use a predetermined resistor to DC couple a bias voltage from a resistor divider string to provide a bias for the input clock signal and the input clock inverse signal.

10. The frequency divider according to claim 9, wherein The clock bias circuit includes a first bias tube with a gate-drain short-circuited connection, the resistor divider string, a second bias tube with a gate-drain short-circuited connection, and another duty cycle selection tube. The first bias tube is connected between the power supply of the frequency divider and the resistor divider string, and the second bias tube and the other duty cycle selection tube are connected in parallel between the resistor divider string and ground.

11. The frequency divider according to claim 10, wherein The first bias tube is a switch tube of the same type as the dynamic load or clock pair tube, the second bias tube is a switch tube of the same type as the clock differential pair tube, and the sizes of the first bias tube and the second bias tube are mirrored to the sizes of the dynamic load or clock pair tube and the clock differential pair tube.

12. The frequency divider according to claim 10, wherein The clock bias circuit further includes a decoder and a plurality of switches. The plurality of switches are turned on or off under the control of the decoder, and the bias voltage from the resistor divider string changes with the turning on or off of the plurality of switches.

Images