Linearity calibration and precision expansion method and system for numerical control phase interpolator DPI of high-speed serial interface

Abstract

The invention relates to a high-speed serial interface circuit, and discloses a linearity calibration and precision expansion method of a numerical control phase interpolator. According to the method, a digital delay converter (DDC) is cascaded behind a digital control phase interpolator (DPI), and delay compensation is carried out on an interpolated clock signal; sampling the compensated clock signal by using an analog-to-digital converter (ADC) to obtain a phase sampling value; the calibration control module calculates a phase error and generates a delay control word; when the numerical control phase interpolator DPI works, phase control words and delay control words are synchronously provided for corresponding modules, and linearity calibration and precision expansion are achieved. According to the method, a special detection circuit does not need to be added, hardware resources existing in a high-speed serial interface are utilized, the method can be achieved through simple digital control logic, the phase integral linearity is improved to be within 25 fs from 250 fs, meanwhile, the precision of an 8-bit phase interpolator is improved to be close to the 11-bit level, and the method is suitable for large-scale popularization and application. And the clock recovery performance and the data transmission reliability of the high-speed communication system are obviously improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a phase control technology for high-speed signal processing. Background Art

[0002] In high-speed serial interface chips, the Digital Phase Interpolator (DPI) is a core component of the clock and data recovery circuitry. It is typically used at the receiver end to interpolate orthogonal clock signals to generate clock signals with specific phases for data sampling and synchronization. The performance parameters of the DPI, particularly its phase integral linearity and phase differential linearity, directly determine the clock quality of the entire serial interface chip, and thus directly affect the bit error rate of the entire system.

[0003] As serial interface chip protocol rates continue to increase, so too do the requirements for the linearity and accuracy of digitally controlled phase interpolators. Currently, high-speed serial interfaces typically operate at frequencies exceeding 10s or even tens of GHz, requiring phase interpolators to achieve accuracy and integral linearity on the order of 100 fs or even less. This makes high-digital digitally controlled interpolators and their linearity calibration particularly important.

[0004] However, current high-bit phase interpolators are primarily implemented by increasing the number of bits in the current control code. This approach becomes difficult to expand beyond 8-bit control code due to area and current accuracy limitations. This makes digitally controlled phase interpolators a technical bottleneck in high-precision, high-speed serial interface circuits.

[0005] In addition, most existing phase linearity calibration methods only calibrate the four-phase orthogonal input signals of the digitally controlled phase interpolator. This method cannot calibrate the linearity of the digitally controlled phase interpolator more accurately.

[0006] Therefore, key technical challenges currently facing the field of high-speed serial interfaces include improving the accuracy of digitally controlled phase interpolators, expanding the number of control bits, and achieving high-precision calibration of their output linearity. Existing technologies have yet to provide a reasonable and effective solution, and a new approach is urgently needed to overcome these limitations. Summary of the Invention

[0007] The purpose of this application is to provide a method and system for linearity calibration and accuracy expansion of a digitally controlled phase interpolator (DPI) for a high-speed serial interface, so as to solve the problems raised in the above-mentioned background technology.

[0008] The present application discloses a method for linearity calibration and precision extension of a digitally controlled phase interpolator (DPI) for a high-speed serial interface, comprising the following steps:

[0009] According to the input phase control word, the orthogonal clock signal is interpolated by the digitally controlled phase interpolator DPI to generate clock signals of multiple target phases; wherein the phase control word corresponds to different target phases;

[0010] A digital delay converter DDC is cascade-connected to the digitally controlled phase interpolator DPI, the clock signals of the multiple target phases are received through the digital delay converter DDC, and delay compensation is performed on the clock signal according to the input delay control word to obtain a clock signal with expanded precision;

[0011] The precision-extended clock signal is sampled using an analog-to-digital converter (ADC) and converted into a digital signal to obtain a phase sampling value corresponding to each target phase; wherein the phase sampling value reflects the actual phase information of the target phase;

[0012] The calibration control module receives the phase sampling value, calculates the deviation between the phase sampling value and the ideal phase value, and generates the delay control word for compensating for the nonlinear error of the digitally controlled phase interpolator DPI;

[0013] During the normal operation of the digitally controlled phase interpolator DPI, the calibration control module selects the corresponding delay control word based on the currently input phase control word, and synchronously provides the phase control word and the delay control word to the digitally controlled phase interpolator DPI and the digital delay converter DDC. By performing delay compensation on the interpolated clock signal, the linearity calibration and accuracy expansion of the digitally controlled phase interpolator DPI are achieved.

[0014] In a preferred example, the digital delay converter DDC uses a buffer plus a variable capacitor to achieve delay compensation for the clock signal, and accurately controls the signal edge delay by adjusting the size of the variable capacitor. The delay compensation accuracy can reach 25fs.

[0015] In a preferred example, the analog-to-digital converter ADC implements the function of a time-to-digital converter by sampling a ramp signal, and is used to sense the phase difference of the digitally controlled phase interpolator DPI.

[0016] In a preferred example, the target phases used for calibration include 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees; during calibration, the phase control word is first adjusted to 0 degrees, and the output of the analog-to-digital converter ADC is recorded. Then, the phase is adjusted to 45 degrees, and the output value of the analog-to-digital converter ADC is used to calibrate the delay control word, and the same operation is performed on the remaining phases.

[0017] In a preferred example, the delay control words of different phases are recorded and a lookup table is established. When the digitally controlled phase interpolator DPI is working, the calibration control module searches for the corresponding delay control word according to the phase control word, and synchronously sends these two parts of the control word to the digitally controlled phase interpolator DPI and the digital delay converter DDC.

[0018] In a preferred example, the input control bit range of the digitally controlled phase interpolator DPI is 7-9 bits; the accuracy compensation range of the digital delay converter DDC is 2ps; and the sampling accuracy of the analog-to-digital converter ADC is not less than 12-bit.

[0019] In a preferred example, the calibration control module uses a least square method to generate the delay control word through iterative calculation to minimize the phase error.

[0020] In a preferred embodiment, the digitally controlled phase interpolator DPI implements phase interpolation by the following formula:

[0021] (α0-a180)*sinθ+(a90-a270)*cosθ=sin (θ+φ) Formula 1

[0022] φ=arctan((a90-a270) / (a0-a180)), a0, a90, a180, a270≥0 Formula 2

[0023] Among them, a0, a90, a180, and a270 represent the control codes of two orthogonal clock signals respectively, and sinθ and cosθ represent two orthogonal clock signals.

[0024] In a preferred example, the accuracy of the digital delay converter DDC is 25fs, the digitally controlled phase interpolator DPI is 8 bits, the phase accuracy is 244fs, and the overall phase accuracy after calibration can reach ±0.1LSB.

[0025] The present application also discloses a linearity calibration and precision extension system for a digitally controlled phase interpolator (DPI) for a high-speed serial interface, comprising:

[0026] A digitally controlled phase interpolator DPI, configured to interpolate the quadrature clock signal according to an input phase control word to generate clock signals of multiple target phases; wherein the phase control word corresponds to different target phases;

[0027] A digital delay converter DDC is cascade-connected to the digitally controlled phase interpolator DPI, and is used to receive the clock signals of the multiple target phases and perform delay compensation on the clock signals according to the input delay control word to obtain a clock signal with expanded accuracy;

[0028] An analog-to-digital converter (ADC) is used to sample the precision-extended clock signal and convert it into a digital signal to obtain a phase sampling value corresponding to each target phase; wherein the phase sampling value reflects the actual phase information of the target phase;

[0029] A calibration control module is used to receive the phase sampling value, calculate the deviation between it and the ideal phase value, and generate the delay control word to compensate for the nonlinear error of the digitally controlled phase interpolator DPI; during the normal operation of the digitally controlled phase interpolator DPI, the corresponding delay control word is selected according to the currently input phase control word, and the phase control word and the delay control word are synchronously provided to the digitally controlled phase interpolator DPI and the digital delay converter DDC, and the linearity calibration and accuracy extension of the digitally controlled phase interpolator DPI are achieved by delay compensation of the interpolated clock signal.

[0030] This application provides a method and system for linearity calibration and precision extension of a digitally controlled phase interpolator (DPI) for a high-speed serial interface, which has the following beneficial effects:

[0031] By cascading the digital delay converter DDC after the digitally controlled phase interpolator DPI, the phase interpolation accuracy is expanded. Figure 4 As shown in the figure, taking the 8-bit phase interpolator DPI and the 3-bit digital delay converter DDC as examples, the phase accuracy can be theoretically increased from 8 bits to 11 bits, greatly reducing the design difficulty and cost of the high-precision phase interpolator.

[0032] The analog-to-digital converter (ADC) is used to sample the clock signal output by the digital delay converter (DDC) to obtain accurate phase information, providing a reliable data basis for linearity calibration. Figure 6 As shown, by measuring the offset of different phase points (such as 0 degrees, 45 degrees, etc.), the accurate characterization of the DPI nonlinear error of the digitally controlled phase interpolator is achieved.

[0033] The calibration control module is introduced to realize the adaptive linearity calibration of the digital controlled phase interpolator DPI through a closed-loop feedback mechanism. Figure 5 As shown, the calibration control module calculates the optimal delay control word based on the sampling results of the analog-to-digital converter ADC and feeds it back to the digital delay converter DDC to dynamically compensate for the nonlinear error of the phase interpolation, so that the actual output phase is closer to the ideal value.

[0034] By storing the delay control words corresponding to different phases in a lookup table, real-time synchronous control of phase interpolation and delay compensation is achieved. Figure 5As shown in the figure, during the operation of the digitally controlled phase interpolator DPI, the calibration control module selects the corresponding delay control word from the lookup table according to the current phase control word, so that the linearity calibration and phase adjustment are carried out synchronously to ensure the continuity and stability of the dynamic calibration.

[0035] The linearity calibration and precision expansion method of the present application significantly improves the performance index of the digital controlled phase interpolator DPI. Figure 7 As shown, the calibrated phase points (blue circles) are closer to the ideal straight line, and the integral nonlinearity (INL) and differential nonlinearity (DNL) are significantly improved. Taking an 8-bit digitally controlled phase interpolator (DPI) operating at 16 GHz as an example, the phase accuracy before calibration is approximately 244 fs, and the INL is approximately 1 LSB (250 fs). After calibration, the phase accuracy is within 25 fs, significantly outperforming existing solutions.

[0036] This application leverages the precise delay control capabilities of digital delay converters (DDCs) and the high-speed sampling characteristics of analog-to-digital converters (ADCs) to construct a complete linearity calibration system. This system can be widely applied to the design and optimization of high-speed serial interface chips. The system's simple structure and high degree of modularity make it easy to integrate into existing high-speed serial transceiver architectures, significantly improving the system's data transmission reliability and robustness.

[0037] The digital delay converter DDC of the present application adopts a circuit structure of buffer plus variable capacitor, such as Figure 8 As shown in Figure 1, precise delay control of 25 fs is achieved by adjusting the variable capacitor. This circuit structure is easy to layout, has low power consumption, and good process compatibility, making it particularly suitable for high-speed, low-power, and small-area integrated circuit design scenarios.

[0038] The implementation scheme of the present application is simple and easy to implement. It reuses the existing analog-to-digital converter ADC and its calibration circuit. It only requires adding a digital logic circuit for phase error calibration to the chip. It has low power consumption and cost, improves the utilization efficiency of hardware resources, and lowers the technical threshold for realizing a high-precision phase interpolator.

[0039] To sum up, the digitally controlled phase interpolator linearity calibration and precision expansion technology provided in this application has significant advantages and innovations in terms of phase accuracy, linearity indicators, architectural performance, cost-effectiveness, etc., and can well meet the increasing demand for high-speed data transmission, and has broad application prospects.

[0040] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be considered as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 1 is a flow chart of a method for linearity calibration and accuracy extension of a digitally controlled phase interpolator for a high-speed serial interface according to an embodiment of the present application;

[0042] Figure 2 1 is a circuit implementation diagram of a digitally controlled phase interpolator DPI for a high-speed serial interface according to a method for linearity calibration and precision extension of a digitally controlled phase interpolator in an embodiment of the present application;

[0043] Figure 3 This is a block diagram of a clock recovery circuit for a method for linearity calibration and accuracy extension of a digitally controlled phase interpolator for a high-speed serial interface according to an embodiment of the present application, which illustrates the application of a digitally controlled phase interpolator (DPI) in a clock recovery circuit.

[0044] Figure 4 This is a block diagram of a precision-scalable digitally controlled phase interpolator DPI according to a method for linearity calibration and precision extension of a digitally controlled phase interpolator for a high-speed serial interface according to an embodiment of the present application, which shows a cascaded architecture of the digitally controlled phase interpolator DPI and a digital delay converter DDC;

[0045] Figure 5 This is a linearity calibration block diagram of a digitally controlled phase interpolator (DPI) for a high-speed serial interface according to a linearity calibration and precision extension method of a digitally controlled phase interpolator in an embodiment of the present application, which shows a calibration system structure based on an analog-to-digital converter (ADC);

[0046] Figure 6This is a schematic diagram of analog-to-digital converter (ADC) sampling for a linearity calibration and accuracy extension method of a digitally controlled phase interpolator for a high-speed serial interface according to an embodiment of the present application, which illustrates the process of sampling multiple target phases;

[0047] Figure 7 is a linearity calibration diagram of a linearity calibration and accuracy extension method for a digitally controlled phase interpolator for a high-speed serial interface according to an embodiment of the present application, which shows a comparison between an ideal phase point and phase points before and after calibration;

[0048] Figure 8 This is a circuit implementation diagram of a digital delay converter DDC for a linearity calibration and accuracy extension method of a digitally controlled phase interpolator for a high-speed serial interface according to an embodiment of the present application, which shows a delay adjustment structure based on a buffer and a variable capacitor. DETAILED DESCRIPTION

[0049] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0050] Description of some concepts:

[0051] Digitally controlled phase interpolator (DPI): A circuit that can generate a clock signal with any phase using a digital control word. It is often used to implement clock recovery in high-speed serial interfaces.

[0052] Digital Delay Converter (DDC): A circuit that can precisely control the delay of a signal. In this application, a buffer plus a variable capacitor is used to achieve delay compensation for the clock signal.

[0053] Analog-to-Digital Converter (ADC): A device that converts analog signals into digital signals. In this application, it is used to sample the clock signal and convert it into a digital signal.

[0054] Phase control word: A digital instruction used to control the digitally controlled phase interpolator to output a specific phase clock signal.

[0055] Delay control word: A digital instruction used to control the digital delay converter to delay the signal to a specific time.

[0056] Phase sampling value: A digital value representing the actual phase obtained by sampling the clock signal through an analog-to-digital converter.

[0057] Calibration control module: a functional module responsible for receiving phase sampling values, calculating the deviation from the ideal phase, and generating delay control words.

[0058] Linearity calibration: The process of correcting the nonlinear error of the digitally controlled phase interpolator through delay compensation to achieve a better linear relationship between the output phase and the control word.

[0059] Precision expansion: A technical means to improve the overall phase resolution of the digitally controlled phase interpolator through fine adjustment of the digital delay converter.

[0060] Look-Up Table (LUT): A data structure that stores the delay control words corresponding to different phase control words, used for fast query and application of calibration parameters.

[0061] The following is a summary of some of the innovative features of this application:

[0062] In general, under the challenge of the continuous increase in the rate of high-speed serial interface protocols, this application has creatively constructed a multi-dimensional complementary compensation mechanism by deeply understanding the inherent accuracy bottleneck and nonlinear characteristics of the digitally controlled phase interpolator DPI, which cleverly achieves the coordinated optimization of the analog front-end and the digital back-end. Specifically, this application adopts a heterogeneous cascade architecture of the digitally controlled phase interpolator DPI and the digital delay converter DDC (such as Figure 4 As shown in Figure 2), it not only avoids the design dilemma of traditional 8-bit or above phase interpolators due to the physical limit of current accuracy, but also uses a buffer plus variable capacitor fine-tuning circuit (as shown in Figure 2). Figure 8 More importantly, the present application innovatively reuses the analog-to-digital converter (ADC) as a time-to-digital converter for phase domain sampling (as shown in Figure 6 As shown), combined with the calibration control module to build a "sampling-calculation-compensation-verification" closed-loop feedback system (as shown Figure 5As shown), the phase control word and the delay control word can be dynamically matched and adjusted synchronously in real time in a multi-dimensional parameter space. Through this complex and sophisticated synergistic mechanism, this application reduces the integral nonlinearity INL of the digitally controlled phase interpolator DPI from the traditional 1LSB (250fs) to within 0.1LSB without significantly increasing the hardware resource overhead, and improves the phase accuracy from 244fs to 25fs, achieving a double breakthrough in accuracy and linearity. This multi-level, multi-dimensional technology integration and collaborative optimization solution has overturned the traditional technical route of simply relying on increasing the number of control bits or calibrating the orthogonal input signal, and provides a new technical approach for the accuracy expansion and linearity calibration of digitally controlled phase interpolators DPI in high-speed serial interfaces.

[0063] The working principle of this application revolves around the linearity calibration and precision expansion of the digitally controlled phase interpolator DPI in the high-speed serial interface. The digitally controlled phase interpolator DPI is usually used in the clock and data recovery circuit of the receiving end of the high-speed serial interface chip, such as Figure 3 As shown, it receives the data stream, detects the clock frequency offset information through the phase detector and the filter, and converts the information into a digital control code for controlling the digitally controlled phase interpolator DPI.

[0064] The basic principle of the digital phase interpolator DPI can be expressed by the following formula:

[0065]

[0066] Among them, a0, a90, a180, and a270 represent the control codes of two orthogonal clock signals, such as Figure 2 As shown in Figure 1, these control codes interpolate the two quadrature clock signals, sinθ and cosθ, using differential transistor circuits. By adjusting the control code values, various phases between 0° and 360° can be generated. In practical circuit design, the precision of the control codes is limited, typically using N-bit digital control codes, which limits the minimum accuracy of the phase interpolator.

[0067] The precision expansion solution proposed in this application is as follows: Figure 4 As shown in Figure 1, further improvement in phase accuracy is achieved by cascading a digital delay converter (DDC) after a traditional digitally controlled phase interpolator (DPI). Taking an 8-bit phase interpolator and a 3-bit digital delay converter as an example, theoretically, up to 11-bit accuracy can be achieved, and the 256 phases generated by the 8-bit phase interpolator can be calibrated with 3-bit accuracy.

[0068] The implementation of the digital delay converter DDC is as follows Figure 8As shown, a buffer plus variable capacitor approach is used. By adjusting the size of the variable capacitor, precise control of signal edge delay is achieved, achieving an accuracy of less than 25 fs. This digital delay converter (DDC) fine-tunes the clock signal output by the digitally controlled phase interpolator (DPI), thereby compensating for the nonlinearity of the phase interpolator.

[0069] The linearity calibration process is as follows Figure 5 As shown, the phase calibration first adjusts the phase control word to a specific phase (such as 0 degrees), records the output of the analog-to-digital converter ADC, and then adjusts it to the next phase (such as 45 degrees). The output value of the analog-to-digital converter ADC is used to calibrate the delay control word. Figure 6 The sampling principle of analog-to-digital converter (ADC) is demonstrated. It realizes the function of time-to-digital converter by sampling the ramp signal, which is used to accurately measure the phase difference.

[0070] After calibration is completed, Figure 7 As shown in the figure, the actual phase point (blue circle) is closer to the ideal straight line, significantly improving linearity. When the digitally controlled phase interpolator (DPI) is operating normally, the calibration control module selects the corresponding delay control word from the lookup table based on the current phase control word and synchronously provides these two control words to the digitally controlled phase interpolator (DPI) and the digital delay converter (DDC), achieving dynamic linearity calibration and accuracy expansion.

[0071] For an 8-bit CNC phase interpolator (DPI) operating at 16GHz, the original phase accuracy is approximately 244fs, and the integral nonlinearity is approximately 1LSB (250fs). The calibration method of this application can improve the phase accuracy to within 25fs, significantly outperforming existing technical solutions. This greatly reduces the design difficulty of high-precision CNC phase interpolators and improves the data transmission reliability of high-speed serial interfaces.

[0072] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0073] The first embodiment of the present application relates to a method for linearity calibration and precision extension of a digitally controlled phase interpolator DPI for a high-speed serial interface, the process of which is as follows: Figure 1 As shown, the method includes the following steps:

[0074] Step 100 generates an initial multi-phase clock signal:

[0075] According to the input phase control word, the orthogonal clock signal is interpolated by the digitally controlled phase interpolator DPI to generate clock signals of multiple target phases; wherein the phase control word corresponds to different target phases.

[0076] Step 200 performs precision expansion:

[0077] The digital delay converter DDC is cascade-connected to the digitally controlled phase interpolator DPI, the clock signals of the multiple target phases are received through the digital delay converter DDC, and the clock signal is delay-compensated according to the input delay control word to obtain a clock signal with expanded accuracy.

[0078] Step 300 collects phase information:

[0079] The precision-expanded clock signal is sampled using an analog-to-digital converter (ADC) and converted into a digital signal to obtain a phase sampling value corresponding to each target phase; wherein the phase sampling value reflects the actual phase information of the target phase.

[0080] Step 400 calculates calibration parameters:

[0081] The phase sampling value is received by a calibration control module, the deviation between the phase sampling value and the ideal phase value is calculated, and the delay control word is generated to compensate for the nonlinear error of the digitally controlled phase interpolator DPI.

[0082] Step 500 performs linearity calibration:

[0083] During the normal operation of the digitally controlled phase interpolator DPI, the calibration control module selects the corresponding delay control word based on the currently input phase control word, and synchronously provides the phase control word and the delay control word to the digitally controlled phase interpolator DPI and the digital delay converter DDC. By performing delay compensation on the interpolated clock signal, the linearity calibration and accuracy expansion of the digitally controlled phase interpolator DPI are achieved.

[0084] Furthermore, this method utilizes a cascaded architecture of a digitally controlled phase interpolator (DPI) and a digital delay converter (DDC), combined with the sampling function of the analog-to-digital converter (ADC). Through a calibration control module, a closed-loop feedback system is constructed to achieve linearity calibration and precision expansion of the DPI. The DPI generates initial multi-phase clock signals, which are fine-tuned by the digital delay converter (DDC). The ADC measures the adjusted phase information, and the calibration control module calculates compensation parameters based on the sampling results. This ultimately achieves dynamic linearity calibration, effectively addressing the limitations of phase interpolation accuracy and linearity in high-speed serial interfaces.

[0085] Optionally, in step 200, the digital delay converter DDC uses a buffer plus a variable capacitor to achieve delay compensation for the clock signal, and by adjusting the size of the variable capacitor to achieve precise control of the signal edge delay, the delay compensation accuracy can reach 25fs. (See Figure 8)

[0086] More specifically, the digital delay converter (DDC) uses a multi-stage buffer series structure, with a variable capacitor connected to ground under each buffer stage. The variable capacitor's capacitance is digitally controlled to adjust its value. As the capacitance increases, the buffer's output drive load increases, resulting in an increase in signal edge delay; as the capacitance decreases, the delay decreases accordingly. By precisely controlling the capacitance, a delay accuracy of the order of 25 fs can be achieved, which is significantly less than the minimum phase step of the digitally controlled phase interpolator (DPI) itself (typically hundreds of fs). The advantages of this structure are simple implementation, fast response, and good linearity, making it particularly suitable for fine-tuning the output of the digitally controlled phase interpolator (DPI). Because the digital delay converter (DDC) only needs to cover the delay range of a 1-bit phase interpolator (approximately several hundred fs), its design difficulty is much lower than that of a high-bit phase interpolator.

[0087] Optionally, in step 300, the analog-to-digital converter ADC implements the function of a time-to-digital converter by sampling a ramp signal, so as to sense the phase difference of the digitally controlled phase interpolator DPI.

[0088] (See Figure 6 )

[0089] More specifically, the analog-to-digital converter (ADC) is reused as a time-to-digital converter in this application, and its working principle is to use the time relationship between the clock phase and the data edge for sampling. Figure 6 As shown, the horizontal direction represents different clock phases (0 degrees to 315 degrees), and the vertical direction represents the level of the ramp data signal. When the data signal is in a ramp form, sampling it with clocks of different phases will produce different digital values (such as D0 and D45). The difference in the sampled values between adjacent phase points directly reflects the actual phase difference. By comparing these sampled values with the ideal phase difference, the nonlinear error of the digitally controlled phase interpolator (DPI) can be accurately measured. This method fully utilizes the existing analog-to-digital converter (ADC) resources in the high-speed serial interface, eliminating the need for additional dedicated measurement circuitry, simplifying the design and reducing costs.

[0090] Optionally, in step 300 and step 400, the target phases used for calibration include 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees; during calibration, the phase control word is first adjusted to 0 degrees, and the output of the analog-to-digital converter ADC is recorded. Then, the phase is adjusted to 45 degrees, and the output value of the analog-to-digital converter ADC is used to calibrate the delay control word, and the same operation is performed on the remaining phases.

[0091] (See Figure 6 )

[0092] More specifically, the calibration process is performed in a predetermined sequence of phase points, which are evenly distributed between 0 and 360 degrees, forming an 8-phase calibration scheme. The calibration first establishes a benchmark at the 0-degree phase point, recording the output value D0 of the analog-to-digital converter (ADC) as a reference; the calibration is then sequentially adjusted to phase points such as 45 and 90 degrees, and the corresponding ADC output values (such as D45) are recorded. For each phase point, the corresponding delay control word is calculated based on the deviation of its ADC output value from the ideal value. Compared to the traditional method of calibrating only 4-phase orthogonal inputs, this 8-phase calibration scheme provides more comprehensive phase space coverage and can more accurately characterize and compensate for the nonlinear errors of the digitally controlled phase interpolator (DPI) at different phase points. By calibrating these key phase points, the compensation parameters for all phase points can be derived, achieving linearity calibration for the entire phase space.

[0093] Optionally, in steps 400 and 500, the delay control words of different phases are recorded and a lookup table is established. When the digitally controlled phase interpolator DPI is working, the calibration control module searches for the corresponding delay control word according to the phase control word, and synchronously sends these two control words to the digitally controlled phase interpolator DPI and the digital delay converter DDC. (See Figure 5 )

[0094] More specifically, after the calibration is completed, the optimal delay control words corresponding to all phase points are stored in the lookup table, forming a mapping relationship of "phase control word → delay control word". When the digitally controlled phase interpolator DPI is working normally, when a specific phase control word is input (such as when a 45-degree phase output is required), the calibration control module reads the corresponding delay control word (such as a45) from the lookup table, and then synchronously provides the phase control word and the delay control word to the digitally controlled phase interpolator DPI and the digital delay converter DDC. This synchronous control mechanism ensures that the delay compensation can follow in real time during the phase adjustment process, maintaining the continuity and stability of the calibration effect. The advantages of the lookup table method are fast response speed, simple implementation, and the ability to provide customized compensation parameters for each phase point to optimize the calibration effect.

[0095] Optionally, in step 100 and step 200, the input control bit range of the digitally controlled phase interpolator DPI is 7-9 bits; the accuracy compensation range of the digital delay converter DDC is 2ps; and the sampling accuracy of the analog-to-digital converter ADC is not less than 12-bit.

[0096] More specifically, the number of control bits of the digitally controlled phase interpolator (DPI) determines its basic resolution. A phase resolution of 7-9 bits corresponds to a range of approximately several hundred fs to 1 ps, which is suitable for the requirements of current mainstream high-speed serial interfaces. The 2 ps compensation range of the digital delay converter (DDC) ensures that it can cover multiples of a minimum step of the digitally controlled phase interpolator (DPI) (e.g., approximately 244 fs for an 8-bit interpolator), providing sufficient adjustment margin for linearity calibration. The 12-bit or higher sampling accuracy of the analog-to-digital converter (ADC) ensures high-precision measurement of phase deviation, capable of resolving phase differences of tens of fs. The combination of these three key parameters constitutes the system's fundamental performance indicators, ensuring that the calibration system has sufficient accuracy, range, and resolution to meet the stringent clock phase accuracy requirements of high-speed serial interfaces (e.g., 16 GHz and above).

[0097] Optionally, in step 400, the calibration control module uses a least square method to generate the delay control word through iterative calculation to minimize the phase error.

[0098] More specifically, the calibration control module uses the least squares method to calculate the optimal delay control word, with the goal of minimizing the mean square error between the actual phase measured by the analog-to-digital converter (ADC) and the ideal phase. Specifically, during the calibration process, the phase error is first measured based on the initial delay control word, then the delay control word is adjusted, and the error is measured again and compared. If the error decreases, adjustment continues in that direction; otherwise, the adjustment direction is changed. Through multiple iterations, the delay control word that minimizes the error is eventually found. The least squares method takes into account the overall error distribution and, compared to simple point-to-point calibration, can obtain a smoother calibration curve, reduce oscillations and instability during the calibration process, and improve the reliability and consistency of the calibration results.

[0099] Optionally, in step 100, the digitally controlled phase interpolator DPI implements phase interpolation using the following formula:

[0100]

[0101] Where a0, a90, a180, and a270 represent the control codes of the two quadrature clock signals, and sinθ and cosθ represent the two quadrature clock signals. (Corresponding to Formula 1 and Formula 2)

[0102] More specifically, the basic working principle of the digitally controlled phase interpolator DPI is to perform weighted summation on two orthogonal clock signals. Figure 2As shown, the four control terminals a0, a90, a180, and a270 control the weights of the corresponding phase clock signals, respectively. By adjusting the values of these control codes, different proportions of the two orthogonal clock signals, sinθ and cosθ, can be combined to produce the desired output phase. According to Equations 1 and 2, when a0, a90, a180, and a270 satisfy specific relationships, the phase of the output signal is θ + φ, where φ is the phase offset determined by the control codes. In practical applications, these control codes typically use N-bit digital control, resulting in a minimum phase accuracy of 360° / (2^(N+2)) for the digitally controlled phase interpolator (DPI). For example, for an 8-bit control code, the theoretical phase accuracy is approximately 0.35°, corresponding to a time accuracy of 244 fs at a 16 GHz clock. This method based on interpolation of orthogonal signals is the mathematical foundation for achieving precise phase control in the digitally controlled phase interpolator (DPI).

[0103] Optionally, in step 200 and step 500, the accuracy of the digital delay converter DDC is 25fs, the digitally controlled phase interpolator DPI is 8 bits, the phase accuracy is 244fs, and the overall phase accuracy after calibration can reach ±0.1LSB.

[0104] More specifically, the 25fs accuracy compensation capability provided by the digital delay converter (DDC) complements the 244fs base accuracy of the 8-bit DPI digital phase interpolator (DPI). By combining the two, the system can achieve higher phase resolution than using the DPI alone. Specifically, the DDC's 25fs accuracy is approximately 1 / 10 the DPI's minimum step size. This means the original 244fs phase step can be subdivided into 10 smaller adjustment units, significantly improving the fineness of phase adjustment. After calibration, the overall phase accuracy reaches ±0.1LSB, meaning the phase error is controlled within a ±24.4fs range, a performance far superior to that of traditional DPIs. In high-speed serial interface applications, this improved accuracy directly translates into lower clock jitter, higher sampling accuracy, and lower system bit error rates, which is particularly important for high-speed interfaces operating at tens or even hundreds of GHz.

[0105] In order to make the technical solution of the present invention clearer, Figures 2 to 8 The preferred embodiments of the present invention are described in detail, but it should be understood that the described embodiments are only illustrative and not restrictive.

[0106] Figure 2This is a schematic diagram of the circuit implementation of the digitally controlled phase interpolator DPI in an embodiment of the present application, which shows a differential circuit structure including a VDD power supply, a resistor R, and a transistor. The circuit includes four groups of differential transistor units, and the control end of each group of units is connected to the four control signal input terminals a0, a90, a180, and a270 respectively. These control signal inputs correspond to the control digital codes, which enable the circuit to realize the interpolation function of the orthogonal clock signal. The common-mode output of the differential circuit realizes the weighted summation of the orthogonal clock signal through the differential current of the transistor, thereby generating the required phase output.

[0107] Figure 3 This is a block diagram of the clock recovery circuit in an embodiment of the present application, clearly illustrating the operating principle of clock recovery in a high-speed serial interface. The data signal is first input to a phase detector, which detects the clock frequency offset information contained in the data and converts it into a control signal. This control signal is processed by a filter and outputs a digital control code. This digital control code is then transmitted to a digitally controlled phase interpolator (DPI) for phase adjustment. The DPI also receives an orthogonal local clock signal as a reference input, adjusts the clock phase according to the control code, and ultimately outputs a phase-adjusted clock signal, forming a complete closed-loop clock recovery system.

[0108] Figure 4 This is a schematic diagram of a digitally controlled phase interpolator system with scalable precision in an embodiment of the present application, which illustrates the core technical solution of the present application. The figure shows a cascade structure consisting of a digitally controlled phase interpolator DPI with an 8-bit control bit and a digital delay converter DDC with a 3-bit control bit. The orthogonal local clock signal is first input to the digitally controlled phase interpolator DPI, and the clock signal after 8-bit phase interpolation is then connected to the digital delay converter DDC. The digital delay converter DDC implements finer delay adjustment based on the 3-bit control bit, ultimately achieving higher precision than a single 8-bit phase interpolator, theoretically up to 11-bit precision.

[0109] Figure 5 This is a block diagram of the linearity calibration of the digitally controlled phase interpolator (DPI) in an embodiment of the present application, showing the complete calibration system structure. The dashed box on the left shows a high-precision, calibrated analog circuit consisting of a digitally controlled phase interpolator (DPI) with a phase control word input and a digital delay converter (DDC). The right side shows the analog-to-digital converter (ADC) and digital logic unit. The ADC samples the delay-compensated signal, and the digital logic unit calculates calibration parameters based on the sampling results and feeds back the delay control word to the digital delay converter (DDC), achieving linearity calibration through closed-loop feedback.

[0110] Figure 6This is a schematic diagram of the analog-to-digital converter ADC sampling in the embodiment of the present application. The figure specifically shows the signal sampling principle during the calibration process. The upper part shows the clock phase scale (from 0 degrees to 315 degrees), the lower part shows the data sampling points (such as D0 and D45), and the offset measurement interval is also marked in the figure. This figure shows how to use the analog-to-digital converter ADC to sample different phase points (such as 0 degrees, 45 degrees, 90 degrees, etc.), and to achieve linearity calibration of the digitally controlled phase interpolator DPI by measuring the offset between adjacent phase points.

[0111] Figure 7 This is a schematic diagram of linearity calibration in an embodiment of the present application. In a coordinate system with the phase control word on the horizontal axis and the output phase on the vertical axis, this diagram clearly shows the correspondence between the ideal phase points (black circles) and the calibrated phase points (blue circles). The phase points before calibration deviate from the ideal straight line, while the calibrated phase points are closer to the ideal straight line, intuitively demonstrating the effectiveness of the present calibration method.

[0112] Figure 8 This is a schematic diagram of the circuit implementation of the digital delay converter (DDC) in this embodiment. It uses a three-stage buffer structure in series, with variable capacitors connected to ground below each buffer stage. By adjusting the size of the variable capacitors, precise control of signal edge delay can be achieved, achieving delay adjustment accuracy of 25 fs, thus meeting the requirements of high-precision phase calibration.

[0113] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0114] In high-speed serial port systems, the receiver clock is recovered by data and clock recovery circuits. Figure 3 As shown in Figure 1, a commonly used clock recovery circuit includes a phase detector, a filter, and a digitally controlled phase interpolator (DPI). This circuit uses the phase detector and filter to convert the clock frequency offset information contained in the data into a digital control code, which is used to control the DPI. Therefore, the accuracy of the DPI completely determines the accuracy of the recovered clock. The linearity of the DPI becomes particularly important when there is a large deviation between the data clock frequency and the local clock frequency. For high-precision, high-speed serial port circuits, not only does the DPI need to be highly accurate, but its output linearity also needs to be calibrated.

[0115] This example proposes a new method to improve the accuracy of the digital phase interpolator DPI, such as Figure 4As shown. This method achieves the precision expansion of the traditional digitally controlled phase interpolator DPI by connecting a digital delay converter DDC in series behind the traditional digitally controlled phase interpolator DPI. Taking the 8-bit phase interpolator DPI and the 3-bit digital delay converter DDC as an example, an 8-bit digitally controlled phase interpolator DPI connected in series with a 3-bit digital delay converter DDC can achieve a precision greater than that of an 8-bit phase interpolator, theoretically up to 11 bits. Using the precision-scalable phase interpolator system proposed in this example, it is possible to calibrate the 2^8=256 phases generated by the 8-bit phase interpolator DPI with 3-bit precision.

[0116] The calibration method of the digital phase interpolator DPI is as follows Figure 5 As shown, the analog-to-digital converter ADC here can be regarded as a time-to-digital converter, which can accurately reflect the phase information. Taking the calibration of 8 phases (0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees) as an example, the phase calibration process first adjusts the phase control word to 0 degrees, records the output of the analog-to-digital converter ADC, and then adjusts the phase to 45 degrees. The output value of the analog-to-digital converter ADC is used to calibrate the delay control word, and the same operation is performed for the remaining phases. After the calibration is completed, when the digitally controlled phase interpolator DPI is working normally, the delay control word calibration results of each phase need to be synchronously provided to the digitally controlled phase interpolator DPI and the digital delay converter DDC together with the phase control word, thereby realizing the phase calibration and accuracy extension of the digitally controlled phase interpolator DPI.

[0117] The digital delay converter DDC in this example mainly adopts Figure 8 The buffer plus variable capacitor approach shown in the figure features high precision, rapid stability, and good linearity. The digital delay converter (DDC) precisely controls signal edge delay by adjusting the size of the variable capacitor, achieving accuracy below 25 fs. Because the DDC is used to calibrate the phase of the digitally controlled phase interpolator (DPI), its control word must be synchronized with that of the DPI. This requires that the DDC's settling time cannot exceed that of the DPI, otherwise additional nonlinear errors will be introduced.

[0118] In this example, the accuracy of the digital delay converter (DDC) determines the ultimate accuracy of the phase calibration of the entire digitally controlled phase interpolator (DPI). For example, if the DDC's accuracy is 25 fs, the phase accuracy of an 8-bit DPI operating at 16 GHz is 244 fs. Theoretically, the final calibrated phase accuracy can reach ±25 fs / 244 fs = 0.1 LSB.

[0119] This example uses foreground calibration to calibrate the linearity of the digitally controlled phase interpolator (DPI). Currently, the linearity of the DPI, especially its integral linearity, significantly limits the accuracy of system clock recovery under large frequency offsets, thereby affecting the system's bit error rate (BER). In current high-speed SERDES designs, the DPI's linearity limitations have become a significant drawback in system design. Therefore, DPI phase calibration is crucial for improving system performance.

[0120] In this example, the input control bit range of the digitally controlled phase interpolator (DPI) is 7 to 9 bits, the accuracy of the digital delay converter (DDC) is 25 fs, the compensation range is 2 ps, and the sampling accuracy of the analog-to-digital converter (ADC) is at least 12 bits. The calibration control module uses the least squares method to calculate the error, gradually reducing the error and ultimately achieving stable calibration.

[0121] In this example, the control word for the digital delay converter (DDC) varies for different phases. For example, the control word for 0 degrees is a0, and the control word for 45 degrees is a45. These control words are recorded in a lookup table after calibration. When the DPI is operating, it uses the DPI control word (e.g., 0->a0 / 45->a45) to look up the corresponding control word for the digital delay converter (DDC). These two control words are then synchronously sent to the DPI and the digital delay converter (DDC), thus achieving phase compensation for the DPI.

[0122] The analog-to-digital converter ADC in this example is an analog-to-digital converter in the multiplexed SERDES, which can sample a ramp signal to implement the function of a time-to-digital converter, such as Figure 6 The present application utilizes this time-to-digital converter to sense the phase difference of the digitally controlled phase interpolator (DPI), and ultimately achieves phase calibration.

[0123] The integral linearity of the existing 8-bit digitally controlled phase interpolator DPI at the current 16 GHz operating frequency is approximately 1 LSB, or 250 fs. The calibration method in this example can improve the phase accuracy to less than 25 fs, which is significantly better than the existing technical solutions.

[0124] Through the above technical solution, the DPI linearity calibration and accuracy expansion method of the digitally controlled phase interpolator provided in this example can effectively solve the problems of phase interpolation accuracy and linearity in high-speed serial interfaces, improve the clock recovery accuracy of the system, reduce the bit error rate, and provide more reliable technical support for high-speed data communications.

[0125] The second embodiment of the present application relates to a linearity calibration and precision extension system for a digitally controlled phase interpolator DPI for a high-speed serial interface, the structure of which is shown in FIG. Figure 2 , Figure 4 , Figure 5 and Figure 6 The linearity calibration and accuracy extension system for the digitally controlled phase interpolator (DPI) for high-speed serial interfaces includes:

[0126] A digitally controlled phase interpolator DPI, configured to interpolate the quadrature clock signal according to an input phase control word to generate clock signals of multiple target phases; wherein the phase control word corresponds to different target phases;

[0127] A digital delay converter DDC is cascade-connected to the digitally controlled phase interpolator DPI, and is used to receive the clock signals of the multiple target phases and perform delay compensation on the clock signals according to the input delay control word to obtain a clock signal with expanded accuracy;

[0128] An analog-to-digital converter (ADC) is used to sample the precision-extended clock signal and convert it into a digital signal to obtain a phase sampling value corresponding to each target phase; wherein the phase sampling value reflects the actual phase information of the target phase;

[0129] A calibration control module is used to receive the phase sampling value, calculate the deviation between it and the ideal phase value, and generate the delay control word to compensate for the nonlinear error of the digitally controlled phase interpolator DPI; during the normal operation of the digitally controlled phase interpolator DPI, the corresponding delay control word is selected according to the currently input phase control word, and the phase control word and the delay control word are synchronously provided to the digitally controlled phase interpolator DPI and the digital delay converter DDC, and the linearity calibration and accuracy extension of the digitally controlled phase interpolator DPI are achieved by delay compensation of the interpolated clock signal.

[0130] This system architecture achieves functional separation and collaborative operation through modular design. The digitally controlled phase interpolator (DPI) is responsible for basic phase generation, the digital delay converter (DDC) is responsible for fine adjustment, the analog-to-digital converter (ADC) is responsible for error detection, and the calibration control module is responsible for parameter calculation and control logic. Each module has clear interfaces and works together to form a complete calibration closed loop, ensuring stable and efficient system operation in complex operating environments.

[0131] Application scenarios of the embodiment:

[0132] The linearity calibration and accuracy expansion method and system of the present application are particularly suitable for clock recovery circuits in high-speed serial interfaces. In high-speed data communication systems, the receiving end needs to recover an accurate clock signal from the transmitted data to correctly sample the data. When there is a deviation between the data clock frequency and the local clock frequency, the linearity of the phase interpolator becomes particularly important. The traditional 8-bit digitally controlled phase interpolator DPI is prone to phase discontinuity or jumps under large frequency offset conditions, resulting in sampling errors and increased system bit error rate. The present application effectively solves this problem by improving phase accuracy and linearity, so that the system can maintain stable clock recovery performance within a wider frequency offset range.

[0133] Furthermore, as serial interface rates increase, the eye diagram margin of transmitted signals decreases, requiring a higher-precision sampling clock. The technical solution of this application improves phase accuracy to the order of 25 fs, providing the necessary clock accuracy for high-speed interfaces exceeding 10 Gbps, meeting the needs of next-generation high-speed serial communication systems.

[0134] In summary, the digitally controlled phase interpolator DPI linearity calibration and precision expansion method and system provided in this application realizes high-precision dynamic calibration of the phase interpolation process by innovatively combining the digital delay converter DDC, the analog-to-digital converter ADC and the calibration control module, solves the key technical bottlenecks of phase interpolation accuracy and linearity in high-speed serial interfaces, and provides important support for high-performance communication systems.

[0135] The first embodiment is a method embodiment corresponding to the present embodiment. The technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.

[0136] The above embodiments have the following technical effects:

[0137] By cascading the digital delay converter DDC after the digitally controlled phase interpolator DPI, the phase interpolation accuracy is expanded. Figure 4 As shown in the figure, taking the 8-bit phase interpolator DPI and the 3-bit digital delay converter DDC as examples, the phase accuracy can be theoretically increased from 8 bits to 11 bits, greatly reducing the design difficulty and cost of the high-precision phase interpolator.

[0138] The analog-to-digital converter (ADC) is used to sample the clock signal output by the digital delay converter (DDC) to obtain accurate phase information, providing a reliable data basis for linearity calibration. Figure 6 As shown, by measuring the offset of different phase points (such as 0 degrees, 45 degrees, etc.), the accurate characterization of the DPI nonlinear error of the digitally controlled phase interpolator is achieved.

[0139] The calibration control module is introduced to realize the adaptive linearity calibration of the digital controlled phase interpolator DPI through a closed-loop feedback mechanism. Figure 5 As shown, the calibration control module calculates the optimal delay control word based on the sampling results of the analog-to-digital converter ADC and feeds it back to the digital delay converter DDC to dynamically compensate for the nonlinear error of the phase interpolation, so that the actual output phase is closer to the ideal value.

[0140] By storing the delay control words corresponding to different phases in a lookup table, real-time synchronous control of phase interpolation and delay compensation is achieved. Figure 5 As shown in the figure, during the operation of the digitally controlled phase interpolator DPI, the calibration control module selects the corresponding delay control word from the lookup table according to the current phase control word, so that the linearity calibration and phase adjustment are carried out synchronously to ensure the continuity and stability of the dynamic calibration.

[0141] The linearity calibration and precision expansion method of the above embodiment significantly improves the performance index of the digital controlled phase interpolator DPI. Figure 7 As shown, the calibrated phase points (blue circles) are closer to the ideal straight line, and the integral nonlinearity (INL) and differential nonlinearity (DNL) are significantly improved. Taking an 8-bit digitally controlled phase interpolator (DPI) operating at 16 GHz as an example, the phase accuracy before calibration is approximately 244 fs, and the INL is approximately 1 LSB (250 fs). After calibration, the phase accuracy is within 25 fs, significantly outperforming existing solutions.

[0142] The above-described embodiment leverages the precise delay control capabilities of the digital delay converter (DDC) and the high-speed sampling characteristics of the analog-to-digital converter (ADC) to construct a complete linearity calibration system. This system can be widely applied to the design and optimization of high-speed serial interface chips. With its simple structure and high degree of modularity, this system is easily integrated into existing high-speed serial transceiver architectures, significantly improving the system's data transmission reliability and robustness.

[0143] The digital delay converter DDC in the above embodiment adopts a circuit structure of a buffer plus a variable capacitor, such as Figure 8 As shown in Figure 1, precise delay control of 25 fs is achieved by adjusting the variable capacitor. This circuit structure is easy to layout, has low power consumption, and good process compatibility, making it particularly suitable for high-speed, low-power, and small-area integrated circuit design scenarios.

[0144] The implementation scheme of the above embodiment is simple and easy to implement. It reuses the existing analog-to-digital converter ADC and its calibration circuit. It only needs to add a digital logic circuit for phase error calibration in the chip. It has low power consumption and cost, improves the utilization efficiency of hardware resources, and lowers the technical threshold for realizing a high-precision phase interpolator.

[0145] To sum up, the digitally controlled phase interpolator linearity calibration and precision expansion technology provided in the above embodiments has significant advantages and innovations in terms of phase accuracy, linearity indicators, architectural performance, cost-effectiveness, etc., and can well meet the increasing demand for high-speed data transmission, and has broad application prospects.

[0146] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0147] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A method for linearity calibration and precision extension of a digitally controlled phase interpolator (DPI) for a high-speed serial interface, characterized in that: The steps include: According to the input phase control word, the orthogonal clock signal is interpolated by the digitally controlled phase interpolator DPI to generate clock signals of multiple target phases; wherein the phase control word corresponds to different target phases; A digital delay converter DDC is cascade-connected to the digitally controlled phase interpolator DPI, the clock signals of the multiple target phases are received through the digital delay converter DDC, and delay compensation is performed on the clock signal according to the input delay control word to obtain a clock signal with expanded precision; The precision-extended clock signal is sampled using an analog-to-digital converter (ADC) and converted into a digital signal to obtain a phase sampling value corresponding to each target phase; wherein the phase sampling value reflects the actual phase information of the target phase; The calibration control module receives the phase sampling value, calculates the deviation between the phase sampling value and the ideal phase value, and generates the delay control word for compensating for the nonlinear error of the digitally controlled phase interpolator DPI; During the normal operation of the digitally controlled phase interpolator DPI, the calibration control module selects the corresponding delay control word according to the currently input phase control word, and synchronously provides the phase control word and the delay control word to the digitally controlled phase interpolator DPI and the digital delay converter DDC.

2. The method according to claim 1, wherein The digital delay converter DDC uses a buffer plus a variable capacitor to perform delay compensation on the clock signal.

3. The method according to claim 1, wherein The analog-to-digital converter ADC realizes time-to-digital conversion by sampling a ramp signal.

4. The method according to claim 1, wherein The target phases used for calibration include 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees. During calibration, the phase control word is first adjusted to 0 degrees, and the output of the analog-to-digital converter ADC is recorded. Then, the phase is adjusted to 45 degrees, and the output value of the analog-to-digital converter ADC is used to calibrate the delay control word. The same operation is performed for the remaining phases.

5. The method according to claim 1, wherein The delay control words of different phases are recorded and a lookup table is established. When the digitally controlled phase interpolator DPI is working, the calibration control module searches for the corresponding delay control word according to the phase control word, and synchronously sends these two parts of the control word to the digitally controlled phase interpolator DPI and the digital delay converter DDC.

6. The method according to claim 1, wherein The input control bit range of the digitally controlled phase interpolator DPI is 7-9 bits; the accuracy compensation range of the digital delay converter DDC is 2ps; and the sampling accuracy of the analog-to-digital converter ADC is not less than 12 bits.

7. The method according to claim 1, wherein The calibration control module generates the delay control word through iterative calculation using the least square method.

8. The method according to claim 1, wherein The digitally controlled phase interpolator DPI implements phase interpolation using the following formula: Among them, a0, a90, a180, and a270 represent the control digital codes of two orthogonal clock signals respectively, and sinθ and cosθ represent two orthogonal clock signals.

9. The method according to claim 1, wherein The delay step of the digital delay converter DDC is 25fs, the digitally controlled phase interpolator DPI is 8 bits, and the phase step is 244fs.

10. A linearity calibration and precision extension system for a digitally controlled phase interpolator (DPI) for a high-speed serial interface, characterized in that: include: A digitally controlled phase interpolator DPI, configured to interpolate the quadrature clock signal according to an input phase control word to generate clock signals of multiple target phases; wherein the phase control word corresponds to different target phases; A digital delay converter DDC is cascade-connected to the digitally controlled phase interpolator DPI, and is used to receive the clock signals of the multiple target phases and perform delay compensation on the clock signals according to the input delay control word to obtain a clock signal with expanded accuracy; An analog-to-digital converter (ADC) is used to sample the precision-extended clock signal and convert it into a digital signal to obtain a phase sampling value corresponding to each target phase; wherein the phase sampling value reflects the actual phase information of the target phase; A calibration control module is used to receive the phase sampling value, calculate the deviation between the phase sampling value and the ideal phase value, and generate the delay control word to compensate for the nonlinear error of the digitally controlled phase interpolator DPI; during the normal operation of the digitally controlled phase interpolator DPI, the corresponding delay control word is selected according to the currently input phase control word, and the phase control word and the delay control word are synchronously provided to the digitally controlled phase interpolator DPI and the digital delay converter DDC.

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