Memory and forming method thereof

Abstract

A memory includes a substrate and a capacitor structure over the substrate. The capacitor structure includes: a lower electrode; the capacitor dielectric is positioned above the lower electrode and is provided with a first dielectric and a second dielectric positioned above the first dielectric, the first dielectric is made of hafnium oxide, and the second dielectric is made of zirconium oxide; and an upper electrode over the second dielectric substance. The memory made of the high-k material can realize higher capacitance.

Description

Technical Field

[0001] The present invention relates to a memory and a method for forming the same. Background Art

[0002] The present invention relates to a memory device and a method for manufacturing the same. As DRAM capacitors shrink, significant effort is being invested in finding new material stacks to overcome the current material scaling limitations. Because capacitance is limited by the shrinking size of the capacitor, dielectrics with higher k values are required to achieve reasonable capacitance. A newly discovered modal phase boundary (MPB) between the ferroelectric orthorhombic and tetragonal phases in HfO2-ZrO2 is proposed for use in high-capacitance dielectric capacitors. Unlike other high-k dielectrics, whose k values decrease with decreasing film thickness, the k values of these films increase with decreasing film thickness. Summary of the Invention

[0003] One aspect of the present invention provides a memory device comprising a substrate and a capacitor structure overlying the substrate. The capacitor structure comprises: a lower electrode; a capacitor dielectric overlying the lower electrode and comprising a first dielectric and a second dielectric overlying the first dielectric, wherein the first dielectric is composed of hafnium oxide and the second dielectric is composed of zirconium oxide; and an upper electrode overlying the second dielectric.

[0004] In some embodiments, the second dielectric is doped with aluminum.

[0005] In some embodiments, the second dielectric has an aluminum concentration of about 1% to about 8%.

[0006] In some embodiments, the first dielectric does not contain aluminum.

[0007] In some embodiments, the first dielectric has a first thickness, and the second dielectric has a second thickness different from the first thickness.

[0008] In some embodiments, the first thickness is less than the second thickness.

[0009] In some embodiments, the first dielectric has a first thickness of about 0.5 nm to about 2.0 nm, and the second dielectric has a second thickness of about 3.0 nm to about 7.0 nm.

[0010] In some embodiments, the capacitor dielectric has a crystal structure having a tetragonal phase and an orthorhombic phase.

[0011] In some embodiments, the capacitor dielectric has a ratio of tetragonal phase to orthorhombic phase of about 0.1 to about 0.3.

[0012] In some embodiments, the memory further includes: a word line structure located above the substrate; and a bit line structure located above the substrate and electrically connected to a doped region of the substrate located on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.

[0013] One aspect of the present invention provides a method for forming a memory device, comprising: forming a capacitor structure located above a substrate, comprising: depositing a bottom electrode; depositing a first dielectric located above the bottom electrode, wherein the first dielectric is composed of hafnium oxide; depositing a second dielectric located above the first dielectric, wherein the second dielectric is composed of zirconium oxide; and depositing a top electrode located above the second dielectric.

[0014] In some embodiments, the second dielectric is doped with aluminum.

[0015] In some embodiments, the second dielectric has an aluminum concentration of about 1% to about 8%.

[0016] In some embodiments, the first dielectric does not contain aluminum.

[0017] In some embodiments, the first dielectric has a first thickness, and the second dielectric has a second thickness different from the first thickness.

[0018] In some embodiments, the first thickness is less than the second thickness.

[0019] In some embodiments, the method further includes performing an annealing process after depositing the second dielectric, so that a combination of the first dielectric and the second dielectric has a crystal structure having a tetragonal phase and an orthorhombic phase.

[0020] In some embodiments, the temperature of the annealing process is between about 400°C and about 500°C.

[0021] In some embodiments, the ratio of the tetragonal phase to the orthorhombic phase is from about 0.1 to about 0.3.

[0022] In some embodiments, the method further includes: forming a word line structure located above the substrate; and forming a bit line structure located above the substrate and electrically connected to a doped region of the substrate located on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.

[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 is a schematic diagram illustrating a capacitor structure according to some embodiments of the present invention.

[0026] Figure 2 is a circuit diagram of a memory cell of a memory according to some embodiments of the present invention.

[0027] Figure 3 is a cross-sectional view of a memory according to some embodiments of the present invention.

[0028] Figure 4-12 are cross-sectional views of various stages in forming a memory according to some embodiments of the present invention. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same drawing reference numerals are used in the drawings and the description to refer to the same or like components.

[0030] As used herein, "approximately," "about," or "substantially" may generally mean within 20%, within 10%, or within 5% of a given value or range. The values given herein are approximate, and if not explicitly stated, the terms "approximately," "about," or "substantially" may be inferred. However, those skilled in the art will recognize that the values or ranges listed throughout the description are merely examples and may be reduced or changed as integrated circuits shrink.

[0031] Figure 1 FIG is a schematic diagram showing a capacitor structure according to some embodiments of the present invention. Figure 1 As shown, the capacitor structure 10 includes a bottom electrode 100, a capacitor dielectric 110 above the bottom electrode 100, and a top electrode 120 above the capacitor dielectric 110. The capacitor dielectric 110 includes a first dielectric 112 and a second dielectric 114 above the first dielectric 112. In some embodiments, the bottom electrode 100 and the top electrode 120 can be formed of, for example, TiN, Ti, W, WN, Pt, Ir, Ru, and other conductive materials.

[0032] In some embodiments, the first dielectric 112 and the second dielectric 114 can be made of different high-k dielectric materials. For example, the first dielectric 112 can include hafnium oxide (HfO2). On the other hand, the second dielectric 114 can include zirconium oxide (ZrO2). In some embodiments, the second dielectric 114 (e.g., ZrO2) can be doped with aluminum (Al) at a concentration between about 1% and about 8% to suppress leakage current. In some embodiments, the first dielectric 112 can be free of aluminum. That is, the aluminum concentration in the first dielectric 112 can be lower than the aluminum concentration in the second dielectric 114.

[0033] First dielectric 112 has a thickness T1, and second dielectric 114 has a thickness T2. In some embodiments, thickness T1 is different from thickness T2. In some embodiments, thickness T2 is greater than thickness T1. In some embodiments, thickness T1 is in a range of approximately 0.5 nm to approximately 2.0 nm, and thickness T2 is in a range of approximately 3.0 nm to approximately 7.0 nm. In some embodiments, the ratio of thickness T1 to thickness T2 can be in a range of approximately 1.5 to approximately 14.

[0034] Based on the above structure, the capacitor dielectric 110 including the first dielectric 112 and the second dielectric 114 may include a crystal structure having a tetragonal phase and an orthorhombic phase. In some embodiments, the ratio of the tetragonal phase to the orthorhombic phase of the capacitor dielectric 110 can be measured by a technique such as X-ray diffractometry (XRD) and is in a range of about 0.1 to about 0.3 (e.g., 0.2).

[0035] The following will describe in more detail the manufacturing method for producing the capacitor structure 10. Figure 1 As shown, in some embodiments, the bottom electrode 100, the first dielectric 112, the second dielectric 114 and the top electrode 120 can be deposited in sequence by, for example, chemical vapor deposition (CVD), PECVD, low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD) or other suitable deposition processes.

[0036] In some embodiments where the second dielectric 114 is made of zirconium oxide (ZrO2), a CVD process can be used to form the second dielectric 114. In the CVD process, a zirconium source (e.g., ZrCl4), an oxygen source (e.g., oxygen), and a carrier gas (e.g., argon or nitrogen) are supplied to a CVD chamber. The chamber of the CVD process is controlled to reach a sufficient temperature to promote the decomposition of the zirconium source and its subsequent reaction with the oxygen source present in the chamber, thereby forming a zirconium oxide film. In some embodiments where the second dielectric 114 is composed of zirconium oxide (ZrO2) doped with aluminum (Al), an aluminum source (e.g., trimethylaluminum (TMA) or aluminum chloride) can also be supplied to the CVD chamber during the CVD process. In such embodiments, the flow rate of the aluminum source can be less than the flow rate of the zirconium source, resulting in an aluminum concentration in the range of about 1% to about 8%.

[0037] In other embodiments where the second dielectric 114 is made of zirconium oxide (ZrO2) doped with aluminum (Al), an ALD process may be used to form the second dielectric 114. The ALD process may include alternating multiple zirconium oxide (ZrO2) deposition cycles and multiple aluminum oxide (Al2O3) deposition cycles in an alternating manner until the second dielectric 114 reaches a desired thickness.

[0038] In addition, before depositing the top electrode 120, the capacitor dielectric 110 is subjected to an annealing process. The temperature of the annealing process is between about 400°C and about 500°C. After the annealing process, the capacitor dielectric 110 is crystallized to an ideal crystalline phase. In some embodiments, the ratio of the tetragonal phase to the orthorhombic phase of the capacitor dielectric 110 can be measured by a technique such as X-ray diffractometer (XRD), and the ratio is in the range of about 0.1 to about 0.3 (e.g., 0.2). In other embodiments, the equivalent oxide thickness (EOT) of the capacitor dielectric 110 can be about 0.6nm to increase capacitance and reduce leakage current.

[0039] Although the above Figure 1 Only planar capacitors are shown in the figure, but the spirit of the present invention can also be applied to capacitors with different designs, such as cylindrical capacitors or pedestal capacitors.

[0040] Figure 2 FIG. 1 is a circuit diagram of a memory cell of a memory according to some embodiments of the present invention. Figure 2, the memory 200 is composed of a plurality of memory cells 202 arranged in a rectangular matrix configuration. In some embodiments, the memory 200 is a dynamic random access memory (DRAM) device. The memory cell 202 of the memory 200 is composed of a transistor 200T and a capacitor 200C electrically connected to the transistor 200T as a main structure. One side of the capacitor 200C is coupled to the drain region of the transistor 200T, and the other side of the capacitor 200C is coupled to the ground. The memory 200 also includes a word line 200W coupled to the gate region of the transistor 200T and a bit line 200B coupled to the source region of the transistor 200T. Specifically, the memory cell 202 uses the capacitor 200C to store a logic value (0 or 1). If the capacitor 200C is in a blank state (i.e., not charged), it represents a logic value of 0. If the capacitor 200C is in a fully charged state, it represents a logic value of 1. Transistor 200T controls access to memory cell 202 by opening or closing the gate of transistor 200T, thereby allowing values to be read or written. Writing data involves charging or discharging capacitor 200C, while reading data involves detecting the charge to determine the stored logic value.

[0041] refer to Figure 2 , word line 200W connected to transistor 200T is used to control the gate of transistor 200T by applying a voltage to transistor 200T, thereby allowing charge to be read or written. Bit line 200B is perpendicular to word line 200W and is also connected to transistor 200T. When reading, the charge on capacitor 200C is sensed by bit line 200B to determine whether the stored value is 0 or 1. When writing, bit line 200B is used to set the charge on capacitor 200C to the desired logical value. Thus, word line 200W selects memory cell 202, and bit line 200B carries data during operation.

[0042] Figure 3 1 is a cross-sectional view of a memory according to some embodiments of the present invention. FIG. 1 shows a memory 300. In some embodiments, the cross-sectional view of the memory 300 may be as follows: Figure 2 An example of memory 200 is discussed.

[0043] Memory 300 includes a substrate 301. In some embodiments, substrate 301 may be made of a suitable semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium phosphide, germanium, indium antimonide, indium phosphide, or indium arsenide. Substrate 301 may also be doped with a suitable dopant. For example, substrate 301 may be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), or aluminum (Al). In other embodiments, substrate 301 may be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb).

[0044] The isolation structure 302 is disposed in the substrate 301. The isolation structure 302 may be a suitable isolation structure, such as a shallow trench isolation (STI) structure. Figure 3 In the cross-sectional view of FIG, two isolation structures 302 are shown, which define an active region 301A, on which at least one transistor is formed. In some embodiments, the isolation structures 302 can be made of a suitable dielectric material, such as silicon oxide, silicon nitride, etc.

[0045] The memory 300 further includes a plurality of word line structures 316A and 316B. Figure 3 In the cross-sectional view of , the word line structure 316A is embedded in the active region 301A of the substrate 301 , while the word line structure 316B is embedded in the isolation structure 302 .

[0046] Memory 300 also includes a dielectric layer 306A located above the corresponding word line structure 316A, and a dielectric liner 303A lining the corresponding word line structure 316A and the corresponding dielectric layer 306A. In some embodiments, dielectric layer 306A may include a suitable dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, dielectric liner 303A may include a suitable dielectric material, such as silicon oxide, silicon nitride, etc.

[0047] Similarly, memory 300 also includes a dielectric layer 306B overlying a corresponding word line structure 316B, and a dielectric liner 303B lining the corresponding word line structure 316B and the corresponding dielectric layer 306B. The materials of dielectric layer 306B and dielectric liner 303B may be similar to those described with respect to dielectric layer 306A and dielectric liner 303A, and thus, for the sake of brevity, the relevant details will not be repeated.

[0048] In some embodiments, each word line structure 316A includes a bottom conductive material 304A and a top conductive material 305A above the bottom conductive material 304A. In some embodiments, the bottom conductive material 304A and the top conductive material 305A are made of different materials. In some embodiments, the bottom conductive material 304A may include a suitable conductive material, such as cobalt, nickel, titanium, titanium nitride, tungsten, tungsten nitride, or the like, or a combination thereof. For example, in some embodiments, a combination of titanium nitride and tungsten is used as the bottom conductive material 304A. In some embodiments, the top conductive material 305A may be a suitable material that reduces energy band bending between the active region 301A and the dielectric liner 303A. The top conductive material 305A may be a semiconductor material or a conductive material. In some embodiments, polysilicon is used for the top conductive material 305A. In some other embodiments, doped polysilicon is used for the top conductive material 305A. Although the top conductive material 305A is illustrated as having a rectangular cross-section, the present invention is not limited thereto. In other embodiments, the cross-section of the top conductive material 305A may also be semicircular, triangular, trapezoidal, inverted trapezoidal, or irregular.

[0049] With respect to word line structures 316B, each word line structure 316B includes a bottom conductive material 304B and a top conductive material 305B above the bottom conductive material 304B. The materials of the bottom conductive material 304B and the top conductive material 305B can be similar to those described for the bottom conductive material 304A and the top conductive material 305A, and thus, for the sake of brevity, the relevant details will not be repeated.

[0050] Memory 300 also includes a plurality of doped regions 301D within active region 301A of substrate 301, wherein a pair of doped regions 301D are disposed on opposite sides of wordline structure 316A. In some embodiments, doped regions 301D may comprise a conductivity type opposite to that of substrate 301. For example, when substrate 301 is a p-type substrate, doped regions 301D may be n-type doped regions. Similarly, when substrate 301 is an n-type substrate, doped regions 301D may be p-type doped regions.

[0051] Here, the word line structure 316A, the dielectric liner 303A, the pair of doped regions 301D on opposite sides of the word line structure 316A, and the active region 301A of the substrate 301 may collectively function as a transistor of the memory 300 (eg, Figure 2 In more detail, the word line structure 316A may serve as a gate electrode of the transistor, the dielectric liner 303A may serve as a gate dielectric of the transistor, the active region 301A of the substrate 301 may serve as a channel region of the transistor, and the doped region 301D may serve as a source / drain region of the transistor.

[0052] Memory 300 also includes a bit line structure 317 located above substrate 301 and electrically coupled to one of the plurality of doped regions 301D. In some embodiments, bit line structure 317 may include a shield contact 312A and a bit line 311A located above shield contact 312A. In some embodiments, shield contact 312A includes a portion embedded in substrate 301 and a portion protruding from substrate 301. In some embodiments, shield contact 312A may be made of doped silicon or polysilicon. In some embodiments, bit line 311A may be made of a suitable conductive material, such as tungsten, tungsten nitride, titanium nitride, or a combination thereof.

[0053] Memory 300 also includes capacitor contact structures 318 above substrate 301 and electrically coupled to doped region 301D. In some embodiments, each capacitor contact structure 318 may include a shield contact 312B and a metal contact 311B above shield contact 312B. In some embodiments, shield contact 312B has a portion embedded in substrate 301 and a portion protruding from substrate 301. In some embodiments, shield contact 312B and metal contact 311B may be made of materials similar to those described with respect to shield contact 312A and bit line 311A, and therefore, for the sake of brevity, the relevant details will not be repeated.

[0054] Memory 300 also includes capacitor structures 315 over respective capacitor contact structures 318. In some embodiments, each capacitor structure 315 includes a lower electrode 308, a first dielectric 309A, a second dielectric 309B, and an upper electrode 310, wherein the first dielectric 309A and the second dielectric 309B are disposed between the upper electrode 310 and the lower electrode 308. In some embodiments, the lower electrode 308, the first dielectric 309A, and the second dielectric 309B can have a U-shaped cross-section.

[0055] Figure 3 The capacitor structure 315 may be similar to that in Figure 1 In more detail, the bottom electrode 308, first dielectric 309A, second dielectric 309B, and top electrode 310 of capacitor structure 315 may have similar materials and formation methods as the bottom electrode 100, first dielectric 112, second dielectric 114, and top electrode 120 of capacitor structure 10, respectively. Therefore, for the sake of brevity, the relevant details will not be repeated.

[0056] Memory 300 further includes a dielectric layer 307 disposed over substrate 301 and laterally surrounding bit line structure 317, capacitor contact structure 318, and capacitor structure 315. In some embodiments, dielectric layer 307 may be formed of, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, a low-k dielectric material, or a combination thereof.

[0057] Figure 4-12 is a cross-sectional view showing various stages of forming a memory according to some embodiments of the present invention. In more detail, Figure 4-12 shows the method for forming Figure 3 The method of the memory 300 discussed. Therefore, like elements are labeled with the same figure numbers and the relevant details will not be repeated for the sake of brevity.

[0058] Please refer to Figure 4 , a substrate 301 is provided. An isolation structure 302 is formed in the substrate 301 to define an active region 301A. For example, a series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) above the substrate 301. A photolithography process may be performed to define the position of the isolation structure 302. After the photolithography process, an etching process such as an anisotropic dry etching process may be performed to form a trench that penetrates the pad oxide layer, the pad nitride layer, and the substrate 301. In some embodiments, the cleaning process may be performed by an appropriate cleaning method, such as wet cleaning. An insulating material may be deposited into the trench, and a planarization process such as chemical mechanical polishing may then be performed to remove excess fill material until the substrate 301 is exposed. After the isolation structure 302 is formed, a doped region 301D may be formed in the active region 301A of the substrate 301 by an implantation process.

[0059] Please refer to Figure 5 , trench 501A and trench 501B are formed in substrate 301 and isolation structure 302, respectively. In some embodiments, a patterned mask (e.g., a photoresist) is formed over substrate 301, wherein the patterned mask may include openings that define the positions of trench 501A and trench 501B. Subsequently, an etching process may be performed from the openings of the patterned mask to remove portions of substrate 301 and isolation structure 302 to form trench 501A and trench 501B. In some embodiments, the etching process may be a suitable etching process, such as wet etching or dry etching. In some embodiments, an anisotropic etching process, such as RIE, DRIE, etc., may be performed. In some embodiments, the aspect ratio of trench 501A may be different from (or the same as) the aspect ratio of trench 501B.

[0060] Please refer to Figure 6Dielectric liner 303A and wordline structure 316A are respectively formed in trench 501A, while dielectric liner 303B and wordline structure 316B are respectively formed in trench 501B. Wordline structure 316A includes bottom conductive material 304A and top conductive material 305A above bottom conductive material 304A. Wordline structure 316B includes bottom conductive material 304B and top conductive material 305B above bottom conductive material 304B.

[0061] In some embodiments, a first deposition process may be performed to form a material of dielectric liner 303A and dielectric liner 303B over substrate 301 and on the liner sidewalls of trench 501A and trench 501B. In some embodiments, the first deposition process may be a suitable deposition method, such as CVD, PECVD, low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), atomic layer deposition (ALD), or similar deposition methods.

[0062] Thereafter, a second deposition process may be performed to form bottom conductive material 304A and bottom conductive material 304B over substrate 301 and overfill trenches 501A and 501B. Next, an etch-back process may be performed to lower the top surface of bottom conductive material 304A and bottom conductive material 304B.

[0063] Next, a third deposition process may be performed to form the material of the top conductive material 305A and the top conductive material 305B and overfill the trench 501A and the trench 501B.

[0064] After the deposition process, a planarization process such as CMP may be performed on the materials of top conductive materials 305A and 305B until substrate 301 is exposed. As a result, the top surface of substrate 301, the top surface of top conductive material 305A, the top surface of top conductive material 305B, and the top surface of isolation structure 302 are substantially coplanar. In some embodiments, a cleaning process may be performed after the planarization process.

[0065] Please refer to Figure 7 An etch-back process may be performed to lower the top surfaces of the top conductive material 305A and the top conductive material 305B to form the recess 701A and the recess 701B over the word line structure 316A and the word line structure 316B, respectively.

[0066] Please refer to Figure 8 Dielectric layer 306A and dielectric layer 306B are formed over word line structure 316A and word line structure 316B, respectively. In some embodiments, a deposition process may be performed to form a dielectric material over substrate 301 and cover word line structure 316A and word line structure 316B.

[0067] Next, a planarization process may be performed to remove excess dielectric material until substrate 301 is exposed. In some embodiments, the planarization process may be performed to make the top surfaces of dielectric layer 306A and dielectric layer 306B coplanar with the surface of substrate 301.

[0068] Please refer to Figure 9 , recesses 911A and recesses 911B are formed in the doped region 301D of the substrate 301. In some embodiments, the bottoms of recesses 911A and recesses 911B may be higher than the top surface of the top conductive material 305A. In some embodiments, a patterned mask (not shown) is formed above the substrate 301, and an etching process is performed to remove the portion of the substrate 301 exposed by the patterned mask to form recesses 911A and recesses 911B. In some embodiments, a cleaning process may be performed after the etching process. In some embodiments, recesses 911A may be formed between adjacent dielectric layers 306A. In some embodiments, recesses 911B may be formed between adjacent dielectric layers 306A and 306B.

[0069] Please refer to Figure 10 , a first conductive layer 121 is formed over substrate 301, and a second conductive layer 123 is formed over first conductive layer 121. In some embodiments, first conductive layer 121 may fill recesses 911A and 911B and may contact doped region 301D. In some embodiments, first conductive layer 121 and second conductive layer 123 may be formed using a suitable deposition process.

[0070] Please refer to Figure 11 The first conductive layer 121 and the second conductive layer 123 are patterned to form a bit line structure 317 and a capacitor contact structure 318. In some embodiments, the bit line structure 317 includes a shield contact 212A and a bit line 211A above the shield contact 212A, wherein the shield contact 212A is the remaining portion of the first conductive layer 121, and the bit line 211A is the remaining portion of the second conductive layer 123. On the other hand, the capacitor contact structure 318 includes a shield contact 212B and a metal contact 211B above the shield contact 212B, wherein the shield contact 212B is the remaining portion of the first conductive layer 121, and the metal contact 211B is the remaining portion of the second conductive layer 123.

[0071] Please refer to Figure 12A dielectric layer 307 is formed over the substrate 301 and covers the bit line structure 317 and the capacitor contact structure 318. Subsequently, capacitor structures 315 are formed in the dielectric layer 307 and contact the corresponding capacitor contact structures 318. In some embodiments, the dielectric layer 307 can be formed using a suitable deposition process. In some embodiments, the capacitor structures 315 can be formed by, for example, patterning the dielectric layer 307 to form openings exposing the capacitor contact structures 318, depositing the lower electrode 308, the first dielectric 309A, the second dielectric 309B, and the upper electrode 310 in the openings, and then performing a planarization process until the dielectric layer 307 is exposed.

[0072] In some embodiments, additional processes and steps may be performed to complete the memory manufacturing process. In some embodiments, additional back-end-of-line (BEOL) processes may be performed on the memory 300.

[0073] Although the present invention has been described in detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0074] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims.

[0075] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processing procedures and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made thereto without departing from the spirit and scope of the present disclosure.

[0076]

Explanation of symbols

[0077] 10: Capacitor structure

[0078] 100: bottom electrode

[0079] 110: Capacitor dielectric

[0080] 112: First dielectric

[0081] 114: Second dielectric

[0082] 120: Top electrode

[0083] 121: conductive layer

[0084] 123: conductive layer

[0085] 200: Memory

[0086] 200B: bit line

[0087] 200C:Capacitor

[0088] 200T: Transistor

[0089] 200W: Character Line

[0090] 202: Storage unit

[0091] 211A: Bit line

[0092] 211B:Metal contact

[0093] 212A: Shielded contact

[0094] 212B: Shielded contact

[0095] 300: Memory

[0096] 301:Substrate

[0097] 301A: Active Area

[0098] 301D: doped area

[0099] 302: Isolation Structure

[0100] 303A: Dielectric liner

[0101] 303B: Dielectric liner

[0102] 304A: Bottom conductive material

[0103] 304B: bottom conductive material

[0104] 305A: Top conductive material

[0105] 305B: Top conductive material

[0106] 306A: Dielectric layer

[0107] 306B: Dielectric layer

[0108] 307: dielectric layer

[0109] 308: lower electrode

[0110] 309A: First dielectric

[0111] 309B: Second dielectric

[0112] 310: Upper electrode

[0113] 311A: Bit line

[0114] 311B: Metal contact

[0115] 312A: Shielded contact

[0116] 312B: Shielded contact

[0117] 315:Capacitor structure

[0118] 316A: Character line structure

[0119] 316B: Character line structure

[0120] 317: Bit line structure

[0121] 318:Capacitor contact structure

[0122] 501A: Groove

[0123] 501B: Groove

[0124] 701A: Groove

[0125] 701B: Groove

[0126] 911A: Groove

[0127] 911B: Groove

[0128] T1:Thickness

[0129] T2: Thickness.

Claims

1. A memory, characterized in that: Include: substrate; and A capacitor structure, located above the substrate, comprises: lower electrode; a capacitor dielectric located above the bottom electrode and comprising a first dielectric and a second dielectric located above the first dielectric, wherein the first dielectric is composed of hafnium oxide and the second dielectric is composed of zirconium oxide; and The upper electrode is located above the second dielectric.

2. The memory according to claim 1, wherein the second dielectric is doped with aluminum. 3 . The memory according to claim 2 , wherein the aluminum concentration of the second dielectric is 1% to 8%. The memory according to claim 2 , wherein the first dielectric does not contain aluminum. 5 . The memory of claim 1 , wherein the first dielectric has a first thickness, and the second dielectric has a second thickness different from the first thickness. The memory according to claim 5 , wherein the first thickness is smaller than the second thickness. 7 . The memory according to claim 5 , wherein the first thickness of the first dielectric is 0.5 nm to 2.0 nm, and the second thickness of the second dielectric is 3.0 nm to 7.0 nm.

8. The memory device according to claim 1, wherein the capacitor dielectric has a crystal structure having a tetragonal phase and an orthorhombic phase.

9. The memory device according to claim 8, wherein a ratio of a tetragonal phase to an orthorhombic phase of the capacitor dielectric is 0.1 to 0.

3.

10. The memory according to claim 1, wherein Further including: a word line structure located above the substrate; and A bit line structure is located above the substrate and electrically connected to a doped region of the substrate on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.

11. A method for forming a memory, characterized in that: Include: A capacitor structure is formed, located above the substrate, comprising: depositing the bottom electrode; Depositing a first dielectric over the bottom electrode, wherein the first dielectric is composed of hafnium oxide; depositing a second dielectric over the first dielectric, wherein the second dielectric is composed of zirconium oxide; and A top electrode is deposited over the second dielectric. The method according to claim 11 , wherein the second dielectric is doped with aluminum.

13. The method according to claim 12, wherein the aluminum concentration of the second dielectric is 1% to 8%. The method of claim 12 , wherein the first dielectric does not contain aluminum.

15. The method of claim 11, wherein the first dielectric has a first thickness, and the second dielectric has a second thickness different from the first thickness. The method according to claim 15 , wherein the first thickness is smaller than the second thickness.

17. The method according to claim 11, wherein The method further includes performing an annealing process after depositing the second dielectric, so that a combination of the first dielectric and the second dielectric has a crystal structure having a tetragonal phase and an orthorhombic phase.

18. The method according to claim 17, wherein the temperature of the annealing process is between 400°C and 500°C.

19. The method according to claim 17, wherein a ratio of the tetragonal phase to the orthorhombic phase is 0.1 to 0.

3.

20. The method according to claim 11, wherein Further including: forming a word line structure above the substrate; and A bit line structure is formed over the substrate and electrically connected to a doped region of the substrate on a first side of the word line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.

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