Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure. The semiconductor structure comprises a bonding pad array and a first boundary bonding pad, the pad array includes a plurality of storage node pads arranged along a first direction and a second direction. The first boundary pad includes a plurality of triangular protrusions continuously connected along a third direction and disposed on a first side of the pad array, where each of the triangular protrusions includes a vertex and first and second beveled edges intersecting at the vertex, and the second beveled edge includes a recessed profile. When the semiconductor structure is used for manufacturing a dynamic random access memory comprising a stacked capacitor, the problem of stripping or collapsing of a capacitor structure in a peripheral region can be improved, and the reliability of an element is improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure comprising a pad array and a boundary pad and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that includes an array region consisting of multiple memory cells and a peripheral area consisting of control circuits. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array region and are electrically connected to each memory cell.

[0003] To achieve higher chip density, the structure of memory cells has been developing towards three-dimensionality, such as the use of buried wordline connections and stacked capacitor technology. Stacked capacitor technology refers to placing the capacitor of the memory cell above the substrate and achieving vertical electrical connection with the transistor in the substrate through a plug structure and contact pads. This saves the substrate area occupied by the capacitor and can also conveniently obtain a larger capacitance by increasing the height of the capacitor electrode plate. However, there are still some technical problems that need further improvement, such as the problem of capacitor structure peeling or collapse in the peripheral area. Summary of the Invention

[0004] The present invention aims to provide a semiconductor structure and a method for manufacturing the same, wherein the special design of the boundary pad and the adjacent pad array can improve the problem of capacitor structure peeling or collapse in the peripheral area and enhance the reliability of the component.

[0005] An embodiment of the present invention provides a semiconductor structure comprising a pad array and a first boundary pad. The pad array comprises a plurality of storage node pads arranged along a first direction and a second direction. The first boundary pad comprises a plurality of triangular protrusions continuously connected along a third direction and disposed on a first side of the pad array, wherein each triangular protrusion comprises a vertex and a first hypotenuse and a second hypotenuse intersecting at the vertex, and the second hypotenuse comprises a concave profile.

[0006] One embodiment of the present invention provides a method for manufacturing a semiconductor structure. The method includes sequentially forming a conductive material layer, a first mask layer, and a second mask layer on a substrate. A first self-aligned double patterning process is then performed to form a plurality of first annular trenches in the second mask layer to define a plurality of line patterns. The line patterns extend along a first direction and are mutually parallel. A second self-aligned double patterning process is then performed to form a plurality of second annular trenches in the second mask layer. The second annular trenches extend along a second direction and intersect the line patterns, thereby forming a pad array pattern and a boundary pattern surrounding the pad array pattern. The boundary pattern includes a first boundary pattern located on a first side of the pad array pattern, comprising a plurality of triangular protrusions continuously connected along a third direction, wherein each triangular protrusion includes a vertex and a first hypotenuse and a second hypotenuse intersecting at the vertex, and the second hypotenuse includes a concave profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 8 Illustrated is a schematic structural diagram of a semiconductor structure during a manufacturing process according to an embodiment of the present invention;

[0008] in,

[0009] Figures 1 to 5 It is a plan schematic diagram;

[0010] Figure 6 To follow Figure 1 Schematic diagram of the cross section along the AA line;

[0011] Figure 7 To follow Figure 3 Schematic diagram of the cross section along the AA line;

[0012] Figure 8 To follow Figure 5 Schematic diagram of the cross section along the AA line;

[0013] Figure 9 Illustrated is a schematic plan view of a semiconductor structure according to an embodiment of the present invention;

[0014] Figure 10 FIG2 is a schematic plan view of a semiconductor structure according to an embodiment of the present invention.

[0015] The description of the accompanying drawings is as follows:

[0016] 10: substrate;

[0017] 12: active region;

[0018] 14: Isolation structure;

[0019] 16: word line structure;

[0020] 20: bit line structure;

[0021] 32: first side wall;

[0022] 34: second side wall;

[0023] 36: third side wall;

[0024] 42: semiconductor layer;

[0025] 44: barrier layer;

[0026] 50: conductive material layer;

[0027] 52: plug structure;

[0028] 54: storage node pad;

[0029] 56: triangular protrusion;

[0030] 60: first mask layer;

[0031] 64: land pattern;

[0032] 70: second mask layer;

[0033] 72: Line pattern;

[0034] 74: land pattern;

[0035] 76: triangular protrusion;

[0036] 120: Boundary structure;

[0037] 500: pad array;

[0038] 501: first boundary pad;

[0039] 502: second boundary pad;

[0040] 541: first pad;

[0041] 542: second pad;

[0042] 543: third pad;

[0043] 544: fourth pad;

[0044] 581: first branch pad;

[0045] 582: second branch pad;

[0046] 600: pad array pattern;

[0047] 601: first border pattern;

[0048] 602: second border pattern;

[0049] 681: First branch pattern;

[0050] 682: Second branch pattern;

[0051] 700: pad array pattern;

[0052] 701: first border pattern;

[0053] 702: second border pattern;

[0054] 741: first land pattern;

[0055] 742: second land pattern;

[0056] 743: third land pattern;

[0057] 744: fourth land pattern;

[0058] 781: First branch pattern;

[0059] 782: Second branch pattern;

[0060] 20a: semiconductor layer;

[0061] 20b: metal layer;

[0062] 20c: mask layer;

[0063] 500a: first side;

[0064] 500b: Second side;

[0065] 56a: first hypotenuse;

[0066] 56b: second hypotenuse;

[0067] 56c: Vertex;

[0068] 56d: bottom point;

[0069] 700a: first side;

[0070] 700b: second side;

[0071] 76a: first hypotenuse;

[0072] 76b: second hypotenuse;

[0073] 76c: Vertex;

[0074] 76d: bottom point;

[0075] AA: tangent;

[0076] AR: unit area;

[0077] D1: first direction;

[0078] D2: Second direction;

[0079] D3: third direction;

[0080] D4: fourth direction;

[0081] H: height;

[0082] H': height;

[0083] L1: length;

[0084] L1': length;

[0085] L3: length;

[0086] L3': length;

[0087] L4: length;

[0088] L4': length;

[0089] PR: Peripheral District;

[0090] R1: concave contour;

[0091] R2: concave contour;

[0092] S1: maximum spacing;

[0093] S1': maximum spacing;

[0094] S2: maximum spacing;

[0095] S2': maximum spacing;

[0096] TR1: first annular groove;

[0097] TR2: second annular groove;

[0098] W: bottom width;

[0099] W': bottom width. DETAILED DESCRIPTION

[0100] To help those skilled in the art better understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, details the components and intended effects of the present invention. It should be noted that features from various embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present invention.

[0101] In order to make it easier for readers to understand and to simplify the illustrations, the various illustrations in the present invention only depict a portion of the semiconductor structure, and specific components in the illustrations are not drawn according to the actual scale. In addition, the number and size of each component in the figure are for illustration only and are not intended to limit the scope of the present invention. In order to simplify the illustrations, some components may be omitted from the figures. The description of the upper and lower relationships of the relative components in the figures in the text should be understood by those skilled in the art to refer to the relative positions of the components. Therefore, they can all be flipped to present the same structure, which should all fall within the scope of the invention of this specification.

[0102] To facilitate illustration and understanding of the semiconductor structure of the present invention, the figures illustrate spatial reference directions, such as a first direction D1, a second direction D2, a third direction D3, and a fourth direction D4. The first direction D1, the second direction D2, the third direction D3, and the fourth direction D4 are parallel to the surface of the substrate 100, and the third direction D3 and the fourth direction D4 are perpendicular to each other. The first direction D1 and the second direction D2 each include an angle with the third direction D3 between 15 and 75 degrees, but are not limited thereto. The angle between the first direction D1 and the second direction D2 is between 30 and 90 degrees, but is not limited thereto.

[0103] Figures 1 to 8 FIG. 1 is a schematic diagram of a semiconductor structure during a manufacturing process according to an embodiment of the present invention, wherein Figures 1 to 5 It is a plan diagram. Figure 6 To follow Figure 1 Schematic diagram of the cross section of the AA tangent line, Figure 7 To follow Figure 3 Schematic diagram of the cross section of the AA tangent line, Figure 8 To follow Figure 5 Schematic cross-sectional view of the AA tangent line. The AA tangent line is a straight line substantially along the fourth direction D4.

[0104] The semiconductor structure of the present invention can be used to manufacture dynamic random access memory (DRAM) including stacked capacitors. Without departing from the spirit of the present invention, the present invention can also be applied to other types of semiconductor devices.

[0105] like Figure 1 and Figure 6As shown, a substrate 10 is first provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. A cell region AR and a peripheral region PR are defined on the substrate 10. The cell region AR, which may also be referred to as an array region, is an area where an array of memory cells is arranged, where the memory cells are, for example, dynamic random access memory cells. The peripheral region PR is disposed adjacent to the cell region AR to separate the cell region AR from other circuit regions of the substrate 10. In some embodiments, the peripheral region PR may also include peripheral circuits, such as drivers, buffers, amplifiers, and decoders, but not limited thereto. In some embodiments, the peripheral region PR is also an area where word lines and bit lines that control the operation of the memory cells are electrically connected to the peripheral circuits. Isolation structures 14 are disposed in the substrate 10 to define a plurality of active regions 12 in the cell region AR, which are arranged parallel to each other and staggered along a first direction D1 to form an active region array. In some embodiments, the active regions 12 may be arranged in parallel along other directions according to design requirements.

[0106] In some embodiments, the isolation structure 14 also defines a boundary structure 120 in the peripheral region PR, which extends along the boundary between the peripheral region PR and the cell region AR.

[0107] Multiple word line structures 16 are disposed in substrate 10, extending along a fourth direction D4 and arranged parallel to a third direction D3. They intersect active area 12 and isolation structure 14, dividing active area 12 into two end portions and a central portion. The portions of word line structures 16 that intersect active area 12 serve as the gates of the memory cell transistors. The portions of word line structures 106 that intersect isolation structure 104 serve as passing gates.

[0108] A plurality of bitline structures 20 are disposed on a substrate 10, extending along a third direction D3 and arranged in parallel along a fourth direction D4. The bitline structures 20 may include a multilayer structure, for example, a semiconductor layer 20a, a metal layer 20b, and a mask layer 20c. Sidewall substructures are provided on the sidewalls of the bitline structures 20 to electrically isolate the bitline structures 20 from subsequently fabricated semiconductor layers 42 and plug structures 52. The sidewall substructures may be a multilayer structure consisting of a first sidewall substructure 32, a second sidewall substructure 34, and a third sidewall substructure 36.

[0109] Please refer to Figure 2 、 Figure 3 and Figure 7A dielectric layer (not shown) is then formed on the substrate 10 and filled in the gaps between the bitline structures 20. A portion of the dielectric layer is then removed, thereby forming a plurality of contact holes (not shown) between the bitline structures 20, separated from each other by the remaining dielectric layer and exposing the ends of the active regions 12. A semiconductor layer 42 is then formed at the bottom of the contact holes, and a barrier layer 44 and a conductive material layer 50 are formed to cover the semiconductor layer 42 and the bitline structures 20 and fill the contact holes. After planarizing the surface of the conductive material layer 50, a first mask layer 60 and a second mask layer 70 are sequentially formed on the conductive material layer 50. A first self-aligned double patterning (SADP) process is then performed to form a plurality of narrow, long, and parallel first annular trenches TR1 in the second mask layer 70. These first annular trenches TR1 extend in the first direction D1 and are arranged in parallel. This defines a plurality of line patterns 72 in the first mask layer 60. The line patterns 72 extend in the first direction D1 and are parallel to each other.

[0110] Subsequently, a second self-aligned double patterning process is performed to form a plurality of narrow second annular grooves TR2 with their long axes extending along the second direction D2 and arranged in parallel in the second mask layer 70, which intersect with the first annular grooves TR1 and cut through the line pattern 72, thereby defining a pad array pattern 700 composed of the pad pattern 74 and a boundary pattern at least partially surrounding the pad array pattern 700 in the second mask layer 70.

[0111] The layout shape of the border pattern is defined by the angle at which the first annular groove TR1 and the second annular groove TR2 intersect and the length of the end portions. Figure 3 As shown, the boundary pattern includes a first boundary pattern 701 provided on the first side 700a of the pad array pattern 700, which includes a plurality of triangular protrusions 76 continuously connected along the third direction D3. Each triangular protrusion 76 includes a first oblique side 76a, a second oblique side 76b, a vertex 76c, and two base points 76d. The first oblique side 76a extends substantially along the first direction D1, and the second oblique side 76b extends substantially along the second direction D2. The first oblique side 76a and the second oblique side 76b intersect at the vertex 76c and the base point 76d. According to one embodiment of the present invention, the first oblique side 76a is a flat side, and the portion of the second oblique side 76b adjacent to the base point 76d includes a recessed profile R1 defined by the end of the first annular groove TR1. According to one embodiment of the present invention, the recessed profile R1 is an arc-shaped recessed profile.

[0112] The ratio of the width and height of the triangular protrusion 76 is controlled by the angle between the first direction D1 and the second direction D2. Herein, the base width W of the triangular protrusion 76 is defined as the distance between the two base points 76d, and the height H of the triangular protrusion 76 is defined as the distance between the vertex 76c and the two base points 76d. According to one embodiment of the present invention, the base width W of each triangular protrusion 76 is greater than the height H.

[0113] The pad array pattern 700 includes, in a portion adjacent to the first boundary pattern 701, a first pad pattern 741 that is closest to the first oblique edge 76a in the second direction D2, a second pad pattern 742 that is closest to the second oblique edge 76b in the first direction D1, a third pad pattern 743 that is located on a side away from the first boundary pattern 701 relative to the first pad pattern 741 and the second pad pattern 742, and a fourth pad pattern 744 that is located between the first pad pattern 741 and the second oblique edge 76b and aligned with the first pad pattern 741 along the first direction D1, wherein the fourth pad pattern 744 is also located between the second pad pattern 742 and the first oblique edge 76a and aligned with the second pad pattern 742 along the second direction D2.

[0114] According to an embodiment of the present invention, a maximum length L1 of the first pad pattern 741 along the first direction D1 is greater than a maximum length L3 of the third pad pattern 743 along the first direction D1.

[0115] According to an embodiment of the present invention, a maximum length L4 of the fourth pad pattern 744 along the first direction D1 is smaller than a maximum length L3 of the third pad pattern 743 along the first direction D1.

[0116] According to an embodiment of the present invention, a maximum distance S1 between the first pad pattern 741 and the recessed profile R1 of the second oblique side 76b in the first direction D1 is greater than a maximum distance S2 between the second pad pattern 742 and the first oblique side 76a in the second direction D2.

[0117] According to an embodiment of the present invention, Figure 3 As shown, the border pattern further includes a second border pattern 702 disposed along the fourth direction D4 on the second side 700b of the pad array pattern 700, and a plurality of first branch patterns 781 and second branch patterns 782, which extend along the first direction D1 and are alternately arranged along the fourth direction D4 between the second border pattern 702 and the pad array pattern 700. The second border pattern 702 is structurally connected to the first border pattern 701. The first branch pattern 781 is structurally connected to the second border pattern 702, and the second branch pattern 782 is structurally separated from the second border pattern 702.

[0118] Please refer to Figure 4After patterning the second mask layer 70, the first mask layer 60 is subjected to a first etching process using the second mask layer 70 as an etching mask, and the first annular trench TR1, the second annular trench TR2, the pad array pattern 700 and the boundary pattern are transferred to the first mask layer 60, thereby obtaining a pad array pattern 600 consisting of a pad pattern 64, a first boundary pattern 601, a second boundary pattern 602, a first branch pattern 681 and a second branch pattern 682.

[0119] Please refer to Figure 5 and Figure 8 Next, a second etching process is performed on the conductive material layer 50 using the patterned first mask layer 60 as an etching mask to transfer the first annular trench TR1, the second annular trench TR2, the pad array pattern 600, the first boundary pattern 601, the second boundary pattern 602, the first branch pattern 681, and the second branch pattern 682 into the conductive material layer 50, thereby obtaining a patterned conductive material layer 50.

[0120] At this point in the process, the semiconductor structure of the present invention is obtained, which can be used to manufacture dynamic random access memory (DRAM) devices including stacked capacitors. The capacitor structure (not shown) is disposed on pad array 500 and electrically connected to transistors in substrate 10 via storage node pads 54 and plug structures 52. The special design of the boundary pads and the adjacent pad array of the present invention can alleviate the problem of capacitor structure delamination or collapse in the peripheral region, thereby improving device reliability.

[0121] In detail, Figure 5 and Figure 8 As shown, the semiconductor structure of the present invention includes a substrate 10, a pad array 500 disposed on the substrate 10, and a boundary pad surrounding at least one side of the pad array 500. The pad array 500 includes a plurality of storage node pads 54 separated from each other and arranged along a first direction D1 and a second direction D2. The portion of the conductive material layer 50 located between the bitline structures 20 forms a plug structure 52. The plug structure 52 is structurally integrally formed with the storage node pads 54. The boundary pad includes a first boundary pad 501 disposed on a first side 500a of the pad array 500. The first boundary pad 501 includes a plurality of triangular protrusions 56 connected continuously along a third direction D3. Each triangular protrusion 56 has a first oblique side 56a, a second oblique side 56b, a vertex 56c, and two bases 56d. The first oblique side 56a extends generally along the first direction D1, and the second oblique side 56b extends generally along the second direction D2. The first oblique side 56a and the second oblique side 56b intersect at a vertex 56c and a base 56d. According to one embodiment of the present invention, the first oblique side 76a is a flat side, and the portion of the second oblique side 56b adjacent to the bottom point 56d includes a concave profile R1. According to one embodiment of the present invention, the concave profile R1 is an arc-shaped concave profile.

[0122] The ratio of the width and height of the triangular protrusion 56 is controlled by the angle between the first direction D1 and the second direction D2. Herein, the base width W' of the triangular protrusion 56 is defined as the distance between the two base points 56d, and the height H' of the triangular protrusion 56 is defined as the distance between the vertex 56c and the two base points 56d. According to one embodiment of the present invention, the base width W' of each triangular protrusion 56 is greater than the height H'.

[0123] The pad array 500 includes, in a portion adjacent to the first boundary pad 501, a first pad 541 that is closest to the first oblique edge 56a in the second direction D2, a second pad 542 that is closest to the second oblique edge 56b in the first direction D1, a third pad 543 that is located on a side away from the first boundary pad 501 relative to the first pad 541 and the second pad 542, and a fourth pad 544 that is located between the first boundary pad 501 and the second oblique edge 56b and aligned with the first pad 541 along the first direction D1, wherein the fourth pad 544 is also located between the second pad 542 and the first oblique edge 56a and aligned with the second pad 542 along the second direction D2.

[0124] According to an embodiment of the present invention, a maximum length L1 ′ of the first pad 541 along the first direction D1 is greater than a maximum length L3 ′ of the third pad 543 along the first direction D1 .

[0125] According to an embodiment of the present invention, a maximum length L4 ′ of the fourth pad 544 along the first direction D1 is smaller than a maximum length L3 ′ of the third pad 543 along the first direction D1 .

[0126] According to an embodiment of the present invention, a maximum distance S1 ′ between the first pad 541 and the recessed profile R1 of the second oblique side 56 b in the first direction D1 is greater than a maximum distance S2 ′ between the second pad 542 and the first oblique side 56 a in the second direction D2 .

[0127] According to an embodiment of the present invention, Figure 5 As shown, the boundary pad further includes a second boundary pad 502 disposed along the fourth direction D4 on the second side 500b of the pad array 500, and a plurality of first branch pads 581 and second branch pads 582, which extend along the first direction D1 and are alternately arranged along the fourth direction D4 between the second boundary pad 502 and the pad array 500. The second boundary pad 502 is structurally connected to the first boundary pad 501. The first branch pads 581 are structurally connected to the second boundary pad 502, and the second branch pads 582 are structurally separated from the second boundary pad 502.

[0128] The following describes various embodiments of the present invention. To simplify the description, the following focuses on the differences between the embodiments and does not reiterate the similarities. Identical components in each embodiment are labeled with the same reference numerals to facilitate cross-reference between the embodiments.

[0129] Please refer to Figure 9 , which is a schematic plan view of the conductive material layer 50 and the second mask layer 70 after patterning of the semiconductor structure according to one embodiment of the present invention, and which is similar to the above Figure 3 and Figure 5 The main difference between the embodiments is that, during the second self-aligned double patterning process, the end length of the second annular trench TR2 can be shortened, so that the area of the fourth pad pattern 744 is reduced to such a level that it will not be formed in the second mask layer 70. Therefore, after the pattern of the second mask layer 70 is subsequently transferred to the first mask layer 60 and then to the conductive material layer 50, no fourth pad 544 will be formed in the conductive material layer 50.

[0130] Please refer to Figure 10 , which is a schematic plan view of the conductive material layer 50 and the second mask layer 70 after patterning of the semiconductor structure according to one embodiment of the present invention, and which is similar to the above Figure 3 and Figure 5 The main difference between the embodiments is that, during the second self-aligned double patterning process, the end length of the second annular trench TR2 is extended, thereby also defining another concave profile R2 on the first oblique side 76a of the triangular protrusion 76 of the first boundary pattern 701. Therefore, after the pattern of the second mask layer 70 is subsequently transferred to the first mask layer 60 and then to the conductive material layer 50, the first oblique side 56a of the triangular protrusion 56 of the first boundary pad 501 also has a concave profile R2. The width W1 of the concave profile R1 along the second direction D2 and the width W2 of the concave profile R2 along the first direction D2 are determined by the end profiles of the first annular trench TR1 and the second annular trench TR2, respectively. According to one embodiment of the present invention, width W1 is different from width W2. According to another embodiment of the present invention, width W1 is equal to width W2.

[0131] In general, the present invention defines the pad array and the boundary pad by forming the intersecting first annular groove TR1 and the second annular groove TR2 through two self-aligned double patterning processes, and can adjust the angle of intersection and the length of the end of the first annular groove TR1 and the second annular groove TR2 to adjust the shape of the boundary pad and the layout of the pad array adjacent to the boundary pad to match the setting of the capacitor structure in the peripheral area, reduce the problem of capacitor structure peeling or collapse in the peripheral area, and improve the reliability of the component.

[0132] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that include: A pad array includes a plurality of storage node pads arranged along a first direction and a second direction; as well as The first boundary pad includes a plurality of triangular protrusions continuously connected along a third direction and arranged on a first side of the pad array, wherein each triangular protrusion includes a vertex and a first oblique side and a second oblique side intersecting at the vertex, and the second oblique side includes a concave contour.

2. The semiconductor structure according to claim 1, wherein The bottom width of each triangular protrusion is greater than the height of each triangular protrusion.

3. The semiconductor structure according to claim 1, wherein: The first oblique side extends along the first direction, and the second oblique side extends along the second direction.

4. The semiconductor structure according to claim 1, wherein: The plurality of storage node pads include: a first pad, being closest to the first oblique edge in the second direction; a second pad, being closest to the second oblique edge in the first direction; and A third pad is located on a side away from the first boundary pad relative to the first pad and the second pad, and is aligned with the first pad along the second direction and aligned with the second pad along the first direction, wherein the maximum length of the first pad along the first direction is greater than the maximum length of the third pad along the first direction.

5. The semiconductor structure according to claim 4, wherein: The first oblique side is a flat side, and a maximum distance between the first pad and the concave contour of the second oblique side in the first direction is greater than a maximum distance between the second pad and the first oblique side in the second direction.

6. The semiconductor structure according to claim 1, wherein The first beveled edge includes another concave profile.

7. The semiconductor structure according to claim 6, wherein: The concave profile of the first oblique side and the concave profile of the second oblique side have different widths.

8. The semiconductor structure according to claim 6, wherein: The plurality of storage node pads include: a first pad, being closest to the first oblique edge in the second direction; a second pad, being closest to the second oblique edge in the first direction; a third pad located on a side away from the first boundary pad relative to the first pad and the second pad, and aligned with the first pad along the second direction and aligned with the second pad along the first direction; and A fourth solder pad is located between the first solder pad and the second oblique side and aligned with the first solder pad along the first direction, and is also located between the second solder pad and the first oblique side and aligned with the second solder pad along the second direction, wherein the maximum length of the fourth solder pad along the first direction is less than the maximum length of the third solder pad along the first direction.

9. The semiconductor structure according to claim 1, wherein: Also includes: a second boundary pad disposed on a second side of the pad array along a fourth direction, wherein the fourth direction is perpendicular to the third direction; as well as A plurality of first branch pads and second branch pads extend respectively along the first direction and are alternately arranged between the second boundary pad and the pad array along the fourth direction, wherein the first branches are connected to the second boundary pad and the second branches are separated from the second boundary pad.

10. A method for manufacturing a semiconductor structure, characterized in that: include: forming a conductive material layer, a first mask layer, and a second mask layer on the substrate in sequence; Performing a first self-aligned double patterning process to form a plurality of first annular trenches in the second mask layer to define a plurality of line patterns, wherein the line patterns extend along a first direction and are parallel to each other; as well as A second self-aligned double patterning process is performed to form a plurality of second annular grooves in the second mask layer, wherein the second annular grooves extend along a second direction and cut through the line pattern to obtain a pad array pattern and a boundary pattern surrounding the pad array pattern, wherein the boundary pattern includes a first boundary pattern located on a first side of the pad array pattern, which includes a plurality of triangular protrusions continuously connected along a third direction, wherein each of the triangular protrusions includes a vertex and a first hypotenuse and a second hypotenuse intersecting at the vertex, and the second hypotenuse includes a concave profile.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The bottom width of each triangular protrusion is greater than the height of each triangular protrusion.

12. The method for manufacturing a semiconductor structure according to claim 10, wherein: The first oblique side extends along the first direction, and the second oblique side extends along the second direction.

13. The method for manufacturing a semiconductor structure according to claim 10, wherein: The pad array pattern includes: a first pad pattern, being closest to the first oblique side in the second direction; a second pad pattern, being closest to the second oblique side in the first direction; and A third pad pattern is located on a side away from the first boundary pattern relative to the first pad pattern and the second pad pattern, and is aligned with the first pad pattern along the second direction and aligned with the second pad pattern along the first direction, wherein the length of the first pad pattern along the first direction is greater than the length of the third pad pattern along the first direction.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The first oblique side is a flat side, and a maximum distance between the first pad pattern and the concave contour of the second oblique side in the first direction is greater than a maximum distance between the second pad pattern and the first oblique side in the second direction.

15. The method for manufacturing a semiconductor structure according to claim 10, wherein: The first beveled edge includes another concave profile.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein: The concave profile of the first oblique side and the concave profile of the second oblique side have different widths.

17. The method for manufacturing a semiconductor structure according to claim 15, wherein: The pad array pattern includes: a first pad pattern, being closest to the first oblique side in the second direction; a second pad pattern, being closest to the second oblique side in the first direction; a third pad pattern located on a side away from the first boundary pattern relative to the first pad pattern and the second pad pattern, and aligned with the first pad pattern along the second direction and aligned with the second pad pattern along the first direction; and A fourth pad pattern is located between the first pad pattern and the second oblique side and aligned with the first pad pattern along the first direction, and is also located between the second pad pattern and the first oblique side and aligned with the second pad pattern along the second direction, wherein the length of the fourth pad pattern along the first direction is less than the length of the third pad pattern along the first direction.

18. The method for manufacturing a semiconductor structure according to claim 10, wherein: The border pattern further includes: a second boundary pattern disposed along a fourth direction on a second side of the pad array pattern, wherein the fourth direction is perpendicular to the third direction; and A plurality of first branch patterns and second branch patterns extend along the first direction respectively and are alternately arranged between the second boundary pattern and the pad array pattern along the fourth direction, wherein the first branch pattern is connected to the second boundary pattern, and the second branch pattern is separated from the second boundary pattern.

19. The method for manufacturing a semiconductor structure according to claim 10, wherein: Also includes: performing a first etching process using the second mask layer as an etching mask to transfer the pad array pattern and the boundary pattern into the first mask layer; as well as A second etching process is performed using the first mask layer as an etching mask to transfer the pad array pattern and the boundary pattern into the conductive material layer to obtain a pad array and boundary pads surrounding the pad array.

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