Groove type MIM capacitor and preparation method thereof
Through the back etching process, the intermediate insulation layer is protected in the trench MIM capacitor, avoiding the recessed defect caused by CMP abrasion, solving the leakage channel problem and increasing the breakdown voltage.
Patent Information
- Application Number
- CN202510293345.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-08-08
AI Technical Summary
In the existing trench MIM capacitor process, the CMP process causes the top of the intermediate insulation layer to be depressed and defective, resulting in leakage channels, resulting in smaller device leakage and breakdown voltages.
The metal upper plate layer and adhesive layer are removed by using the back etching process to avoid CMP grinding, and an anti-reflective layer is formed to protect the intermediate insulating layer and avoid recessed defects.
Eliminates leakage channels, increases the breakdown voltage of the device and prevents leakage of the device.
Smart Images
Figure CN120456568A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a trench-type MIM capacitor and a method for preparing the same. Background Art
[0002] The trench-type MIM capacitor process can effectively increase the capacitance due to its larger plate contact area, but the thickness of the capacitor's intermediate insulating layer filled with deep trenches is generally thin due to the limitations of the ALD (atomic layer deposition) process.
[0003] In the trench-type MIM capacitor process used in some specific occasions, after the tungsten metal top plate is deposited in the trench, a CMP (chemical mechanical polishing) process is usually required to flatten the tungsten metal material at the top of the trench. However, the CMP process can easily cause the intermediate insulating layer at the top of the trench to be over-polished, resulting in a concave defect at the top of the intermediate insulating layer, which in turn causes the MIM capacitor to generate a leakage channel in the trench, causing device leakage and resulting in a low breakdown voltage. Summary of the Invention
[0004] The present application provides a trench-type MIM capacitor and a preparation method thereof, which can solve the problem that the trench-type MIM capacitor process is affected by the CMP process, resulting in the intermediate insulating layer generating a leakage channel at the top of the trench, causing device leakage.
[0005] On the one hand, an embodiment of the present application provides a method for preparing a trench MIM capacitor, comprising: A semiconductor structure is provided, wherein a metal bottom plate layer, a first barrier layer and a first interlayer dielectric layer are sequentially formed on the semiconductor structure; Etching the first interlayer dielectric layer and the first barrier layer to the surface of the metal bottom plate layer to form a trench; forming a first adhesive layer, wherein the first adhesive layer covers the first interlayer dielectric layer and the sidewalls and bottom wall of the trench; forming an intermediate insulating layer, wherein the intermediate insulating layer covers the first adhesive layer; forming a second adhesive layer, wherein the second adhesive layer covers the intermediate insulating layer; forming a metal upper electrode layer, wherein the metal upper electrode layer covers the second adhesive layer and fills the remaining space of the groove; By means of an etch-back process, the metal upper plate layer and the second adhesive layer above the first interlayer dielectric layer are etched away and the etching stops on the surface of the intermediate insulating layer; forming an anti-reflection layer, wherein the anti-reflection layer covers the intermediate insulating layer and the metal upper plate layer in the groove; Etching a portion of the anti-reflection layer, a portion of the intermediate insulating layer, and a portion of the first adhesive layer on a surface of the first interlayer dielectric layer away from the groove; forming a second barrier layer, wherein the second barrier layer covers the anti-reflection layer and the first interlayer dielectric layer; A second interlayer dielectric layer is formed, where the second interlayer dielectric layer covers the second barrier layer.
[0006] Optionally, in the method for preparing the trench MIM capacitor, after forming the second interlayer dielectric layer, the method for preparing the trench MIM capacitor further comprises: A first conductive plug and a second conductive plug are formed, wherein the first conductive plug penetrates the second interlayer dielectric layer, the second barrier layer, the first interlayer dielectric layer and the first barrier layer and is connected to the metal lower plate layer, and the second conductive plug penetrates the second interlayer dielectric layer, the second barrier layer and the anti-reflection layer and is connected to the metal upper plate layer.
[0007] Optionally, in the method for preparing the trench MIM capacitor, the thickness of the intermediate insulating layer is 100 angstroms to 300 angstroms.
[0008] Optionally, in the method for preparing the trench MIM capacitor, the material of the intermediate insulating layer is Al2O3.
[0009] Optionally, in the method for preparing the trench MIM capacitor, the material of the first barrier layer and the material of the second barrier layer are both SiCN.
[0010] Optionally, in the method for preparing the trench MIM capacitor, the material of the first adhesive layer and the material of the second adhesive layer are both tungsten nitride.
[0011] Optionally, in the method for preparing the trench MIM capacitor, the anti-reflection layer is made of SiON.
[0012] On the other hand, an embodiment of the present application further provides a trench MIM capacitor, comprising: A semiconductor structure having a metal bottom plate layer, a first barrier layer, and a first interlayer dielectric layer sequentially formed thereon, wherein trenches are formed in the first interlayer dielectric layer and the first barrier layer; a first adhesive layer, wherein the first adhesive layer covers the sidewalls and bottom wall of the trench and a portion of the first interlayer dielectric layer; an intermediate insulating layer, the intermediate insulating layer covering the first adhesive layer; a second adhesive layer, wherein the second adhesive layer covers the intermediate insulating layer on the sidewall of the trench; a metal upper electrode layer, the metal upper electrode layer covering the second adhesive layer and filling a remaining space in the groove; an anti-reflection layer, the anti-reflection layer covering the intermediate insulating layer and the metal upper plate layer in the groove; a second barrier layer, the second barrier layer covering the anti-reflection layer and the first interlayer dielectric layer; A second interlayer dielectric layer covers the second barrier layer.
[0013] The technical solution of this application has at least the following advantages: The present application provides a trench-type MIM capacitor and a preparation method thereof. In the preparation method, after forming a metal top plate layer, it is not necessary to use CMP grinding to remove excess metal top plate layer. Instead, a back etching process is used to etch away the metal top plate layer and the second adhesive layer above the first interlayer dielectric layer and stop at the surface of the intermediate insulating layer. Then, an anti-reflection layer is deposited on the exposed surface of the intermediate insulating layer and the surface of the metal top plate layer in the trench. This can prevent the intermediate insulating layer at the top of the trench from being over-grinded, thereby avoiding the generation of a concave defect at the top of the intermediate insulating layer, eliminating leakage channels, eliminating leakage of the device, and improving the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0015] Figure 1 is a flow chart of a method for preparing a trench MIM capacitor according to an embodiment of the present invention; Figure 2-Figure 12 Schematic diagram of the semiconductor structure in each process step of preparing a trench MIM capacitor according to an embodiment of the present invention; The description of the accompanying drawings is as follows: 10-semiconductor structure, 11-anti-reflective layer, 12-first conductive plug, 13-second conductive plug, 20-metal lower plate layer, 31-first barrier layer, 32-second barrier layer, 41-first interlayer dielectric layer, 42-second interlayer dielectric layer, 51-first photoresist layer, 52-second photoresist layer, 60-groove, 71-first adhesion layer, 72-second adhesion layer, 80-intermediate insulating layer, 90-metal upper plate layer. DETAILED DESCRIPTION
[0016] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0017] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0018] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0019] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0020] The present invention provides a method for preparing a trench MIM capacitor. Figure 1 , Figure 1 1 is a flow chart of a method for preparing a trench MIM capacitor according to an embodiment of the present invention, wherein the method for preparing a trench MIM capacitor comprises: First, perform step S1: refer to Figure 2 , Figure 2 Schematic diagram of a semiconductor structure after forming a first interlayer dielectric layer according to an embodiment of the present application. A semiconductor structure 10 is provided, on which a metal bottom plate layer 20, a first barrier layer 31 and a first interlayer dielectric layer 41 are sequentially formed.
[0021] In this embodiment, the metal bottom plate layer 20 includes a stacked tungsten nitride layer and a metal tungsten layer from bottom to top; further, the material of the first barrier layer 31 is SiCN.
[0022] It is worth noting that the specific film layer of the semiconductor structure 10 may be a film layer in the front-end process of a conventional MOS device, and the present application does not impose any limitation on the specific film layer of the semiconductor structure 10 .
[0023] Then, execute step S2: refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the groove is formed in an embodiment of the present application. First, a first photoresist layer 51 is coated on the surface of the first interlayer dielectric layer 41, and then a groove pattern is defined on the first photoresist layer 51 through a photolithography process. Then, the patterned first photoresist layer 51 is used as a mask and a dry etching process is adopted to etch the first interlayer dielectric layer 41 and the first barrier layer 31 to the surface of the metal lower electrode layer 20 to form a groove 60.
[0024] In this embodiment, after the trench 60 is formed, the patterned first photoresist layer 51 is removed.
[0025] Next, execute step S3: refer to Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the first adhesive layer is formed in an embodiment of the present application. The first adhesive layer 71 is formed, and the first adhesive layer 71 covers the first interlayer dielectric layer 41 and the sidewalls and bottom walls of the trench 60.
[0026] Preferably, the first adhesive layer 71 is made of tungsten nitride, and the first adhesive layer 71 can provide better adhesion to the subsequently deposited intermediate insulating layer 80 .
[0027] Further, step S4 is performed: refer to Figure 5 , Figure 5 3 is a schematic diagram of a semiconductor structure after an intermediate insulating layer is formed according to an embodiment of the present application, wherein an intermediate insulating layer 80 is formed, and the intermediate insulating layer 80 covers the first adhesive layer 71 .
[0028] Preferably, the thickness of the intermediate insulating layer 80 is 100 angstroms to 300 angstroms.
[0029] In this embodiment, the material of the intermediate insulating layer 80 is Al 2 O 3 .
[0030] Then, execute step S5: refer to Figure 6 , Figure 6 3 is a schematic diagram of a semiconductor structure after forming a second adhesive layer according to an embodiment of the present application. A second adhesive layer 72 is formed, and the second adhesive layer 72 covers the intermediate insulating layer 80 .
[0031] Preferably, the material of the second adhesive layer 72 is tungsten nitride. The second adhesive layer 72 can provide better adhesion to the subsequently deposited metal top plate layer 90 .
[0032] Further, step S6 is performed: refer to Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after forming a metal upper plate layer according to an embodiment of the present application, wherein a metal upper plate layer 90 is formed, and the metal upper plate layer 90 covers the second adhesive layer 72 and fills the remaining space of the groove 60 .
[0033] In this embodiment, the metal top plate layer 90 is a metal tungsten layer.
[0034] Then, execute step S7: refer to Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure of an embodiment of the present application after the metal upper plate layer and the second adhesive layer above the first interlayer dielectric layer are etched away through a back etching process and stopped on the surface of the intermediate insulating layer. The metal upper plate layer 90 and the second adhesive layer 72 above the first interlayer dielectric layer 41 are etched away through a back etching process and stopped on the surface of the intermediate insulating layer 80.
[0035] After the etch-back process, the upper surface of the intermediate insulating layer 80 is flush with the upper surface of the metal upper plate layer 90 . Similarly, the upper surface of the intermediate insulating layer 80 is flush with the top of the second adhesive layer 72 .
[0036] Further, step S8 is performed: refer to Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the second photoresist layer is formed in an embodiment of the present application, forming an anti-reflection layer 11, which covers the intermediate insulating layer 80 and the metal upper plate layer 90 in the groove 60 and covers the top of the second adhesive layer 72 in the groove 60.
[0037] Preferably, the anti-reflection layer 11 is made of SiON.
[0038] In the present application, after forming the metal top plate layer, there is no need to use CMP (chemical mechanical polishing) to grind and remove the excess metal top plate layer. Instead, a back etching process is used to etch and remove the metal top plate layer and the second adhesive layer above the first interlayer dielectric layer and stop at the surface of the intermediate insulating layer. Then, an anti-reflective layer is deposited on the exposed surface of the intermediate insulating layer and the surface of the metal top plate layer in the groove. This can avoid the intermediate insulating layer at the top of the groove from being over-grinded, thereby avoiding the generation of a concave defect at the top of the intermediate insulating layer, eliminating the leakage channel, eliminating the leakage of the device, and improving the breakdown voltage of the device.
[0039] Then, execute step S9: continue to refer to Figure 9 , and references Figure 10 , Figure 10 This is a schematic diagram of the semiconductor structure after etching part of the anti-reflection layer, part of the intermediate insulating layer and part of the first adhesive layer on the surface of the first interlayer dielectric layer away from the groove in an embodiment of the present application. First, a second photoresist layer 52 is coated on the surface of the anti-reflection layer 11, and then the area to be removed is defined on the second photoresist layer 52 through a photolithography process. Then, using the patterned second photoresist layer 52 as a mask, part of the anti-reflection layer 11, part of the intermediate insulating layer 80 and part of the first adhesive layer 71 on the surface of the first interlayer dielectric layer 41 away from the groove 60 are etched, and finally the patterned second photoresist layer 52 is removed.
[0040] Further, step S10 is performed: refer to Figure 11 , Figure 11 3 is a schematic diagram of a semiconductor structure after forming a second interlayer dielectric layer according to an embodiment of the present application, wherein a second barrier layer 32 is formed, and the second barrier layer 32 covers the anti-reflection layer 11 and the first interlayer dielectric layer 41 .
[0041] In this embodiment, the second barrier layer 42 is made of SiCN.
[0042] Finally, execute step S11: continue to refer to Figure 11 , forming a second interlayer dielectric layer 42 , wherein the second interlayer dielectric layer 42 covers the second barrier layer 32 .
[0043] For further reference, Figure 12 , Figure 12 This is a schematic diagram of the semiconductor structure after the first conductive plug and the second conductive plug are formed in an embodiment of the present application. After the second interlayer dielectric layer 42 is formed, the method for preparing the trench MIM capacitor also includes step S12: forming a first conductive plug 12 and a second conductive plug 13, the first conductive plug 12 penetrates the second interlayer dielectric layer 42, the second barrier layer 32, the first interlayer dielectric layer 41 and the first barrier layer 31 and is connected to the metal lower electrode layer 20, the second conductive plug 13 penetrates the second interlayer dielectric layer 42, the second barrier layer 32 and the anti-reflection layer 11 and is connected to the metal upper electrode layer 90.
[0044] Based on the same inventive concept, the present application also provides a trench MIM capacitor, referring to Figure 11 , the trench MIM capacitor includes: A semiconductor structure 10, on which a metal bottom plate layer 20, a first barrier layer 31, and a first interlayer dielectric layer 41 are sequentially formed, wherein a trench 60 is formed in the first interlayer dielectric layer 41 and the first barrier layer 31; a first adhesive layer 71 , wherein the first adhesive layer 71 covers the sidewalls and bottom wall of the trench 60 and a portion of the first interlayer dielectric layer 41 ; an intermediate insulating layer 80 , wherein the intermediate insulating layer 80 covers the first adhesive layer 71 ; a second adhesive layer 72 , the second adhesive layer 72 covering the intermediate insulating layer 80 on the sidewall of the groove 60 ; a metal upper electrode layer 90 , the metal upper electrode layer 90 covering the second adhesive layer 72 and filling the remaining space of the groove 60 ; an anti-reflection layer 11, the anti-reflection layer 11 covering the intermediate insulating layer 80 and the metal upper plate layer 90 in the groove 60; a second barrier layer 32, the second barrier layer 32 covering the anti-reflection layer 11 and the first interlayer dielectric layer 41; A second interlayer dielectric layer 42 covers the second barrier layer 32 .
[0045] For further reference, Figure 12 The trench MIM capacitor also includes: a first conductive plug 12 and a second conductive plug 13, the first conductive plug 12 penetrates the second interlayer dielectric layer 42, the second barrier layer 32, the first interlayer dielectric layer 41 and the first barrier layer 31 and is connected to the metal lower electrode layer 20, the second conductive plug 13 penetrates the second interlayer dielectric layer 42, the second barrier layer 32 and the anti-reflection layer 11 and is connected to the metal upper electrode layer 90.
[0046] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A method for preparing a trench MIM capacitor, characterized in that: include: A semiconductor structure is provided, wherein a metal bottom plate layer, a first barrier layer and a first interlayer dielectric layer are sequentially formed on the semiconductor structure; Etching the first interlayer dielectric layer and the first barrier layer to the surface of the metal bottom plate layer to form a trench; forming a first adhesive layer, wherein the first adhesive layer covers the first interlayer dielectric layer and the sidewalls and bottom wall of the trench; forming an intermediate insulating layer, wherein the intermediate insulating layer covers the first adhesive layer; forming a second adhesive layer, wherein the second adhesive layer covers the intermediate insulating layer; forming a metal upper electrode layer, wherein the metal upper electrode layer covers the second adhesive layer and fills the remaining space of the groove; By means of an etch-back process, the metal upper plate layer and the second adhesive layer above the first interlayer dielectric layer are etched away and the etching stops at the surface of the intermediate insulating layer; forming an anti-reflection layer, wherein the anti-reflection layer covers the intermediate insulating layer and the metal upper plate layer in the groove; Etching a portion of the anti-reflection layer, a portion of the intermediate insulating layer, and a portion of the first adhesive layer on a surface of the first interlayer dielectric layer away from the groove; forming a second barrier layer, wherein the second barrier layer covers the anti-reflection layer and the first interlayer dielectric layer; A second interlayer dielectric layer is formed, where the second interlayer dielectric layer covers the second barrier layer.
2. The method for preparing a trench MIM capacitor according to claim 1, wherein: After forming the second interlayer dielectric layer, the method for preparing the trench MIM capacitor further includes: A first conductive plug and a second conductive plug are formed, wherein the first conductive plug penetrates the second interlayer dielectric layer, the second barrier layer, the first interlayer dielectric layer and the first barrier layer and is connected to the metal lower plate layer, and the second conductive plug penetrates the second interlayer dielectric layer, the second barrier layer and the anti-reflection layer and is connected to the metal upper plate layer.
3. The method for preparing a trench MIM capacitor according to claim 1, wherein: The thickness of the intermediate insulating layer is 100 angstroms to 300 angstroms.
4. The method for preparing a trench MIM capacitor according to claim 1, wherein: The material of the intermediate insulating layer is Al2O3.
5. The method for preparing a trench MIM capacitor according to claim 1, wherein: The material of the first barrier layer and the material of the second barrier layer are both SiCN.
6. The method for preparing a trench MIM capacitor according to claim 1, wherein: The material of the first adhesive layer and the material of the second adhesive layer are both tungsten nitride.
7. The method for preparing a trench MIM capacitor according to claim 1, wherein: The anti-reflection layer is made of SiON.
8. A trench MIM capacitor, characterized in that: include: A semiconductor structure having a metal bottom plate layer, a first barrier layer, and a first interlayer dielectric layer sequentially formed thereon, wherein trenches are formed in the first interlayer dielectric layer and the first barrier layer; a first adhesive layer, wherein the first adhesive layer covers the sidewalls and bottom wall of the trench and a portion of the first interlayer dielectric layer; an intermediate insulating layer, the intermediate insulating layer covering the first adhesive layer; a second adhesive layer, wherein the second adhesive layer covers the intermediate insulating layer on the sidewall of the trench; a metal upper electrode layer, the metal upper electrode layer covering the second adhesive layer and filling a remaining space in the groove; an anti-reflection layer, the anti-reflection layer covering the intermediate insulating layer and the metal upper plate layer in the groove; a second barrier layer, the second barrier layer covering the anti-reflection layer and the first interlayer dielectric layer; A second interlayer dielectric layer covers the second barrier layer.