Ring gate nanosheet field effect transistor, electronic device and preparation method thereof

Abstract

The invention relates to the technical field of field effect transistors, and discloses a gate-all-around nanosheet field effect transistor, an electronic device and a preparation method of the gate-all-around nanosheet field effect transistor. The channel is positioned on the surface of one side of the substrate; the channels comprise first sub-channels parallel to the horizontal direction and second sub-channels parallel to the vertical direction, and the second sub-channels in the vertical direction are at least in contact with the two first sub-channels; the source region and the drain region are connected through a channel; a gate structure at least partially surrounding the channel; a gate dielectric of the gate structure fills a space between the first sub-channel and the second sub-channel. Through the arrangement of the first sub-channels and the second sub-channels, channels which are distributed in a transverse and vertical staggered manner can be formed, so that more contact surfaces exist between the gate structure and the channels, it is ensured that the ring gate nanosheet field effect transistor has a large channel transmission area, and then it is ensured that the ring gate nanosheet field effect transistor has higher performance.

Description

Technical Field

[0001] The present application relates to the technical field of field effect transistors, and in particular to a ring-gate nanosheet field effect transistor, an electronic device, and a method for preparing a ring-gate nanosheet field effect transistor. Background Art

[0002] Due to the continued scaling of process nodes, the GAA (Gate-All-Around Field Effect Transistor) architecture has become the industry's mainstream next-generation architecture due to its superior gate control capabilities and outstanding performance, and has been successfully mass-produced. It uses nanosheets (NS) as its channel. Currently, increasing the width and number of nanosheets is the key to improving GAA performance. However, a wider NS leads to a decrease in transistor density, and an increase in the number of NS stacks leads to higher aspect ratio etching, which also increases the overall process difficulty. Therefore, how to provide a new gate-all-around nanosheet field-effect transistor that can effectively increase the channel transmission area is an urgent problem for those skilled in the art. Summary of the Invention

[0003] The present application discloses a ring-gate nanosheet field-effect transistor and an electronic device having a large channel transmission area; another object of the present invention is to provide a method for preparing a ring-gate nanosheet field-effect transistor, wherein the prepared ring-gate nanosheet field-effect transistor has a large channel transmission area.

[0004] In a first aspect, the present application provides a ring-gate nanosheet field-effect transistor, comprising: a substrate; a channel located on a surface of one side of the substrate; the channel comprising a first sub-channel parallel to the horizontal direction and a second sub-channel parallel to the vertical direction, wherein the second sub-channel is in contact with at least one of the first sub-channels in the vertical direction; a source region and a drain region connected by the channel; a gate structure at least partially surrounding the channel; and a gate dielectric of the gate structure filling the space between the first sub-channel and the second sub-channel.

[0005] By setting the first sub-channel and the second sub-channel, a channel with a horizontally and vertically staggered distribution can be formed, so that there are more contact surfaces between the gate structure and the channel, ensuring that the ring-gate nanosheet field-effect transistor has a larger channel transmission area, and thus ensuring that the ring-gate nanosheet field-effect transistor has higher performance.

[0006] In one possible implementation, the second sub-channel is connected to all of the first sub-channels and extends to the substrate. This structure can maximize the contact area between the channel and the gate structure and can provide some support during the fabrication process.

[0007] In one possible embodiment, the channel extends along a length and includes at least two channel segments along the length. The gate structure at least partially surrounds the channel segments, and the source region or the drain region is disposed between adjacent channel segments. Both the source region and the drain region need to be in contact with both the first sub-channel and the second sub-channel. This structure, by arranging the source region or the drain region between the channel segments, facilitates the integration of gate-all-around nanosheet field-effect transistors.

[0008] In one possible implementation, at least two gate structures are included, one gate structure surrounds one channel segment, and adjacent gate structures are isolated from each other. Providing multiple gate structures corresponding to the channel segments can facilitate the integration of gate-all-around nanosheet field-effect transistors.

[0009] In one possible embodiment, the gate structure includes a gate electrode disposed on a side of the channel away from the substrate, adjacent gate electrodes are isolated from each other by an insulating dielectric, and the gate dielectric filling the gap between the first sub-channel and the second sub-channel is isolated from the source region or the drain region by an inner sidewall. The inner sidewall and the insulating dielectric ensure isolation between the gate structure and the source and drain regions.

[0010] In a possible embodiment, at least two channels are provided along the width direction, and adjacent channels are separated from each other. Providing multiple channels can facilitate the integration of the gate-all-around nanosheet field-effect transistor.

[0011] In one possible embodiment, a gate structure surrounds at least two of the channels along the width direction, the gate dielectric fills the gap between adjacent channels, and an isolation dielectric is provided on the side of the gate dielectric between adjacent channels facing the substrate. In this case, a single gate structure can control multiple channels, facilitating the integration of gate-all-around nanosheet field-effect transistors.

[0012] In one possible implementation, the source region and the drain region are in contact with a plurality of the channels along the width direction. In this case, multiple channels are provided between the source region and the drain region, and this structure facilitates the integration of gate-all-around nanosheet field-effect transistors.

[0013] In a second aspect, the present application provides an electronic device comprising a gate-all-around nanosheet field-effect transistor as described in any of the above. The arrangement of the first and second sub-channels can form channels that are staggered horizontally and vertically, thereby increasing the contact surface between the gate structure and the channel, ensuring that the gate-all-around nanosheet field-effect transistor has a larger channel transmission area, thereby ensuring that the gate-all-around nanosheet field-effect transistor has higher performance.

[0014] In a third aspect, the present application provides a method for preparing a gate-all-around nanosheet field-effect transistor, comprising:

[0015] Arranging a nanosheet on the surface of the substrate; the nanosheet includes sacrificial layers and first sub-channels alternately stacked along the thickness direction;

[0016] Etching the nanosheet along a thickness direction to form a first groove;

[0017] A second sub-channel is provided in the first trench; the second sub-channel contacts at least one of the first sub-channels in a vertical direction to form a channel;

[0018] A ring-gate nanosheet field-effect transistor is prepared based on a nanosheet provided with the second sub-channel; the ring-gate nanosheet field-effect transistor includes a source region and a drain region connected by the channel; a gate structure at least partially surrounding the channel; and a gate dielectric of the gate structure fills the space between the first sub-channel and the second sub-channel.

[0019] By setting the first sub-channel and the second sub-channel, a channel with a horizontally and vertically staggered distribution can be formed, so that there are more contact surfaces between the gate structure and the channel, ensuring that the ring-gate nanosheet field-effect transistor has a larger channel transmission area, and thus ensuring that the ring-gate nanosheet field-effect transistor has higher performance.

[0020] In a possible implementation, etching the nanosheet along the thickness direction to form the first groove includes:

[0021] Etching the nanosheet at least to the bottommost first sub-channel in a thickness direction to form a first groove;

[0022] The providing a second sub-channel in the first trench comprises:

[0023] The second sub-channel is epitaxially grown from bottom to top in the first trench, connecting the second sub-channel to all the first sub-channels. This structure can maximize the contact area between the channel and the gate structure and provide a certain support during the fabrication process.

[0024] In one possible embodiment, preparing a gate-all-around nanosheet field-effect transistor based on a nanosheet provided with the second sub-channel includes:

[0025] Etching the nanosheet provided with the second sub-channel to form at least two sub-nanosheets, each of the sub-nanosheets including at least one second sub-channel;

[0026] An isolation medium is provided at the bottom between adjacent sub-nanosheets.

[0027] By etching out the sub-nanosheets, multiple channels can be made subsequently, simplifying the preparation process of the ring-gate nanosheet field-effect transistor integration.

[0028] In one possible embodiment, preparing a gate-all-around nanosheet field-effect transistor based on a nanosheet provided with the second sub-channel includes:

[0029] At least two dummy gates are provided on a surface of the nanosheet away from the substrate; the dummy gates extend along the width direction, and adjacent dummy gates are separated from each other;

[0030] Disposing a gate sidewall on the side of the dummy gate;

[0031] Etching the nanosheet from a position between the opposite gate sidewalls to form a second trench; the sidewalls of the second trench expose the channel and the sacrificial layer, and a recess is formed between an end surface of the sacrificial layer exposed by the sidewalls of the second trench and an end surface of the trench;

[0032] providing an inner side wall in the recess;

[0033] A source region and a drain region are grown in the second trench provided with the inner sidewall based on the exposed channel as an epitaxial substrate.

[0034] Since the channel exposed by the sidewall of the second trench includes a first sub-channel extending laterally and a second sub-channel extending vertically, it can have a continuous interface when used as a substrate, providing an ideal growth interface for subsequent epitaxial growth of the source and drain regions, thereby achieving high-stress defect-free source and drain epitaxial growth.

[0035] In a possible implementation manner, after growing the source region or the drain region, the method further includes:

[0036] Filling an insulating medium between the opposite gate sidewalls;

[0037] After filling the insulating medium, removing the dummy gate and releasing the sacrificial layer to form a space to be filled;

[0038] A gate dielectric is provided in the space to be filled to form the gate structure.

[0039] Due to the support of the second sub-channel, in this step, the sacrificial layer can be released at one time and then the gate dielectric can be set, thereby simplifying the device manufacturing process.

[0040] In a possible implementation manner, after forming the space to be filled, the method further includes:

[0041] The first sub-channel and the second sub-channel are thinned to a target thickness.

[0042] This solution supports first setting a thicker first sub-channel and second sub-channel and then thinning them, so as to further ensure high stress defect-free source and drain epitaxial growth when growing the source and drain regions.

[0043] In a possible implementation, thinning the first sub-channel and the second sub-channel to a target thickness includes:

[0044] A cycle of oxidation etching is performed on the first sub-channel and the second sub-channel to thin the first sub-channel and the second sub-channel.

[0045] This method can accurately form the first sub-channel and the second sub-channel of target thickness, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 A schematic front view of a gate-all-around nanosheet field-effect transistor provided by an embodiment of the present invention;

[0048] Figure 2 for Figure 1 Schematic diagram of the top view structure;

[0049] Figure 3 Schematic diagram of the structures of various channels provided by embodiments of the present invention;

[0050] Figure 4 A schematic cross-sectional view of a gate-all-around nanosheet field-effect transistor along the CC' plane provided by an embodiment of the present invention;

[0051] Figure 5 A schematic top view of a specific gate-all-around nanosheet field-effect transistor provided by an embodiment of the present invention;

[0052] Figure 6 A schematic cross-sectional view of a specific gate-all-around nanosheet field-effect transistor along the AA' plane provided by an embodiment of the present invention;

[0053] Figure 7 A schematic cross-sectional structure diagram of a specific gate-all-around nanosheet field-effect transistor along plane BB' provided by an embodiment of the present invention;

[0054] Figures 8 to 11 A process flow chart of a method for preparing a gate-all-around nanosheet field-effect transistor provided by an embodiment of the present invention;

[0055] Figures 12 to 29A process flow chart of a specific method for preparing a gate-all-around nanosheet field-effect transistor provided in an embodiment of the present invention.

[0056] Description of reference numerals:

[0057] 1-substrate;

[0058] 2-channel;

[0059] 21 - first sub-channel; 22 - second sub-channel; 23 - sacrificial layer;

[0060] 3- Source area;

[0061] 4-drain area;

[0062] 5-gate structure;

[0063] 51-dummy gate; 52-gate electrode;

[0064] 6-Isolation medium;

[0065] 7-gate sidewall;

[0066] 8-Insulation medium;

[0067] 9-Inner wall;

[0068] 101-first groove;

[0069] 102-second groove;

[0070] 103-Space to be filled. DETAILED DESCRIPTION

[0071] The ring-gate nanosheet field-effect transistor provided in this application has a larger channel transmission area and has better performance than the traditional GAA architecture.

[0072] Example 1

[0073] Please refer to Figures 1 to 3 , Figure 1 A schematic front view of a gate-all-around nanosheet field-effect transistor provided by an embodiment of the present invention; Figure 2 for Figure 1 Schematic diagram of the top view structure; Figure 3 Schematic diagram of the structures of various channels provided by embodiments of the present invention.

[0074] See also Figure 1 as well as Figure 2In an embodiment of the present invention, a gate-all-around nanosheet field-effect transistor includes: a substrate 1; a channel 2 located on a surface of one side of the substrate 1; the channel 2 includes a first sub-channel 21 parallel to the horizontal direction and a second sub-channel 22 parallel to the vertical direction, wherein the second sub-channel 22 contacts at least one first sub-channel 21 in the vertical direction; a source region 3 and a drain region 4 connected by the channel 2; a gate structure 5 at least partially surrounding the channel 2; and a gate dielectric of the gate structure 5 filling the space between the first sub-channel 21 and the second sub-channel 22.

[0075] The above-mentioned substrate 1 is the substrate 1 used to prepare the functional structure in the ring-gate nanosheet field-effect transistor. The substrate 1 is usually silicon. Of course, the specific material and structure of the substrate 1 can refer to the existing technology. In this embodiment, the specific material of the substrate 1 is not specifically limited.

[0076] In this embodiment, a channel 2 is provided on the surface of the substrate 1, and the channel 2 serves as a channel for transmitting current between the source region 3 and the drain region 4 in the ring-gate nanosheet field-effect transistor. In this embodiment, the channel 2 generally includes a first sub-channel 21 and a second sub-channel 22, wherein the first sub-channel 21 is arranged horizontally, the second sub-channel 22 is arranged vertically, and the second sub-channel 22 is in contact with at least one first sub-channel 21, so that the first sub-channel 21 and the second sub-channel 22 form a fixed connection structure. The materials of the first sub-channel 21 and the second sub-channel 22 can be the same or different, and their materials are generally Si. Of course, they can also be SiGe, SiC, Ge, etc., which are not specifically limited here. When the material of the first sub-channel 21 is the same as that of the second sub-channel 22, the firmness between the two can be improved.

[0077] See also Figure 3 In this embodiment, the channel 2 has an extension direction, which is the length direction. In the horizontal plane, the direction perpendicular to the length direction is the width direction. The first sub-channel 21 and the second sub-channel 22 usually need to extend along the length direction. In the width direction, the second sub-channel 22 can be located at the center of the first sub-channel 21, that is, arranged along the central axis of the first sub-channel 21, or can be arranged offset from the center of the first sub-channel 21. The first sub-channel 21 can contact more than two first sub-channels 21, or can only contact two first sub-channels 21, or can only contact one first sub-channel 21. Usually, in this embodiment, the second sub-channel 22 contacts at least two adjacent first sub-channels 21. The second sub-channel 22 can protrude or not protrude from the topmost first sub-channel 21, or can protrude or not protrude from the bottommost first sub-channel 21. Its specific structure can be set according to actual conditions and is not specifically limited here.

[0078] Preferably, in this embodiment, the second sub-channel 22 is connected to all the first sub-channels 21 and extends to the substrate 1. This structure can connect the traditionally separated first sub-channels 21 to each other into a whole through the second sub-channel 22, and the connection of the second sub-channel 22 to the substrate 1 can increase the support of the entire channel 2, which can improve the yield rate of device preparation during the preparation process. It should be noted that in this embodiment, usually only one second sub-channel 22 is provided for one channel 2 to avoid multiple second sub-channels 22 and the first sub-channel 21 forming a cavity that is not connected to the outside world.

[0079] The source region 3 and the drain region 4 of the above-mentioned ring-gate nanosheet field-effect transistor will be connected through the above-mentioned channel 2. The specific positions of the source region 3 and the drain region 4 will be described in detail in the following embodiments and will not be repeated here. The above-mentioned gate structure 5 is arranged at least partially around the above-mentioned channel 2 to control the current flowing in the channel 2 during operation. The gate structure 5 usually includes a gate electrode 52 and a gate dielectric, wherein the gate electrode 52 is usually arranged on the surface of the channel 2 facing away from the substrate 1, and the gate dielectric will cover the channel 2. In this embodiment, the gate dielectric needs to fill the space between the above-mentioned first sub-channel 21 and the second sub-channel 22 to ensure that there is sufficient contact area between the above-mentioned channel 2 and the gate structure 5.

[0080] The ring-gate nanosheet field-effect transistor provided in this embodiment can form a channel 2 that is staggered horizontally and vertically by setting the first sub-channel 21 and the second sub-channel 22, so that there are more contact surfaces between the gate structure 5 and the channel 2, ensuring that the ring-gate nanosheet field-effect transistor has a higher channel 2 transmission area, thereby ensuring that the ring-gate nanosheet field-effect transistor has higher performance.

[0081] The specific structure of the ring-gate nanosheet field-effect transistor provided in this application will be described in detail in the following embodiments.

[0082] Example 2

[0083] Please refer to Figures 4 to 7 , Figure 4 A schematic cross-sectional view of a gate-all-around nanosheet field-effect transistor along the CC' plane provided by an embodiment of the present invention; Figure 5 A schematic top view of a specific gate-all-around nanosheet field-effect transistor provided by an embodiment of the present invention; Figure 6 A schematic cross-sectional view of a specific gate-all-around nanosheet field-effect transistor along the AA' plane provided by an embodiment of the present invention; Figure 7 This is a schematic cross-sectional structural diagram of a specific gate-all-around nanosheet field-effect transistor along plane BB' provided by an embodiment of the present invention.

[0084] Different from the above embodiment, this embodiment further defines the source region 3, the drain region 4, the gate structure 5 and other structures based on the above embodiment. The remaining contents have been described in detail in the above embodiment and will not be repeated here.

[0085] See also Figures 4 to 7 In this embodiment, the channel 2 extends along the length direction, and the channel 2 includes at least two channel segments along the length direction. The gate structure 5 at least partially surrounds the channel segment, and the source region 3 or the drain region 4 is arranged between adjacent channel segments. The source region 3 and the drain region 4 need to be in contact with the first sub-channel 21 and the second sub-channel 22 at the same time.

[0086] Along the length of the channel 2, in this embodiment, the channel 2 can be divided into at least two channel segments by etching or other methods. In this case, each channel segment includes a first sub-channel 21 and a second sub-channel 22. The gate structure 5 specifically surrounds each channel segment at least partially, thereby forming a ring-gate nanosheet field-effect transistor based on each channel segment. At this time, there is a gap between adjacent channel segments, in which a source region 3 or a drain region 4 can be set. That is, a source region 3 or a drain region 4 is set between adjacent channel segments. Generally speaking, only one of the source region 3 or the drain region 4 is set between adjacent channel segments, and along the above-mentioned length direction, the source region 3 and the drain region 4 are usually alternately arranged. In this embodiment, the material of the source region 3 and the drain region 4 is generally the same. For example, SiGe can be used as the source region 3 and the drain region 4. However, the doping concentration of the source region 3 and the drain region 4 may be different. The specific material and composition of the source region 3 and the drain region 4 can be set according to actual conditions and are not specifically limited here. In this embodiment, both the source region 3 and the drain region 4 need to be in contact with the first sub-channel 21 and the second sub-channel 22 at the same time, so that the source region 3 and the drain region 4 are connected through the combined structure of the first sub-channel 21 and the second sub-channel 22. Therefore, in this embodiment, the structure along the length direction of the channel 2 is generally as follows: channel section → source region 3 → channel section → drain region 4 → channel section.

[0087] Accordingly, in this embodiment, at least two gate structures 5 may be included, with one gate structure 5 surrounding one channel segment, and adjacent gate structures 5 isolated from each other. Based on the multiple channel segments arranged along the length direction, multiple gate structures 5 are correspondingly provided, with one gate structure 5 surrounding one channel segment. Multiple gate structures 5 are distributed along the length direction, and adjacent gate structures 5 are isolated from each other. The gate dielectric in the gate structure 5 fills the space between the first sub-channel 21 and the second sub-channel 22 in the channel segment.

[0088] In this embodiment, the gate structure 5 includes a gate electrode 52 disposed on the side of the channel 2 away from the substrate 1. Adjacent gate electrodes 52 are isolated from each other by an insulating dielectric 8. The gate dielectric filling the first sub-channel 21 and the second sub-channel 22 is isolated from the source region 3 or the drain region 4 by an inner sidewall 9. The gate structure 5 includes a gate electrode 52 disposed on the side of the channel 2 away from the substrate 1. The gate electrode 52 is typically fabricated based on a dummy gate 51. The gate structure 5 also includes a gate dielectric filling the channel 2. The material filling the gate electrode 52 typically includes a high-k (HK) material, which is typically used as a gate dielectric layer. The above-mentioned gate dielectric generally includes a work function (WF) material and a dipole-related material. For the specific material of the gate structure 5, reference may be made to the prior art. In this embodiment, the gate dielectric is a dielectric material used to constitute the gate structure 5, which is a general term for the materials used in the gate structure 5. The material provided in the above-mentioned gate electrode 52 also belongs to the gate dielectric in this embodiment. In this application, the gate dielectric needs to fill the space between the first sub-channel 21 and the second sub-channel 22 to ensure surrounding coverage of the channel 2.

[0089] The side of the gate electrode 52 is usually provided with a gate sidewall 7, and the outer side of the gate sidewall 7 is usually filled with an insulating dielectric 8, so that the gate electrodes 52 are isolated from each other. As for the gate dielectric filled between the first sub-channel 21 and the second sub-channel 22, it is necessary to ensure isolation from the source region 3 or the drain region 4. In this embodiment, an inner sidewall 9 is set between the gate dielectric and the corresponding source region 3 and drain region 4, and isolation is performed based on the inner sidewall 9. The gate sidewall 7 usually includes a low-K material layer in direct contact with the gate electrode 52, and a protective layer located on the surface of the low-K material layer away from the gate electrode 52. The protective layer can be SiN or the like. The specific material of the gate sidewall 7 can be set according to actual conditions and is not specifically limited here. The inner sidewall 9 needs to ensure isolation between the gate dielectric and the source region 3 and drain region 4. The inner sidewall 9 cannot block the contact between the source region 3, drain region 4 and the channel 2.

[0090] In this embodiment, at least two channels 2 are provided along the width direction, with adjacent channels 2 separated from each other. That is, in this embodiment, multiple channels 2 can be provided on the surface of substrate 1. These channels 2 are typically arranged sequentially along the width direction, with each channel 2 parallel to the length direction and to each other, and each channel 2 includes the first sub-channel 21 and the second sub-channel 22. Providing multiple channels 2 in substrate 1 facilitates the integrated configuration of multiple gate-all-around nanosheet field-effect transistors.

[0091] In this embodiment, the gate structure 5 surrounds at least two of the channels 2 along the width direction, and the gate dielectric fills between adjacent channels 2. That is, the gate structure 5 can specifically extend along the width direction, thereby surrounding at least two channels 2 in the width direction. Correspondingly, the gate dielectric of the gate structure 5 will specifically fill between adjacent channels 2. At this time, one gate structure 5 can control the current transmitted by at least two channels 2. Specifically, in this embodiment, an isolation dielectric 6 is provided on the side of the gate dielectric located between adjacent channels 2 facing the substrate 1. The isolation dielectric 6 is used to increase the isolation between the two channels 2, and the isolation dielectric 6 is usually provided at the bottom between the two adjacent channels 2. The specific material of the isolation dielectric 6 is not specifically limited in this embodiment and depends on the specific situation.

[0092] Please refer to Figure 3 When multiple channels 2 are provided in the width direction, the combined structure of the multiple channels 2 can be Figure 3 Any combination of the various channels 2 shown, for example, all of Figure 3 (g) The combination of channels 2 shown, or alternate arrangement Figure 3 (e) with Figure 3 Any combination of the channels 2 shown in (f) is possible and is not particularly limited here.

[0093] Accordingly, in this embodiment, the source region 3 and the drain region 4 can contact multiple channels 2 along the width direction. That is, the source region 3 and the drain region 4 can also be extended along the width direction, and the source region 3 and the drain region 4 can be in contact with each other through multiple channels 2, and the corresponding multiple channels 2 are simultaneously controlled accordingly. In this embodiment, each channel 2 can include multiple channel segments along the length direction, and multiple channels 2 can be provided in total along the width direction to form an integrated gate-all-around nanosheet field-effect transistor structure.

[0094] Example 3

[0095] This embodiment further provides an electronic device comprising a gate-all-around nanosheet field-effect transistor provided by any of the above-mentioned embodiments. The specific structure of the gate-all-around nanosheet field-effect transistor has been described in detail in the above-mentioned embodiments and will not be repeated here.

[0096] Since the electronic device provided by this embodiment, such as a chip, is provided with the above-mentioned ring-gate nanosheet field-effect transistor, the chip can have higher performance.

[0097] Example 4

[0098] Please refer to Figures 8 to 11 , Figures 8 to 11This is a process flow chart of a method for preparing a gate-all-around nanosheet field-effect transistor provided by an embodiment of the present invention.

[0099] See also Figure 8 In an embodiment of the present invention, a method for preparing a gate-all-around nanosheet field-effect transistor includes:

[0100] S101: Arrange nanosheets on the substrate surface.

[0101] See also Figure 9 In this embodiment, the nanosheet includes sacrificial layers 23 and first sub-channels 21 alternately stacked along the thickness direction. The nanosheet is typically made of two materials, such as SiGe / Si, by superlattice epitaxial growth on the surface of a substrate 1. One of the two materials is the sacrificial layer 23, and the other is the material required to form the first sub-channel 21. For example, in a SiGe / Si stacked nanosheet, SiGe is typically used as the sacrificial layer 23, and sheet-like Si is typically used as the first sub-channel 21. Specific materials include, but are not limited to, Si / SiGe / SiC / Ge / SiP, and combinations thereof.

[0102] S102: Etching the nanosheet along the thickness direction to form a first groove.

[0103] See also Figure 10 In this embodiment, the first groove 101 usually connects at least two layers of the first sub-channels 21. Of course, the first groove 101 can also only expose or pass through the topmost layer of the first sub-channel 21. The first groove 101 is used to set the second sub-channel 22. In this step, the nanosheet needs to be etched along the thickness direction. Specifically, in this step, a grinding layer can be first introduced on the surface of the nanosheet. Then, based on the photolithography and etching process, the first groove 101 is formed at the position where the first sub-channel 21 needs to be set. The first groove 101 will specifically extend along the length direction. The width of the first groove 101 can be equal to or slightly larger than the target width of the second sub-channel 22. When the width of the first groove 101 is larger than the target width of the second sub-channel 22, the second sub-channel 22 usually needs to be thinned in subsequent steps to reach the target width. In this step, the width of the first groove 101 is usually between 6nm and 17nm.

[0104] Specifically, in this embodiment, when the second sub-channel 22 is required to contact all the first sub-channels 21, the first groove 101 needs to extend to the bottom first sub-channel 21 or pass through the bottom first sub-channel 21 along the thickness direction. Accordingly, this step may specifically include: etching the nanosheet at least to the bottom first sub-channel 21 along the thickness direction to form the first groove 101. When the second sub-channel 22 is required to contact all the first sub-channels 21 and extend to the substrate 1 to provide certain support performance, the first groove 101 needs to extend to the substrate 1 along the thickness direction; the corresponding second sub-channel 22 will be connected to all the first sub-channels 21 and extend to the substrate 1. Accordingly, this step may specifically include: etching the nanosheet at least to the substrate 1 along the thickness direction to form the first groove 101.

[0105] S103: Disposing a second sub-channel in the first trench.

[0106] See also Figure 11 In this embodiment, the second sub-channel 22 is in contact with at least two of the first sub-channels 21 in the vertical direction to form a channel 2. The specific structures of the first sub-channel 21 and the second sub-channel 22 have been described in detail in the above embodiments and will not be repeated here. In this step, the material corresponding to the second sub-channel 22 is usually grown in the first trench 101 by bottom-up epitaxial growth to form the second sub-channel 22. The material grown in the first trench 101 in this step can be Si or a combination of other epitaxial materials, such as SiGe, SiC, Ge, etc., which are not specifically limited here. See Figure 3 It should be noted that, in this embodiment, according to the different depths of the first trench 101, Figure 3 The channel 2 of structures (a), (b), and (g) can be realized by combining the depth of the first groove 101, the thickness of the groove mask, and the height control of the epitaxial growth of the second sub-channel 22. The above-mentioned groove mask is a mask layer provided on the surface of the nanosheet when etching the first groove 101. On the other hand, the position of the first groove 101 and the etching depth can be controlled to realize the channel 2 of structures (e) and (f). The types shown in the figure are just examples of key types based on the position, depth, and epitaxial growth height of the first groove 101. The actual covered structures are not limited to the examples already listed.

[0107] Specifically, in this embodiment, in order to maximize the contact area between the channel 2 and the gate structure 5, and to enable the second sub-channel 22 to provide a certain support to the channel 2 as a whole during the preparation process, the above-mentioned S102 may specifically include: etching the nanosheet to the substrate 1 along the thickness direction to form a first trench 101, at which time the first trench 101 will extend to the substrate 1 along the thickness direction. Correspondingly, this step S103 may specifically include: epitaxially growing the second sub-channel 22 from bottom to top in the first trench 101, so that the second sub-channel 22 is connected to all the first sub-channels 21, at which time the second sub-channel 22 will be connected to all the first sub-channels 21 and extend to the substrate 1 to play the above-mentioned role. The channel 2 of this structure can also provide a larger area of continuous epitaxial substrate when the source region 3 and the drain region 4 are subsequently grown.

[0108] S104: preparing a gate-all-around nanosheet field-effect transistor based on the nanosheet provided with the second sub-channel.

[0109] In this embodiment, the gate-all-around nanosheet field-effect transistor includes a source region 3 and a drain region 4 connected by a channel 2; a gate structure 5 at least partially surrounding the channel 2; and a gate dielectric of the gate structure 5 filling the space between the first sub-channel 21 and the second sub-channel 22. The specific structure of the gate-all-around nanosheet field-effect transistor has been described in detail in the above embodiments and will not be repeated here.

[0110] The present embodiment provides a method for preparing a ring-gate nanosheet field-effect transistor. By setting the first sub-channel 21 and the second sub-channel 22, a channel 2 that is staggered horizontally and vertically can be formed, so that there are more contact surfaces between the gate structure 5 and the channel 2, ensuring that the ring-gate nanosheet field-effect transistor has a higher channel 2 transmission area, thereby ensuring that the ring-gate nanosheet field-effect transistor has higher performance.

[0111] The specific content of the preparation method of the ring-gate nanosheet field-effect transistor will be described in detail in the following examples.

[0112] Example 5

[0113] Please refer to Figures 12 to 29 , Figures 12 to 29 A process flow chart of a specific method for preparing a gate-all-around nanosheet field-effect transistor provided in an embodiment of the present invention.

[0114] See also Figure 12 In an embodiment of the present invention, a method for preparing a gate-all-around nanosheet field-effect transistor includes:

[0115] S201: Arrange nanosheets on the surface of a substrate.

[0116] S202: Etching the nanosheet along the thickness direction to form a first groove.

[0117] In this step, it is usually necessary to first deposit a mask layer such as a hard mask (HM) on the surface of the nanosheet as a trench mask. In subsequent steps, different heights of the trench mask can be realized based on the different thicknesses of the trench mask. Figure 3 The structures (c), (d), and (h) in .

[0118] S203: Disposing a second sub-channel in the first trench.

[0119] See also Figure 13 as well as Figure 14 The above S201 to S203 are basically the same as S101 to S103 in the above embodiment. The difference lies in the position and number of the first channel 2, and the position and number of the second sub-channel 22. Please refer to the above embodiment for details and will not be repeated here.

[0120] S204: etching the nanosheet provided with the second sub-channel to form at least two sub-nanosheets, each sub-nanosheet including the second sub-channel.

[0121] See also Figure 15 In the process of etching to form the first groove 101 and setting the second sub-channel 22, a plurality of second sub-channels 22 extending along the length direction and distributed in parallel in the width direction can be set in the nanosheet. In this step, the nanosheet can be etched to form multiple sub-nanosheets, and each sub-nanosheet can form a channel 2. Specifically, in this step, a mask layer needs to be deposited on the surface of the nanosheet first, and then the sub-nanosheets are formed through multiple patterning processes such as SADP (Self-Aligned Double Patterning), SAQP (Self-Aligned Quadruple Patterning), or single photolithography and etching.

[0122] S205: Setting an isolation medium on the surface of the sub-nanosheet.

[0123] See also Figure 16 In this step, isolation material can be firstly filled between adjacent sub-nanosheets by processes such as FCVD (Flowable Chemical Vapor Deposition) and atomic layer deposition, and then planarized and finally etched back to form an isolation medium 6 disposed on the surface of the sub-nanosheet. Specifically, the isolation medium 6 can be a structure such as an oxide layer. The specific material of the isolation medium 6 is not specifically limited in this embodiment.

[0124] S206: Disposing at least two dummy gates on a surface of the nanosheet away from the substrate.

[0125] See also Figure 17 as well as Figure 18 ,in Figure 17 is the cross-sectional view of the structure along AA' in this step, Figure 18 This is a cross-sectional view of the structure along BB' in this step. In this embodiment, the dummy gate 51 extends along the width direction, and adjacent dummy gates 51 are separated from each other. The dummy gate 51 is a temporary structure for preparing the gate structure 5. The specific structure of the dummy gate 51 can refer to the existing technology. It usually includes a medium such as polysilicon and will not be described in detail here. The dummy gate 51 will specifically extend along the width direction to extend to the surfaces of multiple sub-nanosheets, and multiple dummy gates 51 will be arranged in sequence in the length direction, with gaps between adjacent dummy gates 51.

[0126] S207: Setting gate sidewalls on the sides of the dummy gate.

[0127] See also Figure 19 as well as Figure 20 ,in Figure 19 is the cross-sectional view of the structure along AA' in this step, Figure 20 This is a cross-sectional view of the structure along line BB' in this step. In this step, a low-K material and a protective layer such as SiN are sequentially deposited on the dummy gate 51 to form a gate spacer 7. The gate spacer 7 needs to cover at least the side surfaces of the dummy gate 51, and gaps are typically left between adjacent gate spacers 7 for forming the source region 3 and the drain region 4.

[0128] S208: Etching the nanosheet from a position between opposite gate sidewalls to form a second trench.

[0129] See also Figure 21 as well as Figure 22 ,in Figure 21 is the cross-sectional view of the structure along AA' in this step, Figure 22 In this embodiment, the sidewalls of the second trench 102 expose the channel 2 and the sacrificial layer 23 , and a recess is formed between the exposed end surface of the sacrificial layer 23 and the trench end surface.

[0130] In this step, the nanosheet is specifically groove-etched from the position between adjacent gate sidewalls 7. In this step, the protective layer and low-K material on the top of the pseudo gate 51 can be etched away to expose the top of the pseudo gate 51, and the nanosheet is etched along the thickness direction to form a second groove 102. The second groove 102 usually extends to the substrate 1. The sidewall of the second groove 102 exposes the cross-sectional structure of the nanosheet along the width direction, that is, the sidewall of the second groove 102 exposes the channel 2 structure formed by the combination of the first sub-channel 21 and the second sub-channel 22, and the sacrificial layer 23 located between the first sub-channel 21 and the second sub-channel 22.

[0131] The above-mentioned recess is mainly formed by the high selectivity lateral etching between the sacrificial layer 23 and the channel 2 material. For example, when the sacrificial layer 23 is SiGe and the channel 2 material is Si, the high selectivity lateral etching can result in different etching rates for the sacrificial layer 23 and the channel 2 material, thereby resulting in different etching depths of the sacrificial layer 23 and the channel 2 material along the length of the second trench 102 sidewalls. Generally, the etching depth of the sacrificial layer 23 is greater than the etching depth of the channel 2 material, thereby forming a recess between the end surface of the sacrificial layer 23 and the end surface of the trench, with the bottom of the recess usually being the sacrificial layer 23. The above-mentioned recess can be formed by the high selectivity lateral etching between the sacrificial layer 23 and the channel 2 material while etching the second trench 102, or by first etching the second trench 102 with relatively flat sidewalls and then etching the sidewalls of the second trench 102 to form the above-mentioned recess.

[0132] S209: Setting an inner wall in the recess.

[0133] See also Figure 23 In this step, an inner sidewall 9 can be formed in the recess based on a deposition and etching process or a selective deposition process. The inner sidewall 9 does not cover the first sub-channel 21 and the second sub-channel 22 exposed on the sidewall of the second trench 102. That is, in this step, only the trench 2 and the inner sidewall 9 are usually exposed on the sidewall of the second trench 102. Accordingly, in this step, the cross-sectional view at BB' is the same as that in the above figure. Figure 22 same.

[0134] S210 : growing a source region and a drain region in a second trench provided with an inner sidewall based on the exposed channel as an epitaxial substrate.

[0135] See also Figure 24 as well as Figure 25 ,in Figure 24 is the cross-sectional view of the structure along AA' in this step, Figure 25This is a cross-sectional view of the structure along BB' in this step. Since the channel 2 exposed on the sidewall of the second trench 102 is specifically a cross structure formed by the first sub-channel 21 and the second sub-channel 22, when the channel 2 exposed by the second trench 102 is used as an epitaxial substrate to grow the source region 3 and the drain region 4 in this step, it can provide a continuous epitaxial substrate, and then in this step, a high-performance source region 3 and drain region 4 can be formed based on the continuous epitaxial substrate. Compared with the traditional GAA architecture that only uses parallel and separated nanosheets as the channel 2, it cannot provide a continuous epitaxial substrate when growing the source region 3 and the drain region 4. It can only provide a non-continuous single crystal interface. Therefore, the source region 3 and drain region 4 grown therein are highly defective and stress-free, making it difficult to achieve ideal device performance, and the process is very difficult. In this step, a high-performance source region 3 and drain region 4 can be formed based on a continuous epitaxial substrate. When materials such as Si are selected as the materials of the first sub-channel 21 and the second sub-channel 22 , this step can provide a continuous single crystal epitaxial substrate for the growth of the source region 3 and the drain region 4 .

[0136] S211: filling an insulating dielectric between opposite gate sidewalls.

[0137] See also Figure 26 as well as Figure 27 ,in Figure 26 is the cross-sectional view of the structure along AA' in this step, Figure 27 This is a cross-sectional view of the structure along line BB' in this step. In this step, the gaps between the gate sidewalls 7 and the source regions 3 and 4 are filled with an insulating dielectric 8 and planarized. The insulating dielectric 8 can be filled using FVCD or other processes, and is not specifically limited here.

[0138] S212: After filling the insulating dielectric, the dummy gate is removed and the sacrificial layer is released to form a space to be filled.

[0139] See also Figure 28 as well as Figure 29 ,in Figure 28 is the cross-sectional view of the structure along AA' in this step, Figure 29 This is a cross-sectional view of the structure along CC' in this step. In this step, the polysilicon in the dummy gate 51 can be etched away based on the high selectivity between the dummy gate 51 and the gate sidewall 7. At this time, structures such as the bottom isolation dielectric 6 are usually left at the original dummy gate 51 position. Later, in this step, the isolation dielectric 6 on the top and sidewalls of the nanosheet needs to be removed, and the sacrificial layer 23 is released based on the high selectivity of the sacrificial layer 23 to other materials to obtain a space to be filled 103. The space to be filled 103 is the space required for preparing the gate structure 5. The space to be filled 103 usually includes the space where the dummy gate 51 is located and the space between the first sub-channel 21 and the second sub-channel 22 originally occupied by the sacrificial layer 23.

[0140] S213: thinning the first sub-channel and the second sub-channel to a target thickness.

[0141] If the thickness of the first sub-channel 21 and the second sub-channel 22 were set to be greater than the target thickness required to meet electrical requirements in the previous step to ensure the yield rate, the first sub-channel 21 and the second sub-channel 22 can be thinned in this step to reach the target thickness. If the thickness of the first sub-channel 21 and the second sub-channel 22 have already been set to the target thickness required to meet electrical requirements by controlling the thickness of the nanosheet layers and the width of the first trench 101 in the previous step, this step can be skipped and the subsequent steps can be performed directly.

[0142] Specifically, this step may include performing a cycle of oxidation etching on the first sub-channel 21 and the second sub-channel 22 to thin the first sub-channel 21 and the second sub-channel 22. That is, this step may gradually thin the thickness of the first sub-channel 21 and the second sub-channel 22 through the oxidation etching cycle to reach the target thickness. Specifically, this step may thin the first sub-channel 21 and the second sub-channel 22 by 5 nm to 12 nm to meet electrical requirements.

[0143] S214: Disposing a gate dielectric in the space to be filled to form a gate structure.

[0144] See also Figures 4 to 7 In this step, gate dielectrics such as HK material and WF material are arranged in the above-mentioned space to be filled 103 and patterned, and combined with the dipole process to form the required gate structure 5, completing the preparation of the ring-gate nanosheet field-effect transistor.

[0145] The present embodiment provides a method for preparing a ring-gate nanosheet field-effect transistor, which can ensure high-quality preparation of the source region 3 and the drain region 4 by setting a first sub-channel 21 and a second sub-channel 22 to form a cross-structured channel 2, and using the cross-structure as a continuous epitaxial substrate to grow the source region 3 and the drain region 4.

[0146] The above preferred embodiments further illustrate the objectives, technical solutions and advantages of the present invention in detail. It should be understood that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A gate-all-around nanosheet field-effect transistor, characterized in that: include: substrate; A channel located on one side surface of the substrate; the channel includes a first sub-channel parallel to the horizontal direction and a second sub-channel parallel to the vertical direction, and the second sub-channel contacts at least one of the first sub-channels in the vertical direction; a source region and a drain region connected by the channel; A gate structure at least partially surrounds the channel; a gate dielectric of the gate structure fills a space between the first sub-channel and the second sub-channel.

2. The gate-all-around nanosheet field-effect transistor according to claim 1, wherein: The second sub-channel is connected to all of the first sub-channels and extends to the substrate.

3. The gate-all-around nanosheet field-effect transistor according to claim 1, wherein: The channel extends along a length direction, and includes at least two channel segments along the length direction. The gate structure at least partially surrounds the channel segments. The source region or the drain region is arranged between adjacent channel segments. The source region and the drain region both need to be in contact with the first sub-channel and the second sub-channel at the same time.

4. The gate-all-around nanosheet field-effect transistor according to claim 3, wherein: It comprises at least two gate structures, one gate structure surrounds one channel segment, and adjacent gate structures are isolated from each other.

5. The gate-all-around nanosheet field-effect transistor according to claim 4, wherein: The gate structure includes a gate electrode arranged on the side of the channel away from the substrate, adjacent gate electrodes are isolated from each other by an insulating medium, and the gate dielectric filling the first sub-channel and the second sub-channel is isolated from the source region or the drain region by an inner sidewall.

6. The gate-all-around nanosheet field-effect transistor according to claim 1, wherein: At least two channels are provided along the width direction, and adjacent channels are separated from each other.

7. The gate-all-around nanosheet field-effect transistor according to claim 6, wherein: The gate structure surrounds at least two of the channels along the width direction, the gate dielectric fills between adjacent channels, and an isolation dielectric is provided on the side of the gate dielectric between adjacent channels facing the substrate.

8. The gate-all-around nanosheet field-effect transistor according to claim 7, wherein: The source region and the drain region are in contact with the plurality of channels along the width direction.

9. An electronic device, characterized in that: The invention comprises the gate-all-around nanosheet field-effect transistor according to any one of claims 1 to 8.

10. A method for preparing a gate-all-around nanosheet field-effect transistor, characterized in that: include: Arranging a nanosheet on the surface of the substrate; the nanosheet includes sacrificial layers and first sub-channels alternately stacked along the thickness direction; Etching the nanosheet along a thickness direction to form a first groove; A second sub-channel is provided in the first trench; the second sub-channel contacts at least one of the first sub-channels in a vertical direction to form a channel; preparing a gate-all-around nanosheet field-effect transistor based on the nanosheet provided with the second sub-channel; The ring-gate nanosheet field-effect transistor includes a source region and a drain region connected through the channel; a gate structure at least partially surrounding the channel; and a gate dielectric of the gate structure filling the space between the first sub-channel and the second sub-channel.

11. The preparation method according to claim 10, characterized in that: Etching the nanosheet along the thickness direction to form a first groove comprises: Etching the nanosheet at least to the bottommost first sub-channel in a thickness direction to form a first groove; The providing a second sub-channel in the first trench comprises: The second sub-channel is epitaxially grown from bottom to top in the first trench, so that the second sub-channel is connected to all the first sub-channels.

12. The preparation method according to claim 10, characterized in that The method of preparing a gate-all-around nanosheet field-effect transistor based on the nanosheet provided with the second sub-channel includes: Etching the nanosheet provided with the second sub-channel to form at least two sub-nanosheets, each of the sub-nanosheets including the second sub-channel; An isolation medium is provided at the bottom between adjacent sub-nanosheets.

13. The preparation method according to claim 10, characterized in that The method of preparing a gate-all-around nanosheet field-effect transistor based on the nanosheet provided with the second sub-channel includes: At least two dummy gates are provided on a surface of the nanosheet away from the substrate; the dummy gates extend along the width direction, and adjacent dummy gates are separated from each other; Disposing a gate sidewall on the side of the dummy gate; Etching the nanosheet from a position between the opposite gate sidewalls to form a second trench; the sidewalls of the second trench expose the channel and the sacrificial layer, and a recess is formed between an end surface of the sacrificial layer exposed by the sidewalls of the second trench and an end surface of the trench; providing an inner side wall in the recess; A source region and a drain region are grown in the second trench provided with the inner sidewall based on the exposed channel as an epitaxial substrate.

14. The preparation method according to claim 13, characterized in that After the source region or drain region is grown, it also includes: Filling an insulating medium between the opposite gate sidewalls; After filling the insulating medium, removing the dummy gate and releasing the sacrificial layer to form a space to be filled; A gate dielectric is provided in the space to be filled to form the gate structure.

15. The preparation method according to claim 14, characterized in that After forming the space to be filled, it also includes: The first sub-channel and the second sub-channel are thinned to a target thickness.

16. The preparation method according to claim 15, characterized in that Thinning the first sub-channel and the second sub-channel to a target thickness includes: A cycle of oxidation etching is performed on the first sub-channel and the second sub-channel to thin the first sub-channel and the second sub-channel.

Images