Packaging structure for heterogeneous integration of multiple Chiplet chips

Abstract

The invention belongs to the technical field of semiconductor packaging, and discloses a multi-Chiplet chip heterogeneous integrated packaging structure which at least comprises two layers, the bottommost layer is a substrate, the upper layer comprises a plurality of heterogeneous Chiplet chips, the Chiplet chips comprise an upper Chiplet chip set and a lower Chiplet chip, the lower Chiplet chip is arranged on the substrate, the upper Chiplet chip set is arranged on the lower Chiplet chip, and the lower Chiplet chip set is arranged on the substrate. The lower surface of the upper Chiplet chip set, the upper surface of the lower Chiplet chip and the upper surface of the substrate are provided with bonding pads, the lower Chiplet chip and the upper Chiplet chip set are connected through the bonding pads, and the lower Chiplet chip and the substrate are connected through the bonding pads. According to the invention, the high-density, low-delay and reliable interconnection between the Chiplet chips is realized through the layered stacking and hybrid bonding technology.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a packaging structure for heterogeneous integration of multiple chiplets. Background Art

[0002] In the post-Moore era, chiplet technology, as an emerging heterogeneous integration solution, significantly improves chip performance and flexibility by modularizing small chips with different functions and interconnecting them. However, existing chiplet packaging technology typically relies on interposers and silicon / glass through-via (TSV / TGV) processes to achieve inter-chip interconnection, which not only increases design difficulty but also increases manufacturing costs. There is an urgent need for a new chiplet packaging structure that can achieve high-density, low-latency, and reliable inter-chip interconnection without increasing process complexity, while reducing packaging costs and improving overall performance. Summary of the Invention

[0003] The present invention aims to provide a packaging structure for heterogeneous integration of multiple chiplets to solve the above-mentioned technical problems.

[0004] To solve the above technical problems, the specific technical solution of the packaging structure of a multi-chiplet heterogeneous integration of the present invention is as follows: A packaging structure for heterogeneous integration of multiple chiplets comprises at least two layers. The bottom layer is a substrate, and the upper layer contains multiple heterogeneous chiplets. The chiplets include an upper chiplet chipset and a lower chiplet chip. The lower chiplet chip is arranged on the substrate, and the upper chiplet chipset is arranged on the lower chiplet chip. Pads are provided on the lower surface of the upper chiplet chipset, the upper surface of the lower chiplet chip, and the upper surface of the substrate. The lower chiplet chip and the upper chiplet chipset, as well as the lower chiplet chip and the substrate, are connected via the pads.

[0005] Furthermore, the pads on the upper surface of the lower chiplet are distributed around and inside. The pads around are substrate pads, which are used to connect to the substrate, and the pads inside are used to connect to the upper chiplet chipset.

[0006] Furthermore, bumps are formed on the solder pads on the lower surface of the upper chiplet chipset and the inner surface of the upper surface of the lower chiplet chip. The solder pad on the lower surface of the upper chiplet chipset forms bump 1, and the solder pad on the inner surface of the upper surface of the lower chiplet chip forms bump 2. Bumps 1 and 2 connect the upper chiplet chipset to the lower chiplet chip by thermocompression bonding, reflow soldering, or copper-copper bonding.

[0007] Furthermore, the bumps are solder ball bumps or copper bumps.

[0008] Furthermore, it includes an underfill material, and the underfill material is filled in the bump connection.

[0009] Furthermore, a heat dissipation structure is included, which is arranged on the upper surface of the upper chiplet chipset for heat dissipation.

[0010] Furthermore, the substrate is a lead frame, an organic substrate or a printed circuit board, and a lower layer pad is provided on the substrate for connecting to the surrounding pads of the lower layer chiplet chip by wire bonding.

[0011] Furthermore, the pads between the upper chiplet chipset and the lower chiplet chips are processed and distributed through an RDL process.

[0012] Furthermore, the connection between the lower chiplet chip and the substrate is achieved by wire bonding. The wire is a metal wire, one end of which is connected to the substrate pad of the lower chiplet chip, and the other end is connected to the lower pad on the substrate.

[0013] Furthermore, the packaging structure also includes a plastic packaging material for protecting the chiplet chip and the substrate.

[0014] The multi-chiplet heterogeneous integrated packaging structure of the present invention has the following advantages: High-density integration: By vertically stacking the upper chiplet chipset and the lower chiplet chips, and connecting the chips through pads and bumps, high-density chip integration is achieved. This structure can integrate more functional modules within a limited space, improving the overall performance and functional diversity of the chip.

[0015] Low-latency interconnection: The upper-layer chiplet chipset is directly connected to the lower-layer chiplet through bumps, eliminating the use of traditional interposers and through-silicon vias (TSVs), reducing signal transmission latency and improving inter-chip communication efficiency.

[0016] Reduced manufacturing costs: This invention avoids complex interposer and TSV processes, simplifying the manufacturing process and reducing packaging costs. Furthermore, by using mature bonding technologies such as thermocompression bonding and reflow soldering, process complexity and manufacturing costs are further reduced.

[0017] Flexibility and scalability: Thanks to the modular chiplet design, chiplets with different functions and process nodes can be flexibly combined to quickly create multi-functional chip products. This design approach shortens the R&D cycle and enables rapid adjustment of product configurations based on market demand.

[0018] Excellent heat dissipation performance: The present invention sets a heat dissipation structure on the top of the package structure, which can effectively dissipate the heat generated by the upper chiplet chipset, improve the heat dissipation performance of the chip, and ensure the stable operation of the chip under high load.

[0019] High reliability: By filling the underfill material at the bump connection, the stress distribution of the solder joint is improved, the strain amplitude of the solder joint is reduced, the thermal fatigue life of the solder joint is extended, and the reliability and durability of the packaging structure are improved.

[0020] Strong compatibility: The substrate in the present invention can be in various forms such as a lead frame, an organic substrate or a printed circuit board, has a wide range of compatibility, and can adapt to different application scenarios and packaging requirements.

[0021] Simplify the design process: The pads are processed and distributed through the RDL (redistribution layer) process, which simplifies the interconnection design between chips, reduces the design complexity, and improves the design flexibility and manufacturability.

[0022] In summary, the heterogeneous integrated packaging structure of multiple chiplets in the present invention not only achieves high-density, low-latency chip interconnection, but also significantly reduces manufacturing costs and improves the heat dissipation performance and reliability of the chip, thus having broad application prospects and market value. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A side view of the chiplet packaging structure of the present invention; Figure 2 Bottom view of one of the chips in the upper chiplet chipset; Figure 3 Top view of the lower chip; Figure 4 Top view of the upper and lower chips after bonding; Figure 5 Side view of the upper and lower chiplets after underfill; Figure 6 Top view of the chiplet and substrate after bonding. DETAILED DESCRIPTION

[0024] To better understand the purpose, structure, and function of the present invention, the following describes in further detail a packaging structure for heterogeneous integration of multiple chiplets according to the present invention, in conjunction with the accompanying drawings.

[0025] Chiplets are small chips or cores, or small SoC chips. Chiplets can operate independently or be bonded together with other chips to form multifunctional chips. Chiplets with different functions and different production process nodes can be combined heterogeneously to quickly and flexibly form a variety of chips, shortening R&D cycles and reducing production costs.

[0026] The present invention provides a multi-chiplet heterogeneous integrated packaging structure comprising at least two layers. The bottom layer is a substrate 7, and the upper layer contains multiple heterogeneous chiplets. These chiplets include, but are not limited to, CPUs, memory, HBMs, SOCs, and I / O units. The chiplet chip includes an upper chiplet chipset 2 and a lower chiplet 5. The lower surface of the upper chiplet chipset 2 includes solder pads. These pads are distributed on the bottom and are used to connect to the lower chiplet 5. These pads can be distributed and mapped during chip design or reprocessed and produced using the RDL process.

[0027] The lower chiplet chip 5 is a larger chiplet chip that can accommodate the stacking of all chips in the upper chiplet chipset 2. The upper surface of the lower chiplet chip 5 includes pads. These pads are distributed around and inside the chiplet chip. The pads around the chiplet chip 5 connect to the substrate 7. The pads inside the chiplet chip 5 connect to the upper chiplet chipset 2. These pads can be distributed during chip design or processed and produced using the RDL process.

[0028] The bottom layer is the substrate 7, which can be a lead frame, an organic substrate, or a printed circuit board (PCB). These types of substrates 7 can carry the entire chiplet, and the substrate 7 itself also has pads or solder points.

[0029] The pad includes at least two bonding methods, which can be thermal compression bonding (TCB), reflow soldering and wire bonding, copper-copper bonding.

[0030] Chiplet chips can be connected using bonding methods such as thermal compression bonding (TCB), reflow soldering, and copper-copper bonding.

[0031] The lower chiplet 5 and the bottommost substrate 7 are connected by wire bonding.

[0032] Chiplet chips are connected via bumps 3, which can be solder bumps or copper bumps. These bumps can be generated by electroplating, sputtering, ball implantation, etc.

[0033] The lead connecting the lower chiplet 5 and the bottom substrate 7 is a conductive metal lead 73. One end of the metal lead 73 is connected to the pads around the upper surface of the lower chiplet 5, and the other end of the metal lead 73 is connected to the pad or solder point on the bottom substrate 7.

[0034] The top layer of the packaging structure may include a heat dissipation structure 9, and the heat dissipation structure 9 and the upper chiplet chipset 2 are bonded together by heat dissipation material. Example

[0035] like Figure 1 As shown in FIG. A multi-chiplet heterogeneous integrated packaging structure of the present invention includes, from bottom to top, a substrate 7, a lower chiplet chip 5, an upper chiplet chipset 2, and a heat dissipation structure 9. Pads are provided on the lower surface of the upper chiplet chipset 2 and the upper surface of the lower chiplet chip 5. The lower chiplet chip 5 and the upper chiplet chipset 2 are connected via the pads. Bumps 3 are formed on the pads. The pads on the lower surface of the upper chiplet chipset 2 form bump 1 31, and the pads on the upper surface of the lower chiplet chip 5 form bump 2 32.

[0036] As attached Figure 2 As shown, first, the upper chiplet chipset 2 is prepared. The lower surface of these upper chiplet chipset 2 includes pads. Bumps 31 are formed on these pads through processes such as sputtering, electroplating, and deposition.

[0037] like Figure 3 As shown, the lower chiplet 5 is prepared. The upper surface of the chiplet 5 includes pads. These pads are divided into two parts: one part is the substrate pads 51 distributed around the chip; the other part is the pads distributed inside the surface. Bumps 32 are formed on the internal pads through processes such as sputtering, electroplating, and deposition.

[0038] like Figure 4As shown, the upper chiplet chipset 2 is placed on the lower chiplet 5 at a specified position. The upper chiplet chipset 2 and the lower chiplet 5 are connected together through bumps 3 by using bonding methods such as thermocompression bonding (TCB), reflow soldering, and copper-copper bonding.

[0039] like Figure 5 As shown in FIG, after the upper and lower chiplets are bonded, an underfill material 4 is filled at the bump connection. The underfill material 4 can improve the stress distribution of the solder joint, reduce the strain amplitude of the solder joint, and extend the thermal fatigue life of the solder joint.

[0040] Next, if Figure 6 As shown, Figure 4 The chip is fixed to the substrate 7 using conductive or non-conductive adhesive. The substrate 7 has lower pads 72. Through the wire bonding process, heat, pressure, and ultrasonic energy are used to connect one end of the metal wire 73 to the substrate pads 51 around the lower chiplet 5 and the other end to the lower pads 72 on the substrate 7, thus achieving electrical interconnection between the chiplet and the substrate 7.

[0041] Then, a heat sink 9 is installed on the upper surface of the upper chiplet chipset 2.

[0042] Finally, Figure 5 The bonded chiplet and substrate 7 are protected by the plastic packaging material 1.

[0043] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. A packaging structure for heterogeneous integration of multiple chiplets, comprising at least two layers, the bottom layer being a substrate (7), and the upper layer comprising multiple heterogeneous chiplets, characterized in that: The chiplet chip comprises an upper chiplet chipset (2) and a lower chiplet chip (5), wherein the lower chiplet chip (5) is arranged on a substrate (7), and the upper chiplet chipset (2) is arranged on the lower chiplet chip (5), and the lower surface of the upper chiplet chipset (2), the upper surface of the lower chiplet chip (5), and the upper surface of the substrate (7) are provided with solder pads, and the lower chiplet chip (5) and the upper chiplet chipset (2) as well as the lower chiplet chip (5) and the substrate (7) are connected via the solder pads.

2. The multi-chiplet heterogeneous integrated packaging structure according to claim 1, characterized in that: The pads on the upper surface of the lower chiplet chip (5) are distributed around and inside, the pads around are substrate pads (51), the substrate pads (51) are used to connect to the substrate (7), and the internal pads are used to connect to the upper chiplet chip group (2).

3. The multi-chiplet heterogeneous integrated packaging structure according to claim 2, characterized in that: Bumps (3) are formed on the solder pads on the lower surface of the upper chiplet chipset (2) and the upper surface of the lower chiplet chip (5), the solder pads on the lower surface of the upper chiplet chipset (2) form bump 1 (31), and the solder pads on the upper surface of the lower chiplet chip (5) form bump 2 (32), and the bumps 1 (31) and the bumps 2 (32) connect the upper chiplet chipset (2) and the lower chiplet chip (5) by means of thermocompression bonding, reflow soldering, or copper-copper bonding.

4. The multi-chiplet heterogeneous integrated packaging structure according to claim 3, characterized in that: The bumps (3) are solder ball bumps or copper bumps.

5. The multi-chiplet heterogeneous integrated packaging structure according to claim 3, characterized in that: It comprises an underfill material (4), wherein the underfill material (4) is filled at the connection of the bumps (3).

6. The multi-chiplet heterogeneous integrated packaging structure according to claim 1, characterized in that: It comprises a heat dissipation structure (9), which is arranged on the upper surface of the upper chiplet chip group (2) and is used for heat dissipation.

7. The multi-chiplet heterogeneous integrated packaging structure according to claim 2, characterized in that: The substrate (7) is a lead frame, an organic substrate or a printed circuit board, and a lower layer pad (72) is provided on the substrate (7) for connecting to the surrounding pads of the lower layer chiplet (5) by wire bonding.

8. The multi-chiplet heterogeneous integrated packaging structure according to claim 1, characterized in that: The pads between the upper chiplet chipset (2) and the lower chiplet chip (5) are processed and distributed through an RDL process.

9. The multi-chiplet heterogeneous integrated packaging structure according to claim 7, characterized in that: The connection between the lower chiplet chip (5) and the substrate (7) is achieved by wire bonding, wherein the wire is a metal wire (73), one end of the metal wire (73) is connected to the substrate pad (51) of the lower chiplet chip (5), and the other end is connected to the lower pad (72) on the substrate (7).

10. The multi-chiplet heterogeneous integrated packaging structure according to claim 1, characterized in that: The packaging structure further comprises a plastic packaging material (1) for protecting the chiplet and the substrate (7).

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