Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of shallow trench isolations, a channel layer and at least one gate structure. The shallow trench isolation is arranged in the substrate and comprises a first insulating layer, a second insulating layer and a third insulating layer which are stacked in sequence. The channel layer directly contacts a top surface and sidewalls of the substrate, and a top surface of the first insulating layer. The at least one gate structure is arranged on the channel layer and comprises a gate dielectric layer and a conductive layer which are arranged in sequence, and the gate dielectric layer is in direct contact with the top surface of the channel layer. Therefore, the assembly efficiency of the semiconductor device is improved, and the operation performance of the semiconductor device is optimized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device with an epitaxial channel layer and a manufacturing method thereof. Background Art

[0002] Shallow trench isolation (STI) is currently the main method used to achieve device isolation in large-scale integrated circuits. For example, trench isolation structures can be used to isolate adjacent active areas (AA) from each other, thereby avoiding mutual interference between components formed on different active areas. In addition, a large number of electrically conductive structures are usually provided in semiconductor integrated circuits. The electrically conductive structures can be used to achieve electrical transmission, or only as redundant components (i.e., they do not achieve electrical functions). Generally speaking, the electrically conductive structures in integrated circuits will deviate from the trench isolation structure settings. Based on this, it is necessary to reserve a certain amount of accommodation space for the electrically conductive structures. With the continuous development of semiconductor technology, the size of integrated circuits tends to decrease. Even if the size of the integrated circuit can be reduced by reducing the size of the electrically conductive structures, it is still necessary to reserve a large space for the electrically conductive structures, making it difficult to further reduce the overall size of the semiconductor integrated circuit. Summary of the Invention

[0003] One objective of the present application is to provide a semiconductor device that improves the structural stability of a gate structure disposed above the epitaxial channel layer by disposing an epitaxial channel layer on the top surface and sidewalls of a substrate, such that the epitaxial channel layer at least partially fills a recess between a shallow trench isolation (STI) and the substrate. As a result, the semiconductor device of the present application has a more optimized component structure and performance, thereby enhancing the operating performance of the semiconductor device.

[0004] One objective of the present application is to provide a method for fabricating a semiconductor device, wherein an epitaxial channel layer is formed on the top surface and sidewalls of a substrate, at least partially filling a recess between a shallow trench isolation (STI) and the substrate. This allows a gate structure subsequently formed above the epitaxial channel layer to have improved structural stability. Consequently, the fabrication method of the present application can produce a semiconductor device with improved structure and performance.

[0005] To achieve the above objectives, one embodiment of the present application provides a semiconductor device comprising a substrate, a plurality of shallow trench isolations (STIs), a channel layer, and at least one gate structure. The STIs are disposed in the substrate and comprise a first insulating layer, a second insulating layer, and a third insulating layer stacked in sequence. The channel layer directly contacts the top surface and sidewalls of the substrate and the top surface of the first insulating layer. The at least one gate structure is disposed on the channel layer and comprises a gate dielectric layer and a conductive layer disposed in sequence, the gate dielectric layer directly contacting the top surface of the channel layer.

[0006] To achieve the above-mentioned objectives, one embodiment of the present application provides a method for manufacturing a semiconductor device, comprising the following steps: providing a substrate, forming a plurality of shallow trench isolations in the substrate, wherein each shallow trench isolation comprises a first insulating layer, a second insulating layer, and a third insulating layer stacked in sequence; forming a channel layer on the surface and sidewalls of the substrate, directly contacting the top surface and sidewalls of the substrate and the top surface of the first insulating layer; forming at least one gate structure on the channel layer, comprising a gate dielectric layer and a conductive layer arranged in sequence, the gate dielectric layer directly contacting the top surface of the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of the embodiments of the present application and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for illustrative and drawing convenience. The same symbols in different embodiments represent corresponding or similar features.

[0008] Figure 1 FIG2 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present application;

[0009] Figure 2 FIG2 is an enlarged schematic diagram of the dotted-line boxes A, B, and C of the semiconductor device according to the first embodiment of the present application;

[0010] Figure 3 FIG2 is a schematic cross-sectional view of a method for manufacturing a semiconductor device after shallow trench isolation is formed according to the first embodiment of the present application;

[0011] Figure 4 FIG2 is a schematic cross-sectional view of a method for manufacturing a semiconductor device after forming a channel layer according to the first embodiment of the present application;

[0012] Figure 5 FIG2 is a schematic cross-sectional view of a method for manufacturing a semiconductor device after forming a gate dielectric material layer according to the first embodiment of the present application;

[0013] Figure 6FIG2 is a schematic cross-sectional view of the method for manufacturing a semiconductor device according to the first embodiment of the present application after forming a conductive material layer and a covering material layer;

[0014] Figure 7 FIG2 is a schematic cross-sectional view of a method for manufacturing a semiconductor device after forming a gate structure according to the first embodiment of the present application;

[0015] Figure 8 FIG2 is a schematic diagram of a semiconductor device according to a second embodiment of the present application;

[0016] Figure 9 FIG2 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present application;

[0017] Figure 10 FIG2 is an enlarged schematic diagram of the dotted-line boxes D, E, and F in the semiconductor device according to the third embodiment of the present application;

[0018] Figure 11 FIG2 is a schematic cross-sectional view of a method for manufacturing a semiconductor device after forming a gate dielectric material layer according to a third embodiment of the present application;

[0019] Figure 12 FIG2 is a schematic cross-sectional view of a method for manufacturing a semiconductor device after forming a bottom barrier material layer according to a third embodiment of the present application;

[0020] Figure 13 FIG. 1 is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to a third embodiment of the present application after forming a conductive material layer and a covering material layer.

[0021] The description of the accompanying drawings is as follows:

[0022] 10, 20, 30 semiconductor devices

[0023] 100 substrate

[0024] Areas 100A, 100B, and 100C

[0025] 100s sidewall

[0026] 100t top surface

[0027] 110a, 110b, 110c Shallow Trench Isolation

[0028] 112 first insulation layer

[0029] 112t top surface

[0030] 114 Second insulation layer

[0031] 114s sidewall

[0032] 114t top surface

[0033] 116 Third insulation layer

[0034] 116t top surface

[0035] 122, 122a, 122b, 122c channel layer

[0036] 122t top surface

[0037] 124, 124a, 124b, 124c: gate dielectric layer

[0038] 126 conductive layer

[0039] 128 semiconductor layer

[0040] 130 Barrier Layer

[0041] 132 Metal Layer

[0042] 134 Covering

[0043] 140, 140a, 140b, 140c gate structure

[0044] 150 spacer structure

[0045] 152 first spacer

[0046] 154 Second spacer

[0047] 156 Third interspace wall

[0048] 222 channel layer

[0049] 222a first sub-channel layer

[0050] 222b second sub-channel layer

[0051] 222t top surface

[0052] 224 gate dielectric material layer

[0053] 228 semiconductor material layer

[0054] 230 barrier material layer

[0055] 232 Metal Material Layer

[0056] 234 Covering Material Layer

[0057] 322 channel layer

[0058] 322t top surface

[0059] 324a, 324b, 324c: gate dielectric layer

[0060] 326a, 326b, 326c dielectric layer

[0061] 330a, 330b, 330c conductive layer

[0062] 332 bottom barrier layer

[0063] 334 semiconductor layer

[0064] 336 Top Barrier Layer

[0065] 338 Metal Layer

[0066] 340a, 340b, 340c gate structures

[0067] 342 Covering

[0068] 424 gate dielectric material layer

[0069] 426 dielectric material layer

[0070] 432 bottom barrier material layer

[0071] 434 semiconductor material layer

[0072] 436 top barrier material layer

[0073] 438 Metal Material Layer

[0074] 442 Covering Material Layer

[0075] B1, B2, B3, B4, B5 bottom

[0076] H1, H2, H3 height difference

[0077] R1, R2, R2', R3 grooves

[0078] R4, R5, R6 grooves

[0079] S1, S2, S3 curved surfaces DETAILED DESCRIPTION

[0080] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, details the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, reorganized, or combined to create other embodiments without departing from the spirit of the present invention.

[0081] Please refer to Figures 1 to 2 , which is a schematic diagram of a semiconductor device 10 according to a first embodiment of the present application, wherein: Figure 1 is a schematic cross-sectional view of the semiconductor device 10, and Figure 2 This is an enlarged schematic diagram of the dotted box A, B, and C in the semiconductor device. Figure 1 As shown, the semiconductor device 10 includes a substrate 100, a plurality of shallow trench isolation (STI) trenches 110a, 110b, and 110c disposed within the substrate 100, and a channel layer 122 and at least one gate structure 140 sequentially disposed on the substrate 100. The substrate 100 may include, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and may include, but is not limited to, a plurality of adjacent regions 100A, 100B, and 100C. The STI trenches 110a, 110b, and 110c are disposed within the substrate 100 within the regions 100A, 100B, and 100C, respectively, to define a plurality of active areas (AA) on the substrate 100. Each STI trench 110a, 110b, and 110c comprises a composite structure, such as a first insulating layer 112, a second insulating layer 114, and a third insulating layer 116 disposed sequentially. At least one gate structure 140 is disposed on the channel layer 122 and further includes a gate dielectric layer 124 and a conductive layer 126 disposed in sequence. It should be noted that the channel layer 122 directly contacts the top surface 100t and sidewalls 100s of the substrate 100, and the top surface 112t of the first insulating layer 112, while the gate dielectric layer 124 directly contacts the top surface of the channel layer 122. In this way, the channel layer 122, comprising the epitaxial material, can be more stably disposed, partially covering the top surface (i.e., the top surface 100t of the substrate 100) and sidewalls (i.e., the sidewalls 100s of the substrate 100) of each active region of the substrate 100, thereby improving the structural stability of the semiconductor device 10 and enhancing the device performance and operational performance of the semiconductor device 10.

[0082] Specifically, the first insulating layer 112, the second insulating layer 114, and the third insulating layer 116 of each shallow trench isolation 110a, 110b, and 110c each comprise different insulating materials, selected from, but not limited to, the group consisting of silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride. In one embodiment, the second insulating layer 114 preferably comprises an insulating material different from that of the first insulating layer 112 and the third insulating layer 116, such as silicon nitride. Furthermore, a top surface 114t of the second insulating layer 114 is higher than the top surface 100t of the substrate 100 and lower than the top surface 122t of the channel layer 122, such that a height difference H1 is defined between the top surface 114t of the second insulating layer 114 and the top surface 122t of the channel layer 122. The top surface 112t of the first insulating layer 112 and the top surface 116t of the third insulating layer 116 are both lower than the top surface 100t of the substrate 100, and the top surface 116t of the third insulating layer 116 can be slightly lower than or substantially flush with the top surface 112t of the first insulating layer 112. Figure 1 In another embodiment, the first insulating layer 112, the second insulating layer 114 and the third insulating layer 116 may also be affected by different etching parameters to respectively present arc-shaped surfaces that are partially concave or partially protruding, and the first insulating layer 112 and the third insulating layer 116 comprising the same insulating material may also be formed by different etching processes to form arc-shaped surfaces with different heights and / or tilt angles. For example, Figure 2 As shown, the first insulating layer 112, for example, has an arc-shaped surface S1 inclined toward the substrate 100, the second insulating layer 114, for example, has an arc-shaped surface S2 inclined downward on both sides, and the third insulating layer 116, for example, has an arc-shaped surface S3 inclined toward the center. In this way, the gate dielectric layer 124 (including the gate dielectric layer 124a, the gate dielectric layer 124b, and the gate dielectric layer 124c) disposed on each shallow trench isolation 110a, 110b, 110c can also be optionally conformally covered on the arc-shaped surface S2 of the second insulating layer 114 and the arc-shaped surfaces S1 and S3 of the first insulating layer 112 and the third insulating layer 116, and have corresponding local arc surfaces, such as Figure 2 As shown. The inclination angles of the arcuate surface S2 on the two sides are, for example, different, and the arcuate surface S2 is higher than the arcuate surfaces S1 and S3 in a direction perpendicular to the top surface 100t of the substrate 100, while the arcuate surface S1 is higher than the arcuate surface S3, but this is not limiting. A person skilled in the art will readily understand that the relative heights of the arcuate surfaces S1, S2, and S3 are, for example, based on the height of their highest or lowest points as a comparison basis, but this is not limiting.

[0083] Thus, a recess R1 is defined between the sidewalls 100s of the substrate 100, the sidewalls 114s of the second insulating layer 114 of each shallow trench isolation 110a, 110b, and 110c, and the top surface 112t of the first insulating layer 112. It should be noted that the channel layer 122a disposed in the region 100A covers the active area within the region 100A and fills the recess R1 of the shallow trench isolation 110a on both sides thereof. Thus, the channel layer 122a disposed in the region 100A can simultaneously physically contact the top surface 112t of the first insulating layer 112 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110a. On the other hand, the channel layer 122b disposed in region 100B covers the active area in region 100B and partially fills the recess R1 of the shallow trench isolation 110b on either side thereof. A recess R2 is defined between the channel layer 122b, the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110b, and the top surface 112t of the first insulating layer 112. The channel layer 122c disposed in region 100C covers the active area in region 100C and also partially fills the recess R1 of the shallow trench isolation 110c on either side thereof. In one embodiment, the channel layer 122 comprises an epitaxial material such as, but not limited to, epitaxial silicon (Si), epitaxial silicon phosphorus (SiP), epitaxial silicon germanium (SiGe), or epitaxial germanium (Ge).

[0084] For example Figure 1As shown, the semiconductor device 10 includes a plurality of gate structures 140a, 140b, 140c respectively arranged in the region 100A, the region 100B and the region 100C, and each gate structure 140a, 140b, 140c is respectively arranged across two adjacent shallow trench isolations 110a, 110b, 110c in the region 100A, the region 100B and the region 100C. Specifically, the gate structure 140a disposed in the region 100A is disposed on the channel layer 122a and includes a gate dielectric layer 124a (e.g., comprising silicon oxide), a conductive layer 126, and a capping layer 134 (which are sequentially disposed on the channel layer 122a. It should be noted that the gate dielectric layer 124a of the gate structure 140a directly covers the channel layer 122a and a portion of the shallow trench isolation 110a, and can simultaneously physically contact the top surface of the channel layer 122a, the top surface 114t and sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110a, and the top surface 116t of the third insulating layer 116. The gate structure 140b disposed in the region 100B is disposed Disposed on the channel layer 122b, the gate dielectric layer 124b, the conductive layer 126, and the capping layer 134 are sequentially disposed on the channel layer 122b. The gate dielectric layer 124b of the gate structure 140b is also partially disposed between the channel layer 122b and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110b, and fills the recess R2. In other words, a portion of the gate dielectric layer 124b directly contacts the top surface 112t of the first insulating layer 112 of the shallow trench isolation 110b and the sidewalls 114s of the second insulating layer 114 on opposite sides, such that a bottom surface B1 of the portion of the gate dielectric layer 124b is lower than the top surface 114t of the second insulating layer 114.

[0085] Meanwhile, a gate structure 140c disposed within region 100C is disposed on the channel layer 122c and includes a gate dielectric layer 124c, a conductive layer 126, and a capping layer 134 sequentially disposed on the channel layer 122c. The gate dielectric layer 124c of the gate structure 140c is also partially disposed between the channel layer 122c and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110c, further defining a recess R3. Thus, the gate dielectric layer 124c also directly and partially contacts the top surface 112t of the first insulating layer 112 of the shallow trench isolation 110c and the sidewalls 114s of the second insulating layer 114 on opposite sides. Furthermore, the gate dielectric layer 124c and the conductive layer 116 of the gate structure 140c are both partially located between the channel layer 122c and the gate dielectric layer 124c, such that the conductive layer 116 completely fills the recess R3. In one embodiment, the conductive layer 116 of each gate structure 140a, 140b, and 140c further includes a semiconductor layer 128, a barrier layer 130, and a metal layer 132, which are sequentially arranged. In one embodiment, the semiconductor layer 128 includes, for example, a semiconductor material such as doped polysilicon or doped amorphous silicon; the barrier layer 130 includes, for example, a conductive barrier material such as titanium and / or titanium nitride, tantalum, and / or tantalum oxide; the metal layer 132 includes, for example, a low-resistance metal material such as tungsten, aluminum, or copper; and the cap layer 134 includes, for example, an insulating material such as silicon nitride, silicon carbonitride, or silicon oxynitride, but is not limited thereto. A portion of the semiconductor layer 128 of the gate structure 140c is further disposed between the channel layer 122c and the sidewall 114s of the second insulating layer 114 of the shallow trench isolation 110c, such that the bottom surface B2 of the portion is lower than the top surface 114t of the second insulating layer 114. Figure 1 shown.

[0086] Furthermore, the semiconductor device 10 further includes a spacer structure 150 disposed on the sidewalls of each of the gate structures 140a, 140b, and 140c. Specifically, the spacer structure 150 is located on the top surface 116t of the third insulating layer 116 of the shallow trench isolation 110 and further includes a first spacer 152, a second spacer 154, and a third spacer 156 disposed sequentially horizontally on the sidewalls of the gate structures 140a, 140b, and 140c. In one embodiment, the first spacer 152 comprises a material such as silicon nitride or silicon carbonitride, the second spacer 154 comprises a material such as silicon oxide or silicon oxynitride, and the third spacer 156 comprises a material such as silicon nitride or silicon carbonitride, but the present invention is not limited thereto. In this configuration, the gate structures 140a, 140b, 140c located in different regions 100A, 100B, 100C can respectively form the required transistor components together with the doped regions (not shown) disposed in the substrate 100 on both sides, and are suitable for various required applications under actual device requirements.

[0087] According to the semiconductor device 10 of this embodiment, channel layers 122a, 122b, and 122c including epitaxial material are arranged on the substrate 100 in different areas 100A, 100B, and 100C, so that the channel layers 122a, 122b, and 122c directly contact the top surface 100t and sidewalls 100s of the substrate 100, and also completely or partially occupy the grooves R1 within the shallow trench isolations 110a, 110b, and 110c. In this way, the gate dielectric layers 124a, 124b, 124b of the gate structures 140a, 140b, 140c, respectively disposed above the channel layers 122a, 122b, 122c, can directly contact the top surfaces of the channel layers 122a, 122b, 122c, or be partially sandwiched between the channel layers 122b, 122c and the shallow trench isolations 110b, 110c, thereby improving the structural stability of the gate structures 140a, 140b, 140c. As a result, the semiconductor device 10 of this embodiment has a more optimized device structure and performance, thereby improving the operating performance of the semiconductor device 10.

[0088] In order to enable a person skilled in the art to which this application relates to easily understand the semiconductor device 10 of this application, the following further describes a method for manufacturing the semiconductor device 10 of this application.

[0089] See also Figures 3 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 in a first embodiment of the present invention. Figure 3As shown, a substrate 100 is provided, and shallow trench isolations 110a, 110b, and 110c are formed in different regions 100A, 100B, and 100C of the substrate 100, respectively, thereby simultaneously defining the active regions. In one embodiment, the shallow trench isolations 110a, 110b, and 110c are formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then sequentially forming a first insulating layer 112, a second insulating layer 114, and a third insulating layer 116 in the trenches. Among them, the second insulating layer 114 preferably includes an insulating material different from the first insulating layer 112 and the third insulating layer 116, such as silicon nitride, so that the top surface 114t of the formed second insulating layer 114 is higher than the top surface 100t of the substrate 100, and the top surface 112t of the formed first insulating layer 112 and the top surface 116t of the third insulating layer 116 are both lower than the top surface 100t of the substrate 100, but not limited to this. It should be noted that since the top surfaces 112t, 114t, 116t of the first insulating layer 112, the second insulating layer 114 and the third insulating layer 116 of each shallow trench isolation 110a, 110b, 110c are of different heights, a groove R1 can be defined between the side wall 100s of the substrate 100 and the side wall 114s of the second insulating layer 114 and the top surface 112t of the first insulating layer 112 of each shallow trench isolation 110a, 110b, 110c.

[0090] In addition, in another embodiment, the etching parameters of the first insulating layer 112, the second insulating layer 114, and the third insulating layer 116 can be adjusted to form arc-shaped surfaces with different heights and / or tilt angles. In addition, in the other embodiment, a first insulating material (not shown, for example, including silicon oxide or silicon oxynitride), a second insulating material (not shown, for example, including silicon nitride or silicon carbonitride), and a third insulating material (not shown, for example, including the same material as the first insulating material) can be sequentially formed in the trench, and then two etching processes are performed to form the arc-shaped surfaces. Figure 2The first insulating layer 112 and the third insulating layer 116 are shown. In this way, the first insulating layer 112 and the third insulating layer 116 comprising the same material can respectively form an arcuate surface S1 inclined toward the substrate 100 and an arcuate surface S3 inclined toward the center, and the arcuate surface S1 is, for example, slightly higher than the arcuate surface S3, but not limited to this. On the other hand, the second insulating layer 114 comprising a different material forms an arcuate surface S2 inclined downward from both sides due to the difference in etching selection. The arcuate surface S2 can be higher than the arcuate surfaces S1 and S3 in the direction perpendicular to the top surface 100t of the substrate 100, and the inclination angles of the arcuate surface S2 on the two sides are, for example, affected by the two etching processes and can be different from each other, but not limited to this. Under this operation, the subsequent deposition process can be assisted by the arcuate surfaces S1, S2, and S3, so that the formed film layer (such as Figure 5 The gate dielectric material layer 224 (as shown) conformally covers the shallow trench isolations 110 a , 110 b , and 110 c and partially or completely fills the recess R1 to avoid air gaps.

[0091] like Figure 4 As shown, an epitaxial growth process is performed to form a channel layer 122 on all exposed surfaces of the substrate 100. The top surface 122t of the channel layer 122 is preferably higher than the top surface 114t of the second insulating layer 114, such that a height difference H1 exists between the top surface 114t of the second insulating layer 114 and the top surface 122t of the channel layer 122. In one embodiment, the channel layer 122 comprises an epitaxial material such as epitaxial silicon, epitaxial silicon phosphorus, epitaxial silicon germanium, or epitaxial germanium, preferably epitaxial silicon germanium, but not limited thereto. In other embodiments, the channel layer may also comprise a composite layer structure (not shown) composed of the aforementioned epitaxial materials, but not limited thereto. It should be noted that the channel layer 122a formed in the region 100A not only covers the active area in the region 100A and partially contacts the top surface 100t and sidewalls 100s of the substrate 100, but also fills the recess R1 of the shallow trench isolation 110a on both sides thereof. In this way, the channel layer 122a can simultaneously physically contact the top surface 112t of the first insulating layer 112 of the shallow trench isolation 110a and the sidewalls 114s of the second insulating layer 114. The channel layers 122b and 122c formed in the region 100B and region 100C are respectively located on the active areas of the regions 100B and 100C, and partially fill the recesses R1 of the shallow trench isolations 110b and 100c on both sides thereof. Recesses R2 and R2' are defined between the channel layers 122b and 122c and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolations 110b and 100c.

[0092] like Figure 5As shown, a deposition process is performed to form a gate dielectric material layer 224 on the substrate 100. In one embodiment, the gate dielectric material layer 224 includes, for example, a dielectric material such as silicon oxide, or a high-k dielectric material such as hafnium oxide, aluminum oxide, or tantalum oxide, but is not limited thereto. Specifically, the gate dielectric material layer 224 conformally covers the channel layers 122a, 122b, 122c and the shallow trench isolations 110a, 110b, and 100c, filling the groove R2 of the shallow trench isolation 110b and partially filling the groove R2' of the shallow trench isolation 110c (as shown in FIG. Figure 4 That is, the gate dielectric material layer 224 is partially formed between the channel layer 122b and the sidewall 114s of the second insulating layer 114 of the shallow trench isolation 110b, occupying all of the space of the recess R2, and is also partially formed between the channel layer 122c and the sidewall 114s of the second insulating layer 114 of the shallow trench isolation 110c, further defining a recess R3 between the channel layer 122c and the sidewall 114s of the second insulating layer 114 of the shallow trench isolation 110c.

[0093] like Figure 6 As shown, multiple deposition processes, such as chemical vapor deposition (CVD) processes, are performed to sequentially form a semiconductor material layer 228, a barrier material layer 230, a metal material layer 232, and a capping material layer 234 on the gate dielectric material layer 224. The semiconductor material layer 228 has an overall flat top surface and is partially formed between the channel layer 122c and the sidewall 114s of the second insulating layer 114 of the shallow trench isolation 110c, filling the recess R3.

[0094] like Figure 7 As shown, a patterning process is performed to partially remove the Figure 6 The capping material layer 234, the metal material layer 232, the barrier material layer 230, the semiconductor material layer 228, and the gate dielectric material layer 224 are shown to form the capping layer 134, the metal layer 132, the barrier layer 130, the semiconductor layer 128, and the gate dielectric layer 124. The metal layer 132, the barrier layer 130, and the semiconductor layer 128 collectively form the conductive layer 126. Thus, the capping layer 134, the conductive layer 126, and the gate dielectric layer 124a formed in the region 100A collectively form the gate structure 140a. Meanwhile, the capping layer 134, the conductive layer 126, and the gate dielectric layer 124b formed in the region 100B collectively form the gate structure 140b. Furthermore, the capping layer 134, the conductive layer 126, and the gate dielectric layer 124c formed in the region 100C collectively form the gate structure 140c.

[0095] Then, multiple deposition and etch-back processes are continued on the substrate 100 to sequentially form the following on the sidewalls of each gate structure 140b: Figure 1 The first spacer 152 (e.g., comprising materials such as silicon nitride or silicon carbonitride), the second spacer 154 (e.g., comprising materials such as silicon oxide or silicon oxynitride), and the third spacer 156 (e.g., comprising materials such as silicon nitride or silicon carbonitride) are shown, so that the first spacer 152, the second spacer 154, and the third spacer 156 together form a spacer structure 150, thus completing the fabrication of the semiconductor device 10 of this embodiment. In this operation, the gate structures 140a, 140b, and 140c formed in different regions 100A, 100B, and 100C can be combined with the doped regions formed in the substrate 100 on both sides of the gate structures 140a, 140b, and 140c to form the desired transistor components, and can be applied to various desired applications according to actual device requirements.

[0096] According to the manufacturing method of the semiconductor device 10 of this embodiment, channel layers 122a, 122b, and 122c including epitaxial material are formed on the substrate 100 in different areas 100A, 100B, and 100C, directly covering and contacting the top surface 100t and sidewalls 100s of the substrate 100, and also completely or partially occupying the recesses R1 within the shallow trench isolations 110a, 110b, and 110c. As such, the gate dielectric layers 124a, 124b, 124b of the gate structures 140a, 140b, 140c formed above the channel layers 122a, 122b, 122c, respectively, can directly contact the top surfaces of the channel layers 122a, 122b, 122c, or be partially sandwiched between the channel layers 122b, 122c and the shallow trench isolations 110b, 110c, thereby improving the structural stability of the gate structures 140a, 140b, 140c. Thus, the semiconductor device 10 formed by the fabrication method of this embodiment can have a more optimized device structure and performance, thereby achieving optimized operating performance.

[0097] A person skilled in the art of the present invention should readily understand that, in order to meet actual product requirements, the semiconductor device and its manufacturing method of the present invention may also have other aspects and are not limited to the aforementioned aspects. The following will further describe other embodiments or variations of the semiconductor device and its manufacturing method of the present invention. To simplify the description, the following description will primarily detail the differences between the various embodiments, without reiterating the similarities. Furthermore, the same components in the various embodiments of the present invention are designated by the same reference numerals to facilitate comparison between the various embodiments.

[0098] See also Figure 8 FIG2 is a schematic diagram of a method for manufacturing a semiconductor device 20 in a second embodiment of the present invention. The semiconductor device 20 in this embodiment is substantially the same as the semiconductor device 10 in the aforementioned embodiment, with the main difference being that the channel layer 222 in this embodiment comprises a composite layer structure.

[0099] Specifically, the channel layer 222 includes, for example, a first sub-channel layer 222a and a second sub-channel layer 222b sequentially formed on the substrate 100. The first sub-channel layer 222a directly contacts the top surface 100t of the substrate 100 and does not contact the sidewalls 100s of the substrate 100. The second sub-channel layer 222b is disposed on the first sub-channel layer 222a, covering both the first sub-channel layer 222a and the sidewalls 100s of the substrate 100. In one embodiment, the first sub-channel layer 222a and the second sub-channel layer 222b each include different epitaxial materials, such as, but not limited to, epitaxial silicon (Si), epitaxial silicon phosphorus (SiP), epitaxial silicon germanium (SiGe), or epitaxial germanium (Ge). Thus, the first sub-channel layer 222a and the second sub-channel layer 222b jointly occupy or partially occupy the recess R1 within the shallow trench isolations 110a, 110b, and 110c. Furthermore, it should be noted that the top surface of the first sub-channel layer 222a is preferably higher than the top surface 114t of the second insulating layer 114, such that a height difference H2 exists between the top surface 114t of the second insulating layer 114 and the top surface 222t of the channel layer 222. In another embodiment, the thickness of the second sub-channel layer 222b may be further reduced based on actual device requirements. For example, an additional etch-back process may be performed on the second sub-channel layer 222b after the second sub-channel layer 222b is formed. In this way, the height difference H2 between the top surface 114t of the second insulating layer 114 and the top surface 222t of the channel layer 222 may be correspondingly reduced, but the present invention is not limited thereto.

[0100] According to the semiconductor device 20 of this embodiment, a channel layer 222 comprising an epitaxial material is similarly disposed on the substrate 100 in different regions 100A, 100B, and 100C. The first and second sub-channel layers 222a and 222b of the channel layer 222 respectively contact the top surface 100t and sidewalls 100s of the substrate 100 and jointly occupy or partially occupy the recesses R1 within the shallow trench isolations 110a, 110b, and 110c. As such, the gate dielectric layers 124a, 124b, and 124b of the gate structures 140a, 140b, and 140c, respectively disposed above the channel layer 222, can also directly contact the top surface 222t of the channel layer 222 or be partially sandwiched between the channel layer 222 and the shallow trench isolations 110b and 110c, thereby improving the structural stability of the gate structures 140a, 140b, and 140c. Therefore, the semiconductor device 20 of this embodiment can also have a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device 20 .

[0101] Please refer to Figures 9 and 10 FIG. 1 is a schematic diagram of a semiconductor device 30 according to a third embodiment of the present application, wherein: Figure 9 is a schematic cross-sectional view of the semiconductor device 30, and Figure 10 FIG3 is a partially enlarged schematic diagram of the semiconductor device 30. The semiconductor device 30 of this embodiment is substantially the same as the semiconductor device 10 of the aforementioned embodiment, with the main difference being that the gate structures 340 a, 340 b, and 340 c of this embodiment include different stacked film layers, resulting in different film layers partially interposed between the channel layer 322 and the first insulating layer 112 of the shallow trench isolations 110 a, 110 b, and 110 c.

[0102] like Figure 9 As shown, the channel layer 322 is disposed on the active region, directly contacting the top surface 100t and sidewalls 100s of the substrate 100, and the top surface 112t of the first insulating layer 112 of the shallow trench isolations 110a, 110b, and 110c on both sides. The top surface 322t of the channel layer 322 is also higher than the top surface 114t of the second insulating layer 114, with a height difference H3 therebetween. The channel layer 322 is partially filled with Figure 1 Recess R1 is shown, and recesses R4, R5, and R6 are defined between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of each shallow trench isolation 110a, 110b, and 110c. Gate structures 340a, 340b, and 340c are disposed on the channel layer 322 and also span two adjacent shallow trench isolations 110a, 110b, and 110c in regions 100A, 100B, and 100C, respectively. Specifically, gate structure 340a further includes a gate dielectric layer 324a, a dielectric layer 326a, a conductive layer 330a, and a capping layer 342, disposed in sequence. The gate dielectric layer 324a and the dielectric layer 326a conformally overlie the channel layer 322 and the shallow trench isolation 110a. Portions of the gate dielectric layer 324a and the dielectric layer 326a are further disposed between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110a, filling the recess R4. Thus, the bottom surface B3 of the portion of the dielectric layer 326a is lower than the top surface 114t of the second insulating layer 114 of the shallow trench isolation 110a. In one embodiment, the conductive layer 330a includes a bottom barrier layer 332, a semiconductor layer 334, a top barrier layer 336, and a metal layer 338, sequentially disposed above the dielectric layer 326a. The bottom barrier layer 332 has a generally flat top surface.

[0103] On the other hand, the gate structure 340b further includes a gate dielectric layer 324b, a dielectric layer 326b, a conductive layer 330b, and a capping layer 342, disposed in sequence. Portions of the gate dielectric layer 324b, dielectric layer 326b, and conductive layer 330b are disposed between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110b, filling the recess R5. Specifically, the conductive layer 330b also includes a bottom barrier layer 332, a semiconductor layer 334, a top barrier layer 336, and a metal layer 338, disposed in sequence above the dielectric layer 326b. A portion of the bottom barrier layer 332 of the conductive layer 330b fills the recess R5, interposed between the channel layer 322 and the second insulating layer 114 of the shallow trench isolation 110b, and has a bottom surface B4 that is lower than the top surface 114t of the second insulating layer 114 of the shallow trench isolation 110b. The gate structure 340c further includes a gate dielectric layer 324c, a dielectric layer 326c, a conductive layer 330c, and a capping layer 342, which are sequentially disposed. The gate dielectric layer 324c, dielectric layer 326c, and conductive layer 330c are also partially disposed between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110c, filling the recess R6. The conductive layer 330c also includes a bottom barrier layer 332, a semiconductor layer 334, a top barrier layer 336, and a metal layer 338, which are sequentially disposed above the dielectric layer 326c. A portion of the bottom barrier layer 332 and the semiconductor layer 334 of the conductive layer 330c are simultaneously filled into the recess R6 and interposed between the channel layer 322 and the second insulating layer 114 of the shallow trench isolation 110c, such that the bottom surface B5 of the portion is lower than the top surface 114t of the second insulating layer 114 of the shallow trench isolation 110c. In one embodiment, the gate dielectric layers 324a, 324b, and 324c include a dielectric material such as silicon oxide, while the dielectric layers 326a, 326b, and 326c include a high-k dielectric material having a higher k than that of silicon oxide, such as hafnium oxide, aluminum oxide, or tantalum oxide, but the present invention is not limited thereto.

[0104] Please refer to Figure 10As shown, in another aspect of this embodiment, the first insulating layer 112 and the third insulating layer 116, which are made of the same insulating material, can be formed using different etching processes to form arcuate surfaces with different heights and / or tilt angles. For example, the first insulating layer 112 has an arcuate surface S1 tilted toward the substrate 100, the second insulating layer 114 has arcuate surfaces S2 with two sides tilted downward, and the third insulating layer 116 has an arcuate surface S3 with two sides tilted toward the center. Thus, the lowest points of the channel layer 322, the gate dielectric layer 324a, and the dielectric layer 326a that are collectively filled in the groove R4 may not be coplanar, the lowest points of the channel layer 322, the gate dielectric layer 324b, the dielectric layer 326b, and the bottom barrier layer 332 that are collectively filled in the groove R5 may not be coplanar, and the lowest points of the channel layer 322, the gate dielectric layer 324c, the dielectric layer 326c, the bottom barrier layer 332, and the semiconductor layer 334 that are collectively filled in the groove R6 may not be coplanar, as shown in FIG. Figure 10 As shown, but not limited to this. Furthermore, the gate dielectric layers 324a, 324b, 324c and dielectric layers 326a, 326b, 326c, etc., sequentially disposed on the shallow trench isolations 110a, 110b, and 110c, can also optionally conformally cover the arcuate surface S2 of the second insulating layer 114 and the arcuate surfaces S1 and S3 of portions of the first insulating layer 112 and the third insulating layer 116, thereby forming corresponding local arcuate surfaces. In this configuration, the gate structures 340a, 340b, and 340c located in different regions 100A, 100B, and 100C can also be combined with doped regions (not shown) disposed in the substrate 100 on both sides to form a desired transistor component, and can be adapted for various desired applications based on actual device requirements. According to the semiconductor device 30 of this embodiment, a channel layer 322 including an epitaxial material is provided on the substrate 100 in different regions 100A, 100B, and 100C, so that the channel layer 322 directly contacts the top surface 100t and sidewalls 100s of the substrate 100, and the recesses R4, R5, and R6 defined by the shallow trench isolations 110a, 110b, and 110c. Thus, the gate dielectric layers 324a, 324b, 324b, dielectric layers 326a, 326b, 326, and / or conductive layers 330a, 330b, 330c of the gate structures 340a, 340b, 340c, respectively disposed above the channel layer 322, can be partially sandwiched between the channel layer 322 and the shallow trench isolations 110a, 110b, 110c, thereby filling the spaces of the recesses R4, R5, R6 and improving the structural stability of the gate structures 340a, 340b, 340c. As a result, the semiconductor device 30 of this embodiment has a more optimized device structure and performance, thereby improving the operating performance of the semiconductor device 30.

[0105] In order to enable a person skilled in the art to which this application relates to easily understand the semiconductor device 30 of this application, the following further describes a method for manufacturing the semiconductor device 30 of this application.

[0106] See also Figures 11 to 13 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 30 in a third embodiment of the present application. The manufacturing method of this embodiment is substantially the same as that of the previous embodiment. Figures 3 and 4 The main difference between the manufacturing method of this embodiment and the previous embodiment is that the grooves R4, R5, and R6 are defined between the formed channel layer 322 and the sidewalls 114s of the second insulating layer 114 of each shallow trench isolation 110a, 110b, and 110c, so that different film layers of the gate structures 340a, 340b, and 340c subsequently formed on the channel layer 322 are partially filled in the grooves R4, R5, and R6 respectively.

[0107] First, if Figure 11 As shown in the reference Figure 3 and Figure 4 After the fabrication process shown, a channel layer 322 is formed on the active area, directly contacting the top surface 100t and sidewalls 100s of the substrate 100, and the top surface 112t of the first insulating layer 112 of the shallow trench isolations 110a, 110b, and 110c on both sides. Recesses R4, R5, and R6 are defined between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolations 110a, 110b, and 110c. Deposition processes are then performed to sequentially form a gate dielectric material layer 424 and a dielectric material layer 426 on the substrate 100, conformally covering the channel layer 322 and the shallow trench isolations 110a, 110b, and 110c. In one embodiment, the gate dielectric material layer 424 includes a dielectric material such as silicon oxide, and the dielectric material layer 426 includes a high-k dielectric material such as hafnium oxide, aluminum oxide, or tantalum oxide, but the present invention is not limited thereto. It should be noted that a portion of the gate dielectric material layer 424 and the dielectric material layer 426 formed in region 100A also form between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110a, thereby occupying the entire space of recess R4. The gate dielectric material layer 424 and the dielectric material layer 426 formed in regions 100B and 100C are also partially formed between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolation 110b and 110c, but only occupy a portion of the space of recesses R5 and R6.

[0108] like Figure 12As shown, a deposition process is performed again to form a bottom barrier material layer 432 on the dielectric material layer 426, conformally covering the channel layer 322 and each of the shallow trench isolations 110a, 110b, and 110c. In one embodiment, the bottom barrier material layer 432 comprises, but is not limited to, a conductive barrier material such as tantalum and / or tantalum nitride, titanium and / or titanium nitride. The bottom barrier material layer 432 formed in region 100A directly covers the dielectric material layer 426, while a portion of the bottom barrier material layer 432 formed in regions 100B and 100C is also formed between the channel layer 322 and the sidewalls 114s of the second insulating layer 114 of the shallow trench isolations 110b and 110c. As a result, the gate dielectric material layer 424, dielectric material layer 426, and bottom barrier material layer 432 in region 100B collectively occupy the entire space of the recess R5. The gate dielectric material layer 424 , the dielectric material layer 426 and the bottom barrier material layer 432 in the region 100C occupy a portion of the space of the recess R6 .

[0109] like Figure 13 As shown, multiple deposition processes are performed to sequentially form a semiconductor material layer 434, a top barrier material layer 436, a metal material layer 438, and a capping material layer 442 with an overall flat top surface on the bottom barrier material layer 432. It should be noted that the semiconductor material layer 434 formed in regions 100A and 100B directly covers the bottom barrier material layer 432, while the semiconductor material layer 434 formed in region 100C is also formed between the channel layer 322 and the sidewall 114s of the second insulating layer 114 of the shallow trench isolation 110c. As a result, the gate dielectric material layer 424, dielectric material layer 426, bottom barrier material layer 432, and semiconductor material layer 434 in region 100C collectively occupy the entire space of the recess R6.

[0110] For follow-up, refer to the above Figure 7 By performing the patterning process as shown, the following Figure 9Shown are a capping layer 342, a metal layer 338, a top barrier layer 336, a semiconductor layer 334, a bottom barrier layer 332, dielectric layers 326a, 326b, 326c, and gate dielectric layers 324a, 324b, 324c. Thus, the metal layer 338, the top barrier layer 336, the semiconductor layer 334, and the bottom barrier layer 332 form conductive layers 330a, 330b, and 330c, so that the capping layer 342, the conductive layer 330a, the dielectric layer 326a, and the gate dielectric layer 324a formed in the region 100A together form a gate structure 340a. Meanwhile, the capping layer 342, the conductive layer 330b, the dielectric layer 326b, and the gate dielectric layer 324b formed in the region 100B together form a gate structure 340b. The capping layer 342, the conductive layer 330c, the dielectric layer 326c, and the gate dielectric layer 324c formed in the region 100C together form a gate structure 340c. Then, spacer structures 150 (including the following) are formed on the sidewalls of each gate structure 340a, 340b, and 340c. Figure 9 The first spacer 152 , the second spacer 154 , and the third spacer 156 shown complete the fabrication of the semiconductor device 30 in this embodiment.

[0111] During this operation, the gate structures 340a, 340b, and 340c formed in the different regions 100A, 100B, and 100C can be combined with the doped regions formed in the substrate 100 on both sides of the gate structures 340a, 340b, and 340c to form the desired transistor components, and can be adapted for various applications based on actual device requirements. According to the method for fabricating the semiconductor device 30 of this embodiment, a channel layer 322 comprising an epitaxial material is formed on the substrate 100 in the different regions 100A, 100B, and 100C, directly covering and contacting the top surface 100t and sidewalls 100s of the substrate 100, and further defining recesses R4, R5, and R6 between the channel layer 322 and the shallow trench isolations 110a, 110b, and 110c. Thus, the gate dielectric layers 324a, 324b, 324b, dielectric layers 326a, 326b, 326, and / or conductive layers 330a, 330b, 330c of the gate structures 340a, 340b, 340c subsequently formed above the channel layer 322 can be partially formed between the channel layer 322 and the shallow trench isolations 110a, 110b, 110c, and together occupy the space of the recesses R4, R5, R6, thereby improving the structural stability of the gate structures 340a, 340b, 340c. Thus, the semiconductor device 30 formed by the manufacturing method of this embodiment can have a more optimized device structure and performance, thereby achieving optimized operating performance.

[0112] In general, the present invention forms an epitaxial channel layer on a substrate that contacts both the top surface and sidewalls of the substrate. The epitaxial channel layer at least partially fills the groove between the shallow trench isolation (STI) and the substrate. This allows the film layer of a component (such as a gate structure) subsequently formed on the epitaxial channel layer to further fill the groove, thereby enhancing the structural stability of the component. As a result, the semiconductor device of the present invention has a more optimized component structure and performance, thereby improving the operating performance of the semiconductor device.

[0113] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of shallow trench isolations are provided in the substrate, comprising a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence; a channel layer directly contacting the top surface and sidewalls of the substrate and the top surface of the first insulating layer; as well as At least one gate structure is disposed on the channel layer and includes a gate dielectric layer and a conductive layer disposed in sequence, wherein the gate dielectric layer directly contacts the top surface of the channel layer.

2. The semiconductor device according to claim 1, wherein The top surface of the first insulating layer is lower than the top surface of the substrate, and the top surface of the second insulating layer is higher than the top surface of the substrate.

3. The semiconductor device according to claim 1, wherein The channel layer physically contacts the top surface of the first insulating layer and the sidewalls of the second insulating layer at the same time.

4. The semiconductor device according to claim 1, wherein The gate dielectric layer is partially located between the second insulating layer and the channel layer, and a bottom surface of the gate dielectric layer is lower than a top surface of the second insulating layer.

5. The semiconductor device according to claim 4, wherein The gate dielectric layer directly contacts a sidewall of the second insulating layer. The semiconductor device according to claim 1 , wherein: The gate dielectric layer and the conductive layer are both partially located between the second insulating layer and the channel layer, and a bottom surface of the conductive layer is lower than a top surface of the second insulating layer.

7. The semiconductor device according to claim 6, wherein: The conductive layer includes a semiconductor layer, a barrier layer, and a metal layer arranged in sequence, wherein the semiconductor layer is partially arranged between the second insulating layer and the channel layer, and the bottom surface of the semiconductor layer is lower than the top surface of the second insulating layer.

8. The semiconductor device according to claim 1, wherein The at least one gate structure further includes a dielectric layer disposed between the gate dielectric layer and the conductive layer, wherein the dielectric layer is partially disposed between the second insulating layer and the channel layer, and a bottom surface of the dielectric layer is lower than a top surface of the second insulating layer.

9. The semiconductor device according to claim 8, wherein The conductive layer includes a bottom barrier layer, a semiconductor layer, a top barrier layer and a metal layer arranged in sequence, wherein the bottom barrier layer is partially arranged between the second insulating layer and the channel layer, and the bottom surface of the bottom barrier layer is lower than the top surface of the second insulating layer.

10. The semiconductor device according to claim 9, wherein The semiconductor layer is partially disposed between the second insulating layer and the channel layer, and a bottom surface of the semiconductor layer is lower than a top surface of the second insulating layer.

11. The semiconductor device according to claim 1, wherein The gate dielectric layer directly contacts the top surface of the first insulating layer, the top surface of the second insulating layer, and the top surface of the third insulating layer simultaneously.

12. The semiconductor device according to claim 11, wherein Two opposite side walls of the at least one gate structure are respectively disposed on the third insulating layers of the two shallow trench isolations.

13. The semiconductor device according to claim 1, wherein The channel layer further includes a first sub-channel layer and a second sub-channel layer. The first sub-channel layer covers the top surface of the substrate and exposes the sidewall of the substrate. The second sub-channel layer covers the first sub-channel layer and the sidewall of the substrate.

14. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of shallow trench isolations in the substrate, wherein each of the shallow trench isolations comprises a first insulating layer, a second insulating layer, and a third insulating layer stacked in sequence; forming a channel layer on the surface and sidewalls of the substrate, directly contacting the top surface and sidewalls of the substrate and the top surface of the first insulating layer; and At least one gate structure is formed on the channel layer, comprising a gate dielectric layer and a conductive layer arranged in sequence, wherein the gate dielectric layer directly contacts the top surface of the channel layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: When forming the channel layer, the channel layer physically contacts the top surface of the first insulating layer and the sidewall of the second insulating layer at the same time.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: After forming the channel layer, the gate dielectric layer is formed, and the gate dielectric layer directly contacts the sidewall of the second insulating layer.

17. The method for manufacturing a semiconductor device according to claim 14, wherein: After forming the channel layer, the gate dielectric layer and the conductive layer are formed in sequence, wherein both the gate dielectric layer and the conductive layer are partially located between the second insulating layer and the channel layer, and the bottom surface of the conductive layer is lower than the top surface of the second insulating layer.

18. The method for manufacturing a semiconductor device according to claim 14, wherein: After forming the gate dielectric layer and before forming the conductive layer, the method further includes: A dielectric layer is formed between the gate dielectric layer and the conductive layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The gate dielectric layer and the dielectric layer are both partially located between the second insulating layer and the channel layer, and a bottom surface of the dielectric layer is lower than a top surface of the second insulating layer.

20. The method for manufacturing a semiconductor device according to claim 18, wherein: The gate dielectric layer, the dielectric layer, and the conductive layer are all partially located between the second insulating layer and the channel layer, and a bottom surface of the conductive layer is lower than a top surface of the second insulating layer.

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