Electronic component and method for manufacturing the same

Abstract

The invention provides an electronic component and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor-on-insulator (SOI) substrate, wherein the SOI substrate comprises a base substrate, a buried oxide layer on the base substrate and an SOI layer on the buried oxide layer; masking a first region of the SOI substrate, and oxidizing the SOI layer in a second region of the SOI substrate so that the oxidized SOI layer and the buried oxide layer form an oxide layer together; sequentially forming a gate dielectric layer and a gate electrode layer on the SOI substrate, and patterning the gate dielectric layer and the gate electrode layer into a first gate stack in the first region and a second gate stack in the second region; forming a first side wall on the side wall of the first gate stack and forming a second side wall on the side wall of the second gate stack; forming a first source / drain layer on the SOI layer in the first region; in the second region, etching the oxide layer on two opposite sides of the second gate stack to expose the base substrate; and forming a second source / drain layer on the base substrate exposed in the second region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an electronic component and a manufacturing method thereof, and more particularly to an electronic assembly including both a low-voltage semiconductor device and a medium-voltage semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of semiconductor technology, the size of semiconductor devices continues to be miniaturized. In pursuit of device miniaturization, in addition to three-dimensional semiconductor device structures such as fin field-effect transistors (FinFETs), planar semiconductor device structures such as fully depleted semiconductor-on-insulator (FDSOI) with an ultra-thin silicon layer have been proposed. Compared to FinFET devices, FDSOI devices have fewer process steps and can achieve dynamic power optimization by dynamically adjusting the threshold voltage (Vth) by applying a back-gate voltage.

[0003] Furthermore, in some applications, it is desirable to integrate low-voltage devices and medium-voltage devices. However, low-voltage devices and medium-voltage devices have different device structures and therefore require different manufacturing processes. Summary of the Invention

[0004] An object of the present disclosure is at least partially to provide an electronic component and a method for manufacturing the same that can integrate different types of devices, such as low-voltage devices and medium-voltage devices, in a simplified process.

[0005] In a first aspect of the present disclosure, a method for manufacturing an electronic component is provided, which may include: providing a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer; masking a first region of the SOI substrate, and oxidizing the SOI layer in a second region of the SOI substrate so that the oxidized SOI layer forms an oxide layer together with the buried oxide layer; sequentially forming a gate dielectric layer and a gate electrode layer on the SOI substrate, and patterning them into a first gate stack in the first region and a second gate stack in the second region, respectively; forming a first spacer on a sidewall of the first gate stack and forming a second spacer on a sidewall of the second gate stack; forming a first source / drain layer on the SOI layer in the first region; in the second region, etching the oxide layer on opposite sides of the second gate stack to expose the base substrate; and forming a second source / drain layer on the exposed base substrate in the second region.

[0006] According to an embodiment, forming a first spacer on the sidewall of the first gate stack may include: forming a first sub-spacer on the sidewall of the first gate stack and forming a second sub-spacer on the sidewall of the second gate stack in the same spacer formation process. The first spacer may include a first sub-spacer. Forming a second spacer on the sidewall of the second gate stack may include: forming a fourth sub-spacer on the outer sidewall of the second sub-spacer formed on the sidewall of the second gate stack. The second spacer may include a second sub-spacer and a fourth sub-spacer.

[0007] According to an embodiment, the fourth sub-spacer may be formed and the third sub-spacer may be formed on the outer sidewall of the first sub-spacer in the same spacer formation process.

[0008] According to an embodiment of the present disclosure, in the first region, the first sub-spacer may be located on the SOI layer, and the third sub-spacer may be located on the first source / drain layer.

[0009] According to an embodiment of the present disclosure, in the second region, the second sub-spacer and the fourth sub-spacer may be located on the oxide layer.

[0010] According to an embodiment of the present disclosure, a low-voltage semiconductor device may be formed in the first region, and a medium-voltage semiconductor device may be formed in the second region.

[0011] According to an embodiment of the present disclosure, the oxide layer may have a thickness of 30 nm.

[0012] According to an embodiment of the present disclosure, forming the first source / drain layer on the SOI layer in the first region may be performed by selective epitaxial growth after forming the first sub-spacer and before forming the third sub-spacer.

[0013] In a second aspect of the present disclosure, an electronic component is provided, which may include: an SOI substrate including a base substrate, wherein the SOI substrate includes a first region and a second region, the first region including an SOI layer, the second region including a first oxide layer, the first oxide layer including the same semiconductor element and oxygen as the SOI layer; a first semiconductor device in the first region; and a second semiconductor device in the second region. The first semiconductor device may include: a first gate stack including a first gate dielectric layer and a first gate electrode layer on the SOI layer; a first spacer on the sidewalls of the first gate stack; and first source / drain layers on opposite sides of the first gate stack on the SOI layer. The second semiconductor device may include: a second gate stack including a second gate dielectric layer and a second gate electrode layer on the first oxide layer; second spacers on the sidewalls of the second gate stack, wherein the first oxide layer is provided below the second gate stack and the second spacer and exposes the base substrate at opposite ends; and the exposed second source / drain layers on opposite sides of the second gate stack on the base substrate.

[0014] According to an embodiment of the present disclosure, the first semiconductor device may be a low-voltage semiconductor device, and the second semiconductor device may be a medium-voltage semiconductor device.

[0015] According to an embodiment of the present disclosure, the first region may further include a buried oxide layer between the base substrate and the SOI layer, and the second region also includes a buried oxide layer located between the base substrate and the first oxide layer, and the buried oxide layer and the first oxide layer on the buried oxide layer together form a second oxide layer.

[0016] According to an embodiment of the present disclosure, the thickness of the second oxide layer may be 30 nm.

[0017] According to an embodiment of the present disclosure, the second spacer may have a thickness greater than that of the first spacer.

[0018] According to an embodiment of the present disclosure, the first spacer may include a first sub-spacer, and the second spacer may include a second sub-spacer and a fourth sub-spacer. The second sub-spacer may be interposed between the fourth sub-spacer and the second gate stack. The first sub-spacer may have the same material and thickness as the second sub-spacer.

[0019] According to an embodiment of the present disclosure, in the first region, a third sub-spacer as a dummy spacer may be further included on the sidewall of the first sub-spacer. The third sub-spacer may have the same material and thickness as the fourth sub-spacer.

[0020] According to an embodiment of the present disclosure, in the first region, the first sub-spacer may be located on the SOI layer, and the third sub-spacer may be located on the first source / drain layer. In the second region, the second and fourth sub-spacers may be located on the second oxide layer.

[0021] According to an embodiment of the present disclosure, the first gate dielectric layer and the second gate dielectric layer may have the same material and thickness.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0024] Figure 1 is a schematic diagram of a cross-sectional view of an electronic assembly including a low-voltage semiconductor device and a medium-voltage semiconductor device according to an embodiment of the present disclosure;

[0025] Figure 2 is a flow chart of a method for manufacturing an electronic component according to an embodiment of the present disclosure; and

[0026] Figures 3 to 9 According to the embodiment of the present disclosure Figure 1 A cross-sectional view of an intermediate process in an example operation of an electronic assembly. DETAILED DESCRIPTION

[0027] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0028] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Therefore, appearances of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Furthermore, those of ordinary skill in the art will appreciate that the figures provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0029] It should be understood that when an element is referred to as being "coupled to" or "connected to" another element, it can be directly coupled or connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, there are no intervening elements. Like reference numerals indicate like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0032] When expressions such as “at least one of A, B, and C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, and C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). When expressions such as “at least one of A, B, or C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, or C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.).

[0033] According to embodiments of the present disclosure, an electronic component and a method for manufacturing the same are provided. For example, the electronic component may include: a semiconductor-on-insulator (SOI) substrate comprising a base substrate, wherein the SOI substrate further comprises a buried oxide layer on the base substrate and an SOI layer on the buried oxide layer in a first region, and an oxide layer in a second region, wherein the oxide layer comprises the buried oxide layer and an additional oxide layer on the buried oxide layer, the additional oxide layer comprising the same semiconductor element as the SOI layer and oxygen; a first semiconductor device in the first region; and a second semiconductor device in the second region. The first semiconductor device may include: a first gate stack comprising a first gate dielectric layer and a first gate electrode layer on the SOI layer; a first spacer on the sidewalls of the first gate stack; and first source / drain layers on opposite sides of the first gate stack on the SOI layer. The second semiconductor device may include: a second gate stack comprising a second gate dielectric layer and a second gate electrode layer on the oxide layer; second spacers on the sidewalls of the second gate stack, wherein the oxide layer is disposed below the second gate stack and the second spacer and exposes the base substrate at opposite ends; and the exposed second source / drain layers on opposite sides of the second gate stack on the base substrate.

[0034] According to an embodiment, an additional oxide layer can be obtained by oxidizing the SOI layer in the second region, so that the additional oxide layer forms a thicker oxide layer together with the buried oxide layer, which can effectively increase the equivalent thickness of the gate dielectric in the second region to meet the electrical requirements of semiconductor devices formed in the second region, such as medium-voltage devices.

[0035] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with specific embodiments.

[0036] Figure 1 is a schematic cross-sectional view of an electronic component according to an embodiment of the present disclosure.

[0037] like Figure 1As shown, an electronic assembly 100 according to an exemplary embodiment may include a first semiconductor device 10 and a second semiconductor device 20. For example, the first semiconductor device 10 may be a low-voltage device, and the second semiconductor device 20 may be a medium-voltage device, such as a device for use in an approximately 8 to 10 volt (V) voltage environment.

[0038] The first semiconductor device 10 and the second semiconductor device 20 may be formed on the same semiconductor-on-insulator (SOI) substrate. The SOI substrate may include a base substrate 100 and a buried oxide layer 101 on the base substrate 100. The base substrate 100 may include a suitable semiconductor material, such as silicon (Si), and the buried oxide layer 101 may include an oxide, such as silicon oxide.

[0039] The SOI substrate may include a first region S1 and a second region S2. The first region S1 and the second region S2 may be divided according to the type of device to be formed therein, for example, the first region S1 is used to form a low-voltage device and the second region S2 is used to form a medium-voltage device. The first semiconductor device 10 may be formed in the first region S1, and the second semiconductor device 20 may be formed in the second region S2. Although the first region S1 and the second region S2 are shown as separated from each other in the drawings, this is merely for convenience of illustration; however, they may be physically continuous with each other.

[0040] In the first region S1, the SOI substrate may further include an SOI layer 102 on the buried oxide layer 101. The buried oxide layer 102 may include a suitable semiconductor material, for example, the same semiconductor material as the base substrate 100, such as Si, or a semiconductor material different from the base substrate 100, such as silicon germanium (SiGe).

[0041] In the second region S2, the SOI substrate may further include an oxide layer 202' on the base substrate 100. The oxide layer 202' may include the buried oxide layer 101 and an additional oxide layer on the buried oxide layer 101. As described below, the additional oxide layer may be obtained by oxidizing the SOI layer 102 in the second region S2. That is, the additional oxide layer may be an oxidized SOI layer, and thus may include the same semiconductor elements and oxygen as the SOI layer. The oxide layer 202' may serve as an additional gate dielectric for the second semiconductor device 20. In an exemplary embodiment, the thickness of the oxide layer 202' may be in the range of 20 nm to 40 nm, for example, 30 nm.

[0042] The first semiconductor device 10 may include a first gate stack 103 on an SOI layer 102. The first gate stack 103 may include a first gate dielectric layer and a first gate electrode layer on the SOI layer 102. The first gate stack 103 may be a high-K metal gate. For example, the first gate dielectric layer 106 may include a high-K gate dielectric such as hafnium oxide (HfO2), the first gate electrode layer may include a work function layer 107 such as a conductive metal nitride such as titanium nitride (TiN), and a gate conductor layer 108 such as a metal such as tungsten (W). Furthermore, an interfacial layer, such as an oxide, may be formed between the first gate dielectric layer 106 and the SOI layer 102. A hard mask layer, such as one used to facilitate patterning, may also be present on the top surface of the first gate electrode layer. Alternatively, the gate conductor layer may include polysilicon, and silicide may be formed on the polysilicon to reduce contact resistance.

[0043] A first sidewall spacer may be formed on the sidewall of the first gate stack 103. For example, the first sidewall spacer may include a first sub-sidewall spacer 104-1. For example, the first sub-sidewall spacer 104-1 may include a nitride such as silicon nitride. Here, the first sub-sidewall spacer 104-1 is shown as a single-layer structure. However, the present disclosure is not limited to this. For example, the first sub-sidewall spacer 104-1 may include a multi-layer structure. In this example, a third sub-sidewall spacer 104-2 on the sidewall of the first sub-sidewall spacer 104-1 is also shown. As described below, for the first semiconductor device 10, the third sub-sidewall spacer 104-2 may be a dummy sidewall spacer, rather than a real gate sidewall spacer for isolating the gate stack and the source / drain from each other.

[0044] The first semiconductor device 10 may further include first source / drain layers 105 on opposite sides of the first gate stack 103. For example, the first source / drain layers 105 may be grown on the SOI layer 102. The first source / drain layers 105 may include a suitable semiconductor material such as Si or SiGe, and may be doped to a desired conductivity type by, for example, in-situ doping or ion implantation during growth, for example, doping to n-type for an n-type device and doping to p-type for a p-type device.

[0045] In the first semiconductor device 10 , the first sub-spacer 104 - 1 may be located between the first source / drain layer 105 and the first gate stack, and the third sub-spacer 104 - 2 serving as a dummy spacer may be formed on the first source / drain layer 105 .

[0046] The second semiconductor device 20 may include a second gate stack 203 on an oxide layer 202'. Similarly, the second gate stack 203 may include a second gate dielectric layer 206 and a second gate electrode layer on the oxide layer 202'. As shown, the second gate electrode layer may include a work function layer 207 and a gate conductor layer 208. In an exemplary embodiment, the first gate stack 103 in the first region S1 may have the same configuration as the second gate stack 203 in the second region S2. For example, the second gate dielectric layer and the second gate electrode layer in the second gate stack 203 may be formed from the same material layers as the first gate dielectric layer and the first gate electrode layer in the first gate stack 103, respectively, and therefore may have the same thickness and material. The work function layer 207 may be the same as the work function layer 107, and the gate conductor layer 208 may be the same as the gate conductor layer 108. Unlike the first gate stack 103 in the first region S1, which is disposed on the SOI layer 102, the second gate stack 203 in the second region S2 is disposed on the oxide layer 202'.

[0047] A second spacer is provided on the sidewall of the second gate stack 203. Considering the different electrical requirements of the medium voltage device and the low voltage device, the thickness of the second spacer ( Figure 1 The dimension in the X direction) can be greater than the thickness of the first sidewall ( Figure 1 Dimensions in the X direction in the middle). In an exemplary embodiment, the second spacer may include a second sub-spacer 204-1 and a fourth sub-spacer 204-2 on the second sub-spacer 204-1. For example, the second sub-spacer 204-1 and the fourth sub-spacer 204-2 may include the same material, such as nitride, or may include different materials. Here, the second sub-spacer 204-1 and the fourth sub-spacer 204-2 are both shown as single-layer structures, but at least one of them may have a multi-layer structure. Unlike the first spacer in the first region S1 that is disposed on the SOI layer 102, the second spacer in the second region S2 (including the second sub-spacer 204-1 and the fourth sub-spacer 204-2) may be disposed on the oxide layer 202'.

[0048] In the second region S2, the oxide layer 202' may be disposed below the second gate stack 203 and the second spacer (including the second sub-spacer 204-1 and the fourth sub-spacer 204-2), with the base substrate 100 exposed at opposite ends thereof. In an exemplary embodiment, the oxide layer 202' and the buried oxide layer 101 may be self-aligned with the second gate stack 203 and the second spacer.

[0049] The second semiconductor device 20 may further include second source / drain layers 205 on opposite sides of the exposed base substrate, the second gate stack 203. For example, the second source / drain layers 205 may be grown on the exposed base substrate. The second source / drain layers 205 may include a suitable semiconductor material such as Si or SiGe, and may be doped to a desired conductivity type by, for example, in-situ doping or ion implantation during growth. For example, for an n-type device, the second source / drain layers 205 may be doped to n-type, and for a p-type device, the second source / drain layers 205 may be doped to p-type.

[0050] In an exemplary embodiment, silicide may be formed on the second source / drain layer 205 and the first source / drain layer 105 to reduce contact resistance.

[0051] In an exemplary embodiment, the first sub-spacer 104-1 in the first region S1 and the second sub-spacer 204-1 in the second region can be identical and can be formed in the same spacer forming process. In addition, the third sub-spacer 104-2 in the first region S1 and the fourth sub-spacer 204-2 in the second region can be identical and can be formed in the same spacer forming process.

[0052] In the second region S2, the second gate electrode layer in the second gate stack 203 controls the channel in the base substrate 100 (between the second source / drain layer 205) via the second gate dielectric layer and the additional oxide layer 202', thereby increasing the equivalent gate dielectric thickness, which can meet the electrical requirements of medium-voltage applications. In the first region S1, the first gate electrode layer in the first gate stack 103 controls the channel in the SOI layer 102 (between the first source / drain layer 105) via the first gate dielectric layer. Although the first semiconductor device 10 and the second semiconductor device 20 may have different requirements for the equivalent gate dielectric thickness, their respective gate stacks can be manufactured using the same process, thereby simplifying the process.

[0053] Figure 2 is a flow chart of a method 200 of manufacturing an electronic assembly according to an embodiment of the present disclosure.

[0054] like Figure 2 As shown, the method 200 according to this embodiment may include, for example, the following operations.

[0055] In operation S210, an SOI substrate may be provided, and the SOI substrate may include a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer. The SOI substrate may be provided, for example, by a smart-cut process.

[0056] In operation S220 , a first region of the SOI substrate may be masked, and an SOI layer may be oxidized in a second region of the SOI substrate so that the oxidized SOI layer forms an oxide layer together with the buried oxide layer.

[0057] For example, a first mask layer, such as nitride, may be formed on the SOI substrate to mask the first region (eg, Figure 1 S1 shown) and revealing the second region (e.g., Figure 1 An oxidation process is then performed on the SOI layer in the second region exposed by the first mask layer (S2). This oxidation process can be performed by simultaneously performing a heat treatment while implanting oxygen ions into the SOI layer. The resulting oxide layer can have a thickness of 20 nm to 40 nm, for example, 30 nm. After the oxidation process, the first mask layer can be removed.

[0058] In operation S230 , a gate dielectric layer and a gate electrode layer may be sequentially formed on the SOI substrate and patterned into a first gate stack in the first region and a second gate stack in the second region, respectively.

[0059] In operation S240 , a first spacer may be formed on a sidewall of the first gate stack and a second spacer may be formed on a sidewall of the second gate stack.

[0060] The spacer forming process can be performed in the first region and the second region respectively to form the first spacer and the second spacer. According to an embodiment of the present disclosure, the first spacer and the second spacer can also be formed by the same process.

[0061] For example, forming a first spacer on a sidewall of the first gate stack may include forming a first sub-spacer on the sidewall of the first gate stack and forming a second sub-spacer on the sidewall of the second gate stack in the same spacer formation process (first spacer formation process). The first spacer may include the first sub-spacer. The second sub-spacer may constitute a portion of the second spacer.

[0062] Forming the second spacer on the sidewall of the second gate stack may further include: forming a fourth sub-spacer on the outer sidewall of the second sub-spacer formed on the sidewall of the second gate stack. The second spacer may include the second sub-spacer and the fourth sub-spacer.

[0063] In an exemplary embodiment, forming the fourth sub-spacer may include forming the fourth sub-spacer and forming the third sub-spacer on an outer sidewall of the first sub-spacer in the same spacer forming process (second spacer forming process).

[0064] In an exemplary embodiment, in the first region, the first sub-spacer may be located on the SOI layer, and the third sub-spacer may be located on the first source / drain layer. The third sub-spacer may be a dummy spacer.

[0065] According to the embodiments of the present disclosure, the first and second spacers can be formed using the same first and second spacer formation processes, thereby simplifying the process. The third sub-spacer formed in the second spacer formation process can be a dummy spacer, thereby achieving a thickness of the second spacer (including the second and fourth sub-spacers) greater than the thickness of the first spacer (including the first sub-spacer).

[0066] In operation S250 , a first source / drain layer may be formed on the SOI layer of the first region.

[0067] In an exemplary embodiment, forming the first source / drain layer on the SOI layer in the first region may be performed by selective epitaxial growth after forming the first sub-spacer (i.e., a first spacer formation process) and before forming the third sub-spacer (i.e., a second spacer formation process).

[0068] In operation S260 , the oxide layer may be etched at opposite sides of the second gate stack in the second region to expose the base substrate.

[0069] In operation S270 , a second source / drain layer may be formed on the base substrate exposed in the second region.

[0070] In exemplary embodiments, a low voltage semiconductor device may be formed in the first region, and a medium voltage semiconductor device may be formed in the second region.

[0071] Figures 3 to 9 is a cross-sectional view of a portion of an intermediate process in an example operation of manufacturing an electronic component according to an embodiment of the present disclosure. Figure 1 The same reference numerals are used for the same layers / regions in the above drawings. Figure 1 The description is duplicate content.

[0072] like Figure 3 As shown, a first mask layer M1 may be provided on the SOI substrate to mask the first region S1 and expose the second region S2. For example, the first mask layer M1 may include nitride.

[0073] Here, the first region S1 and the second region S2 are shown as two separate regions, but those skilled in the art will appreciate that the first region S1 and the second region S2 may be adjacent to each other.

[0074] An oxidation process may be performed on the SOI layer 102 in the second region S2 exposed by the first mask layer M1. For example, the oxidation process may be performed by performing a heat treatment while implanting oxygen ions into the SOI layer 102. Figure 4As shown, after the oxidation process, the SOI layer in the second region S2 is oxidized, thereby forming an oxide layer 202 ′ together with the buried oxide layer.

[0075] In exemplary embodiments, a bottom surface of the oxide layer 202 ′ may be substantially coplanar with a bottom surface of the buried oxide layer in the first region.

[0076] In addition, after the oxidation process is performed, the first mold layer M1 may be removed.

[0077] like Figure 5 As shown, a first gate stack 103 and a second gate stack 203 may be formed on the first region S1 and the second region S2 , respectively.

[0078] In an exemplary embodiment, the first gate stack 103 and the second gate stack 203 can be formed using the same process to save process steps. For example, a gate dielectric material layer, a work function material layer, and a gate conductor material layer can be sequentially formed on the SOI layer 102 in the first region S1 and on the oxide layer 202' in the second region S2 by deposition, such as chemical vapor deposition (CVD). These deposited material layers can be patterned into stacks in the first region S1 and the second region S2, namely, the first gate stack 103 and the second gate stack 203, respectively, by reactive ion etching (RIE).

[0079] In another exemplary embodiment, the first gate stack 103 and the second gate stack 203 may be individually formed of the same or different materials.

[0080] Spacers may be formed on the sidewalls of the first gate stack 103 and the second gate stack 203. According to electrical requirements, the thickness of the first spacer on the sidewall of the first gate stack 103 may be thinner than the thickness of the second spacer of the second gate stack 203.

[0081] like Figure 6 As shown, in the first region S1, a first sub-spacer 104-1 can be formed on both sides of the first gate stack 103 in the first direction (e.g., X direction), and a second sub-spacer 204-1 can be formed on both sides of the second gate stack 203 in the first direction (e.g., X direction).

[0082] In an exemplary embodiment, to save process steps, the first sub-spacer 104-1 and the second sub-spacer 204-1 can be formed in the same spacer formation process (e.g., the first spacer formation process described above). For example, a spacer material layer, such as a nitride, can be conformally formed in the first region S1 and the second region S2 by deposition, such as CVD, and the deposited spacer material layer can be anisotropically etched, such as by RIE in the vertical direction. This removes the portion of the spacer material layer extending on the lateral surface of the underlying structure, while retaining the portion extending on the vertical surface of the underlying structure (e.g., the sidewall of the gate stack), thereby forming the first sub-spacer 104-1 and the second sub-spacer 204-1. Therefore, the first sub-spacer 104-1 and the second sub-spacer 204-1 can have the same material and thickness.

[0083] In another exemplary embodiment, the first sub-spacer 104 - 1 and the second sub-spacer 204 - 1 may be formed of the same or different materials.

[0084] like Figure 7 As shown, a first source / drain layer 105 may be formed on the SOI layer 102 in the first region.

[0085] For example, the first source / drain layer 105 can be formed by selective epitaxial growth on the SOI layer 102. Therefore, the first source / drain layer 105 can be disposed on the SOI layer. In the second region, due to the presence of the oxide layer 202', no source / drain layers are formed on opposite sides of the second gate stack 203.

[0086] like Figure 8 As shown, a fourth sub-spacer 204 - 2 may be formed on the outer sidewall of the second sub-spacer 204 - 1 .

[0087] Regarding the sidewall formation process, the above has been combined Figure 6 During the process of forming the fourth sub-spacer 204-2 (e.g., the above-mentioned second spacer formation process), the third sub-spacer 104-2 may also be formed on the outer sidewall of the first sub-spacer 104-1. The third sub-spacer 104-2 and the fourth sub-spacer 204-2 may have the same material and thickness.

[0088] The parameters used in the first and second spacer formation processes may be the same or different, and thus the configurations of the second sub-spacer 204-1 and the fourth sub-spacer 204-2 (eg, the number of layers, materials and thickness of each layer, etc.) may be the same or different.

[0089] In another exemplary embodiment, only the fourth sub-spacer 204 - 2 may be formed without forming the third sub-spacer 104 - 2 (eg, by masking the first region in the second spacer formation process).

[0090] like Figure 8 As shown, since the first source / drain region 105 is formed first, the third sub-spacer 104-2 is formed on the first source / drain layer 105. Therefore, the third sub-spacer 104-2 can be a dummy spacer.

[0091] In another exemplary embodiment, a spacer forming process may be performed in the first region S1 and the second region S2 respectively to form a first spacer and a second spacer. When processing one region, the other region may be shielded by a cover layer or the like.

[0092] like Figure 9 As shown, in the second region S2 , the second gate stack 203 and the second spacer (including the second sub-spacer 204 - 1 and the fourth sub-spacer 204 - 2 ) are used as masks to selectively etch both ends of the oxide layer, such as by RIE, to expose the base substrate 100 .

[0093] Return Reference Figure 1 On the exposed base substrate 100 , a second source / drain layer 205 may be formed by, for example, selective epitaxial growth.

[0094] According to the technical concepts of this disclosure, by oxidizing the SOI layer above the buried oxide layer, the equivalent thickness of the gate dielectric in the second region is increased to meet the electrical requirements of semiconductor devices, such as medium-voltage devices, formed in the second region. Furthermore, most of the fabrication processes in the first and second regions are compatible with each other, allowing different devices to be formed in the first and second regions using a simplified process flow.

[0095] Each box in the flow chart or block diagram in the disclosed embodiment can represent a hardware module, a program segment, or a part of code, and the above-mentioned module, program segment, or a part of code can include one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the flow chart or block diagram can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which depends on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart, can be implemented by a special hardware-based system that performs the specified function or operation, or can be implemented by a combination of special hardware and computer instructions.

[0096] Those skilled in the art will appreciate that, although the steps are shown above in order, the various steps shown above may be reordered, added, or deleted. For example, the steps described in this disclosure may be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not intended to limit the present disclosure.

[0097] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0098] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing an electronic component, comprising: Providing a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer; masking a first region of the SOI substrate, and oxidizing the SOI layer in a second region of the SOI substrate so that the oxidized SOI layer forms an oxide layer together with a buried oxide layer; forming a gate dielectric layer and a gate electrode layer in sequence on the SOI substrate, and patterning them into a first gate stack in the first region and a second gate stack in the second region; forming a first spacer on a sidewall of the first gate stack and forming a second spacer on a sidewall of the second gate stack; forming a first source / drain layer on the SOI layer in the first region; In the second region, etching the oxide layer on opposite sides of the second gate stack to expose the base substrate; as well as A second source / drain layer is formed on the base substrate exposed in the second region.

2. The method according to claim 1, wherein Forming a first spacer on the sidewall of the first gate stack includes: forming a first sub-spacer on the sidewall of the first gate stack and forming a second sub-spacer on the sidewall of the second gate stack in the same spacer formation process, wherein the first spacer includes the first sub-spacer, and Forming a second sidewall spacer on the sidewall of the second gate stack includes: forming a fourth sub-sidewall spacer on the outer sidewall of the second sub-sidewall spacer formed on the sidewall of the second gate stack, wherein the second sidewall spacer includes the second sub-sidewall spacer and the fourth sub-sidewall spacer.

3. The method according to claim 1, wherein Forming the fourth sub-spacer includes: In the same spacer forming process, the fourth sub-spacer is formed and the third sub-spacer is formed on the outer sidewall of the first sub-spacer.

4. The method according to claim 3, wherein: In the first region, the first sub-spacer is located on the SOI layer, and the third sub-spacer is located on the first source / drain layer.

5. The method according to claim 2, wherein: In the second region, the second sub-spacer and the fourth sub-spacer are located on the oxide layer.

6. The method according to claim 1, wherein A low-voltage semiconductor device is formed in the first region, and a medium-voltage semiconductor device is formed in the second region.

7. The method according to claim 1, wherein The oxide layer has a thickness of 30 nm.

8. The method according to claim 3, wherein: The first source / drain layer is formed on the SOI layer in the first region by selective epitaxial growth after forming the first sub-spacer and before forming the third sub-spacer.

9. An electronic component comprising: A semiconductor-on-insulator (SOI) substrate, comprising a base substrate, wherein the SOI substrate comprises a first region and a second region, the first region comprising an SOI layer, the second region comprising a first oxide layer, the first oxide layer comprising the same semiconductor element and oxygen element as the SOI layer; The first semiconductor device in the first region includes: a first gate stack, the first gate stack comprising a first gate dielectric layer and a first gate electrode layer on the SOI layer; a first spacer on the sidewall of the first gate stack, and first source / drain layers on opposite sides of the first gate stack on the SOI layer; The second semiconductor device in the second region includes: a second gate stack, the second gate stack comprising a second gate dielectric layer and a second gate electrode layer on the first oxide layer, a second spacer on the sidewall of the second gate stack, wherein the first oxide layer is disposed below the second gate stack and the second spacer and exposes the base substrate at opposite ends, and The second source / drain layers on opposite sides of the second gate stack are exposed on the base substrate.

10. The electronic component according to claim 9, wherein The first semiconductor device is a low-voltage semiconductor device, and the second semiconductor device is a medium-voltage semiconductor device.

11. The electronic component according to claim 9, wherein The first region further includes a buried oxide layer between the base substrate and the SOI layer, and The second region further includes a buried oxide layer located between the base substrate and the first oxide layer. The buried oxide layer and the first oxide layer on the buried oxide layer together form a second oxide layer.

12. The electronic component according to claim 11, wherein The thickness of the second oxide layer is 30 nm.

13. The electronic component according to claim 11, wherein The second sidewall has a thickness greater than that of the first sidewall.

14. The electronic component according to claim 13, wherein The first sidewall spacer includes a first sub-sidewall spacer, The second sidewall spacer includes a second sub-sidewall spacer and a fourth sub-sidewall spacer, and the second sub-sidewall spacer is located between the fourth sub-sidewall spacer and the second gate stack. The first sub-spacer has the same material and thickness as the second sub-spacer.

15. The electronic component according to claim 14, wherein The first region further includes a third sub-spacer as a dummy spacer on the sidewall of the first sub-spacer. The third sub-spacer has the same material and thickness as the fourth sub-spacer.

16. The electronic component according to claim 15, wherein In the first region, the first sub-spacer is located on the SOI layer, and the third sub-spacer is located on the first source / drain layer. In the second region, the second sub-spacer and the fourth sub-spacer are located on the second oxide layer.

17. The electronic component according to claim 9, wherein The first gate dielectric layer and the second gate dielectric layer have the same material and thickness.

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