A combined passivation back contact battery and its preparation method

Abstract

The present invention belongs to the technical field of back-contact batteries, and specifically relates to a combined passivation back-contact battery and a preparation method thereof, comprising the following steps: S4, depositing a mask layer on a first semiconductor layer, the mask layer comprising a doped amorphous layer and a silicon nitride film layer formed in sequence, wherein the doping element of the doped amorphous layer is N or C; S5, forming a second semiconductor opening region arranged at intervals; S6, performing texturing and cleaning, simultaneously forming a velvet surface on the front side of the silicon wafer and the second semiconductor opening region, and removing a portion of the mask layer; S7, sequentially depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S8, performing a secondary cleaning to remove the wrap-around coating naturally formed on the back side during S7, followed by backwashing; S9, depositing a second semiconductor layer on the back side obtained in S8. The present invention can completely remove the wrap-around coating layer on the back side, thereby improving the open circuit voltage and short circuit current of the battery, thereby improving the battery efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a combined passivation back contact battery and a preparation method thereof. Background Art

[0002] At present, in the preparation of back contact batteries, the process flow with lower equipment cost is generally the following post-texturing process:

[0003] S101, providing a double-sided polished silicon wafer;

[0004] S102, sequentially depositing a first semiconductor layer and a first mask layer on the back side of the silicon wafer, wherein the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon film layer formed sequentially;

[0005] S103, laser or etching an opening on the back side of the silicon wafer to remove the first mask layer and a portion of the first semiconductor layer to form a second semiconductor opening region;

[0006] S104, texturing and cleaning, forming a texturing surface on the second semiconductor opening area on the back side and the front side, and removing the mask layer;

[0007] S105, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer, and then cleaning and removing the coating layer formed on the back side; and then forming a second semiconductor layer on the back side;

[0008] S106, laser or etching an opening on the back side of the silicon wafer to form a first semiconductor opening region alternately arranged with the second semiconductor opening region;

[0009] S107, depositing a conductive film layer on the back side of the silicon wafer;

[0010] S108, forming an insulating trench between the first semiconductor opening region and the second semiconductor opening region by laser or etching;

[0011] S109 , forming metal electrodes on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer.

[0012] However, in the post-texturing method for the aforementioned back-contact cell, the wrap-around coating layer generated on the back side after front-side coating is cleaned and removed, typically using a low-concentration alkali solution or a mixture of alkali solution and hydrogen peroxide. On the one hand, the low-concentration alkali solution will corrode the first doped polysilicon film layer. While the addition of hydrogen peroxide reduces the corrosion capacity of the first doped polysilicon film layer, it also reduces the corrosion capacity of the wrap-around coating layer in the second semiconductor opening area. On the other hand, if the wrap-around coating layer on the back side is more severe, the interface of the second semiconductor opening area cannot be cleaned thoroughly, resulting in a significant reduction in the passivation performance after the subsequent deposition of the second semiconductor layer, thereby affecting the open-circuit voltage and cell efficiency.

[0013] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0014] The purpose of the present invention is to overcome the defects of the prior art in the post-texturing method of the combined passivation back contact battery, which is caused by serious winding plating after the front side coating and the low open circuit voltage and battery efficiency caused by cleaning the winding plating. A combined passivation back contact battery and a preparation method thereof are provided, which can completely remove the winding plating layer on the back side, thereby improving the open circuit voltage and short circuit current of the battery, and further improving the battery efficiency.

[0015] In order to achieve the above objectives, in a first aspect, the present invention provides a method for preparing a combined passivated back contact cell, comprising the following steps:

[0016] S1, provide double-sided polished silicon wafers;

[0017] S2. forming a first semiconductor layer on the back side of the silicon wafer in sequence, wherein the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon film layer formed in sequence;

[0018] S3, cleaning and removing the phosphosilicate glass layer naturally formed on the surface of the first semiconductor layer in S2;

[0019] S4, depositing a mask layer on the first semiconductor layer, the mask layer comprising a doped amorphous layer and a silicon nitride film layer formed in sequence, wherein the doping element of the doped amorphous layer is N or C;

[0020] S5, performing a first etching opening on the first semiconductor layer on the back side obtained in S4 and its corresponding mask layer to form second semiconductor opening regions arranged at intervals;

[0021] S6, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area at the same time, and removing part of the thickness of the mask layer. The thickness of the mask layer removed is 20%-60% of the total thickness of S4;

[0022] S7, depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer in sequence;

[0023] S8, secondary cleaning to remove the wrap-around coating naturally formed on the back side during S7, followed by backwashing; the secondary cleaning process includes: first using a hydrofluoric acid aqueous solution to remove the anti-reflection wrap-around coating, which will also remove the remaining mask layer, then using a low-concentration alkaline solution with a mass concentration of 0.1%-1% to remove the passivation wrap-around coating, and controlling the thinning amount on the back side of the silicon wafer to 0.1-1µm, and then backwashing;

[0024] S9. Depositing a second semiconductor layer on the back surface of the substrate obtained in S8. The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer formed in sequence. The thickness of the intrinsic amorphous silicon layer is thinned to 5-10 nm, and the thickness of the second doped silicon layer is thinned to 5-15 nm.

[0025] In some preferred embodiments of the present invention, the total thickness of the mask layer in S4 is 35-100 nm; and / or,

[0026] The thickness of the doped amorphous layer is 3-20 nm, and the thickness of the silicon nitride film layer is 30-80 nm.

[0027] In some preferred embodiments of the present invention, the doping concentration of the doping element in the amorphous layer in S4 is 1e18 cm -3 -1e19cm -3 and / or,

[0028] In S4, the refractive index of the doped amorphous layer is 3.0-3.2, and the refractive index of the silicon nitride film layer is 1.8-2.2.

[0029] In some preferred embodiments of the present invention, in S4, the formation conditions of the doped amorphous layer include: introducing silane, hydrogen, and nitrogen or methane, turning on the glow for reaction, during which the reaction temperature is controlled to be 400-480°C, the reaction pressure is 500-3000mtorr, the power is 3000-6000W, and the reaction time is 100-300s; wherein the silane flow rate is 500-1000sccm, the hydrogen flow rate is 1000-5000sccm, the nitrogen flow rate is 500-1000sccm, and the methane flow rate is 100-500sccm.

[0030] In some preferred embodiments of the present invention, the conditions for forming the silicon nitride film layer include: introducing silane and ammonia, turning on the glow to react, during which the reaction temperature is controlled at 400-480°C, the reaction pressure is 500-3000mtorr, the power is 5000-8000W, and the reaction time is 300-600s; wherein the silane flow rate is 800-1200sccm, and the ammonia flow rate is 5000-8000sccm.

[0031] In some preferred embodiments of the present invention, in S7, the passivation layer includes a second tunneling oxide layer and a second doped polycrystalline layer; the thickness of the second tunneling oxide layer is 1-2 nm, and the thickness of the second doped polycrystalline layer is 1-10 nm.

[0032] In some preferred embodiments of the present invention, the anti-reflection layer is silicon nitride, and the thickness of the silicon nitride is 70-120 nm.

[0033] In some preferred embodiments of the present invention, in S8, the passivation layer and the plating layer are removed so that the silicon wafer surface corresponding to the second semiconductor opening region is controlled to have a semi-polished or fully-polished structure, and the semi-polished structure includes a semi-pyramid structure.

[0034] In some preferred embodiments of the present invention, in S8, a chain cleaning machine is used to remove the anti-reflection coating, and the speed of the transmission roller of the chain cleaning machine is 1.2-4.0 m / min.

[0035] In some preferred embodiments of the present invention, in S8, when removing the anti-reflection coating, the reaction temperature of the hydrofluoric acid aqueous solution is controlled to be 20-35° C., and the mass concentration of hydrofluoric acid in the hydrofluoric acid aqueous solution is 2%-10%.

[0036] In some preferred embodiments of the present invention, in S8, the conditions for removing the passivation layer around the plating layer include: using tank cleaning, a reaction temperature of 20-45° C., and a reaction time of 10-120 s.

[0037] In some preferred embodiments of the present invention, in S8, the backwashing process includes sequentially performing alkaline washing, acid washing, and hydrofluoric acid washing, wherein each solution tank in the backwashing process is followed by a water washing step.

[0038] In some preferred embodiments of the present invention, the preparation method further comprises:

[0039] S10, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0040] S11, depositing a conductive film layer on the back surface obtained in S10;

[0041] S12, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench;

[0042] S13 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

[0043] In a second aspect, the present invention provides a combined passivated back contact cell, which is prepared by the preparation method of the combined passivated back contact cell described in the first aspect.

[0044] Beneficial effects:

[0045] The present invention adopts the above-mentioned technical scheme, and adopts a doped amorphous layer and a silicon nitride film layer as a stacked mask layer in the post-texturing method of the combined passivation back contact battery, wherein the doped amorphous layer is doped with N or C. Since the silicon nitride film layer is relatively easy to corrode in hydrofluoric acid, the silicon nitride film layer in the mask layer retained on the first semiconductor layer will be partially or completely corroded in the secondary cleaning after the front coating to remove the anti-reflection layer around the coating layer, but the doped amorphous layer doped with N or C forms Si-N or Si-C bonds, the density of the film layer is improved, and the corrosion resistance to hydrofluoric acid and alkali solution is significantly enhanced (while the undoped amorphous layer has weak corrosion resistance to hydrofluoric acid and alkali solution), the doped amorphous layer doped with N or C is almost not corroded in hydrofluoric acid, so it can be completely retained; in addition, a suitable low-concentration alkaline solution is used to remove the passivation layer around the coating layer, and the second semiconductor opening area on the back side will be corroded at the same time. After corrosion, the velvet surface of the second semiconductor opening area partially or completely disappears, thereby controlling the thinning of the back side of the silicon wafer. The thickness of the doped amorphous layer is 0.1-1µm, forming a semi-polished (i.e., semi-pyramid structure) or fully polished structure, thereby ensuring that the winding coating layer in the second semiconductor opening area is completely removed, and the doped amorphous layer on the first semiconductor layer has enhanced corrosion resistance to alkaline solution after being doped with N or C, and can completely protect the underlying first doped polycrystalline silicon film layer from corrosion in a mild low-concentration alkaline solution, thereby not affecting its passivation performance; and because the method of the present invention can make the structure of the second semiconductor opening area a semi-polished or fully polished structure, which is beneficial to the passivation of the second semiconductor layer, the thickness of the intrinsic amorphous silicon layer and the second doped silicon layer of the second semiconductor layer can be reduced to 10%-30% of the original thickness compared to the velvet structure of the prior art (which is a full pyramid structure), thereby reducing the parasitic absorption of the film layer and being more conducive to increasing the current; thereby, the winding coating layer on the back can be completely removed while taking into account the improvement of the open circuit voltage and short-circuit current of the battery, thereby improving the battery efficiency. DETAILED DESCRIPTION

[0046] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0047] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0048] The endpoints of the ranges and any values ​​disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0049] In the present invention, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0050] In a first aspect, the present invention provides a method for preparing a combined passivated back contact cell, comprising the following steps:

[0051] S1, provide double-sided polished silicon wafers;

[0052] S2. forming a first semiconductor layer on the back side of the silicon wafer in sequence, wherein the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon film layer formed in sequence;

[0053] S3, cleaning and removing the phosphosilicate glass layer naturally formed on the surface of the first semiconductor layer in S2;

[0054] S4, depositing a mask layer on the first semiconductor layer, the mask layer comprising a doped amorphous layer and a silicon nitride film layer formed in sequence, wherein the doping element of the doped amorphous layer is N or C;

[0055] S5, performing a first etching opening on the first semiconductor layer on the back side obtained in S4 and its corresponding mask layer to form second semiconductor opening regions arranged at intervals;

[0056] S6, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area at the same time, and removing part of the thickness of the mask layer. The thickness of the mask layer removed is 20%-60% of the total thickness of S4;

[0057] S7, depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer in sequence;

[0058] S8, secondary cleaning to remove the wrap-around coating naturally formed on the back side during S7, followed by backwashing; the secondary cleaning process includes: first using a hydrofluoric acid aqueous solution to remove the anti-reflection wrap-around coating, which will also remove the remaining mask layer, then using a low-concentration alkaline solution with a mass concentration of 0.1%-1% to remove the passivation wrap-around coating, and controlling the thinning amount on the back side of the silicon wafer to 0.1-1µm, and then backwashing;

[0059] S9. Depositing a second semiconductor layer on the back surface of the substrate obtained in S8. The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer formed in sequence. The thickness of the intrinsic amorphous silicon layer is thinned to 5-10 nm, and the thickness of the second doped silicon layer is thinned to 5-15 nm.

[0060] It can be understood in the present invention that the cleaning in the texturing cleaning in S6 is a single cleaning, and therefore S8 is a secondary cleaning.

[0061] The mass concentration of the low-concentration alkali solution is 0.1%-1%, for example, it can be 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, etc., and the range between any two point values, for example, preferably 0.1%-0.4%.

[0062] The thinning amount of the back side of the silicon wafer is 0.1-1µm, for example, it can be 0.1µm, 0.2µm, 0.3µm, 0.4µm, 0.5µm, 0.6µm, 0.7µm, 0.8µm, 0.9µm, 1µm, etc., and the range between any two point values.

[0063] In the present invention, a phosphosilicate glass layer naturally forms on the surface of the first semiconductor layer in S2, and is removed by cleaning in S3. The cleaning solution and conditions in S3 can refer to the prior art. For example, a cleaning solution containing hydrofluoric acid can be used, and the mass concentration of hydrofluoric acid in the cleaning solution is 1%-5%. For example, the cleaning conditions may include a reaction time of 60-180 seconds and a reaction temperature of 20-30°C.

[0064] In some preferred embodiments of the present invention, the total thickness of the mask layer in S4 is 35-100 nm, for example, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, and any range between any two values. Using a mask layer of appropriate thickness is more conducive to protecting the underlying first semiconductor layer from damage during the texturing process.

[0065] The mask layer of the present invention can be formed by, for example, a tubular PECVD method.

[0066] In some preferred embodiments of the present invention, the thickness of the doped amorphous layer is 3-20 nm, preferably 3-14 nm.

[0067] In the present invention, preferably, the thickness of the silicon nitride film layer is 30-80 nm, more preferably 30-70 nm.

[0068] In a preferred embodiment of the present invention, a suitably thick silicon nitride film layer is used in combination with a relatively suitably thin doped amorphous layer, which is more conducive to improving the bonding strength between the film layers.

[0069] In some preferred embodiments of the present invention, the doping concentration of the doping element in the amorphous layer in S4 is 1e18 cm -3 -1e19cm -3 The use of a doped amorphous layer with an appropriate doping concentration is more conducive to enhancing the density and corrosion resistance of the film layer.

[0070] In some preferred embodiments of the present invention, in S4, the refractive index of the doped amorphous layer is 3.0-3.2, and the refractive index of the silicon nitride film layer is 1.8-2.2. The present invention uses a high-refractive-index doped amorphous layer and a low-refractive-index silicon nitride film layer to further improve the uniformity and density of the different film layers.

[0071] In some preferred embodiments of the present invention, in S4, the conditions for forming the doped amorphous layer include: introducing silane, hydrogen, and nitrogen or methane, turning on the glow light to carry out the reaction, controlling the reaction temperature to 400-480°C, and the reaction time to 100-300 seconds. Nitrogen or methane is selected based on the desired doping element. Further preferably, the conditions for forming the doped amorphous layer also include: a reaction pressure of 500-3000 mtorr and a power of 3000-6000 W.

[0072] Further preferably, in the formation conditions of the doped amorphous layer, the silane flow rate is 500-1000 sccm, the hydrogen flow rate is 1000-5000 sccm, the nitrogen flow rate is 500-1000 sccm, and the methane flow rate is 100-500 sccm.

[0073] In some preferred embodiments of the present invention, the conditions for forming the silicon nitride film include: introducing silane and ammonia gases, turning on a glow light to conduct a reaction, controlling the reaction temperature to be 400-480°C, and the reaction time to be 300-600 seconds. Furthermore, preferably, the conditions for forming the silicon nitride film also include: a reaction pressure of 500-3000 mtorr and a power of 5000-8000 W.

[0074] More preferably, in the formation conditions of the silicon nitride film layer, the silane flow rate is 800-1200 sccm, and the ammonia flow rate is 5000-8000 sccm.

[0075] The texturing solution used in the texturing cleaning step S6 of the present invention can be a mixture of an alkali (such as potassium hydroxide and / or sodium hydroxide), a texturing additive, and water, wherein the mass concentration of the alkali is 1%-5% and the mass concentration of the texturing additive is 0.5%-1%. For example, the texturing conditions may preferably include a texturing time of 8-12 minutes and a texturing temperature of 75-85°C.

[0076] The method for removing a partial thickness of the mask layer and its removal solution in S6 of the present invention can refer to the existing technology, as long as the target film layer can be removed. For example, the removal solution can be a hydrofluoric acid aqueous solution, the reaction temperature of the hydrofluoric acid aqueous solution is controlled to be 20-35°C, and the mass concentration of hydrofluoric acid in the hydrofluoric acid aqueous solution is 2%-10%.

[0077] In some preferred embodiments of the present invention, in S7, the passivation layer includes a second tunneling oxide layer and a second doped polycrystalline layer. This passivation layer structure, combined with the specially passivated first tunneling oxide layer and the first semiconductor layer formed by the first doped polycrystalline silicon film layer, further reduces the equipment cost of plate-type PECVD while improving cell efficiency.

[0078] Further preferably, the thickness of the second tunnel oxide layer is 1-2 nm, and the thickness of the second doped polycrystalline layer is 1-10 nm.

[0079] The doping type of the second doped polycrystalline layer of the present invention is the same as that of the first doped polysilicon film layer, both being N-type or P-type. The passivation layer and the anti-reflection layer of the present invention are preferably formed by a tubular PECVD method.

[0080] In some preferred embodiments of the present invention, the anti-reflection layer is silicon nitride, and the thickness of the silicon nitride is 70-120 nm.

[0081] In some preferred embodiments of the present invention, in S8, the passivation layer and the plating layer are removed so that the silicon wafer surface corresponding to the second semiconductor opening region is controlled to have a semi-polished or fully polished structure, where the semi-polished structure includes a semi-pyramid structure. It is understood that the velvet structure is a complete pyramid structure. The fully polished structure refers to a flat structure without pyramids.

[0082] In some preferred embodiments of the present invention, in S8, a chain cleaning machine is used to remove the anti-reflection coating, and the speed of the transmission roller of the chain cleaning machine is 1.2-4.0 m / min.

[0083] In some preferred embodiments of the present invention, in step S8 of removing the anti-reflection coating, the reaction temperature of the hydrofluoric acid aqueous solution is controlled to be 20-35° C. Preferably, the mass concentration of hydrofluoric acid in the hydrofluoric acid aqueous solution is 2%-10%.

[0084] In some preferred embodiments of the present invention, in S8, the conditions for removing the passivation layer around the plating layer include: using a tank cleaning method, a reaction temperature of 20-45°C, and a reaction time of 10-120 seconds. The alkali in the low-concentration alkaline solution used to remove the passivation layer around the plating layer can be potassium hydroxide and / or sodium hydroxide. The low-concentration alkaline solution can completely remove the plating layer without the need for adding hydrogen peroxide, and will not corrode the first semiconductor layer.

[0085] In some preferred embodiments of the present invention, in S8, the backwashing process includes sequentially performing alkali washing, acid washing, and hydrofluoric acid pickling, wherein a water washing step is performed after each solution tank in the backwashing process. Adopting this preferred solution is more conducive to ensuring the cleanliness of the interface of the second semiconductor opening area, thereby facilitating improving the passivation level of the second semiconductor layer. It is understandable that a water washing step is performed after each solution tank in the backwashing process, which means, for example, alkali washing, acid washing, and hydrofluoric acid pickling, water washing after alkali washing, water washing after acid washing, and water washing after hydrofluoric acid pickling.

[0086] The thickness and corresponding doping concentration of the first tunnel oxide layer and the first doped polysilicon film layer in S2 of the present invention and the corresponding doping concentration and preparation process of the second doped silicon layer in S9 can refer to the scope of the prior art and can be used in the present invention. For example, the thickness of the first tunnel oxide layer is 1-2nm, the thickness of the first doped polysilicon film layer is 70-300nm, and the effective doping concentration is greater than 5e18cm -3 The effective doping concentration of the second doped silicon layer is 1e18 cm -3 -9e19cm -3 The second doped silicon layer may be doped amorphous silicon or microcrystalline silicon. One of the first doped polysilicon film layer and the second doped silicon layer is N-type and the other is P-type.

[0087] The preparation method of the present invention may further comprise other conventional steps. In some preferred embodiments of the present invention, the preparation method further comprises:

[0088] S10, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0089] S11, depositing a conductive film layer on the back surface obtained in S10;

[0090] S12, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench;

[0091] S13 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

[0092] In a second aspect, the present invention provides a combined passivated back contact battery, which is prepared by the preparation method of the combined passivated back contact battery described in the first aspect. The combined passivated back contact battery of the present invention has a good passivation effect, can increase the open circuit voltage and short circuit current of the battery, and thus improve the battery efficiency.

[0093] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0094] Example 1

[0095] A combined passivated back contact cell is prepared by the following steps:

[0096] S1. Provide double-sided polished silicon wafers (N-type single crystal silicon wafers);

[0097] S2. Forming a first semiconductor layer on the back side of the S1 silicon wafer, the first semiconductor layer including a first tunneling oxide layer (first tunneling silicon oxide layer) and a first doped polysilicon film layer (i.e., an N-type polycrystalline layer) sequentially formed on the back side;

[0098] The thickness of the first tunneling silicon oxide layer is 1.5 nm; the thickness of the first doped polysilicon film layer is 100 nm, and the effective doping concentration is 1e19 cm -3 .

[0099] S3. Clean and remove the PSG layer on the surface of the first semiconductor layer; the cleaning solution is a solution containing hydrofluoric acid with a concentration of 2%, the reaction time is 100 s, and the reaction temperature is 25°C.

[0100] S4, depositing a mask layer on the first semiconductor layer;

[0101] The mask layer is a doped amorphous layer and a silicon nitride film layer formed in sequence. The total thickness of the mask layer is 70nm, wherein the doped amorphous layer is doped with N and the concentration of N is 3e18cm -3 , and the thickness of the doped amorphous layer is 10nm and the refractive index is 3.15, the thickness of the silicon nitride film layer is 60nm and the refractive index is 2.0.

[0102] The mask layer is formed by a tubular PECVD method, which specifically includes: in the first stage, silane, hydrogen, and nitrogen are introduced, the glow is turned on, and an N-doped or C-doped amorphous layer is formed by chemical reaction. The reaction temperature is 440°C, the silane flow rate is 800sccm, the hydrogen flow rate is 2000sccm, the doped nitrogen flow rate is 600sccm, the reaction time is 200s, the reaction pressure is 1000mtorr, and the power is 4000W; in the second stage, silane and ammonia are introduced, the glow is turned on, and a second layer of silicon nitride film is formed by chemical reaction. The reaction temperature is 440°C, the silane flow rate is 1000sccm, the NH3 flow rate is 7000sccm, the reaction time is 400s, the reaction pressure is 1000mtorr, and the power is 6000W.

[0103] S5, performing a first etching on the first semiconductor layer on the mask layer on the back side of the S4 silicon wafer to remove the mask layer and a portion of the first semiconductor layer to form second semiconductor opening regions distributed at intervals;

[0104] S6. Through texturing and cleaning, a texture surface is formed in the second semiconductor opening region on the back side and on the front side of the silicon wafer at the same time, and 40% of the thickness of the mask layer is removed;

[0105] The texturing solution used is a mixture of potassium hydroxide, a texturing additive, and water, with a potassium hydroxide concentration of 1% and a texturing additive concentration of 0.5%. The texturing process lasts 10 minutes at a temperature of 75°C. Hydrofluoric acid is used to partially remove the mask layer at a temperature of 25°C and a hydrofluoric acid concentration of 5%.

[0106] S7, forming a passivation layer and an anti-reflection layer in sequence on the front side of the S6 silicon wafer;

[0107] The passivation layer includes a second tunneling oxide layer with a thickness of 1 nm and a second N-type doped polycrystalline layer with a thickness of 5 nm; the passivation layer is formed by a tubular PECVD method and then annealed;

[0108] The anti-reflection layer is silicon nitride with a thickness of 100 nm and is formed by a tubular PECVD method.

[0109] S8, secondary cleaning, remove the back of the plating and backwash;

[0110] A chain cleaning machine is used to remove the anti-reflection layer and the remaining mask layer. The removal solution is an aqueous solution containing hydrofluoric acid with a mass concentration of 6%. The reaction temperature is 25°C, and the transmission roller speed of the chain cleaning machine is 3.0m / min.

[0111] Afterwards, a tank cleaning machine is used to remove the wrap-around plating produced by the passivation layer. The solution used to remove the wrap-around plating of the passivation layer is a low-concentration sodium hydroxide aqueous solution with a sodium hydroxide mass concentration of 0.3%. The reaction temperature is 25°C, the reaction time is 80s, and the thinning amount on the back of the silicon wafer is 0.45µm.

[0112] Then a tank cleaning machine is used for backwashing. The backwashing process is alkaline washing-acid washing-hydrofluoric acid pickling, and a water washing step is required after each solution tank step.

[0113] S9, forming a second semiconductor layer on the back side, the second semiconductor layer including an intrinsic amorphous silicon layer and a P-type second doped amorphous silicon layer sequentially formed on the back side;

[0114] The thickness of the intrinsic amorphous silicon layer is 5 nm, the thickness of the second doped amorphous silicon layer is 6 nm, and the effective doping concentration is 6e19 cm -3 .

[0115] S10, performing a second etching on the polished area on the back side of the silicon wafer to remove the second semiconductor layer and form a first semiconductor opening area;

[0116] S11, forming a transparent conductive film layer on the back side of the silicon wafer to fully cover the entire surface;

[0117] S12. Perform a third etching on the transparent conductive film layer between the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer to form an insulating groove; after etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0118] S13, forming metal electrodes on the outer surfaces of corresponding areas of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer.

[0119] Example 2

[0120] The method was carried out in accordance with Example 1, except that the doping element of the doped amorphous layer was C, 500 sccm of methane was introduced during the preparation, and the carbon doping concentration of the doped amorphous layer was 5e18 cm -3 , the refractive index of the doped amorphous layer is 3.13.

[0121] Example 3

[0122] The process is carried out with reference to Example 1, except that the thickness of the doped amorphous layer is 15 nm and the doping concentration remains unchanged; the total thickness of the corresponding mask layer is 75 nm.

[0123] Example 4

[0124] The process is carried out with reference to Example 1, except that the thickness of the silicon nitride film layer is 75 nm, and the total thickness of the corresponding mask layer is 85 nm.

[0125] Example 5

[0126] The process was carried out with reference to Example 1, except that the mass concentration of the low-concentration alkaline solution in S8 was 0.5%.

[0127] Comparative Example 1

[0128] The process is carried out with reference to Example 1, except that the doped amorphous layer in the mask layer is replaced by undoped amorphous silicon, that is, no corresponding doping elements are introduced during preparation, and the refractive index of the undoped amorphous silicon is 3.31.

[0129] Comparative Example 2

[0130] The process was carried out with reference to Comparative Example 1, except that the low-concentration alkaline solution in S8 was replaced by a mixed solution containing alkali and hydrogen peroxide, the alkali concentration remained unchanged, the concentration of hydrogen peroxide was 3%, and the thinning amount on the back side of the silicon wafer was 0 µm.

[0131] Comparative Example 3

[0132] The process was carried out in accordance with Example 1, except that the low-concentration alkaline solution in S8 was replaced by a higher-concentration solution, the mass concentration of sodium hydroxide was 2%, the reaction temperature was 50°C, the reaction time was 80s, and the thinning amount on the back of the silicon wafer was 2.8µm.

[0133] Test Case

[0134] The back contact cells obtained in Examples 1-5 and Comparative Examples 1-3 were subjected to performance tests, and the results are shown in Table 1.

[0135] Table 1

[0136]

[0137] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can completely remove the back coating layer, thereby improving the open circuit voltage and short circuit current of the battery, and further improving the battery efficiency.

[0138] Furthermore, according to Example 1 and Examples 2-5, it can be seen that the preferred solution of the present invention is more conducive to improving the open circuit voltage and short circuit current of the battery, thereby improving the battery efficiency.

[0139] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, various simple variations of the technical solution of the present invention may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed in the present invention and fall within the scope of protection of the present invention.

Claims

1. A method for preparing a combined passivated back contact battery, characterized in that: The steps include: S1, provide double-sided polished silicon wafers; S2. forming a first semiconductor layer on the back side of the silicon wafer in sequence, wherein the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon film layer formed in sequence; S3, cleaning and removing the phosphosilicate glass layer naturally formed on the surface of the first semiconductor layer in S2; S4, depositing a mask layer on the first semiconductor layer, the mask layer comprising a doped amorphous layer and a silicon nitride film layer formed in sequence, wherein the doping element of the doped amorphous layer is N or C; S5, performing a first etching opening on the first semiconductor layer on the back side obtained in S4 and its corresponding mask layer to form second semiconductor opening regions arranged at intervals; S6, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area at the same time, and removing part of the thickness of the mask layer. The thickness of the mask layer removed is 20%-60% of the total thickness of the mask layer in S4; S7, depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer in sequence; S8, secondary cleaning to remove the wrap-around coating naturally formed on the back side during S7, followed by backwashing; the secondary cleaning process includes: first using a hydrofluoric acid-containing aqueous solution to remove the anti-reflection wrap-around coating, which will also remove the silicon nitride film layer in the remaining mask layer, then using a low-concentration alkaline solution with a mass concentration of 0.1%-1% to remove the passivation wrap-around coating, and controlling the thinning amount on the back side of the silicon wafer to 0.1-1µm, followed by backwashing; S9. Depositing a second semiconductor layer on the back surface of the substrate obtained in S8. The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped silicon layer formed in sequence. The thickness of the intrinsic amorphous silicon layer is thinned to 5-10 nm, and the thickness of the second doped silicon layer is thinned to 5-15 nm.

2. The method for preparing a combined passivated back contact battery according to claim 1, characterized in that: The total thickness of the mask layer in S4 is 35-100 nm; and / or, The thickness of the doped amorphous layer is 3-20 nm, and the thickness of the silicon nitride film layer is 30-80 nm.

3. The method for preparing a combined passivated back contact battery according to claim 1 or 2, characterized in that: The doping concentration of the doping element in the amorphous layer of S4 is 1e18 cm -3 -1e19cm -3 and / or, In S4, the refractive index of the doped amorphous layer is 3.0-3.2, and the refractive index of the silicon nitride film layer is 1.8-2.

2.

4. The method for preparing a combined passivated back contact battery according to claim 1, characterized in that: In S4, the formation conditions of the doped amorphous layer include: introducing silane, hydrogen, and nitrogen or methane, turning on the glow light for reaction, during which the reaction temperature is controlled to be 400-480° C., the reaction pressure is 500-3000 mtorr, the power is 3000-6000 W, and the reaction time is 100-300 s; wherein the silane flow rate is 500-1000 sccm, the hydrogen flow rate is 1000-5000 sccm, the nitrogen flow rate is 500-1000 sccm, and the methane flow rate is 100-500 sccm; and / or, The formation conditions of the silicon nitride film layer include: introducing silane and ammonia, turning on the glow reaction, controlling the reaction temperature at 400-480°C, the reaction pressure at 500-3000mtorr, the power at 5000-8000W, and the reaction time at 300-600s; the silane flow rate is 800-1200sccm, and the ammonia flow rate is 5000-8000sccm.

5. The method for preparing a combined passivated back contact cell according to claim 1, characterized in that: In S7, the passivation layer includes a second tunneling oxide layer and a second doped polycrystalline layer; the thickness of the second tunneling oxide layer is 1-2 nm, and the thickness of the second doped polycrystalline layer is 1-10 nm; and / or, The anti-reflection layer is silicon nitride, and the thickness of the silicon nitride is 70-120 nm.

6. The method for preparing a combined passivation back contact cell according to claim 1, characterized in that: In S8, the passivation layer and the plating layer are removed so that the surface of the silicon wafer corresponding to the second semiconductor opening area is controlled to have a semi-polished or fully-polished structure, where the semi-polished structure includes a semi-pyramid structure.

7. The method for preparing a combined passivated back contact battery according to claim 1, characterized in that: In S8, a chain cleaning machine is used to remove the anti-reflection coating, and the speed of the chain cleaning machine's transmission roller is 1.2-4.0m / min; and / or, In S8, in removing the anti-reflection coating, the reaction temperature of the hydrofluoric acid aqueous solution is controlled to be 20-35° C., and the mass concentration of the hydrofluoric acid in the hydrofluoric acid aqueous solution is 2%-10%.

8. The method for preparing a combined passivation back contact cell according to claim 1, characterized in that: In S8, the conditions for removing the passivation layer around the plating layer include: using a tank cleaning, a reaction temperature of 20-45° C., and a reaction time of 10-120 s; and / or, In S8, the backwashing process includes sequentially performing alkaline washing, acid washing, and hydrofluoric acid washing, wherein each solution tank in the backwashing process is followed by a water washing step.

9. The method for preparing a combined passivated back contact battery according to claim 1, characterized in that: The preparation method further comprises: S10, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S11, depositing a conductive film layer on the back surface obtained in S10; S12, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench; S13 , forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the first semiconductor opening region and the second semiconductor opening region.

10. A combined passivation back contact battery, characterized in that: The battery is prepared by the method for preparing a combined passivated back contact battery as claimed in any one of claims 1 to 9.

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