Photoelectric detector and preparation method thereof
By growing radial PIN junction nanowire arrays on silicon substrates, the problem of small PN junction area in the axial nanowire arrays is solved, and greater optical absorption and multi-path carrier transport are achieved, improving the performance and production efficiency of the photodetector.
Patent Information
- Application Number
- CN202510366393.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-08-08
AI Technical Summary
In existing photodetectors, the PN junction area of the axial nanowire array is small, and photon absorption and carrier transport are in the same direction, limiting the optimization of device performance.
Using a radial PIN junction nanowire array, nanowires are grown directly on the silicon substrate. The nanowires have a core-shell structure, and the core-shell forms a P-N junction, and carriers are drawn through transparent electrodes. The intermediate layer is an intrinsic layer, simplifying the preparation process.
Provides a larger optical absorption area within the same device area, enhances optical resonance, diversified carrier transport paths, improves the photoresponse to 0.97A/W, and is compatible with silicon-based processes, supporting mass production.
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Figure CN120456657A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of photoelectric detection, and in particular to a photoelectric detector and a preparation method thereof. Background Art
[0002] In recent years, photoelectric detection technology has been widely used in military security, industrial production, medical diagnosis, environmental monitoring and other fields.
[0003] Among many structures, self-grown nanowire arrays are favored by many researchers due to their better optical absorption properties brought by a larger specific surface area and good crystal quality.
[0004] In existing research, due to growth process limitations and device structural design difficulties, PN junctions with well-defined lattice structures and uniform doping distributions in nanowire arrays are often found in axial configurations. However, in axial nanowire arrays, the relatively small PN junction area (limited by the nanowire's cross-sectional area) and the fact that photon absorption and carrier transport occur in the same direction limit device performance optimization. Summary of the Invention
[0005] To address the shortcomings of existing photodetectors, which suffer from relatively small PN junctions in axial nanowire arrays and the co-ordination of photon absorption and carrier transport, the present invention proposes a photodetector and its fabrication method. This photodetector utilizes a silicon substrate to directly grow nanowires, enabling direct arraying and integration of the nanowires. This eliminates the need for an additional device substrate during device fabrication, simplifying the fabrication process. Furthermore, the nanowires exhibit radial PN junctions.
[0006] One of the technical solutions of the present invention is to provide a photodetector featuring a radial PIN junction nanowire array. Compared to a single nanowire device, this array not only provides a larger optical absorption area within the same device footprint, enhanced optical resonance, and more tunable parallel carrier transport pathways (multiple nanowires connected in parallel), but also offers improved mechanical stability. Furthermore, heteroepitaxial nanowire array devices on silicon substrates eliminate the need for an additional device substrate, simplifying the process flow and improving compatibility with existing silicon-based processes, while also enabling mass production of repeatable devices.
[0007] Specifically, the detector includes at least an array of photodetection nanowires grown on a silicon-based substrate. The nanowires have a core-shell structure, and the core and shell form a PN junction; the core layer carriers are drawn out through the silicon-based substrate, and the shell layer carriers are drawn out through a transparent electrode coated on the outside of the nanowires.
[0008] Furthermore, there is an intermediate layer between the core and shell layers, and the intermediate layer has different doping characteristics from the core layer and the shell layer.
[0009] The intermediate layer is an intrinsic layer.
[0010] Furthermore, the detector is a near-infrared photodetector, and the nanowire material is a III-V material, including GaAs, InGaAs, InGaN, etc.; the core and shell are doped with different types to form a PN junction.
[0011] Furthermore, the detector is an ultraviolet photodetector, and the nanowire material is a III-V material, including GaN, AlGaN, etc.; the core and shell are doped with different types to form a PN junction.
[0012] Furthermore, the transparent electrode includes ITO and AZO, and the transparent electrode layer and the shell material can form an ohmic contact.
[0013] Furthermore, the shell layer and the transparent electrode are insulated and isolated from the substrate by an isolation medium.
[0014] A second technical solution of the present invention is to provide a method for preparing the above-mentioned photodetector, which specifically includes the following steps: 1) Using Si as substrate, epitaxially grow core-shell nanowires of corresponding materials; 2) pickling the nanowires to remove the intrinsic oxide layer of the nanowires; 3) Filling the upper part of the nanowire with metal Ti to protect the top of the nanowire; 4) Etching the nanowire shell structure to remove the bottom shell of the nanowire; 5) Transparent electrode deposition; 6) Deposition of top electrode and bottom electrode.
[0015] By growing nanowires through molecular beam epitaxy and adjusting the growth parameters in a timely manner, the growth of radial structures and the adjustment of doping concentration can be achieved.
[0016] Furthermore, the etching in step 4 is performed by first soaking in acetone for 10 minutes to remove the bottom-filled photoresist, and then wet-etching the bottom shell layer.
[0017] In some embodiments of the present invention, the preparation of the present invention may include the following steps: 1) Select a P-type doped (111) silicon substrate as the growth substrate and soak it in 2% volume fraction hydrofluoric acid for 2 minutes to remove the intrinsic oxide layer of the nanowires; 2) Spin-coat 5350 photoresist and soft-bake on a hot plate at 105°C for 60 seconds to fill the bottom of the nanowire array and separate the bottom and top areas of the nanowires.
[0018] 3) Magnetron sputtering of 3 nm Ti on the unfilled top area of the nanowires to achieve wrapping protection for the top of the nanowires.
[0019] 4) The bottom fill photoresist was removed by soaking in acetone for 10 minutes. The GaAs and Ti selectivity ratio was then greater than 100:1 using a solution of H3PO4:H2O2:H2O with a ratio of 1:1:25. The sample was etched for 5 minutes to achieve the etching of the bottom GaAs nanowire shell layer, successfully exposing the core layer separately to separate the two electrical connections.
[0020] 5) Spin-coat BCB to fill the bottom area of the nanowires, soft-bake on a hot plate at 120°C for 60 seconds, and anneal at 300°C in a tube furnace under N2 atmosphere for 60 minutes to achieve BCB solidification and isolation of subsequent deposited layers from the substrate.
[0021] 6) Transparent electrode deposition was performed by magnetron sputtering 350nm ITO and annealing at 300℃ for 60s in an Ar atmosphere in a rapid annealing furnace, achieving large-area, high-quality ohmic contact while ensuring light transmittance.
[0022] 7) Magnetron sputtering of 30 nm Ni / 100 nm Au was performed on the top of the device, and magnetron sputtering of 30 nm Al / 100 nm Au was performed on the bottom of the device. The top and bottom electrodes were deposited by rapid annealing in a 300°C N2 atmosphere for 120 s.
[0023] Beneficial effects of the present invention: (1) The nanowires are radial PIN junction nanowire arrays, which provide a larger optical absorption area, enhanced optical resonance, and more tunable parallel carrier transport paths within the same device area, with an excellent photoresponsivity of up to 0.97A / W. This decouples the direction of light absorption from carrier transport, resulting in a larger junction area and smaller surface recombination effects.
[0024] (2) Growing nanowires directly on silicon substrates enables direct realization of nanowire arrays and integration.
[0025] (3) Growing nanowires on a silicon substrate eliminates the need for an additional device substrate, simplifying the process. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 Schematic diagram of radial GaAs nanowire doping.
[0027] Figure 2 Schematic diagram of the photodetector structure of Example 1.
[0028] Figure 3 Schematic diagram of the device preparation process flow in Example 1.
[0029] Figure 4This is the SEM image of the nanowires in Example 1.
[0030] Figure 5 The light response of Example 1 and Comparative Example 1. DETAILED DESCRIPTION
[0031] The following examples are used to further illustrate the present invention. Their purpose is to illustrate the present invention and should not be construed as limiting the scope of the present invention. Unless otherwise specified, all references are by weight and weight percentage.
[0032] Unless otherwise specified, the raw materials used in the present invention are conventional commercial products; the methods used in the present invention are conventional methods in the art unless otherwise specified.
[0033] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0034] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.
[0035] Example 1 1. Nanowire Growth 1.1 Select a 3-inch P-type doped (111) silicon substrate as the growth substrate and clean it according to the standard process. 1.2 GaAs nanowires were grown by molecular beam epitaxy. At the initial stage of growth, the Ga source equivalent pressure, As / Ga flux ratio, and substrate temperature were adjusted to 8.41×10 -8 Toor, 50, and 630 °C were used to achieve the growth of the core layer, while the growth of the shell layer was achieved by turning off the Ga source and consuming the Ga droplet completely and resetting the relevant parameters to 8.41×10 -8 During the growth process, Be source and Si source are turned on to realize P-type and N-type doping respectively according to the doping requirements.
[0036] 2. Shell etching 2.1 Spin-coat 5350 photoresist and soft-bake on a hot plate at 105°C for 60 seconds to fill the bottom of the nanowire array and separate the bottom and top areas of the nanowires.
[0037] 2.2 Magnetron sputtering of 3 nm Ti on the unfilled top area of the nanowires achieves wrapping protection for the top of the nanowires.
[0038] 2.3 Soak in acetone for 10 minutes to remove the bottom-filled 5350 photoresist and expose the bottom of the nanowire.
[0039] 2.4 Use a solution with a H3PO4:H2O2:H2O ratio of 1:1:25 to etch GaAs and Ti with a selectivity ratio greater than 100:1. The sample is etched for 5 minutes to achieve the etching of the bottom GaAs nanowire shell layer and successfully expose the core layer separately.
[0040] 3. Electrode Preparation 3.1 Spin-coat BCB to fill the bottom area of the nanowires, soft-bake at 120°C on a hot plate for 60 seconds, and anneal at 300°C in a tube furnace under N2 atmosphere for 60 minutes to achieve BCB solidification and isolation of subsequent deposited layers from the substrate.
[0041] 3.2 500nm ITO was magnetron sputtered and annealed at 350℃ for 60s in an Ar atmosphere in a rapid annealing furnace, achieving large-area, high-quality ohmic contact while ensuring light transmittance.
[0042] 3.3 30 nm Ni / 100 nm Au was magnetron sputtered on the top of the device, and 30 nm Al / 100 nm Au was magnetron sputtered on the bottom of the device, followed by rapid annealing in a 300 °C N2 atmosphere for 120 s.
[0043] like Figure 1 and Figure 2 As shown, an array of photodetector nanowires grown on a silicon substrate was fabricated. The nanowires have a core-shell structure, forming a PN junction. Core layer carriers are extracted through the silicon substrate, while shell layer carriers are extracted through a transparent ITO electrode coating the nanowires. The core and shell layers form a radial PN junction, with a depletion layer extending along the nanowire radius.
[0044] The incident light is absorbed in the depletion layer near the core-shell interface, exciting electron-hole pairs; the self-built electric field formed by the radial PN junction is distributed along the radius of the nanowire, causing the photogenerated carriers to be quickly separated in three-dimensional space - the electrons are driven by the electric field to drift toward the N-type core layer, and the holes migrate to the P-type shell layer. The core electrons are vertically transported to the external circuit through the silicon-based substrate, and the shell holes are laterally exported through the encapsulating transparent conductive layer. The dual-channel design avoids carrier path intersection and recombination losses. The introduction of the intermediate intrinsic layer further expands the depletion region, forcing the carriers to separate mainly in the strong electric field area, significantly reducing the proportion of diffusion transport. By testing the IV characteristics of the device, such as Figure 5 As shown, it has an excellent photoresponsivity of up to 0.97 A / W.
[0045] Comparative Example 1 Axial PIN junction GaAs nanowire detectors were prepared. The doping concentration of each nanowire layer was the same as that of the sample in Example 1. The same ITO sputtering and filling processes were used. The two types of contact metal electrodes were also consistent with those in this example. The specific steps are as follows: Using Si as the substrate, epitaxially grow nanowires with varying doping types and concentrations of the corresponding materials along the axial direction; Fill the gaps between nanowires with BCB and etch to expose the tops of the nanowires (3) Pickling the nanowires to remove the intrinsic oxide layer of the nanowires; (4) Transparent electrode deposition; (5) Deposition of top electrode and bottom electrode.
[0046] Using the same illumination conditions as in Example 1, the IV characteristics of the device were tested, as shown in FIG. Figure 5 As shown, its light response is significantly lower than that of Example 1. In the figure, the typical value is Comparative Example 1, and this experiment represents Example 1.
[0047] The above embodiments describe in detail the structure, features and effects of the present invention. The above are only preferred embodiments of the present invention. Any changes made in accordance with the concept of the present invention, or modifications to equivalent embodiments with equivalent changes, which do not exceed the scope covered by the specification, should be within the scope of protection of the present invention.
Claims
1. A photoelectric detector, characterized in that: It at least includes an array of photoelectric detection nanowires grown on a silicon-based substrate. The nanowires have a core-shell structure, and the core and shell form a PN junction; the core layer carriers are led out through the silicon-based substrate, and the shell layer carriers are led out through a transparent electrode coated on the outside of the nanowires.
2. The photodetector according to claim 1, wherein There is also an intermediate layer between the core and shell layers, and the intermediate layer has different doping characteristics from the core layer and the shell layer.
3. The photodetector according to claim 2, wherein: The intermediate layer is an intrinsic layer.
4. The photodetector according to claim 1, wherein The detector is a near-infrared photodetector, and the nanowire material is a III-V material; the core and shell are doped with different types to form a PN junction.
5. The photodetector according to claim 1, wherein The detector is an ultraviolet photoelectric detector, and the nanowire material is a III-V material; the core and the shell are doped with different types to form a PN junction.
6. The photodetector according to claim 1, wherein: The transparent electrode is ITO or AZO, and the transparent electrode layer and the shell material can form an ohmic contact.
7. The photodetector according to claim 1, wherein The shell layer and the transparent electrode are insulated and isolated from the substrate by an isolation medium.
8. A method for preparing the photodetector according to claim 1, characterized in that: The specific steps include: 1) Using Si as substrate, epitaxially grow core-shell nanowires of corresponding materials; 2) acid washing the nanowires to remove the intrinsic oxide layer of the nanowires; 3) Filling the upper part of the nanowire with metal Ti to protect the top of the nanowire; 4) Etching the nanowire shell structure to remove the bottom shell of the nanowire; 5) Transparent electrode deposition; 6) Deposition of top electrode and bottom electrode.
9. The preparation method according to claim 8, characterized in that The etching method in step 4 is to first remove the bottom-filled photoresist by soaking in acetone for 10 minutes, and then remove the bottom shell layer.