Driving backboard and display panel

Abstract

The invention provides a driving backboard and a display panel. The driving backboard comprises a substrate and a plurality of pixel circuits, the plurality of pixel circuits are located on one side of the substrate, the plurality of pixel circuits are arranged in an array, and each pixel circuit comprises a plurality of transistors; at least one transistor comprises a first transistor, the first transistor comprises at least three grid electrodes and at least two active layers, the grid electrodes and the active layers are sequentially and alternately stacked on one side of the substrate, and orthographic projections of the grid electrodes and the active layers on the substrate are partially overlapped; the at least three gates are connected in parallel, and the at least two active layers are connected in parallel. According to the driving backboard, on one hand, the carrier mobility of the transistor is improved, and the conduction performance and the driving capability of the transistor are improved; and on the other hand, the resolution ratio of the display panel adopting the driving backboard can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of display, and in particular relates to a driving backplane and a display panel. Background Art

[0002] Mini LED (Mini Light-Emitting Diode) direct display technology is experiencing rapid development. Market demand for Mini LED direct display applications in areas such as office and conference displays, indoor commercial displays, and security monitoring is also rapidly growing. Mini LED direct display technology offers advantages such as higher contrast, a wider color gamut, and improved viewing angles, significantly improving display quality and user experience, and has been widely welcomed by users. Summary of the Invention

[0003] The present invention addresses the problem that the current layout area of thin-film transistors is relatively large, which is not conducive to reducing the layout space of pixel drive circuits in display products, reducing the spacing between pixel structures, and improving the resolution of display products. The present invention provides a driver backplane and display panel. The driver backplane improves the carrier mobility of transistors, thereby enhancing their conduction performance and driving capability; it also improves the resolution of display panels using the driver backplane.

[0004] The present invention provides a driving backplane, comprising a substrate and a plurality of pixel circuits, wherein the plurality of pixel circuits are located on one side of the substrate and arranged in an array.

[0005] The pixel circuit includes a plurality of transistors;

[0006] at least one of the transistors comprises a first transistor,

[0007] The first transistor includes at least three gates and at least two active layers, wherein the gates and the active layers are alternately stacked on one side of the substrate, and the orthographic projections of the gates and the active layers on the substrate partially overlap;

[0008] The at least three gates are connected in parallel, and the at least two active layers are connected in parallel.

[0009] In some embodiments, the first transistor includes a first gate, a second gate, a third gate, a first active layer, a second active layer, a source electrode, and a drain electrode;

[0010] The source and the drain are arranged in the same layer,

[0011] The first gate, the first active layer, the second gate, the second active layer, the third gate, the source electrode, and the drain electrode are stacked in sequence away from the substrate, and an insulating layer is provided between any two adjacent ones;

[0012] The orthographic projections of the first gate, the first active layer, the second gate, the second active layer, and the third gate on the substrate partially overlap;

[0013] The source electrode and the drain electrode overlap with the orthographic projections of the first active layer and the second active layer on the substrate,

[0014] The orthographic projections of the source electrode and the drain electrode on the substrate are located at opposite ends of the orthographic projection of the first active layer on the substrate.

[0015] The orthographic projections of the source electrode and the drain electrode on the substrate are located at two opposite ends of the orthographic projection of the second active layer on the substrate.

[0016] The source and the drain are electrically connected to the first active layer through a first via hole and a second via hole respectively opened in the insulating layer, and the source and the drain are electrically connected to the second active layer through a third via hole and a fourth via hole respectively opened in the insulating layer.

[0017] In some embodiments, the orthographic projections of the first active layer and the second active layer on the substrate partially do not overlap;

[0018] The orthographic projections of the first via hole and the second via hole on the substrate are located in an area of the first active layer that does not overlap with the orthographic projection of the second active layer;

[0019] The orthographic projections of the third via hole and the fourth via hole on the substrate are located in a region of the second active layer overlapping with the orthographic projection of the first active layer.

[0020] In some embodiments, the number of the first via hole, the second via hole, the third via hole, and the fourth via hole are multiple, respectively.

[0021] The number of the first via holes, the second via holes, the third via holes and the fourth via holes is the same.

[0022] In some embodiments, a first connecting structure is further included, which is located in the same layer as the source and the drain.

[0023] The first connection structure does not overlap with the orthographic projections of the first active layer and the second active layer on the substrate.

[0024] The first connecting structure partially overlaps with the orthographic projections of the first gate, the second gate, and the third gate on the substrate;

[0025] The first connection structure is electrically connected to the first gate through a fifth via hole opened in the insulating layer.

[0026] The first connection structure is electrically connected to the second gate through a sixth via hole opened in the insulating layer.

[0027] The first connection structure is electrically connected to the third gate through a seventh via hole opened in the insulating layer.

[0028] In some embodiments, a first signal line is further included, which is located in the same layer as the source and the drain.

[0029] The first signal line is electrically connected to the first connection structure.

[0030] In some embodiments, the second connection structure, the third connection structure and the second signal line are further included.

[0031] The second connection structure, the second signal line and the third gate are located in the same layer, and the second signal line is electrically connected to the second connection structure;

[0032] The third connection structure is located in the same layer as the source and the drain,

[0033] The third connection structure is electrically connected to the source electrode, and the third connection structure is electrically connected to the second connection structure through an eighth via hole opened in the insulating layer.

[0034] In some embodiments, the orthographic projection shapes of the first gate and the second gate on the substrate include an L-shape;

[0035] The orthographic projection shape of the third gate on the substrate includes a rectangle;

[0036] An orthographic projection shape of the first active layer and the second active layer on the substrate includes an H shape.

[0037] In some embodiments, the active layer is made of amorphous silicon material, low-temperature polysilicon material, or oxide semiconductor material.

[0038] In some embodiments, one of the transistors includes a plurality of the first transistors, and the plurality of the first transistors are connected in parallel.

[0039] The present invention also provides a display panel including the above-mentioned driving backplane.

[0040] In some embodiments, the system further includes a plurality of display units located on one side of the driving backplane, wherein the plurality of display units are electrically connected to the plurality of pixel circuits in the driving backplane in a one-to-one correspondence.

[0041] The display unit includes an organic electroluminescent element, a sub-millimeter light emitting diode, a micro light emitting diode or a liquid crystal pixel.

[0042] Beneficial effects of the present invention: The driving backplane provided by the present invention is such that the gates and the active layers are alternately stacked on one side of the substrate, and the orthographic projections of the gates and the active layers on the substrate partially overlap; at least three gates are connected in parallel, and at least two active layers are connected in parallel. On the one hand, compared with the current single-gate or double-gate structure transistors, the first transistor has at least one additional gate and at least one additional active layer, so that the channel area of the first transistor of the same size is larger than that of the single-gate or double-gate structure transistor, thereby improving the carrier mobility of the transistor, improving the conduction performance and driving capability of the transistor, and thus improving the driving capability of the driving backplane; at the same time, the first transistor is used The pixel circuit can carry a larger current, thereby enhancing the anti-static breakdown (ESD) capability of the pixel circuit and the anti-static breakdown capability in the pixel circuit manufacturing process to a certain extent; on the other hand, the increase in the area of the channel region of the first transistor is achieved by increasing the overlapping area of the gate and the active layer in the direction perpendicular to the substrate, without increasing the arrangement area of the transistor on the substrate plane, so that the arrangement area of the first transistor can be reduced or unchanged relative to the current single-gate or double-gate structure transistor, thereby reducing the arrangement area of the pixel circuit, and is conducive to reducing the spacing between adjacent pixel circuits, while also improving the resolution of the display panel using the driving backplane.

[0043] The display panel provided by the present invention can improve the display performance of the display panel and enhance the anti-static breakdown capability of the display panel by adopting the above-mentioned driving backplane, while being conducive to improving the resolution of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1a A schematic top view of a dual-gate thin film transistor in a current pixel driving circuit;

[0045] Figure 1b A schematic top view of a structure in which four dual-gate thin-film transistors arranged in an array on a plane are connected in parallel to form a transistor;

[0046] Figure 2a This is a schematic top view of the structure of the first transistor in the driver backplane according to an embodiment of the present invention;

[0047] Figure 2b For the Figure 2a Schematic diagram of the structural section along the AA' section line;

[0048] Figure 3a Schematic top view of a first gate of a first transistor in a driving backplane according to an embodiment of the present invention;

[0049] Figure 3b For Figure 3a A schematic top view of a first active layer stacked on the basis of FIG.

[0050] Figure 3c For Figure 3b A schematic top view of a second gate superimposed on the basis of FIG.

[0051] Figure 3d For Figure 3c A schematic top view of a second active layer stacked on the basis of FIG.

[0052] Figure 3e For Figure 3d A schematic top view of a third gate superimposed on the basis of FIG.

[0053] Figure 3f For Figure 3e A schematic top view of the insulating layer after being superimposed on the basis;

[0054] Figure 3g For Figure 3f A schematic top view of a structure after source and drain conductive layers are stacked on the structure;

[0055] Figure 4 FIG. 4 is a top view schematically showing a transistor formed by connecting a plurality of first transistors in parallel in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the technical solution of the present invention, a driving backplane and a display panel of the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] With the demand for high resolution (PPI) and small pitch (pitch refers to the distance between pixel structures, and the pixel structure refers to the overall structure formed by the electrical connection between the pixel circuit and the Mini LED device in the display panel) of display products (such as Mini LED display products), pixel driving circuits are generally used instead of integrated chip (IC) drivers. Pixel driving circuits such as LTPS (low-temperature poly-silicon) circuits or LTPO (low-temperature polycrystalline oxide) circuits have a core component of the thin-film transistor (TFT) structure, and its performance directly determines the display effect of the display product.

[0058] Currently, thin film transistors in pixel driving circuits usually adopt a single-gate or double-gate structure, such as Figure 1a and Figure 1bAs shown, the carrier mobility and driving capability of a thin film transistor with a single gate or dual gate structure are limited. In order to increase the carrier mobility and driving capability of the thin film transistor, it is necessary to increase the area of its channel region. Currently, this is mainly achieved by connecting multiple thin film transistors 10 arranged in sequence on a plane in parallel. Figure 1b As shown, four thin-film transistors 10 arranged in an array on a plane are connected in parallel to form a single transistor. This arrangement results in a larger arrangement area for the thin-film transistors, and consequently, a larger arrangement area for the entire pixel driving circuit. This is not conducive to reducing the arrangement space for the pixel driving circuit in a display product, nor is it conducive to reducing the spacing between pixel structures and improving the resolution of the display product.

[0059] In order to solve the above problems, the embodiment of the present invention provides a driving backplane, such as Figure 2a and Figure 2b As shown, the driving backplane includes a substrate 1 and a plurality of pixel circuits, the plurality of pixel circuits are located on one side of the substrate 1, the plurality of pixel circuits are arranged in an array, and the pixel circuit includes a plurality of transistors; at least one transistor includes a first transistor 2, the first transistor 2 includes at least three gates 20 and at least two active layers 21, the gates 20 and the active layers 21 are alternately stacked on one side of the substrate 1, and the orthographic projections of at least three gates 20 and at least two active layers 21 on the substrate 1 partially overlap; at least three gates 20 are connected in parallel, and at least two active layers 21 are connected in parallel.

[0060] Among them, by alternately stacking the gate 20 and the active layer 21 on one side of the substrate 1, and the orthographic projections of the gate 20 and the active layer 21 on the substrate 1 partially overlap; at least three gates 20 are connected in parallel, and at least two active layers 21 are connected in parallel. On the one hand, compared with the current single-gate or double-gate structure transistor, the first transistor 2 adds at least one gate 20 and at least one active layer 21, so that the channel area of the first transistor 2 of the same size is larger than that of the single-gate or double-gate structure transistor, thereby improving the carrier mobility of the transistor, improving the conduction performance and driving capability of the transistor, and at the same time, the pixel circuit using the first transistor 2 can carry more A large current passes through, which can enhance the anti-static breakdown (ESD) capability of the pixel circuit and the anti-static breakdown capability in the pixel circuit process to a certain extent; on the other hand, the increase in the channel area of the first transistor 2 is achieved by increasing the overlapping area of the gate 20 and the active layer 21 in the direction perpendicular to the substrate 1, without increasing the arrangement area of the transistor on the plane of the substrate 1, so that the arrangement area of the first transistor 2 can be reduced or unchanged relative to the current single-gate or double-gate structure transistor, thereby reducing the arrangement area of the pixel circuit, and is conducive to reducing the spacing between adjacent pixel circuits, while also improving the resolution of the display panel using the driving backplane.

[0061] In some embodiments, as Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 3c 、 Figure 3d 、 Figure 3e 、 Figure 3f and Figure 3g As shown, the first transistor 2 includes a first gate 201, a second gate 202, a third gate 203, a first active layer 211, a second active layer 212, a source 3 and a drain 4; the source 3 and the drain 4 are arranged in the same layer, the first gate 201, the first active layer 211, the second gate 202, the second active layer 212, the third gate 203, the source 3 and the drain 4 are stacked away from the substrate 1 in sequence, and an insulating layer 5 is provided between any two adjacent ones; the orthographic projections of the first gate 201, the first active layer 211, the second gate 202, the second active layer 212 and the third gate 203 on the substrate 1 partially overlap; The source electrode 3 and the drain electrode 4 overlap with the orthographic projections of the first active layer 211 and the second active layer 212 on the substrate 1. The orthographic projections of the source electrode 3 and the drain electrode 4 on the substrate 1 are located at opposite ends of the orthographic projection of the first active layer 211 on the substrate 1. The orthographic projections of the source electrode 3 and the drain electrode 4 on the substrate 1 are located at opposite ends of the orthographic projection of the second active layer 212 on the substrate 1. The source electrode 3 and the drain electrode 4 are electrically connected to the first active layer 211 through a first via hole 51 and a second via hole 52 respectively provided in the insulating layer 5. The source electrode 3 and the drain electrode 4 are electrically connected to the second active layer 212 through a third via hole 53 and a fourth via hole 54 respectively provided in the insulating layer 5.

[0062] In some embodiments, the orthographic projections of the first active layer 211 and the second active layer 212 on the substrate 1 do not partially overlap; the orthographic projections of the first via 51 and the second via 52 on the substrate 1 are located in an area of the first active layer 211 that does not overlap with the orthographic projection of the second active layer 212; and the orthographic projections of the third via 53 and the fourth via 54 on the substrate 1 are located in an area of the second active layer 212 that overlaps with the orthographic projection of the first active layer 211.

[0063] The first active layer 211 and the second active layer 212 are connected in parallel by connecting the source electrode 3 to the first active layer 211 and the second active layer 212 and by connecting the drain electrode 4 to the first active layer 211 and the second active layer 212 .

[0064] In some embodiments, the number of the first via hole 51 , the second via hole 52 , the third via hole 53 and the fourth via hole 54 are plural, and the number of the first via hole 51 , the second via hole 52 , the third via hole 53 and the fourth via hole 54 are the same.

[0065] The number of each via hole is set to be multiple, which can reduce the connection impedance between the source electrode 3 and the first active layer 211 and the second active layer 212, and between the drain electrode 4 and the first active layer 211 and the second active layer 212. The same number of each via hole can ensure that the input and output currents of the first transistor 2 are balanced.

[0066] In some embodiments, the driving backplane also includes a first connection structure 6, which is located on the same layer as the source 3 and the drain 4. The first connection structure 6 does not overlap with the orthographic projections of the first active layer 211 and the second active layer 212 on the substrate 1, and the first connection structure 6 partially overlaps with the orthographic projections of the first gate 201, the second gate 202 and the third gate 203 on the substrate 1; the first connection structure 6 is electrically connected to the first gate 201 through a fifth via 55 opened in the insulating layer 5, the first connection structure 6 is electrically connected to the second gate 202 through a sixth via 56 opened in the insulating layer 5, and the first connection structure 6 is electrically connected to the third gate 203 through a seventh via 57 opened in the insulating layer 5.

[0067] The first connection structure 6 realizes the parallel connection of the first gate 201, the second gate 202, and the third gate 203. The first connection structure 6 is located on the same layer as the source 3 and the drain 4, so that the first connection structure 6, the source 3, and the drain 4 can be manufactured through a single patterning process, thereby eliminating the need for additional manufacturing steps for the driver backplane and reducing manufacturing costs.

[0068] In some embodiments, the driving backplane further includes a first signal line 7 , which is located in the same layer as the source 3 and the drain 4 . The first signal line 7 is electrically connected to the first connection structure 6 .

[0069] The first signal line 7 may be a gate line (ie, a scan line), and the first signal line 7 inputs the gate driving signal output by the gate driving circuit to the first gate 201 , the second gate 202 , and the third gate 203 through the first connection structure 6 .

[0070] In some embodiments, the driving backplane also includes a second connection structure 8, a third connection structure 11 and a second signal line 9. The second connection structure 8 and the second signal line 9 are located on the same layer as the third gate 203, and the second signal line 9 is electrically connected to the second connection structure 8; the third connection structure 11 is located on the same layer as the source 3 and the drain 4, the third connection structure 11 is electrically connected to the source 3, and the third connection structure 11 is electrically connected to the second connection structure 8 through an eighth via 58 opened in the insulating layer 5.

[0071] The second connection structure 8, the second signal line 9, and the third gate electrode 203 can be fabricated in a single patterning process, and the third connection structure 11, the source electrode 3, and the drain electrode 4 can be fabricated in a single patterning process, thereby eliminating the need for additional manufacturing processes for the driver backplane and reducing manufacturing costs. The second signal line 9 can be a data line that can transmit a data signal provided by a data driver chip to the source electrode 3 via the second connection structure 8 and the third connection structure 11.

[0072] In addition, the second signal line 9 may also be other signal lines such as a power line, a reset signal line, etc., which is specifically determined according to the connection condition of the first transistor 2 in the pixel circuit, and will not be elaborated here.

[0073] In some embodiments, the orthographic projection shapes of the first gate 201 and the second gate 202 on the substrate 1 include L shapes; the orthographic projection shape of the third gate 203 on the substrate 1 includes a rectangle; and the orthographic projection shapes of the first active layer 211 and the second active layer 212 on the substrate 1 include an H shape.

[0074] The orthographic projection shapes of each gate and each active layer on the substrate 1 are not limited to the above shapes, and can be any other shapes.

[0075] In this embodiment, the L-shaped openings of the first L-shaped gate 201 and the second L-shaped gate 202 face in opposite directions.

[0076] In some embodiments, the active layer 21 is made of amorphous silicon, low-temperature polysilicon, or oxide semiconductor material. That is, the first transistor 2 can be an amorphous silicon transistor, a low-temperature polysilicon transistor, or an oxide semiconductor transistor. The structural arrangement of the first transistor 2 in this embodiment is applicable to transistors of any type or material.

[0077] In some embodiments, as Figure 4 As shown, a transistor includes a plurality of first transistors 2, and the plurality of first transistors 2 are connected in parallel. Figure 1b In the embodiment, four thin film transistors arranged in an array on a plane are connected in parallel to form a transistor. In this embodiment, two first transistors 2 arranged in sequence on a plane are connected in parallel to form a transistor. Figure 1b The transistors in the embodiment have the same conduction performance. In this embodiment, the arrangement area of a transistor formed by connecting two first transistors 2 arranged in parallel on a plane is much smaller than that of the transistors in the embodiment. Figure 1b The arrangement area of the transistor formed by connecting four thin film transistors in parallel can be reduced, thereby reducing the arrangement area of the pixel circuit and facilitating reducing the spacing between adjacent pixel circuits, while also improving the resolution of the display panel using the driving backplane.

[0078] The driving backplane provided by the embodiment of the present invention is configured such that the gates and the active layers are alternately stacked on one side of the substrate, and the orthographic projections of the gates and the active layers on the substrate partially overlap; at least three gates are connected in parallel, and at least two active layers are connected in parallel. On the one hand, compared with the current single-gate or double-gate structure transistors, the first transistor has at least one additional gate and at least one additional active layer, so that the channel area of the first transistor of the same size is larger than that of the single-gate or double-gate structure transistor, thereby improving the carrier mobility of the transistor, improving the conduction performance and driving capability of the transistor, and thus improving the driving capability of the driving backplane; at the same time, the pixel of the first transistor is The circuit can carry a larger current, thereby enhancing the anti-electrostatic breakdown (ESD) capability of the pixel circuit and the anti-electrostatic breakdown capability in the pixel circuit manufacturing process to a certain extent; on the other hand, the increase in the area of the channel region of the first transistor is achieved by increasing the overlapping area of the gate and the active layer in the direction perpendicular to the substrate, without increasing the arrangement area of the transistor on the substrate plane, so that the arrangement area of the first transistor can be reduced or unchanged relative to the current single-gate or double-gate structure transistor, thereby reducing the arrangement area of the pixel circuit, and facilitating reducing the spacing between adjacent pixel circuits, while also improving the resolution of the display panel using the driving backplane.

[0079] An embodiment of the present invention further provides a display panel, comprising the driving backplane in the above embodiment.

[0080] In some embodiments, the display panel further includes multiple display units located on one side of the driver backplane. The multiple display units are electrically connected to the multiple pixel circuits in the driver backplane in a one-to-one correspondence. The display units include organic electroluminescent elements (i.e., OLED elements), sub-millimeter light-emitting diodes (i.e., Mini LEDs), micro light-emitting diodes (i.e., Micro LEDs), or liquid crystal pixels. That is, the display panel in this embodiment can be an OLED display panel, a Mini LED display panel, a Micro LED display panel, or a liquid crystal display panel.

[0081] The display panel provided in this embodiment can improve the display performance of the display panel and enhance the anti-static breakdown capability of the display panel by adopting the driving backplane in the above embodiment, while also being beneficial to improving the resolution of the display panel.

[0082] The display panel can be: OLED panel or TV, Mini LED panel or TV, Micro LED panel or TV, LCD panel or TV, electronic paper, mobile phone, tablet computer, laptop computer, monitor, notebook computer, digital photo frame, navigator, or any other product or component with display function.

[0083] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A driving backplane, comprising a substrate and a plurality of pixel circuits, wherein the plurality of pixel circuits are located on one side of the substrate and arranged in an array. The pixel circuit includes a plurality of transistors; It is characterized by: at least one of the transistors comprises a first transistor, The first transistor includes at least three gates and at least two active layers, wherein the gates and the active layers are alternately stacked on one side of the substrate, and the orthographic projections of the gates and the active layers on the substrate partially overlap; The at least three gates are connected in parallel, and the at least two active layers are connected in parallel.

2. The driving backplane according to claim 1, characterized in that: The first transistor includes a first gate, a second gate, a third gate, a first active layer, a second active layer, a source electrode, and a drain electrode; The source and the drain are arranged in the same layer, The first gate, the first active layer, the second gate, the second active layer, the third gate, the source electrode, and the drain electrode are stacked in sequence away from the substrate, and an insulating layer is provided between any two adjacent ones; The orthographic projections of the first gate, the first active layer, the second gate, the second active layer, and the third gate on the substrate partially overlap; The source electrode and the drain electrode overlap with the orthographic projections of the first active layer and the second active layer on the substrate, The orthographic projections of the source electrode and the drain electrode on the substrate are located at opposite ends of the orthographic projection of the first active layer on the substrate. The orthographic projections of the source electrode and the drain electrode on the substrate are located at two opposite ends of the orthographic projection of the second active layer on the substrate. The source and the drain are electrically connected to the first active layer through a first via hole and a second via hole respectively opened in the insulating layer, and the source and the drain are electrically connected to the second active layer through a third via hole and a fourth via hole respectively opened in the insulating layer.

3. The driving backplane according to claim 2, characterized in that: The orthographic projections of the first active layer and the second active layer on the substrate do not partially overlap; The orthographic projections of the first via hole and the second via hole on the substrate are located in an area of the first active layer that does not overlap with the orthographic projection of the second active layer; The orthographic projections of the third via hole and the fourth via hole on the substrate are located in a region of the second active layer overlapping with the orthographic projection of the first active layer.

4. The driving backplane according to claim 3, characterized in that: The number of the first via hole, the second via hole, the third via hole and the fourth via hole is multiple, The number of the first via holes, the second via holes, the third via holes and the fourth via holes is the same.

5. The driving backplane according to claim 2, characterized in that: It also includes a first connecting structure located in the same layer as the source and the drain. The first connection structure does not overlap with the orthographic projections of the first active layer and the second active layer on the substrate. The first connecting structure partially overlaps with the orthographic projections of the first gate, the second gate, and the third gate on the substrate; The first connection structure is electrically connected to the first gate through a fifth via hole opened in the insulating layer. The first connection structure is electrically connected to the second gate through a sixth via hole opened in the insulating layer. The first connection structure is electrically connected to the third gate through a seventh via hole opened in the insulating layer.

6. The driving backplane according to claim 5, characterized in that: It also includes a first signal line located in the same layer as the source and the drain. The first signal line is electrically connected to the first connection structure.

7. The driving backplane according to any one of claims 2 to 6, characterized in that: Also includes a second connection structure, a third connection structure and a second signal line, The second connection structure, the second signal line and the third gate are located in the same layer, and the second signal line is electrically connected to the second connection structure; The third connection structure is located in the same layer as the source and the drain, The third connection structure is electrically connected to the source electrode, and the third connection structure is electrically connected to the second connection structure through an eighth via hole opened in the insulating layer.

8. The driving backplane according to claim 2, characterized in that: The orthographic projection shapes of the first gate and the second gate on the substrate include an L shape; The orthographic projection shape of the third gate on the substrate includes a rectangle; An orthographic projection shape of the first active layer and the second active layer on the substrate includes an H shape.

9. The driving backplane according to claim 1, characterized in that: The active layer is made of amorphous silicon material, low-temperature polysilicon material or oxide semiconductor material.

10. The driving backplane according to claim 1, characterized in that: One of the transistors includes a plurality of the first transistors, and the plurality of the first transistors are connected in parallel.

11. A display panel, characterized in that: The drive backplane comprises the drive backplane according to any one of claims 1 to 10.

12. The display panel according to claim 11, wherein: It also includes a plurality of display units located on one side of the driving backplane, wherein the plurality of display units are electrically connected to the plurality of pixel circuits in the driving backplane in a one-to-one correspondence. The display unit includes an organic electroluminescent element, a sub-millimeter light emitting diode, a micro light emitting diode or a liquid crystal pixel.

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