A carbon nanotube thin film field effect transistor and its preparation method and chip

Abstract

The present application relates to the field of semiconductor manufacturing technology and provides a carbon nanotube thin film field effect transistor, a preparation method thereof, and a chip. The preparation method comprises providing a substrate; sequentially preparing a bottom gate electrode and a gate dielectric layer on the substrate; preparing a source electrode and a drain electrode on the gate dielectric layer; preparing an amino molecular layer on the surface of the source electrode, the drain electrode, and the gate dielectric layer; removing the amino molecular layer outside the target area; preparing a carbon nanotube thin film in the target area; and performing an annealing treatment. The preparation method exposes the amino molecular layer outside the target area to destroy the amino molecular layer in the non-target area, retaining only the amino molecular layer in the target area, and providing adsorption sites for carbon nanotube film formation in the channel area. During this preparation process, the carbon nanotube thin film does not come into contact with the photoresist, avoiding residues and contamination caused by photoresist protection during traditional carbon nanotube patterning and etching, and effectively ensuring the performance of the carbon nanotube thin film field effect transistor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a carbon nanotube thin film field effect transistor and a preparation method and chip thereof. Background Art

[0002] Carbon nanotubes are widely used due to their unique quasi-one-dimensional lattice structure, excellent carrier mobility and outstanding electrical properties.

[0003] Currently, carbon nanotubes are typically produced using photolithography, which employs photoresist. While photoresist protects non-lithographic areas, its removal is particularly problematic. Even with organic solvent cleaning, it's difficult to guarantee a complete removal of the photoresist residue. Residual photoresist forms a disordered barrier and enhances carrier scattering, leading to mobility degradation and a significant increase in contact resistance, severely impacting the performance of the carbon nanotubes.

[0004] Therefore, there is an urgent need for a preparation method that improves photoresist residue and ensures the performance of carbon nanotubes. Summary of the Invention

[0005] The present application provides a carbon nanotube thin film field effect transistor and a preparation method and chip thereof, in order to solve the technical problem that residual photoresist affects the performance of carbon nanotubes.

[0006] The first aspect of the present application provides a carbon nanotube thin film field effect transistor, comprising: providing a substrate; sequentially preparing a bottom gate electrode and a gate dielectric layer on the substrate; preparing a source electrode and a drain electrode on the gate dielectric layer; wherein the source electrode and the drain electrode are spaced apart; preparing an amino molecular layer on the surface of the source electrode, the drain electrode, and the gate dielectric layer; removing the amino molecular layer outside a target area; wherein the target area includes a first area, a second area, and a third area, wherein the first area and the second area are areas oppositely arranged in the source electrode and the drain electrode, respectively, and the third area is an area connected between the first area and the second area; preparing a carbon nanotube thin film in the target area; and performing an annealing treatment.

[0007] In some feasible implementations, removing the amino molecular layer outside the target area includes: exposing the amino molecular layer outside the target area using a laser direct writing process; wherein the exposure process uses an ultraviolet pulse laser with an intensity of 10 μJ-100 μJ and a scanning speed of 50 mm / s-400 mm / s.

[0008] In some feasible implementations, an amino molecular layer is prepared on the surface of the source electrode, the drain electrode, and the gate dielectric layer, including: pre-treating the source electrode, the drain electrode, and the surface of the gate dielectric layer with oxygen plasma; and soaking the source electrode, the drain electrode, and the surface of the gate dielectric layer with an amino solution to form an amino molecular layer.

[0009] In some feasible implementations, the amino solution includes one of 3-aminopropyltriethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyldiethoxymethylsilane or polylysine; the temperature of the amino solution is 25° C.-70° C.; and the immersion time is 10 min-30 min.

[0010] In some feasible implementations, preparing a carbon nanotube film in a target area includes: sequentially soaking a source electrode, a drain electrode, and a gate dielectric layer with a carbon nanotube mixed solution, an organic solution, and deionized water to adsorb and form a carbon nanotube film in the target area.

[0011] In some feasible implementations, the temperature of the carbon nanotube mixed solution is 20°C-60°C, and the immersion time is 1 min-30 min; the temperature of the organic solution is 50°C-80°C, and the immersion time is 1 min-5 min; the temperature of the deionized water is 50°C-80°C, and the immersion time is 1 min-5 min.

[0012] In some feasible implementations, the carbon nanotube mixed solution includes a surfactant and a semiconductor carbon nanotube solution; the weight percentage of the surfactant is 0.05 wt%-1.5 wt%; and the concentration of the semiconductor carbon nanotube solution is 0.01 μg / mL-1 mg / mL.

[0013] In some feasible implementations, the annealing treatment includes: annealing conditions include vacuum or inert gas, and the annealing temperature is 150° C.-550° C.

[0014] The first aspect of this application provides a method for preparing a carbon nanotube thin film field-effect transistor. This method uses a laser direct writing process to expose the amino-containing molecular layer outside the target area, thereby destroying the amino-containing molecular layer in the non-target area and retaining only the amino-containing molecular layer in the target area. This provides adsorption sites for carbon nanotube film formation in the channel region. This allows the source electrode, drain electrode, and gate dielectric layer to be subsequently immersed in a carbon nanotube mixed solution. The carbon nanotube film can be adsorbed and formed only in the target area to conduct the source and drain electrodes. Furthermore, in this preparation method, the carbon nanotube film does not come into contact with any photoresist, thus avoiding the residual and contamination caused by photoresist protection during traditional carbon nanotube patterning and etching processes, effectively ensuring the performance of the carbon nanotube thin film field-effect transistor.

[0015] The carbon nanotube thin film field effect transistor provided in the second aspect of the present application includes: a substrate; a bottom gate electrode and a gate dielectric layer arranged in sequence on the substrate; a source electrode, arranged in the gate dielectric layer; a drain electrode, arranged in the gate dielectric layer and spaced apart from the source electrode; a carbon nanotube thin film, arranged in a target area; wherein the target area includes a first area, a second area and a third area, the first area and the second area are areas opposite to each other in the source electrode and the drain electrode, respectively, and the third area is an area connecting the first area and the second area.

[0016] A third aspect of the present application provides a chip, comprising a circuit and the carbon nanotube thin film field effect transistor provided by the first aspect and applied to the circuit.

[0017] The carbon nanotube thin film field effect transistor provided in the second aspect of this application is prepared by the preparation method of the carbon nanotube thin film field effect transistor provided in the first aspect, and the chip provided in the third aspect includes the carbon nanotube thin film field effect transistor provided in the second aspect. Therefore, the beneficial technical effects of the second and third aspects can be referred to the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 This is a schematic flow chart of a method for preparing a carbon nanotube thin film field effect transistor provided in an embodiment of the present application;

[0020] Figure 2 This is one of the process flow charts for preparing a carbon nanotube thin film field effect transistor provided in an embodiment of the present application;

[0021] Figure 3 This is a schematic diagram of the structure of a target area provided in an embodiment of the present application;

[0022] Figure 4 This is the second process flow chart of a preparation process of a carbon nanotube thin film field effect transistor provided in an embodiment of the present application;

[0023] Figure 5 It is a three-dimensional schematic diagram of a carbon nanotube thin film field effect transistor provided in an embodiment of the present application.

[0024] Graphic mark:

[0025] 100. Carbon nanotube thin film field-effect transistor; 10. Substrate; 20. Bottom gate electrode; 30. Gate dielectric layer; 40. Source electrode; 50. Drain electrode; a1. Aminated molecular layer; b0. Target region; b1. First region; b2. Second region; b3. Third region; b31. First connection region; b32. Second connection region; b33. Third connection region; 60. Carbon nanotube thin film. DETAILED DESCRIPTION

[0026] The following will clearly describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by ordinary technicians in this field without making any creative work are all within the scope of protection of this application.

[0027] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0028] In addition, in this application, directional terms such as "upper", "lower", "inner" and "outer" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0029] First, a brief introduction to the concepts mentioned in this application is given.

[0030] Laser Direct Writing (LDW) is a maskless, high-precision micro-nano processing technology that uses computer-controlled focused laser beams to induce physical or chemical changes directly on the surface or inside the material, enabling digital manufacturing of complex structures.

[0031] Figure 1 This is a schematic flow chart of a method for preparing a carbon nanotube thin film field effect transistor provided in an embodiment of the present application; Figure 2 This is one of the process flow charts of a method for preparing a carbon nanotube thin film field effect transistor provided in an embodiment of the present application.

[0032] Combine Figure 1 and Figure 2 As shown, the method for preparing the carbon nanotube thin film field effect transistor provided in the embodiment of the present application can be implemented by the following steps S1 to S6.

[0033] Step S1: providing a substrate 10.

[0034] In some feasible implementations, the substrate 10 may include one of a silicon substrate, a silicon dioxide substrate, a quartz substrate, a sapphire substrate, or a silicon carbide substrate.

[0035] The substrate 10 should meet certain cleanliness and flatness requirements to facilitate better growth of subsequent structural layers.

[0036] Step S2: sequentially forming a bottom gate electrode 20 and a gate dielectric layer 30 on the substrate 10 .

[0037] In step S2 , the bottom gate electrode 20 and the gate dielectric layer 30 may be sequentially prepared using a micro-nano processing technology. Step S2 may include step S21 and step S22 .

[0038] Step S21: A bottom gate electrode 20 is fabricated on the substrate 10 using a micro-nano processing technique. The bottom gate electrode 20 mainly functions to control the conductive state of the channel region by applying a voltage, thereby realizing the switching and amplification of the current.

[0039] In some feasible implementations, the material of the bottom gate electrode 20 may include a composite of one or more metals selected from the group consisting of gold, palladium, aluminum, titanium, and chromium.

[0040] Step S22: Using micro-nano processing technology, a gate dielectric layer 30 is formed on the bottom gate electrode 20. The gate dielectric layer 30 mainly converts the gate voltage into the channel electric field, controls the carrier concentration to achieve conduction or shutdown, and isolates the gate from the channel to prevent short circuit.

[0041] In some feasible implementations, the material of the gate dielectric layer 30 may include one of silicon dioxide, silicon nitride, or hafnium oxide.

[0042] The bottom gate electrode 20 may be made of aluminum, and the gate dielectric layer 30 may be made of silicon nitride; or the bottom gate electrode 20 may be made of gold, and the gate dielectric layer 30 may be made of silicon dioxide.

[0043] In some feasible implementations, the thickness of the bottom gate electrode 20 can be greater than or equal to 20 nm. For example, the thickness of the bottom gate electrode 20 can be 20 nm, or the thickness of the bottom gate electrode 20 can be 30 nm, 40 nm, or 50 nm. The thickness of the gate dielectric layer 30 can be adaptively adjusted based on the specific material.

[0044] After step S2 is completed, the following Figure 2 The structure shown in (a).

[0045] Step S3 : forming a source electrode 40 and a drain electrode 50 on the gate dielectric layer 30 .

[0046] In step S3 , the source electrode 40 and the drain electrode 50 may be manufactured by using a micro-nano processing technology. Step S3 may include step S31 and step S32 .

[0047] Step S31: using micro-nano processing technology to prepare a source electrode 40 on the gate dielectric layer 30. The core functions of the source electrode 40 are carrier injection and gate voltage reference.

[0048] Step S32: using micro-nano processing technology to prepare a drain electrode 50 on the gate dielectric layer 30. The core function of the drain electrode 50 is current output and power carrying.

[0049] In steps S31 and S32, the source electrode 40 and the drain electrode 50 are disposed on the same surface of the gate dielectric layer 30, and the source electrode 40 and the drain electrode 50 are spaced apart. Steps S31 and S32 can be performed simultaneously or sequentially. There is no fixed order in which steps S31 and S32 must be performed sequentially.

[0050] The source electrode 40 and the drain electrode 50 may extend in the same direction and may be arranged in parallel.

[0051] In some feasible implementations, the material of the source electrode 40 may include one or more composites of gold, palladium, aluminum, titanium or chromium; the material of the drain electrode 50 may include one or more composites of gold, palladium, aluminum, titanium or chromium.

[0052] The material of the source electrode 40 and the material of the drain electrode 50 may be the same or different, and the material of the source electrode 40 and the material of the drain electrode 50 may be the same or different from the material of the bottom gate electrode 20 .

[0053] For example, the bottom gate electrode 20, the source electrode 40, and the drain electrode 50 can all be made of gold; alternatively, the bottom gate electrode 20 can be made of gold, and the source electrode 40 and the drain electrode 50 can be made of palladium; alternatively, the bottom gate electrode 20 can be made of gold, the source electrode 40 can be made of palladium, and the drain electrode 50 can be made of aluminum. In this way, the materials of the bottom gate electrode 20, the source electrode 40, and the drain electrode 50 can be flexibly adjusted.

[0054] In some feasible implementations, the thickness of the source electrode 40 and the drain electrode 50 can be in the range of 20 nm to 40 nm. The source electrode 40 and the drain electrode 50 have the same size to ensure that the surface of the source electrode 40 and the surface of the drain electrode 50 are coplanar, facilitating the subsequent preparation of the carbon nanotube film. It is worth noting that when the thickness of the source electrode 40 and the drain electrode 50 is relatively small, a continuous metal film cannot be formed, which is not conducive to conductivity. When the thickness of the source electrode 40 and the drain electrode 50 is relatively large, the distance between the surface of the source electrode 40 and the drain electrode 50 and the surface of the gate dielectric layer 30 is large, affecting the subsequent preparation of the carbon nanotube film. Therefore, controlling the thickness of the source electrode 40 and the drain electrode 50 within the range of 20 nm to 40 nm not only ensures the film formation effect of the source electrode 40 and the drain electrode 50, but also facilitates the subsequent deposition of the carbon nanotube film.

[0055] For example, the thickness of the source electrode 40 and the drain electrode 50 may be 20 nm, 30 nm, or 40 nm. Of course, the thickness of the source electrode 40 and the drain electrode 50 may also be other values ​​between 20 nm and 40 nm.

[0056] After step S3 is completed, we can get Figure 2 The structure of (b).

[0057] Step S4 : preparing an amino molecular layer a1 on the surfaces of the source electrode 40 , the drain electrode 50 , and the gate dielectric layer 30 .

[0058] In step S4 , the preparation of the amino molecular layer a1 can be achieved by soaking in a solution containing amino groups.

[0059] This can be specifically achieved by the following steps S41 and S42.

[0060] Step S41 : pre-treating the surfaces of the source electrode 40 , the drain electrode 50 , and the gate dielectric layer 30 using oxygen plasma.

[0061] In step S41, oxygen plasma pretreatment can be performed in an oxygen plasma cleaning machine. The power of the oxygen plasma cleaning machine can be 100 W-160 W, the oxygen flow rate can be 50 sccm-100 sccm, the pretreatment time can be 30 s-120 s, and the chamber pressure of the oxygen plasma cleaning machine can be 10 mTorr-30 mTorr.

[0062] In a specific implementation, the power of the oxygen plasma cleaning machine may be 140 W, the oxygen flow rate may be 75 sccm, the pretreatment time may be 45 s, and the chamber pressure of the oxygen plasma cleaning machine may be 15 mTorr.

[0063] Step S42 : soaking the source electrode 40 , the drain electrode 50 , and the surface of the gate dielectric layer 30 with an amino solution to form an amino molecular layer a1 .

[0064] That is, in step S4, the prepared overall structure including the substrate 10, the bottom gate electrode 20, the gate dielectric layer 30, the source electrode 40 and the drain electrode 50 can be pre-treated with oxygen plasma and then immersed in an amino solution as a whole, or one side of the overall structure including the source electrode 40 and the drain electrode 50 of the substrate 10, the bottom gate electrode 20, the gate dielectric layer 30, the source electrode 40 and the drain electrode 50 can be immersed in an amino solution.

[0065] The amino solution is an organic solution containing amino groups and may include one of 3-aminopropyltriethoxysilane (APTES), 3-aminopropyltrimethoxysilane (APTMS), 3-aminopropyldimethylethoxysilane (APDMES), or poly-L-lysine (PLL). The temperature and immersion time of the amino solution can be adjusted to achieve sufficient amino functionalization of the surfaces of the source electrode 40, the drain electrode 50, and the gate dielectric layer 30, thereby forming an amino-functionalized molecular layer a1.

[0066] In some feasible implementations, the temperature of the amino solution may be 25° C.-70° C.; and the soaking time may be 10 min-30 min.

[0067] For example, the temperature of the amino solution can be one of 25°C, 35°C, 45°C, 55°C, or 65°C. Of course, the temperature of the amino solution can also be other values ​​within the range of 25°C to 70°C. The soaking time can be one of 10 minutes, 12 minutes, 14 minutes, 18 minutes, 22 minutes, 26 minutes, or 30 minutes. Of course, the soaking time can also be other values ​​within the range of 10 minutes to 30 minutes.

[0068] After step S4 is completed, Figure 2 The structure of (c) in the figure. The prepared amino molecular layer a1 is a thin film structure, and the preparation of a single amino molecular layer a1 can be achieved by adjusting the temperature and soaking time, thereby facilitating the subsequent treatment of the amino molecular layer a1.

[0069] Figure 3 This is a schematic diagram of the structure of a target area provided in an embodiment of the present application; Figure 4This is the second process flow chart of the preparation process of a carbon nanotube thin film field effect transistor provided in an embodiment of the present application.

[0070] Step S5: removing the amino-modified molecular layer a1 outside the target area b0.

[0071] See also Figure 3 and Figure 4 As shown, the target region b0 includes a first region b1, a second region b2, and a third region b3. The first region b1 and the second region b2 are regions located opposite each other in the source electrode 40 and the drain electrode 50, respectively. The third region b3 is the region connected between the first region b1 and the second region b2. It is understood that the first region b1 can be the region on the upper surface of the source electrode 40, the second region b2 can be the region on the upper surface of the drain electrode 50, and the third region b3 can be understood as the channel region connected between the source electrode 40 and the drain electrode 50.

[0072] Specifically, the width D11 of the first region b1 may be the same as or smaller than the width of the source electrode 40. The length L of the first region b1 may be the same as or smaller than the length of the source electrode 40. The width D12 of the second region b2 may be the same as or smaller than the width of the drain electrode 50. The length of the second region b2 may be the same as the length of the first region b1, and the length of the second region b2 may be the same as or smaller than the length of the drain electrode 50. The width D11 of the first region b1 may be the same as the width D12 of the second region b2.

[0073] The third region b3 may include a first connection region b31, a second connection region b32, and a third connection region b33. The first connection region b31 is a region of the source electrode 40 facing the drain electrode 50, that is, the first connection region b31 may be a region of the side surface of the source electrode 40. The second connection region b32 may be a region of the drain electrode 50 facing the source electrode 40, that is, the second connection region b32 may be a region of the side surface of the drain electrode 50, and the first connection region b31 and the second connection region b32 are arranged opposite each other. The third connection region b33 may be a region of the gate dielectric layer 30 between the source electrode 40 and the drain electrode 50. The third region b3 is connected to the first region b1 via the first connection region b31, and is connected to the second region b2 via the second connection region b32.

[0074] The width D13 of the third region b3 may be the width of the third connection region b33 , ie, the distance between the source electrode 40 and the drain electrode 50 . The length of the third region b3 is the same as that of the first region b1 and the second region b2 .

[0075] Thus, the width of the target area b0 is the sum of the widths of the first area b1 , the second area b2 , and the third area b3 , and the length of the target area b0 is the length of the first area b1 .

[0076] It should be emphasized that a rectangular coordinate system is established with the width direction of the source electrode 40 and the drain electrode 50 as the x-axis and the extension direction of the source electrode 40 and the drain electrode 50 as the y-axis. In the above example, the width direction of the target area b0 is the x-axis direction, and the length direction of the target area b0 is the y-axis direction. This is only an example. In other examples, if the size of the target area b0 along the x-axis direction is larger than the size along the y-axis direction, then the length direction of the target area b0 is the x-axis direction, and the width direction is the y-axis direction.

[0077] It is worth noting that in the above implementation method, the target area prepared is a regular shape, such as a rectangle or square, so as to match the regular shape of the carbon nanotube film, which is conducive to the stable and uniform performance of the subsequently formed carbon nanotube film field effect transistor.

[0078] In step S5, the target area b0 can be understood as the area where the carbon nanotube film needs to be deposited later. The amino molecular layer a1 outside the target area b0 is removed to facilitate the control of the size of the carbon nanotube film later.

[0079] In some feasible implementations, a laser direct writing process can be used to expose the amino molecular layer a1 outside the target area b0 to destroy the amino molecular layer a1, thereby retaining the amino molecular layer a1 within the target area b0 and providing adsorption sites for carbon nanotube film formation in the channel area.

[0080] In some feasible implementations, the exposure process can use ultraviolet pulsed laser light with an intensity of 10-100 μJ and a scanning speed of 50 mm / s-400 mm / s. The ultraviolet pulsed laser light is light below 400 nm, preferably with wavelengths of 193 nm, 248 nm, and 308 nm.

[0081] For example, the intensity of the ultraviolet pulsed laser can be one of 10 μJ, 20 μJ, 30 μJ, 40 μJ, 50 μJ, 60 μJ, 70 μJ, 80 μJ, 90 μJ, or 100 μJ. Of course, the intensity of the ultraviolet pulsed laser can also be other values ​​within 10-100 μJ.

[0082] The scanning speed may be one of 50 mm / s, 100 mm / s, 150 mm / s, 200 mm / s, 250 mm / s, 300 mm / s, 350 mm / s, or 400 mm / s. Of course, the scanning speed may also be other values ​​between 50 mm / s and 400 mm / s.

[0083] After step S5 is completed, Figure 4 The structure of (a) in the figure. It should be emphasized that Figure 4 As shown in (a), in this implementation, the width of the first region b1 is the same as the width of the source electrode 40, and the width of the second region b2 is the same as the width of the drain electrode 50. The length of the target region b0 can be adjusted according to the actual required size of the carbon nanotube film.

[0084] Step S6: preparing a carbon nanotube film 60 in the target area b0.

[0085] In step S6, the carbon nanotube film 60 can be prepared by immersion. In this way, the preparation method provided by the embodiment of the present application can effectively avoid direct contact between the carbon nanotube film 60 and the photoresist, effectively solving the photoresist contamination problem introduced by the traditional etching process.

[0086] Specifically, the process may include sequentially soaking the source electrode 40 , the drain electrode 50 and the gate dielectric layer 30 with a carbon nanotube mixed solution, an organic solution and deionized water to form a carbon nanotube film 60 by adsorption in the target area b0 .

[0087] Step S6 can be implemented by the following steps S61 and S63.

[0088] S61 : soaking the source electrode 40 , the drain electrode 50 and the gate dielectric layer 30 in a carbon nanotube mixed solution.

[0089] Among them, the target area b0 is immersed in the carbon nanotube mixed solution, and the π electrons of the amino group in the amino molecular layer a1 in the target area b0 can undergo π-π interaction with the abundant π electrons on the surface of the carbon nanotubes, thereby providing a large number of adsorption sites to adsorb carbon nanotubes, which is beneficial to the adsorption and film formation of carbon nanotubes. The formed carbon nanotube film 60 can conduct the source electrode 40 and the drain electrode 50.

[0090] In some feasible implementations, the temperature of the carbon nanotube mixed solution is 20° C.-60° C., and the immersion time is 1 min-30 min.

[0091] For example, the temperature of the carbon nanotube mixed solution may be one of 20°C, 30°C, 40°C, 50°C or 60°C. Of course, the temperature of the carbon nanotube mixed solution may also be other temperatures between 20°C and 60°C.

[0092] In a specific implementation, the temperature of the carbon nanotube mixed solution is 25°C-30°C.

[0093] For example, the soaking time can be one of 1 min, 5 min, 10 min, 15 min, 20 min, 25 min or 30 min. Of course, the soaking time can also be other temperatures between 1 min and 30 min.

[0094] The carbon nanotube mixed solution may include a surfactant and a semiconductor carbon nanotube solution, wherein the weight percentage of the surfactant is 0.05 wt%-1.5 wt% and the concentration of the carbon nanotube solution is 0.01 μg / mL-1 mg / mL.

[0095] In some feasible implementations, the surfactant solution may be a sodium deoxycholate solution. Thus, the surfactant adsorbs and wraps the carbon nanotubes, reducing interfacial tension and generating electrostatic repulsion or steric hindrance, thereby preventing aggregation and achieving stable dispersion, thereby ensuring uniform film formation of the carbon nanotube film 60.

[0096] For example, the weight percentage of the surfactant can be one of 0.05 wt%, 0.25 wt%, 0.5 wt%, 0.75 wt%, 1 wt%, 1.25 wt% or 1.5 wt%. Of course, the weight percentage of the surfactant can also be other values ​​between 0.05 wt% and 1.5 wt%.

[0097] In a specific implementation, the weight percentage of the surfactant is 0.05 wt %.

[0098] In some feasible implementations, the concentration of the semiconducting carbon nanotube solution can be 0.01 μg / mL, 50 μg / mL, 100 μg / mL, 200 μg / mL, 300 μg / mL, 400 μg / mL, 500 μg / mL, 600 μg / mL, 700 μg / mL, 800 μg / mL, 900 μg / mL, or 1 mg / mL. Of course, the concentration of the semiconducting carbon nanotube solution can also be other values ​​between 0.01 μg / mL and 1 mg / mL.

[0099] In a specific implementation, the concentration of the semiconductor carbon nanotube solution is 1 μg / mL-20 μg / mL.

[0100] In some feasible implementations, the temperature of the organic solution is 50° C.-80° C., and the soaking time is 1 min-5 min.

[0101] Step S62 : soaking the source electrode 40 , the drain electrode 50 and the gate dielectric layer 30 with an organic solution.

[0102] The organic solution may include one or more of N-methylpyrrolidone, tetrahydrofuran, chloroform, dichloromethane, methanol, ethanol, and toluene. In other words, the organic solution may be a single solution or a mixture of multiple solutions. This allows for more flexible configuration of the organic solution to remove the surfactant coating the surface of the carbon nanotube film 60 and ensure the film quality of the carbon nanotube film 60.

[0103] In some feasible implementations, the temperature of the organic solution is 50° C.-80° C., and the soaking time is 1 min-5 min.

[0104] For example, the temperature of the organic solution can be one of 50°C, 60°C, 70°C, or 80°C. Of course, the temperature of the organic solution can also be other temperatures between 50°C and 80°C. The soaking time can be one of 1 minute, 2 minutes, 3 minutes, 4 minutes, or 5 minutes. Of course, the soaking time can also be other temperatures between 1 minute and 5 minutes.

[0105] In some feasible implementations, the temperature of the organic solution is 60° C. and the soaking time is 2 minutes.

[0106] Step S63 : soaking the source electrode 40 , the drain electrode 50 and the gate dielectric layer 30 in deionized water.

[0107] The deionized water may be analytically pure, the temperature of the deionized water may be 50° C.-80° C., and the soaking time may be 1 min-5 min.

[0108] For example, the temperature of the deionized water can be 50°C, 60°C, 70°C, or 80°C. Of course, the temperature of the deionized water can also be other temperatures between 50°C and 80°C. The soaking time can be 1 minute, 2 minutes, 3 minutes, 4 minutes, or 5 minutes. Of course, the soaking time can also be other temperatures between 1 minute and 5 minutes.

[0109] In some feasible implementations, the temperature of the deionized water is 50° C., and the soaking time is 3 minutes.

[0110] After step S6 is completed, the carbon nanotube film 60 is formed to obtain Figure 4 The carbon nanotube thin film field effect transistor 100 is shown in (b).

[0111] In some feasible implementations, to ensure the cleanliness of the carbon nanotube thin film field effect transistor 100 , step S64 may be further included after step S63 .

[0112] Step S64: using clean gas to blow dry the carbon nanotube thin film field effect transistor 100.

[0113] The clean gas may include one or more of oxygen, nitrogen, and argon.

[0114] That is to say, the clean gas may include one or more types. In this way, the clean gas can be set more flexibly.

[0115] Step S7: performing annealing treatment.

[0116] Specifically, the annealing process can effectively remove impurities and groups on the carbon nanotube film 60 , improve the contact between the carbon nanotube film 60 and the source electrode 40 and the drain electrode 50 , and thus reduce the contact resistance.

[0117] The annealing process can be performed in an annealing furnace. The annealing conditions in the annealing furnace include vacuum or inert gas. The carbon nanotube thin film field effect transistor 100 is placed in the annealing furnace and heated. In other words, the carbon nanotube thin film field effect transistor 100 can be placed in an annealing furnace in a vacuum environment and heated. An inert gas can also be introduced into the vacuum furnace. The inert gas includes one or more of nitrogen and argon.

[0118] In some feasible implementations, the annealing temperature may be 150° C.-550° C.

[0119] For example, the annealing temperature may be one of 150° C., 200° C., 250° C., 300° C., 350° C., 400° C., 450° C., 500° C., or 550° C. Of course, the annealing temperature may also be other temperatures between 150° C. and 550° C.

[0120] In a specific implementation, the annealing temperature is 300°C-500°C.

[0121] The present invention provides a simple, efficient, and pollution-free method for fabricating a carbon nanotube thin film field-effect transistor. By using a laser direct writing process, the amino-modified molecular layer a1 outside the target region b0 is exposed to light, thereby destroying the amino-modified molecular layer a1 in the non-target region b0 and retaining only the amino-modified molecular layer a1 in the target region b0. This provides adsorption sites for carbon nanotube film formation in the channel region. Consequently, when the source electrode 40, the drain electrode 50, and the gate dielectric layer 30 are subsequently immersed in a carbon nanotube mixed solution, the carbon nanotube film 60 is adsorbed and formed only in the target region b0, thereby providing electrical connection between the source electrode 40 and the drain electrode 50. Furthermore, in this fabrication method, the carbon nanotube film 60 is not in contact with any photoresist, thereby avoiding the residual and contamination caused by photoresist protection during conventional carbon nanotube patterning and etching processes. This method also prevents the formation of disordered potential barriers and enhances carrier scattering, thereby ensuring improved mobility, reducing contact resistance, and ensuring the high frequency response and energy efficiency of the carbon nanotube thin film field-effect transistor 100, thereby effectively guaranteeing the performance of the carbon nanotube thin film field-effect transistor 100.

[0122] Figure 5 It is a three-dimensional schematic diagram of a carbon nanotube thin film field effect transistor provided in an embodiment of the present application.

[0123] Corresponding to the embodiment of the method for preparing the carbon nanotube thin film field effect transistor described above, the present application also provides an embodiment of the carbon nanotube thin film field effect transistor 100 .

[0124] Combine Figure 3 and Figure 5 As shown, the carbon nanotube film field effect transistor 100 may include a substrate 10 , a bottom gate electrode 20 , a gate dielectric layer 30 , a source electrode 40 , a drain electrode 50 , and a carbon nanotube film 60 .

[0125] The bottom gate electrode 20 is provided on the substrate 10. The bottom gate electrode 20 can be prepared by step S21 in the above-mentioned embodiment of the method for preparing the carbon nanotube thin film field effect transistor.

[0126] The gate dielectric layer 30 is provided on the bottom gate electrode 20. The gate dielectric layer 30 can be prepared by step S22 in the above-mentioned embodiment of the method for preparing the carbon nanotube thin film field effect transistor.

[0127] The source electrode 40 is disposed on the gate dielectric layer 30. The source electrode 40 can be prepared by step S31 in the above-mentioned method for preparing the carbon nanotube thin film field effect transistor.

[0128] The drain electrode 50 is disposed on the gate dielectric layer 30 and spaced apart from the source electrode 40. The drain electrode 50 can be prepared by step S32 in the above-mentioned embodiment of the method for preparing the carbon nanotube thin film field effect transistor.

[0129] A carbon nanotube film 60 is disposed in a target region b0. The target region b0 includes a first region b1, a second region b2, and a third region b3. The first region b1 and the second region b2 are regions located opposite each other within the source electrode 40 and the drain electrode 50, respectively. The third region b3 is a region connected between the first region b1 and the second region b2. The carbon nanotube film 60 can be prepared by steps S4 to S6 of the aforementioned method for preparing a carbon nanotube thin film field-effect transistor.

[0130] It is important to emphasize that continuing to combine Figure 4 and Figure 5 As shown, Figure 4 In the carbon nanotube thin film field effect transistor 100 shown, the substrate 10, the bottom gate electrode 20, and the gate dielectric layer 30 may have the same size. Figure 5 The sizes of the substrate 10, bottom gate electrode 20, and gate dielectric layer 30 in the carbon nanotube thin film field effect transistor 100 shown in the figure are different, which are all exemplary. This application does not specifically limit the size relationship between the substrate 10, bottom gate electrode 20, and gate dielectric layer 30.

[0131] Corresponding to the aforementioned embodiment of the carbon nanotube thin film field effect transistor 100 , the present application also provides an embodiment of a chip.

[0132] The chip includes a circuit and the carbon nanotube thin film field effect transistor 100 of the above embodiment applied to the circuit.

[0133] It should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art that are not disclosed in this application.

[0134] It will be understood that the present application is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof, the true scope being indicated by the present application.

Claims

1. A method for preparing a carbon nanotube thin film field effect transistor, characterized in that: include: providing a substrate; sequentially preparing a bottom gate electrode and a gate dielectric layer on the substrate; Preparing a source electrode and a drain electrode on the gate dielectric layer; wherein the source electrode and the drain electrode are spaced apart; preparing an amino molecular layer on the surfaces of the source electrode, the drain electrode, and the gate dielectric layer; Removing the amino-modified molecular layer outside the target area; wherein the target area includes a first area, a second area, and a third area, the first area and the second area are areas opposite to each other in the source electrode and the drain electrode, respectively, and the third area is an area connected between the first area and the second area; removing the amino-modified molecular layer outside the target area, comprising: exposing the amino-modified molecular layer outside the target area using a laser direct writing process; preparing a carbon nanotube film in the target area; Perform annealing treatment.

2. The method for preparing a carbon nanotube thin film field effect transistor according to claim 1, wherein: The exposure process uses ultraviolet pulse laser with an intensity of 10 μJ-100 μJ and a scanning speed of 50 mm / s-400 mm / s.

3. The method for preparing a carbon nanotube thin film field effect transistor according to claim 1, wherein: Preparing an amino molecular layer on the surface of the source electrode, the drain electrode, and the gate dielectric layer, comprising: pretreating the source electrode, the drain electrode, and the surface of the gate dielectric layer using oxygen plasma; The source electrode, the drain electrode, and the surface of the gate dielectric layer are soaked in an amino solution to form an amino molecular layer.

4. The method for preparing a carbon nanotube thin film field effect transistor according to claim 3, wherein: The amino solution includes one of 3-aminopropyltriethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyldiethoxymethylsilane or polylysine; The temperature of the amino solution is 25°C-70°C; and the soaking time is 10 min-30 min.

5. The method for preparing a carbon nanotube thin film field effect transistor according to claim 1, wherein: The method comprises preparing a carbon nanotube film in the target area, comprising: The source electrode, the drain electrode and the gate dielectric layer are soaked in a carbon nanotube mixed solution, an organic solution and deionized water in sequence to form a carbon nanotube film by adsorption in the target area.

6. The method for preparing a carbon nanotube thin film field effect transistor according to claim 5, characterized in that: The temperature of the carbon nanotube mixed solution is 20°C-60°C, and the soaking time is 1 min-30 min; The temperature of the organic solution is 50°C-80°C, and the soaking time is 1 min-5 min; The temperature of the deionized water is 50° C.-80° C., and the soaking time is 1 min-5 min.

7. The method for preparing a carbon nanotube thin film field effect transistor according to claim 6, characterized in that: The carbon nanotube mixed solution includes a surfactant and a semiconductor carbon nanotube solution; The weight percentage of the surfactant is 0.05 wt%-1.5 wt%; The concentration of the semiconductor carbon nanotube solution is 0.01 μg / mL-1 mg / mL.

8. The method for preparing a carbon nanotube thin film field effect transistor according to claim 1, wherein: The annealing treatment comprises: Annealing conditions include vacuum or inert gas, and annealing temperature is 150°C-550°C.

9. A carbon nanotube thin film field effect transistor, characterized in that: The carbon nanotube thin film field effect transistor is prepared by the method for preparing the carbon nanotube thin film field effect transistor according to any one of claims 1 to 8, wherein the carbon nanotube thin film field effect transistor comprises: substrate; A bottom gate electrode and a gate dielectric layer are sequentially arranged on the substrate; a source electrode, disposed on the gate dielectric layer; a drain electrode, disposed on the gate dielectric layer and spaced apart from the source electrode; A carbon nanotube film is arranged in a target area; wherein the target area includes a first area, a second area and a third area, the first area and the second area are areas relatively arranged in the source electrode and the drain electrode respectively, and the third area is an area connecting the first area and the second area.

10. A chip, characterized in that: include: A circuit and the carbon nanotube thin film field effect transistor according to claim 9 applied to the circuit.

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