Digital signal processor for streaming audio applications

Abstract

The invention belongs to the field of basic electronic circuits. Belongs to the field of digital signal processors for streaming audio applications, audio reproduction signal paths comprising digital signal processors (DSPs) for streaming, integrated circuits comprising the digital signal processors, and devices comprising the digital signal processors or the integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the field of basic electronic circuits, in particular to the field of digital signal processors for streaming audio applications, audio reproduction signal paths comprising a digital signal processor (DSP) for streaming, integrated circuits comprising such a digital signal processor, and devices comprising such a digital signal processor or such an integrated circuit. Background Art

[0002] An audio power amplifier consists of basic electronic circuitry that amplifies a low-power audio signal entering the circuit to a high enough power to drive a loudspeaker. Audio power amplifiers have many applications. Audio amplifiers can be combined into a chain of electronic components or circuits, each performing a separate task or contributing to a common one. Essentially, any audio signal can be supplied to a power amplifier, as is commonly done. The power of the output signal of an audio amplifier can range from a few watts to tens or hundreds of watts, sometimes exceeding hundreds of watts. Power amplifiers are often integrated into the (final) product or integrated circuit.

[0003] The design parameters of an audio power amplifier include frequency response, gain, noise, and distortion, which are usually interdependent.

[0004] Class D amplifiers are commonly used in modern consumer audio products, subwoofer amplifiers, and sound reinforcement systems. An amplifier may include filters, preamplifiers, power output stages, and more. Audio filters are typically frequency-dependent circuits designed to operate within a specific audio frequency range. Note that the human hearing range is generally considered to be from 20 to 20,000 Hz. However, there is considerable variability between individuals, especially at high frequencies. Furthermore, people typically lose sensitivity to higher frequencies with age. Furthermore, sensitivity to specific frequencies may also vary with the frequency in question. Therefore, the audio frequency range commonly used in audio amplifiers is from approximately 20 Hz to 20 kHz, sometimes to 40 kHz or even 100 kHz. Audio filters are designed to amplify, pass, or attenuate a specific frequency range. There are many types of filters, such as low-pass filters, high-pass filters, band-pass filters, and all-pass filters that affect the phase of a given frequency component.

[0005] The amount of digital signal processing used in personal audio devices has increased significantly over the past few years. In addition to more traditional applications such as interpolation and decimation filters, new applications such as active noise control (ANC) require signal processing to operate at high sampling rates. Power efficiency for this processing is a significant challenge, especially for small devices such as true wireless earbuds.

[0006] Although traditional digital signal processors (DSPs) are optimized for signal processing, they are typically far from optimal for efficient high-frequency processing. These general-purpose processors are better suited for complex algorithms at low sampling rates (such as compression and voice detection), which require large amounts of program and data memory and control. Power consumption is a concern, as the power involved in control and memory access is often much higher than that of core processing operations. Power efficiency challenges have driven the use of dedicated hardware for high-speed ANC filtering in previous audio IC implementations (e.g., [ADAU1788]), but this hardware has drawbacks and is only suitable for very specific application scenarios.

[0007] Incidentally, reference may be made to US Pat. No. 6,081,783 A, US Pat. No. 2005 / 144210 A1, and US Pat. No. 2019 / 065188 A1. US Pat. No. 6,081,783 A describes an audio decoder for operating on a received compressed audio data stream compressed using an algorithm employing transform coding and a bit allocation routine. A first processor performs a first set of operations on the received compressed audio data stream, including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating bit allocation, and transferring frequency domain coefficients to a shared memory. A second digital signal processor performs a second set of operations on the data transferred from the first digital signal processor to the shared memory, including performing an inverse transform operation on the data transferred from the first digital signal processor. US Pat. No. 2005 / 144210 A1 describes a programmable logic device (PLD) having multiple columns of DSP slices that can be cascaded to create DSP circuits of varying sizes and complexities. Each slice includes a mode port that receives a mode control signal for dynamically changing the functionality and connectivity of the associated slice. This change can be made with or without reconfiguring the PLD. US2019 / 065188 A1 describes an acceleration processor structure on a programmable integrated circuit device, which includes a processor and multiple configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes multiple multipliers. The acceleration processor structure also includes: a first bus for transferring data from the processor to the configurable DSP; and a second bus for transferring data from the configurable DSP to the processor.

[0008] The object of the present invention is to overcome the disadvantages of prior art digital signal processors and amplifiers without compromising their functionality and advantages. Summary of the Invention

[0009] A compact digital signal processor (muDSP) is highly optimized for low-power processing of streaming audio signals. It typically uses very small memory (e.g., 256 words), a wide program memory that can easily encode multiple sub-instructions, and a data path with redundant data formats and no implicit pipelining. The proposed micro-DSP (muDSP) lies between specialized hardware and general-purpose DSP implementations. It aims to achieve a balance between power efficiency and support for a wide range of streaming audio applications. A characteristic of the invention is that it utilizes a compact processing pipeline and very small memory to maintain a high degree of processing locality (sometimes referred to as high data locality). For more complex tasks (or cascaded tasks), multiple muDSPs can be interconnected directly or via a network on a chip (NoC) for increased flexibility.

[0010] Note that the muDSP of this disclosure was built from the ground up, combining techniques commonly used in dedicated hardware implementations with building blocks from processor architectures. Various aspects of the architecture definition and design are outlined below. For further background information, please refer to the accompanying figures. A dedicated hardware implementation without the overhead of existing technologies can be up to two orders of magnitude more efficient than a general-purpose DSP, which itself can be an order of magnitude more efficient than a typical CPU. This represents a significant advancement in this area.

[0011] In this overview of the invention, note the following. From a top-level perspective:

[0012] •muDSP is specifically designed for power-efficient streaming signal processing (especially oversampled audio), typically using simple algorithms with a low data storage footprint per DSP.

[0013] • Memories in a muDSP are highly local, single-cycle accessible, and dedicated to that specific muDSP.

[0014] • More complex tasks (or more precisely: cascaded tasks) can be distributed across multiple muDSPs. The muDSPs have multiple input and output ports to facilitate direct interconnection or NoC connectivity via low-overhead circuit switching.

[0015] • Input ports write directly to the muDSP local X-memory (which is copied as many times as there are input ports).

[0016] • Input port writes are an independent process and do not require any muDSP cycles. When both the muDSP and the input port want to access the same memory at the same time, normally the muDSP is stalled unless it asserts priority using special instruction flags.

[0017] muDSP is event-driven, meaning a program starts when a specific condition occurs, processes the relevant data, and then returns to a low-power idle state. Small, dedicated hardware blocks (such as counters and bound checks on memory pointers) are used to detect events. Here is an example:

[0018]

[0019] The exemplary embodiment has at least one of the following event categories (in order of priority):

[0020] • Startup event (routine executed when muDSP is reset)

[0021] • Invalid input frame event (triggered by invalid frame end input signal)

[0022] • Buffer full event (triggered by memory pointer crossing a programmable threshold)

[0023] • Buffer empty event (triggered by memory pointer crossing a programmable threshold)

[0024] • Input frame event (triggered by the frame end input signal)

[0025] • Counter event (triggered when the internal programmable counter crosses zero)

[0026] In terms of procedures and controls:

[0027] • In addition to a small data memory, the muDSP also has a program memory that is much smaller than typical program memories of prior art DSPs (typically 256 words in the first embodiment).

[0028] • The muDSP can execute multiple sub-operations in parallel, somewhat similar to the Explicitly Parallel Instruction Computing (EPIC) or Very Long Instruction Word (VLIW) instruction set architectures, but at a very simple level.

[0029] • For simple encoding of sub-operations, the program memory is very wide (e.g. 96 bits in an embodiment) and contains different fields for various parts of the address generator, instruction control and data path, for a total of 32 fields in the current embodiment.

[0030] Simply encoding sub-operations into program memory also means that instruction decoding requires no pipeline cycles. For increased efficiency, a local latch bank, storing the last four instructions, is used. Activating the local loop instruction shuts down main memory and iterates N times over these one to four instructions. Each instruction requires only one cycle, so programs in the muDSP can run very quickly and with highly predictable execution times.

[0031] Conditional execution and branching operations are supported. The condition is typically determined by the state of a flag, whose value depends on the result in the datapath. Conditional execution (including conditional execution of jumps) can be implemented using a dedicated "conditional execution" subfield in the opcode. Datapath: The muDSP datapath is typically replicated M times (the number of replications is the same as the number of input ports and XMEMs). Each datapath can be used independently, but they can also function as a single datapath with a word length multiple of M. This provides flexibility in processing various word lengths. In the exemplary embodiment, the datapath length is 32 bits and M = 2, allowing for processing 64-bit signals. Each datapath is divided into 8-bit groups, and a mask setting selects how many 8-bit groups constitute a word, further increasing word length flexibility. The datapath implements small floating-point multiplication (with an 8-bit significand and a 5-bit exponent). This small floating-point number has proven to be sufficiently precise for use as coefficients in IIR filters. If higher precision is required, arbitrary precision can be achieved through multiple iterations. The small floating-point multiplication consists of a barrel shifter whose least significant bit is replicated four times and operates with the four partial products of a modified Booth-coded multiplier. An accumulator (with an accumulation register A) is added after the floating-point multiplier. The accumulator has a second input, which can be the accumulation register (for implementing a MAC operation) or one of the other datapath registers (X, Y, Z). Using its two inputs, the accumulator can perform arithmetic addition / subtraction operations as well as various logical operations for bitwise operations. There is no hidden pipeline. Only minimal pipeline exists between accessible registers in the datapath. This is because many signal processing algorithms are recursive and require the results of previous calculations as inputs for subsequent calculations. Therefore, these results should be available as quickly as possible (without having to wait for pipelines). When executing conditional instructions, it is desirable to avoid the power consumption and complexity added by pipeline flushing. Note that this pipeline flushing option is very likely in future embodiments when speed is more important than efficiency. In order to still be able to accumulate 2*32-bit results without pipelining, a redundant data format is used that adds an additional "guard" bit to each group of 8 bits, effectively encoding a 9-bit signed number (two's complement). The 1-bit overlap between these groups (1-bit redundancy) is used to interrupt carry propagation in such a way that the longest carry chain becomes about 12 bits (because the word length increases from 9 bits to 12 bits when multiple partial products and accumulators are added).

[0032] Parameterized design: The entire muDSP is generated programmatically, for example, with the number of input ports as a parameter (and therefore the number of X memories and datapaths). This enables easy generation of variants with a different number of ports, different memory sizes, or different digital sizes.

[0033] As mentioned above, the overall architecture of muDSP differs from the prior art because it focuses on power efficiency and simplicity. However, within muDSP, we can point to a few areas that differ most from the prior art and deserve separate claims or separate applications:

[0034] Use of small latch banks for efficient local looping; data paths with signed numbers (each with a 1-bit guard bit) and flexible word lengths; floating-point multiplier combining a barrel shifter with Booth multiplication.

[0035] There is typically no instruction decoder.The DSP of the present disclosure provides a simple input-output behavior where the input ports write directly to memory.

[0036] The most straightforward application of this invention is processing oversampled audio signals. Such oversampled signals are commonly used in (sigma-delta) data converters and digital amplifiers, such as those in Axign's audio controller [US10659028]. Oversampled signals are also used in active noise reduction loops, primarily because downsampling the microphone's digitized (bitstream) output would incur excessive latency. To accommodate these applications, the DSP is optimized for high-speed FIR and IIR filtering (it can compute a biquad filter stage in just three cycles).

[0037] For more general audio applications, during muDSP's development, it was ensured that µDSP is well suited to the following algorithm classes:

[0038] • Channel mixing and volume control

[0039] •FIR / IIR filters (for sound processing, interpolation, decimation & ANC)

[0040] • Adaptive filter / algorithm (LMS)

[0041] • Polynomial function evaluation (for ASRC & nonlinear compensation)

[0042] •Signal statistics (mean square, correlation, etc.)

[0043] • Frequency domain analysis (FFT)

[0044] • Auxiliary processing (division for normalization, SQRT for RMS, CORDIC for sin / cos, etc.)

[0045] µDSP can also be applied to other one-dimensional signals, such as for high-speed control loops or data communications.

[0046] In a first aspect, the present invention relates to a digital signal processor (DSP) (1) for streaming audio applications, in particular, a low-power DS processor comprising two or more micro digital signal processors (µDSPs), in particular, 3 to 12 µDSPs, more particularly, 4 to 8 µDSPs, wherein the at least two or more µDSPs form a network, wherein each individual µDSP comprises a size < 2 18 words (specifically, <2 16 More specifically, <2 14 words), wherein each individual word has a size of 256 bits or less, particularly a size of 128 bits or less, more particularly a size of 96 bits or less, for example a size of 32 bits or less, wherein the two or more µDSPs are connected or connectable in series and / or in parallel, wherein the two or more micro digital signal processors (µDSPs) are each individually configured to receive an input signal selected from an audio source input signal and to receive input signals of other µDSPs in the two or more micro digital signal processors (µDSPs), wherein the two or more micro digital signal processors (µDSPs) are each individually configured to receive an input signal selected from an audio source input signal and to receive input signals of other µDSPs in the two or more micro digital signal processors (µDSPs), wherein the two or more micro digital signal processors (µDSPs) are each individually configured to receive an input signal selected from an audio source input signal and to receive input signals of other µDSPs in the two or more micro digital signal processors (µDSPs). is independently configured to provide an output signal selected from the output signal of the digital-to-analog converter and the output signals to other of the two or more micro digital signal processors (µDSPs), wherein the two or more micro digital signal processors (µDSPs) each independently comprise two or more µDSP data interface inputs, wherein each micro digital signal processor is configured to operate at a clock frequency >1 MHz, particularly at a clock frequency >10 MHz, more particularly at a clock frequency >20 MHz, even more particularly at a clock frequency >100 MHz, for example at a clock frequency >200 MHz [see e.g. Figure 1 ].

[0047] In a second aspect, the present invention relates to an audio reproduction signal path comprising a digital signal processor (DSP) (1) for streaming audio applications according to the present invention, in particular, further comprising at least one unit selected from the following units: a loop filter, wherein the loop filter is configured to receive input from at least one micro DSP; a butterfly mixer, wherein the butterfly mixer is configured to receive input from at least one loop filter, mix the input of the loop filter, and provide an output to at least one PWM; a PWM, wherein the PWM is configured to receive input from the loop filter and / or the butterfly mixer, pulse width modulate the input, and provide an output to an output crossbar or an output channel; an output crossbar; an output terminal; a low-latency ADC configured to provide an output to an output terminal or an output crossbar and receive an input from the μDSP; a router, wherein the router is configured to receive input from at least one other unit and provide an output to at least one other unit; a feedback loop filter, wherein the feedback loop filter is configured to provide an output to a digital-to-analog converter (in particular, a Sigma-Delta DAC) and configured to provide an input to at least one of two or more micro digital signal processors (µDSPs); and a decimator configured to receive an input from a low latency analog-to-digital converter (LLADC) and provide an output to the µDSP [see e.g. Figure 1 ].

[0048] In a third aspect, the invention relates to an integrated circuit comprising a digital signal processor (DSP) according to any one of the preceding claims for streaming audio applications.

[0049] In a fourth aspect, the present invention relates to an electronic device comprising an integrated circuit according to the present invention or a digital signal processor according to the present invention, such as an audio amplifier, an active speaker system, an active noise reduction system, a high-speed closed-loop controller, a high-resolution low-latency data converter, an analog-to-digital (A / D) converter, a power supply controller, a motor controller, a digital audio converter, a digital amplifier controller, and combinations thereof.

[0050] Thus, the present invention provides a solution to one or more of the problems set forth above.

[0051] Throughout this specification, the advantages of the present invention are described in detail. DETAILED DESCRIPTION

[0052] In a first aspect, the invention relates to a digital signal processor (DSP) for streaming audio applications according to claim 1 .

[0053] In an exemplary embodiment of a DSP of the present disclosure, each individual micro digital signal processor (µDSP) includes a control interface configured to process input from an external source, such as a host processor, wherein the input is used to write or read the contents of a program memory (PMEM) and / or a coefficient memory (YMEM) to control the behavior of the µDSP and / or read status information. Figure 2 ].

[0054] In an exemplary embodiment of the DSP of the present disclosure, the two or more micro digital signal processors (µDSPs) each individually include two or more µDSP data interface inputs and / or two or more µDSP data interface outputs. The data interface inputs write their data directly to the data memory (XMEM). The data interface outputs receive their data from the output data registers. Figure 2 ].

[0055] In an exemplary embodiment of the DSP of the present disclosure, the at least two or more µDSPs form a network, in particular, a switchable network, wherein the network comprises an array n*m of µDSP routers (i, j), wherein i∈[1,n] and j∈[1,m], in particular, wherein n is between 2 and 2 8 In the range of 2 to 2 8 More specifically, where n is within the range of 2 2 to 2 7 In the range of , specifically, where m is 2 2 to 2 7 In the range of 2, even more specifically, where n is 2 3 to 2 6 In the range of , specifically, where m is 2 3 to 2 6 , specifically, wherein each individual router (i, j) includes a data input and output for the µDSP and further includes at least two router inputs and at least two router outputs for connecting to a router (i, j) selected from router (i+1, j), router (i, j+1), router (i, j-1), and router (i-1, j) [ Figure 4 ].

[0056] In an exemplary embodiment, the DSP of the present disclosure includes at least one 32-bit µDSP, specifically, at least three 32-bit µDSPs and at least one 96-bit µDSP.

[0057] In an exemplary embodiment of the DSP of the present disclosure, the at least one 96-bit μDSP includes three 32-bit sub-memories [ Figure 9 ].

[0058] In an exemplary embodiment of the DSP of the present disclosure, the at least two µDSPs or the network of the at least two µDSPs are configured to receive a plurality of inputs, in particular, wherein the inputs are selected from the group consisting of a pulse width modulator input, a loop filter input, an analog-to-digital converter (ADC) input (in particular, a low latency ADC (LLADC) input), a bitstream input such as a direct stream digital (DSD) or a digital microphone (DMIC) input, a microcontroller (MCU) input, a routing input, and a serial audio port (SAP) input, and / or wherein the at least two μDSPs or the network of the at least two μDSPs are configured to provide a plurality of outputs, in particular, wherein the outputs are selected from the group consisting of a pulse width modulator output, a loop filter output, an ADC output (in particular, a low latency ADC output), a DSD output, a DMIC output, an MCU output, a routing output, and a SAP output. Figure 5 ].

[0059] In an exemplary embodiment of the DSP of the present disclosure, the at least two µDSPs are each individually configured to mark the frame input with a unique identifier in the form of an additional bit immediately adjacent to the data input to mark the end of a frame of data words.

[0060] In an exemplary embodiment of the DSP disclosed herein, the at least two µDSPs are each individually configured to be event-driven. Specifically, the external events are selected from the group consisting of reset, output request sample, invalid frame, and (valid / normal) frame events, and the internal events are selected from the group consisting of buffer full, buffer empty, and counter events. Once triggered, the program associated with an event will run to completion and will not be interrupted by another event. Therefore, events are considered distinct from "interrupts" known in the prior art, and events according to the present invention are also distinct from "interrupts" known in the prior art. Handling interrupts typically requires additional control and memory overhead to store the state of the main program before the interrupt and restore that state afterward. This overhead is considered a significant disadvantage.

[0061] In an exemplary embodiment of the DSP of the present disclosure, each individual µDSP is configured to process data through a data path, wherein the processing is configured to be controlled by a program controller, wherein the controller is configured to control at least one of: receiving input from a local data register; providing a mask (specifically, a 32 to 64 bit mask) on the received input; rotating the masked input; multiplying the rotated input; performing arithmetic operations on the rotated input and / or the local data register input (in computing, an arithmetic logic unit (ALU) is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers); providing a flag on the arithmetic output; providing protection on the arithmetic output; limiting overflow; and providing output to the local data register. Figure 6 ].

[0062] In an exemplary embodiment of the DSP of the present disclosure, the at least two µDSPs are each individually configured to include a guard bit for every eight word bits in the accumulator, wherein the guard bit is the first bit or the last bit of the eight bits of the word. Figure 8 ].

[0063] In an exemplary embodiment of an audio reproduction signal path of the present disclosure, one or more µDSPs (400) provide input to a programmable pulse width modulation (PWM) controller (1), wherein the DSP is used for interpolation of PCM input signals, decimation of loop filter output signals, audio processing and filtering, and / or adjusting the behavior of a loop filter (20). The PWM controller comprises the following items (i), (ii), and (iii) connected in series: (i) at least two parallel loop filters (20) for loop gain and signal processing, preferably at least four loop filters, each loop filter comprising a plurality of inputs (10, 15) and at least one output (25), wherein the loop filter (20) is adapted to receive PCM inputs from the DSP, perform common mode control, differential mode control, and LC compensation, characterized in that each single output (25) is electrically connected to (ii) at least one butterfly mixer (30), the butterfly mixer capable of mixing at least two inputs (25) and providing at least two mixed outputs (35) to (iii) at least two parallel pulse width modulators (PWMs) (40), wherein (iv) the loop filter, the butterfly mixer and the PWM are each independently programmable and adjustable, wherein the loop filter input (15) is adapted to receive at least one of a local digital PWM processed output signal (45) and an ADC output, and includes at least one setting data storage device (440) for loading, adjusting and storing programmable and adjustable settings accessible by the µDSP [ Figure 12 ].

[0064] In an exemplary embodiment, the DSP of the present disclosure includes: at least one local latch buffer memory configured to execute a local loop; at least one local program counter (PCL) for driving a 32-bit output to a data register and for driving an output from a local address register, wherein the PCL is configured to drive an output to an nth local address register and to drive an output from an n+1th local address register, the at least one local latch buffer memory including four local address registers [ Figure 9 ].

[0065] In an exemplary embodiment of the DSP of the present disclosure, the local latch buffer memory is configured to receive program data (PDATA), which is a bundle of signals grouped into fields, where each field encodes a sub-operation (in binary "opcode" form) and all sub-operations can be executed in parallel. In the exemplary embodiment, the fields are as follows:

[0066]

[0067]

[0068] Example of pm_XRM0 opcode:

[0069]

[0070] Example of pm_BX0 opcode:

[0071]

[0072] While the invention has been described in the context of detailed illustrations, it is best understood by referring to the accompanying examples and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Overview of the drawings

[0074] Figures 1 to 12 Details of a digital signal processor and aspects thereof of the present disclosure are shown.

[0075] Detailed description of the drawings

[0076] These figures are exemplary only and elements in the figures may be combined.

[0077] In the attached figure:

[0078]

[0079]

[0080]

[0081] Figure 1 Shown is a schematic layout of an audio signal path including a first DSP and optional microcontroller, followed by the micro DSP and feedback loop of the present disclosure, and an audio output (eg, speaker, etc.).

[0082] Figure 2A block diagram of a µDSP is shown. In an exemplary configuration, the µDSP includes: a 96-bit x 256-word instruction memory (PMEM), whose addresses are generated by the program controller (PC); an auxiliary buffer that stores the most recent instruction's data (PDATA) for reuse by local loops; two 32-bit data input and output interfaces; two 32-bit x 256-word data memories (XMEM0, XMEM1) and their address generation units (AGUs); and a coefficient memory (YMEM), which also has its own AGU. XMEM and YMEM interface with the datapath registers (X0, X1, Y0, Y1, Z0, Z1). The datapath itself also has accumulator registers A0 and A1.

[0083] Figure 3 An exemplary use of multiple µDSPs directly connected to each other is shown, where a µDSP with two inputs and outputs is used to implement a streaming audio application where audio streams are transmitted in left-to-right, right-to-left, and top-to-bottom directions.

[0084] Figure 4 An exemplary use of multiple µDSPs connected via a configurable router network is shown to enable greater flexibility in data flow direction.

[0085] Figure 5 This article illustrates an exemplary use of a network of multiple µDSPs in a digital audio controller, connecting the µDSPs not only to each other but also to various signal sources and destinations. These sources include PCM signals from an MCU, a serial audio port (SAP), or bitstream sources such as direct stream digital (DSD) inputs or digital microphone (DMIC) inputs, or locally generated bitstreams from pulse-width modulators (PWMs) or (low-latency) ADCs. Signal destinations include loop filters, which further process the PCM signals from the µDSPs, typically at a higher sampling frequency to implement high-speed control loops. The outputs of the loop filters can be mixed with each other via a butterfly mixer before being used as inputs to the PWMs. The PWM outputs can be reused as inputs or as controller outputs via a configurable crossbar switch.

[0086] Figure 6A block diagram of one of the µDSP's data paths is shown, with data flowing from top to bottom. Starting in the upper right corner, different data registers can be selected as inputs to a mask that selectively passes or blocks 8-bit groups. The barrel shifter shifts / rotates the masked data and passes the 32 bits of the shifted data to the multiplier. Another input to the multiplier is an 8-bit group selected from various constants or portions of data registers. The multiplier output is fed into the arithmetic logic unit (ALU), which combines the signal with the auxiliary input on the left (which is also various constants or registers). The ALU output is stored in accumulator register A0, which includes multiple guard bits. There is also a single-bit flag register that can be configured to signal various conditions of the ALU output or other data registers (such as greater than zero, less than zero, or equal to zero). The guarded signal in the accumulator is then converted to normal binary form (using clipping or overflow mechanisms) before being stored in datapath output register Z0.

[0087] Figure 7 Exemplary data flows for two exemplary configurations of a µDSP network are shown.

[0088] Figure 8 The figure shows the use of a guard bit for every 8-bit group in the accumulator register, where the guard bit acts as a sign bit, resulting in a 9-bit signed number with one bit of overlap between each signed number. This overlap creates redundancy that can be used to interrupt carry propagation. The redundancy allows the same 32-bit value to be encoded in multiple ways, as shown in the figure.

[0089] Figure 9 The use of a local ring buffer is shown to store the last N PDATA words, corresponding to the last N instructions. In the exemplary µDSP configuration, this is a latch buffer of N = 4. When the current instruction indicates the start of a local loop, the main PMEM memory is disabled to stop its power consumption, and only the local buffer is used for the loop's instructions (thus limiting the local loop to covering a maximum of N instructions).

[0090] Figure 10 Shows examples of loop filters, butterfly mixers, PWMs, and crossbars that can be placed after the µDSP network (see also Figure 5 ).

[0091] Figure 11 A block diagram of a butterfly mixer is shown in more detail.

[0092] Figure 12An example of using a µDSP (400) in an integrated circuit for controlling audio signals is shown, which also uses a loop filter, a butterfly mixer, a PWM modulator, and various other circuits. In the example use in this figure, the µDSP handles interpolation of the incoming audio signal and decimation of the loop filter output.

Claims

1. A digital signal processor (DSP) for streaming audio applications (1), specifically a low-power DSP, comprising: Two or more micro digital signal processors µDSP, specifically 3 to 12 µDSPs, more specifically 4 to 8 µDSPs, wherein at least two or more µDSPs form a µDSP network, Each individual µDSP includes a size <2 18 words, specifically, <2 16 More specifically, <2 14 words, local memory, wherein each individual word has a size of 256 bits or less, specifically, a size of 128 bits or less, more specifically, a size of 96 bits or less, for example, a size of 32 bits or less, wherein the two or more µDSPs are connected in series and / or in parallel or are capable of being connected in series and / or in parallel, wherein each of the two or more micro digital signal processors μDSP is individually configured to receive an input signal selected from an audio source input signal and is configured to receive input signals of other μDSPs in the two or more micro digital signal processors μDSP, wherein the two or more micro digital signal processors µDSP each individually include two or more µDSP data interface inputs, and wherein the two or more micro digital signal processors μDSP are each individually configured to provide an output signal selected from the output signal of the digital-to-analog converter and configured to provide output signals to other μDSPs of the two or more micro digital signal processors μDSP, Each micro digital signal processor is configured to operate at a clock frequency >1 MHz, specifically, at a clock frequency >10 MHz, more specifically, at a clock frequency >20 MHz, even more specifically, at a clock frequency >100 MHz, for example, at a clock frequency >200 MHz.

2. The digital signal processor (1) for streaming audio applications according to claim 1, wherein Each individual micro digital signal processor µDSP comprises a control interface configured to process input from an external source such as a host processor, wherein the input is used to write or read the contents of the program memory PMEM and / or the coefficient memory YMEM, thereby controlling the behavior of the µDSP and / or reading status information.

3. A digital signal processor DSP (1) for streaming audio applications according to claim 1 or 2, wherein: The two or more micro digital signal processors μDSP each individually include two or more μDSP data interface outputs.

4. A digital signal processor DSP (1) for streaming audio applications according to any one of claims 1 to 3, wherein: The at least two or more µDSPs form a switchable network, and / or wherein the network comprises an n*m array of µDSP routers (i, j), wherein i∈[1,n] and j∈[1,m], in particular, wherein n is between 2 and 2 8 In the range of 2 to 2 8 , wherein each individual router (i, j) includes a data input and output of the µDSP and further includes at least two router inputs and at least two router outputs for connecting to a router (i, j) selected from router (i+1, j), router (i, j+1), router (i, j-1), and router (i-1, j).

5. A digital signal processor DSP (1) for streaming audio applications according to any one of claims 1 to 4, comprising at least one 32-bit µDSP, in particular at least three 32-bit µDSPs, and at least one 96-bit µDSP.

6. The digital signal processor DSP (1) for streaming audio applications according to claim 5, wherein The at least one 96-bit µDSP includes three 32-bit sub-memories.

7. A digital signal processor DSP (1) for streaming audio applications according to any one of claims 1 to 6, wherein: The at least two μDSPs or the network of the at least two μDSPs are configured to receive a plurality of inputs, in particular, wherein the inputs are selected from a pulse width modulator input, a loop filter input, an analog-to-digital converter ADC input, a bitstream input such as a direct stream digital DSD or a digital microphone DMIC input, a microcontroller MCU input, a routing input and a serial audio port SAP input, wherein the analog-to-digital converter ADC input is in particular a low latency ADC "LLADC" input, and / or wherein the at least two μDSPs or the network of the at least two μDSPs are configured to provide a plurality of outputs, in particular, wherein the outputs are selected from a pulse width modulator output, a loop filter output, an ADC output, a DSD output, a DMIC output, an MCU output, a routing output and a SAP output, wherein the ADC output is in particular a low latency ADC output.

8. A digital signal processor (DSP) for streaming audio applications according to any one of claims 1 to 7, wherein: The at least two μDSPs are each individually configured to mark a frame input with a unique identifier, in particular in the form of an additional bit immediately adjacent to the data input to mark the end of a frame of data words.

9. A digital signal processor DSP (1) for streaming audio applications according to any one of claims 1 to 8, wherein: The at least two μDSPs are each individually configured to be event-driven, specifically, wherein the events are selected from external events and internal events, the external events being, for example, reset, output request sample, invalid frame, and valid or normal frame events, and the internal events being, for example, buffer full conditions, buffer empty conditions, and counters of events.

10. A digital signal processor (DSP) for streaming audio applications according to any one of claims 1 to 9, wherein: Each individual µDSP is configured to process data through a data path, wherein the processing is configured to be controlled by a program controller, wherein the controller is configured to control at least one of: receiving input from a local data register; providing a mask, specifically a 32 to 64 bit mask, to the received input; rotating the masked input; multiplying the rotated input; performing arithmetic operations on the rotated input and / or the local data register input; providing a flag on the arithmetic output; providing protection on the arithmetic output; limiting overflow; and providing output to the local data register.

11. A digital signal processor (DSP) for streaming audio applications according to any one of claims 1 to 10, wherein: The at least two μDSPs are each individually configured to include one guard bit per eight word bits in the accumulator, wherein the guard bit is the first bit or the last bit of the eight bits of the word.

12. A digital signal processor (DSP) for streaming audio applications according to any one of claims 1 to 11, comprising: at least one local latch buffer memory configured to execute a local loop; at least one local program counter PCL for driving a 32-bit output to a data register and for driving an output from a local address register, wherein the PCL is configured to drive an output to an nth local address register and to drive an output from an n+1th local address register, the at least one local latch buffer memory comprising four local address registers.

13. The digital signal processor DSP (1) for streaming audio applications according to claim 12, wherein The local latch buffer memory is configured to receive program data PDATA, ie signal bundles grouped in fields, in particular, wherein each field encodes a sub-operation, more particularly, wherein all sub-operations are configured to be executed in parallel.

14. An audio reproduction signal path comprising a digital signal processor DSP (1) for streaming audio applications according to any one of claims 1 to 13, in particular further comprising at least one unit selected from the following units: a loop filter, wherein The loop filter is configured to receive input from at least one micro DSP; a butterfly mixer, wherein the butterfly mixer is configured to receive input from at least one loop filter, mix the input of the loop filter, and provide an output to at least one PWM; a PWM, wherein the PWM is configured to receive input from the loop filter and / or the butterfly mixer, pulse-width modulate the input, and provide an output to an output crossbar or an output channel; an output crossbar; an output terminal; a low-latency ADC, configured to provide an output to an output terminal or an output crossbar and receive input from the μDSP; a router, wherein the router is configured to receive input from at least one other unit and provide an output to at least one other unit; a feedback loop filter, wherein the feedback loop filter is configured to receive input from the digital-to-analog converter and is configured to provide input to at least one of the two or more micro digital signal processors μDSP, the digital-to-analog converter being specifically a Sigma-Delta DAC; and a decimator, configured to receive input from the LLADC and provide an output to the μDSP.

15. An audio reproduction signal path comprising a digital signal processor (DSP) (1) for streaming audio applications according to claim 14, said one or more µDSPs (400) providing an input to a programmable pulse width modulation (PWM) controller (100), wherein The DSP is used for interpolation of PCM input signals, extraction of loop filter output signals, audio processing and filtering, and / or adjusting the behavior of the loop filter (20), and the PWM controller includes the following items (i), (ii) and (iii) connected in series: (i) at least two parallel loop filters (20) for loop gain and signal processing, preferably at least four loop filters, each loop filter including a plurality of inputs (10, 15) and at least one output (25), wherein the loop filter (20) is adapted to receive PCM input from the DSP, perform common mode control, differential mode control and LC compensation, and is characterized in that each single output (2 5) electrically connected to (ii) at least one butterfly mixer (30), said butterfly mixer being capable of mixing at least two inputs (25) and providing at least two mixed outputs (35) to (iii) at least two parallel pulse width modulators PWM (40), wherein (iv) the loop filter, the butterfly mixer and the PWM are independently programmable and adjustable, wherein the loop filter input (15) is adapted to receive at least one of a local digital PWM processed output signal (45) and an ADC output, and comprises at least one setting data storage device (440) for loading, adjusting and storing programmable and adjustable settings accessible by said µDSP.

16. An integrated circuit comprising a digital signal processor (DSP) according to any one of the preceding claims for use in streaming audio applications.

17. An electronic device comprising the integrated circuit according to claim 16 or the digital signal processor according to any one of claims 1 to 15, such as an audio amplifier, an active speaker system, an active noise reduction system, a high-speed closed-loop controller, a high-resolution low-latency data converter, an A / D converter, a power supply controller, a motor controller, a digital audio converter, a digital amplifier controller, and combinations thereof.

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