Relay control device and method

Abstract

A relay control device according to one embodiment of the present disclosure includes: a processor configured to output a base control signal for controlling an operation of a relay and a first decision control signal having a differential signal level according to an operation state thereof; a monitoring unit configured to monitor an operating state of the processor and output a second decision control signal having a differential signal level according to the operating state of the processor and a holding signal for holding the operating state of the relay; and a relay state determination unit configured to output one of the basic control signal and the holding signal as a relay control signal for controlling on / off of the relay based on signal levels of the first decision control signal and the second decision control signal.

Description

Technical Field

[0001] This application claims priority from Korean Patent Application No. 10-2023-0077690 filed in Korea on June 16, 2023, the disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a relay control device and method, and more particularly to a relay control device and method capable of maintaining an operating state of a relay even when a processor is reset due to a system error or the like. Background Art

[0003] As demand for portable electronic products such as laptop computers, cameras, and mobile phones that use electricity as a power source rapidly increases, and as mobile robots, electric bicycles, electric carts, and electric vehicles become increasingly commercialized, research on high-performance secondary batteries that can be repeatedly charged and discharged is being actively conducted.

[0004] Commercially available secondary batteries include nickel-cadmium batteries, nickel-metal hydride batteries, nickel-zinc batteries, and lithium secondary batteries. Among these, lithium secondary batteries offer advantages due to their near-no memory effect, flexible charging and discharging capabilities, and a significantly lower self-discharge rate compared to nickel-based secondary batteries. Furthermore, lithium secondary batteries possess high energy density and high operating voltage, resulting in more intensive research and widespread use in practical products than other secondary battery types.

[0005] In recent years, secondary batteries have been widely used not only in small devices such as portable electronic devices but also in medium and large devices such as electric vehicles and energy storage systems (ESS).

[0006] In this case, a battery module in which a plurality of electrically connected secondary batteries are stored together inside a module case is mainly applied, and further, when high power or large capacity is required, a battery pack in which a plurality of such battery modules are electrically connected is also applied.

[0007] For secondary battery cells, cell assemblies, battery modules, or battery packs (collectively referred to as "batteries"), power efficiency and safety are important factors, so research is actively underway on BMSs for monitoring the electrical characteristics of batteries and performing feedback control such as charging and discharging using the monitoring results, as well as battery peripheral devices such as relays for controlling the electrical connection between batteries and loads (motor, electric heater, vehicle electrical components, etc.).

[0008] The power system, specifically a processor provided within the power system, controls the on / off switching of a relay mediating between a battery and a load according to safety issues such as energy efficiency, stable operation of a battery, or suppression of overcharging / overdischarging, thereby causing optimized power to be supplied to the load.

[0009] Electric vehicles (EVs) or hybrid electric vehicles (HEVs) equipped with power systems are generally exposed to an external environment with strong vibrations and fluctuating temperatures and humidity. Furthermore, in recent electric vehicles, air conditioning equipment such as air conditioners and heaters, as well as numerous devices such as cameras, navigation systems, braking systems, and suspension systems, are composed of electrical and electronic components.

[0010] Therefore, since the power system installed in the electric vehicle and composed of electrical and electronic components is constantly exposed to such physical or electromagnetic influences, errors may occur in the processor of the power system.

[0011] When an error occurs in the processor, the processor is designed to recover to a normal state through a reset state (reset state) by running a built-in algorithm or the like, but during this process, a problem occurs in which the processor cannot properly control the relay.

[0012] In particular, if the processor fails to properly control the relay while the vehicle is running, a fatal safety accident may occur, so there is a strong demand to design the relay so that the relay remains in the on state and does not enter the off state even if a system error or the like occurs. Summary of the Invention

[0013] Technical issues

[0014] The present disclosure is designed to solve the problems of the related art, and therefore the present disclosure aims to provide a relay control device and method, which can maintain the connection state of the relay even when the processor enters the reset state due to a system error, etc. by applying an improved configuration that can be clearly operated with a relatively simple structure.

[0015] The technical problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0016] Technical Solution

[0017] A relay control device according to one aspect of the present disclosure may include: a processor configured to output a basic control signal for controlling the operation of a relay and a first decision control signal having a differential signal level according to an operating state thereof; a monitoring unit configured to monitor the operating state of the processor and output a second decision control signal having a differential signal level according to the operating state of the processor and a holding signal for maintaining the operating state of the relay; and a relay state determination unit configured to output one of the basic control signal and the holding signal as a relay control signal for controlling the on / off state of the relay based on the signal levels of the first decision control signal and the second decision control signal.

[0018] Here, the relay state determination unit of the present disclosure may be configured to output one of the basic control signal and the holding signal as the relay control signal based on a signal level of a result signal of calculating the first decision control signal and the second decision control signal.

[0019] In addition, when the operating state of the processor is the reset state, the processor of the present disclosure may be configured to output a first switching control signal to the relay state determination unit, the first switching control signal being a first decision control signal having a signal level different from that of the first decision control signal output when the processor is in the normal state. In addition, when the operating state of the processor is the reset state, the monitoring unit of the present disclosure may be configured to output a second switching control signal to the relay state determination unit, the second switching control signal being a second decision control signal having a signal level different from that of the second decision control signal output when the processor is in the normal state.

[0020] According to an embodiment, the monitoring unit of the present disclosure may be configured to output the second switching control signal only when both software monitoring using feedback information for the request and hardware monitoring using receipt of the trigger signal fail.

[0021] Preferably, the relay state determination unit of the present disclosure can be configured to output the basic control signal as the relay control signal when neither the first switching control signal nor the second switching control signal is received, and to output the holding signal as the relay control signal when both the first switching control signal and the second switching control signal are received.

[0022] Furthermore, when the operating state of the processor is the reset state, the monitoring unit of the present disclosure may be configured to output a hold signal having a signal level corresponding to a basic control signal output by the processor in a normal state immediately before the reset state.

[0023] Furthermore, the monitoring unit of the present disclosure may be configured to output the hold signal at the second signal level when the reset state of the processor continues for a reference time, and output the hold signal at the first signal level after the reference time.

[0024] A battery pack according to another aspect of the present disclosure may include the relay control device according to one aspect of the present disclosure.

[0025] A vehicle according to another aspect of the present disclosure may include the relay control device according to one aspect of the present disclosure.

[0026] According to another aspect of the present disclosure, a relay control method includes: a basic signal receiving step for receiving a basic control signal for controlling the operation of a relay and a first decision control signal having a differential signal level according to an operating state of a processor; a control signal receiving step for receiving a second decision control signal having a differential signal level according to the operating state of the processor and a holding signal for maintaining the operating state of the relay; and a control signal output step for outputting one of the basic control signal and the holding signal as a relay control signal for controlling the on / off of the relay based on the signal levels of the first decision control signal and the second decision control signal.

[0027] Beneficial effects

[0028] According to the present disclosure, the normal state and reset state of the processor can be accurately selected, and by organically incorporating the selected results into the relay control, both the clarity and efficiency of the relay control can be further optimized.

[0029] Furthermore, according to one aspect of the present disclosure, even if the processor is reset, the operating state of one or more relays can be effectively maintained, so that operation interruption or safety accidents caused by processor reset and subsequent relay disconnection can be fundamentally prevented.

[0030] In addition, according to one aspect of the present disclosure, by generating a hold signal corresponding to the control signal output by the processor in the normal state immediately before the reset state, and configuring the relay to be controlled using the hold signal, the relay state before the reset state can be more effectively maintained.

[0031] In addition, according to one aspect of the present disclosure, when the processor enters a reset state, the signal system of the control relay is implemented as an architecture that organically applies dual signals output from the processor itself and various components independent of the processor, thereby faithfully reflecting both independence from the processor and interconnection with the processor, thereby enabling more precise processing.

[0032] Furthermore, the present disclosure may have various other effects, and these effects will be explained in each embodiment, or explanation of effects that can be easily inferred by those skilled in the art will be omitted. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings illustrate preferred embodiments of the present disclosure and, together with the foregoing disclosure, are used to provide a further understanding of the technical features of the present disclosure. Therefore, the present disclosure should not be understood as being limited to the accompanying drawings.

[0034] Figure 1 is a block diagram illustrating a detailed configuration of a relay control device according to one embodiment of the present disclosure.

[0035] Figure 2 It shows Figure 1 A block diagram of the detailed configuration of the relay state determination unit is shown in FIG.

[0036] Figure 3 It shows Figure 1 8 is a block diagram showing a detailed configuration of another embodiment of a relay state determination unit.

[0037] Figure 4 is a flowchart illustrating a processing procedure according to one embodiment of the present disclosure.

[0038] Figure 5 is a flowchart illustrating a processing procedure according to another embodiment of the present disclosure.

[0039] Figure 6 is a flowchart illustrating a processing procedure according to yet another embodiment of the present disclosure.

[0040] Figure 7 is a diagram illustrating a signal system according to each of a normal state and a reset state according to one embodiment of the present disclosure.

[0041] Figure 8 is a diagram illustrating a signal system according to each of a normal state and a reset state according to another embodiment of the present disclosure.

[0042] Figure 9 is a diagram illustrating a signal system according to yet another embodiment of the present disclosure.

[0043] Figure 10 is a diagram illustrating a signal system for controlling a plurality of relays according to one embodiment of the present disclosure.

[0044] Figure 11 is a diagram illustrating a signal system in which a decision control signal is generated according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Before the description, it should be understood that the terms used in the specification and the appended claims should not be interpreted as being limited to general meanings and dictionary meanings, but should be interpreted based on the meanings and concepts corresponding to the technical aspects of the present disclosure on the principle of allowing the inventor to appropriately define the terms for the best interpretation.

[0046] Therefore, the descriptions presented herein are merely preferred examples for illustrative purposes, and are not intended to limit the scope of the present disclosure, and it should be understood that other equivalents and modifications may be made thereto without departing from the scope of the present disclosure.

[0047] Furthermore, in describing the present disclosure, when a detailed description of related known elements or functions is deemed to obscure the key subject matter of the present disclosure, the detailed description will be omitted.

[0048] Throughout the specification, when a part is referred to as “including” or “comprising” any element, it means that the part may further include other elements, but does not exclude other elements, unless specifically stated otherwise.

[0049] In addition, the term "processor" described in this specification refers to a unit that processes at least one function or operation and can be implemented by hardware, software, or a combination of hardware and software.

[0050] Furthermore, throughout the specification, when a part is referred to as being “connected” to another part, it is not limited to the case where they are “directly connected” but also includes the case where they are “indirectly connected” with another element interposed therebetween.

[0051] Figure 1 is a block diagram showing a detailed configuration of a relay control device 100 according to one embodiment of the present disclosure, and Figure 2 and Figure 3 It shows Figure 1 2 is a block diagram of a detailed configuration of the relay state determination unit 130 shown in FIG.

[0052] First, refer to Figure 1 , and related drawings, etc., a detailed configuration of the relay control device 100 according to the present disclosure and processes performed by these configurations will be described in detail, and the relay state determination unit 130 will be described in detail later.

[0053] like Figure 1 As shown in , the relay control device 100 of the present disclosure may be configured to include a processor 110 , a monitoring unit 120 , and a relay state determining unit 130 .

[0054] Specifically, the relay state determining unit 130 may be configured to include a trigger 131, a buffer unit 132, and a gate unit. Figure 2 and Figure 3 As shown in , this depends on the embodiment.

[0055] The relay control device 100 of the present disclosure corresponds to a device that controls the on / off of the relay 200 by organically combining the control signal system originally output by the processor 110 and the signal for the operation of the relay 200 (hereinafter referred to as the "basic control signal") according to the monitoring result of the processor 110 and outputting a signal that ultimately controls the relay 200 (hereinafter referred to as the "relay control signal").

[0056] The drawing shows a first relay 210 corresponding to a high-side relay, which is a high-voltage side relay, and a second relay 220 corresponding to a low-voltage side relay, which is a low-voltage side relay. However, this is only an example, and it is obvious that different numbers and types of relays 200 can be applied.

[0057] The processor 110 provided to the relay control device 100 is a component for executing various control logics executed in the present disclosure, and may selectively include an application-specific integrated circuit (ASIC), other chipsets, logic circuits, registers, communication modems, data processing equipment, etc. known in the art to execute various control logics executed in the present disclosure.

[0058] Furthermore, when the control logic is implemented in software, a set of program modules stored in a memory or the like may be implemented by the processor 110. The memory may be located inside or outside the processor 110 and may be connected to the processor 110 through various well-known means to allow communication.

[0059] Before describing the present disclosure in detail, it is obvious that the relay control device 100 and the relay state determination unit 130 according to the present disclosure can be implemented by various combinations of electronic components, parts, etc., such as storage devices, operation processing devices, and input / output devices. Figure 1 The relay control device 100 shown in FIG. Figure 2 Each component of the relay state determination unit 130 and the like shown in FIG. 1 should be understood as a functionally or logically different component rather than a physically different component.

[0060] That is to say, since each component depicted in the drawings corresponds to a logical structure for effectively explaining the technical idea of the present disclosure, even if each component is configured in an integrated manner or separately, if it can realize the function performed by the logical structure of the present disclosure, it should be interpreted as being within the scope of the present disclosure; if it is a component that performs the same or similar function, it should of course be interpreted as being within the scope of the present disclosure, regardless of whether its name is consistent.

[0061] The relay control device 100 according to the present disclosure is configured to control the on / off of the relay 200 by outputting a relay control signal RCS, which is a signal that ultimately controls the relay 200, to the relay 200 based on the basic control signal CS output by the processor 110 when the operating state of the processor 110 is a normal state.

[0062] Specifically, when the processor 110 outputs the first basic control signal CS1 for controlling the first relay 210 and the second basic control signal CS2 for controlling the second relay 220 (S400, see Figure 4 ), the first relay control signal RCS1 and the second relay control signal RCS2 based on these signals are output to the first relay 210 and the second relay 220 respectively (S455), thereby controlling the on / off of the first relay 210 and the second relay 220 (S460).

[0063] Since the relay 200 is controlled by an on / off method rather than a step control or a linear control, the basic control signal CS or / and the relay control signal RCS may be configured to have a higher signal level (a high level or a second signal level) or a lower signal level (a low level or a first signal level) based on a preset reference.

[0064] Depending on the embodiment, the basic control signal CS or / and the relay control signal RCS, etc. may have a digital signal system through processes such as sampling and quantization.

[0065] In addition, since the input signal can be inverted and output using a simple circuit configuration or gate, a high-level (low-level) signal can be converted to a low-level (high-level) signal at any time.

[0066] Therefore, even if a signal of a certain level is mapped to a certain operation, a signal of an opposite level may be used to control the same specific action, which should be interpreted as self-evident to a person of ordinary skill in the art.

[0067] Needless to say, these interpretation standards can also be applied to the signals described below, specifically the hold signal RS output from the monitoring unit 120 of the present disclosure for maintaining the operating state of the relay 200 and the decision control signal DS having a differential signal level depending on the operating state of the processor 110.

[0068] The processor 110 of the present disclosure outputs a first decision control signal DS1 (S420) having a differential signal level according to its operating state, independent of the aforementioned basic control signal CS. The first decision control signal DS1 is used to determine the relay control signal RCS ultimately output by the relay state determination unit 130 of the present disclosure for controlling the relay 200. Details of this signal will be described later.

[0069] The monitoring unit 120 of the present disclosure is a configuration that monitors the operating state (normal state or reset state, etc.) of the processor 110 , and is preferably designed as a configuration independent of the processor 110 in order to implement a separate signal system.

[0070] The monitoring unit 120 of the present disclosure monitors the operating state of the processor 110 and outputs the second decision control signal DS2 having a differential signal level depending on the operating state of the processor 110 ( S420 ).

[0071] As an example, the monitoring unit 120 of the present disclosure may be configured to output a high-level (second signal level) second decision control signal DS2 when the operating state of the processor 110 is a normal state, and output a low-level (first signal level) second decision control signal DS2 when the operating state of the processor 110 is a reset state. The first decision control signal DS1 output by the processor 110 as described above is also similar to this.

[0072] Furthermore, the monitoring unit 120 of the present disclosure is configured to output a holding signal RS for maintaining the operating state of the relay 200 independently of the second decision control signal DS2 ( S410 ). The holding signal RS may be configured to have different signal levels depending on the embodiment or the main purpose of control.

[0073] Specifically, in an embodiment in which the relay 200 is turned on and maintained regardless of the previous state of the relay 200 when the processor 110 is in the reset state, the hold signal RS may be configured to continuously have a high level (second signal level) (see Figure 7 ).

[0074] In addition, the hold signal RS may be configured to have a low level when the processor 110 is in a normal state and a high level when the processor 110 is in a reset state, depending on the embodiment (see Figure 8 ).

[0075] In an embodiment of the present disclosure aimed at improving energy efficiency and suppressing overcharge / discharge, etc., the signal level of the hold signal RS may be configured to be a high level (second signal level) during a reference time during which the reset state of the processor 110 is maintained so as to turn off the relay 200 after the reference time, but after the reference time, the signal level of the hold signal RS may be configured to be a low level (first signal level) (see Figure 9 ).

[0076] In an embodiment in which the state of the relay 200 is maintained even in the reset state when the processor 110 is in the normal state (immediately before the reset state), that is, in an embodiment in which the relay 200 is to be maintained as being on when the relay 200 is turned on and the relay 200 is to be maintained as being off when the relay 200 is turned off, the monitoring unit 120 of the present disclosure may be configured to output a hold signal RS having a signal level corresponding to the basic control signal CS output by the processor 110 when the processor is in the normal state immediately before the reset state.

[0077] At the same time, the second decision control signal DS2 output by the monitoring unit 120 of the present disclosure and input to the relay state determination unit 130 of the present disclosure and the first decision control signal DS1 output by the processor 110 of the present disclosure and input to the relay state determination unit 130 of the present disclosure are used as signals to determine which signal is to be output by the relay state determination unit 130.

[0078] The relay state determination unit 130 of the present disclosure corresponds to a configuration of determining a relay control signal RCS, which is a signal for ultimately controlling the relay 200 , and outputting the determined relay control signal RCS to the relay 200 .

[0079] Specifically, the relay state determining unit 130 of the present disclosure receives the basic control signal CS and the first decision control signal DS1 from the processor 110 and receives the second decision control signal DS2 and the holding signal RS from the monitoring unit 120 .

[0080] When four types of signals (a basic control signal CS, a holding signal RS, a first decision control signal DS1, and a second decision control signal DS2) are input to the relay state determination unit 130 of the present disclosure, the relay state determination unit 130 of the present disclosure outputs one of the basic control signal CS and the holding signal RS as the relay control signal RCS according to whether the signal levels of the first decision control signal DS1 and the second decision control signal DS2 are high or low (S450, S460).

[0081] As described above, the first decision control signal DS1 and the second decision control signal DS2 have differential signal levels depending on the operating state (normal state or reset state) of the processor 110, so the first decision control signal DS1 and the second decision control signal DS2 represent the operating state of the processor 110 at the current time point.

[0082] That is, when the operating state of the processor 110 is the reset state, the monitoring unit 120 of the present disclosure outputs the second decision control signal DS2 having a signal level different from the second decision control signal DS2 output when the processor 110 is in the normal state. The first decision control signal DS1 output by the processor 110 is also similar.

[0083] In the following description, in order to make relative distinction clear, the first decision control signal DS1 and the second decision control signal DS2 output when the operating state of the processor 110 is the reset state are respectively referred to as "first switching control signal and second switching control signal".

[0084] When the second decision control signal DS2 input from the monitoring unit 120 is the second switching control signal DS2, that is, a signal indicating that the operating state of the processor 110 is a reset state (for example, a signal of a low level (first signal level)), the relay state determination unit 130 of the present disclosure can be configured to output the holding signal RS among the basic control signal CS and the holding signal RS as the relay control signal RCS.

[0085] In order to implement the preferred embodiment, the relay state determination unit 130 of the present disclosure can be configured to additionally check whether the first decision control signal DS1 input from the processor 110 is the first switching control signal DS1, that is, a signal indicating that the operating state of the processor 110 is a reset state (for example, a signal of a low level (first signal level)).

[0086] As an example, the relay state determination unit 130 of the present disclosure may be configured to calculate a first decision control signal DS1 and a second decision control signal DS2, and output one of a basic control signal CS and a holding signal RS as a relay control signal RCS (S450, S455) based on signal levels of the calculated result signals (S430, S440).

[0087] Specifically, the relay state determination unit 130 of the present disclosure may be configured to output the holding signal RS as the relay control signal RCS only when receiving both the first switching control signal DS1 output by the processor 110 and the second switching control signal DS2 output by the monitoring unit 120 ( S450 ).

[0088] The fact that the first switching control signal DS1 and the second switching control signal DS2 are received in this manner means that not only the processor 110, but also the monitoring unit 120, which is implemented as an independent configuration from the processor 110, outputs a signal indicating that the processor 110 is currently in a reset state, so it can be more clearly confirmed that the processor 110 is currently in a reset state.

[0089] In this manner, when the current processor 110 is in the reset state, as described above, the relay state determining unit 130 of the present disclosure outputs the hold signal RS among the basic control signal CS and the hold signal RS as the relay control signal RCS ( S450 ).

[0090] On the contrary, when the first switching control signal DS1 is not received from the processor 110 or the second switching control signal DS2 is not received from the monitoring unit 120, the relay state determining unit 130 of the present disclosure outputs the basic control signal CS among the basic control signal CS and the holding signal RS as the relay control signal RCS (S455).

[0091] This case corresponds to a case where the first decision control signal DS1 or the second decision control signal DS2 inputted from the processor 110 and the monitoring unit 120 respectively is a signal indicating that the operation state of the processor 110 is a normal state (eg, a signal of a high level (second signal level)).

[0092] According to an embodiment, priority may be given to the second decision control signal DS2 output by the monitoring unit 120. In this embodiment, when the first switching control signal DS1 is not input from the processor 110 but the second switching control signal DS2 is input from the monitoring unit 120, the processor 110 may be considered to be in a reset state, and the relay state determination unit 130 may be configured to output the hold signal RS, of the basic control signal CS and the hold signal RS, as the relay control signal RCS.

[0093] Specifically, if the first decision control signal DS1 and the second decision control signal DS2 are input (S420), the relay state determination unit 130 of the present disclosure may be configured to output a result of calculating them using a logic gate or the like as the decision control signal DS (S430), and determine the relay control signal RCS according to whether the signal level of the decision control signal DS is a high level (second signal level) or a low level (first signal level) (S440).

[0094] like Figure 11As shown in , when the relay state determining unit 130 of the present disclosure is configured to calculate the first decision control signal DS1 and the second decision control signal DS2 using an AND gate, the decision control signal DS having a low level is output only when both signals are at a low level (first signal level).

[0095] In other words, as defined above, the decision control signal DS indicating that the processor 110 is in the reset state (hereinafter referred to as "switching control signal") is output only when the first switching control signal DS1 is input from the processor 110 and the second switching control signal DS2 is received from the monitoring unit 120.

[0096] Hereinafter, an embodiment is described in which a low-level decision control signal DS (switching control signal) is output only when both the first decision control signal DS1 and the second decision control signal DS2 are at a low level, as shown in FIG. Figure 11 As shown in .

[0097] When the relay control signal RCS generated by accurately reflecting the operation state of the processor 110 is output to the relay 200 in this manner, the relay 200 of the present disclosure is controlled by the input relay control signal RCS ( S460 ).

[0098] Of course, if the preset termination conditions are not met, such as forced termination, complete system shutdown, or emergency event ( S470 ), the above-mentioned process of the present disclosure may be applied cyclically.

[0099] When the relay 200 is composed of a first relay 210 and a second relay 220, the relay state determination unit 130 of the present disclosure outputs a first relay control signal RCS1 to the first relay 210, and the first relay control signal RCS1 is determined to be one of the first basic control signal CS1 and the holding signal RS according to the signal level of the decision control signal DS; and, from a corresponding perspective, outputs a second relay control signal RCS2 to the second relay 220, and the second relay control signal RCS2 is determined to be one of the second basic control signal CS2 and the holding signal RS according to the signal level of the decision control signal DS.

[0100] Below, reference Figure 7 The above embodiments of the present disclosure are supplementarily described. Figure 7 is a diagram explaining a signal system according to each of a normal state and a reset state according to one embodiment of the present disclosure.

[0101] exist Figure 7, t1 shows a time point when a reset state of the processor 110 (MCU, etc.) starts due to a system error or the like, and t2 shows a time point when the processor 110 recovers to a normal state after the reset state.

[0102] like Figure 7 As shown in , when the processor 110 is in the initial normal state, both the first decision control signal DS1 and the second decision control signal DS2 are at a high level, so the decision control signal DS also becomes a high-level signal. The relay state determination unit 130 of the present disclosure outputs the basic control signal CS (S400) input from the processor 110 and the holding signal RS (S410) input from the monitoring unit 120 as the relay control signal RCS (S455) based on the decision control signal DS.

[0103] Therefore, the relay control signal RCS that ultimately controls the relay 200 until t1 when the processor 110 is in the initial normal state is based on the basic control signal CS.

[0104] When the processor 110 enters the reset state at time point t1, the monitoring unit 120 and the processor 110 respectively output the first decision control signal DS1 and the second decision control signal DS2 having a differential signal level (for example, a low level (first signal level)) from the first decision control signal DS1 and the second decision control signal DS2 in the normal state, that is, the first switching control signal DS1 and the second switching control signal DS2 (S420).

[0105] When the first switching control signal DS1 and the second switching control signal DS2, which are the first decision control signal DS1 and the second decision control signal DS2 having a differential level compared to the first decision control signal DS1 and the first decision control signal DS2 output when the processor 110 is in a normal state, are input to the relay state determination unit 130 (S435), the relay state determination unit 130 of the present disclosure outputs the holding signal RS input from the monitoring unit 120 as the relay control signal RCS (S450).

[0106] Therefore, in the [t1, t2] section, the relay control signal RCS output from the relay state determination unit 130 is based on the hold signal RS.

[0107] When the processor 110 returns to a normal state at time point t2, the processor 110 and the monitoring unit 120 of the present disclosure output a first decision control signal DS1 and a second decision control signal DS2 (e.g., a high level) indicating this situation, and upon receiving the signal, the relay state determination unit 130 of the present disclosure outputs the basic control signal CS among the basic control signal CS and the holding signal RS as the relay control signal RCS.

[0108] Therefore, after the time point t2 when the normal state is restored, the relay control signal RCS of the present disclosure becomes based on the basic control signal CS again.

[0109] Figure 7 The embodiment shown in corresponds to an embodiment in which the monitoring unit 120 of the present disclosure is set to output the holding signal RS having a high level regardless of the operating state of the processor 110 .

[0110] As described above, the relay control signal RCS is selectively set to one of the basic control signal CS and the hold signal RS based on the first decision control signal DS1 and the second decision control signal DS2. Therefore, even if the hold signal RS is set to maintain a high level regardless of the operating state of the processor 110, the hold signal RS is reflected as the relay control signal RCS only when the processor 110 is switched to the reset state, thereby allowing the relay 200 to be maintained in the on state.

[0111] According to the embodiments of the present disclosure, there is an advantage in that, since the signal level of the hold signal RS can be maintained at a constant signal level regardless of the operating state of the processor 110 , circuit design can be simply implemented.

[0112] Figure 5 is a flowchart of a processing procedure according to another embodiment of the present disclosure, and Figure 8 is a diagram showing an example of a signal system according to this embodiment.

[0113] Figure 5 The embodiments of the present disclosure shown in Figure 4 The embodiment described is different in that the monitoring unit 120 is configured to output a high-level holding signal RS only when it is detected that the processor 110 is in a reset state.

[0114] When the processor 110 is in a normal state (S510), if the first and second decision control signals DS1 and DS2 are input at a high level (S530), the relay state determination unit 130 of the present disclosure outputs the basic control signal CS input from the processor 110 (S500) as the relay control signal RCS (S550). The relay 200 is controlled to be turned on and off by the relay control signal RCS output in this manner (S560).

[0115] As described above, if the high-level first decision control signal DS1 and the second decision control signal DS2 are input, the high-level decision control signal DS obtained by calculating these signals is output inside the relay state determination unit 130 (S540), and the basic control signal CS can be output as the relay control signal RCS based on the decision control signal DS (S550).

[0116] On the other hand, when the processor 110 is in the reset state (S510), the monitoring unit 120 of the present disclosure outputs the hold signal RS at a high level (second signal level) (S520). Furthermore, since the processor 110 is in the reset state, the monitoring unit 120 of the present disclosure outputs the second decision control signal DS2 at a low level (first signal level), and the processor 110 of the present disclosure outputs the first decision control signal DS1 at a low level (first signal level) (S535).

[0117] When the low-level first decision control signal DS1 and the second decision control signal DS2 are input to the relay state determining unit 130 in this manner, the relay state determining unit 130 outputs the hold signal RS among the basic control signal CS and the hold signal RS as the relay control signal RCS (S555), and controls the relay 200 through the relay control signal RCS (S560).

[0118] Even in this case, as described above, if the first decision control signal DS1 and the second decision control signal DS2 having a low level are input, the low-level decision control signal DS obtained by calculating these signals is output inside the relay state determination unit 130 (S545), and the basic control signal CS can be output as the relay control signal RCS based on the decision control signal DS (S555).

[0119] In this embodiment, Figure 8 As shown in the lower part of , in the initial normal state (~ t1 ), the relay control signal RCS is output based on the basic control signal CS, and in the section t1 to t2 , the relay control signal RCS is output based on the holding signal RS.

[0120] When the processor 110 returns to a normal state at time point t2, it outputs a first decision control signal DS1 and a second decision control signal DS2 (e.g., a high level) indicating this situation, and upon receiving the signal, the relay state determination unit 130 of the present disclosure outputs the basic control signal CS among the basic control signal CS and the holding signal RS as the relay control signal RCS.

[0121] Therefore, after the time point t2 when the normal state is restored, the relay control signal RCS of the present disclosure becomes based on the basic control signal CS again. Figure 8 As shown in , in this embodiment, when the processor 110 recovers to the normal state ( t2 ), the hold signal RS may be switched to a low level.

[0122] Meanwhile, as described above, when the operating state of the processor 110 is in the reset state, the hold signal RS of the present disclosure may be set to have a signal level corresponding to the basic control signal CS output by the processor 110 in the normal state immediately before the reset state.

[0123] According to this embodiment, if the relay 200 is in the disconnected (off) state before the reset state (in the normal state), the relay 200 can be controlled to remain in the disconnected state even in the reset state, and if the relay 200 is in the closed (on) state before the reset state (in the normal state), the relay 200 can be controlled to remain in the closed state even in the reset state, so that the state of the relay 200 can be maintained the same as the normal state immediately before the reset state, thereby having the advantage of maintaining operational consistency.

[0124] Figure 6 is a flowchart illustrating a processing procedure according to yet another embodiment of the present disclosure. Figure 9 and Figure 10 Supplementary explanation Figure 6 FIG. 2 is a diagram of a signal system of an embodiment shown in FIG.

[0125] Figure 6 The process shown in FIG. 1 assumes that the processor 110 is in a reset state, and the processor 110 and the monitoring unit 120 output the first switching control signal DS1 and the second switching control signal DS2, that is, the first decision control signal DS1 and the second decision control signal DS2 indicating that the processor 110 is in a reset state.

[0126] When the monitoring unit 120 generates a high-level hold signal RS (S600), the hold signal RS is output to the relay state determination unit 130 (S610). The relay state determination unit 130 then outputs the relay control signal RCS, which is determined to be the hold signal RS based on the switching control signal DS (S620), to the relay 200 (S630).

[0127] Through this process, the relay 200 of the present disclosure is controlled to be in the on state ( S640 ).

[0128] If the processor 110 has not returned to a normal state after time t1, the decision control signal DS continues to maintain a low level (the first signal level), and thus the relay control signal RCS does not switch. In other words, after time t1, the relay control signal RCS is output based on the high level of the hold signal RS, and thus the relay 200 remains in the on state.

[0129] like Figure 9 As shown in , when the reset state continues for a reference time (Δt) based on a time point (t1) at which the processor 110 is in the reset state (S650, S600), the monitoring unit 120 of the present disclosure outputs the hold signal RS at the second signal level (high level) during the reference time (Δt), but after the reference time (after t3), the signal level of the hold signal RS becomes the first signal level (low level) (S660).

[0130] In this manner, when the hold signal RS, which has been switched to the low level after the reference time (Δt) has elapsed based on t1, is output to the relay state determining unit 130 (S670), the relay state determining unit 130 outputs the hold signal RS as the relay control signal RCS (S680, S685).

[0131] When the relay control signal RCS based on the low level is output to the relay 200 in this manner, the relay 200 is controlled to be turned off ( S690 ).

[0132] According to this embodiment of the present disclosure, if the processor 110 has not returned to a normal state even after the reference time has passed, the relay 200 can be turned off, thereby preventing unnecessary energy waste. In addition, since the failure of the processor 110 to return to a normal state in the medium to long term may indicate the possibility that an actual fatal error or defect has occurred, the embodiments of the present disclosure can prevent safety accidents and the like in advance.

[0133] Figure 10 is a diagram showing an example of a signal system generated or output when the relays 200 to be controlled are the first relay 210 and the second relay 220, and is similar to Figure 9 The signal systems shown in are basically the same.

[0134] Figure 10 A portion D shown in φ represents a signal delay occurring during a process in which the processor 110 transitions from the normal state to the reset state. Figures 7 to 9 This part is omitted.

[0135] Figure 10 The first output signal Q1 and the second output signal Q2 shown in FIG are signal values outputted in combination with the signal switching output of the decision control signal DS, and are the same as when the relay state determination unit 130 of the present disclosure is as shown in FIG. Figure 2 and Figure 3 , corresponds to a signal output from the flip-flop 131 when the configuration shown in is to include the flip-flop 131. A description thereof will be given later.

[0136] At the same time, the monitoring unit 120 of the present disclosure can be configured to output a switching control signal using the results of at least one of software monitoring and hardware monitoring, wherein the software monitoring uses feedback information for the request to determine the current state of the processor 110, and the hardware monitoring uses whether a trigger signal is received to determine the current state of the processor 110.

[0137] As described above, the monitoring unit 120 of the present disclosure is configured to output the second switching control signal DS2 , which is a second decision control signal DS2 indicating that the operating state of the processor 110 is not a normal state, ie, a reset state.

[0138] As described above, the switching control signal DS corresponds to an important parameter signal that determines a signal determined as the relay control signal RCS in the relay state determination unit 130 .

[0139] Therefore, in order to more accurately monitor the operating state of the processor 110, it is desirable that the monitoring unit 120 of the present disclosure is configured to output the switching control signal DS only when both the software monitoring (S / W) of determining the current operating state of the processor 110 and the hardware monitoring (H / W) using the receipt of the trigger signal fail.

[0140] Software monitoring can be applied by methods such as sending a request (inquiry, etc.) within a certain period of time through a WDT (window watchdog) and checking whether a corresponding feedback (answer, etc.) is received, and hardware monitoring can be applied by methods such as allocating one or more lines or channels and checking whether a specific signal is triggered normally.

[0141] In the following, reference Figure 2 and Figure 3, a specific embodiment of the relay state determining unit 130 as a component of the relay control device 100 according to the present disclosure will be described.

[0142] like Figure 2 and Figure 3 As shown in , the relay state determining unit 130 of the present disclosure may be configured to include a trigger 131 , a buffer unit 132 , and a first gate unit 134 .

[0143] The flip-flop 131 is a logic circuit capable of storing and maintaining 1 bit of information. Depending on the embodiment, Figure 3 The flip-flop 131 shown in FIG. 1 may be implemented as a D flip-flop, an RS flip-flop, a JK flip-flop, or a T flip-flop.

[0144] The flip-flop 131 may have a data terminal D to which the second basic control signal CS2 is input and a clock terminal C to which the decision control signal DS is input as input terminals, and may include a first output terminal Q and a second output terminal Q′.

[0145] The first output signal Q1 output from the first output terminal Q is determined by the signal levels of the second basic control signal CS2 and the decision control signal DS, which are signals input to the flip-flop 131, and the second output signal Q2 output from the second output terminal Q′ can be designed to have a signal level (a first signal level and a second signal level) opposite to that of the first output signal Q1.

[0146] The first gate unit 134 of the present disclosure is configured to output a decision control signal DS. If the first decision control signal DS1 is input from the processor 110 and the second decision control signal DS2 is input from the monitoring unit 120, the first gate unit 134 calculates these and outputs the decision control signal DS. As described above, the first gate unit 134 can be implemented by an AND gate or a combination of an AND gate and a NOT gate.

[0147] As a specific example, when the decision control signal DS is switched from a high level to a low level by the internal design of the flip-flop 131, the first output signal Q1 can be configured to switch from a low level to a high level in conjunction therewith. At this time, since the second output signal Q2 is designed to have an opposite level to the first output signal Q1, the second output signal Q2 becomes a low-level signal.

[0148] The buffer unit 132 receives the first and second basic control signals CS1 and CS2 from the processor 110 , receives the first and second output signals Q1 and Q2 from the flip-flop 131 , and receives the hold signal RS from the monitoring unit 120 .

[0149] The buffer unit 132 is configured to output the first relay control signal RCS1 and the second relay control signal RCS2 , which are signals that ultimately control the on / off of the first relay 210 and the second relay 220 , to the first relay 210 and the second relay 220 by implementing the circuit architecture of the technical idea of the present disclosure described above.

[0150] More specifically, the buffer unit 132 may include a plurality of buffers, one of which, ie, the first buffer, may be configured to receive the hold signal RS and the first output signal Q1 and determine whether to output the hold signal RS based on the signal level of the first output signal Q1.

[0151] For example, when the signal level of the first output signal Q1 is the second signal level (high level), the hold signal RS can be output through the first buffer, and when the signal level of the first output signal Q1 is the first signal level (low level), the hold signal RS can be designed not to be output.

[0152] Among the plurality of buffers, the second buffer may be designed to receive the first basic control signal CS1 and the second output signal Q2 and determine whether to output the first basic control signal CS1 based on a signal level of the second output signal Q2.

[0153] For example, when the signal level of the second output signal Q2 is the second signal level (high level), the first basic control signal CS1 can be output through the second buffer, and when the signal level of the second output signal Q2 is the first signal level (low level), the first basic control signal CS1 can be designed not to be output.

[0154] Furthermore, the output channels (lines) of the first buffer and the output channels (lines) of the second buffer may be configured to be integrated with each other. In this case, since the first and second buffers receive the first output signal Q1 and the second output signal Q2, respectively, which have opposite signal levels as described above, when the hold signal RS is output from the first buffer, the first basic control signal CS1 may not be output from the second buffer.

[0155] As described above, outputting the hold signal RS from the first buffer means that the signal level of the first output signal Q1 input to the first buffer is the second signal level (high level), and the second output signal Q2 input to the second buffer is a low-level signal, which is the opposite level to the first output signal Q1. Since the low-level second output signal Q2 is input to the second buffer in this manner, the first basic control signal CS1 is not output from the second buffer.

[0156] Therefore, depending on the signal levels of the first output signal Q1 and the second output signal Q2, one of the first basic control signal CS1 and the holding signal RS may be output as the first relay control signal RCS1 through the buffer unit 132. As described above, the first output signal Q1 and the second output signal Q2 are based on the first decision control signal DS1 and the second decision control signal DS2 output by the processor 110 and the monitoring unit 120, and the first decision control signal DS1 and the second decision control signal DS2 are based on the operating state of the processor 110.

[0157] Therefore, the relay control device 100 of the present disclosure ultimately controls the on / off of the first relay 210 by "monitoring the operating status and self-decision of the processor 110, outputting the first decision control signal DS1 and the second decision control signal DS2 according to the monitoring results, outputting the first output signal Q1 and / or the second output signal Q2, determining one of the first basic control signal CS1 and the holding signal RS, and outputting the determined signal as the first relay control signal RCS1".

[0158] In this manner, the relay control device 100 according to the present disclosure can output the first relay control signal RCS1 that controls the first relay 210 as a dual signal system that differs according to the operation state by accurately reflecting the operation state of the processor 110 .

[0159] The second relay control signal RCS2, which ultimately controls the second relay 220, can also be output by selecting one of the second basic control signal CS2 or the hold signal RS through a plurality of buffers (e.g., a third buffer, a fourth buffer, etc.) implementing the above-described technical configuration. Since the contents of the third and fourth buffers correspond to the first and second buffers described above, their detailed descriptions are omitted.

[0160] According to one embodiment, the relay state determination unit 130 of the present disclosure may further include a second gate unit 133 that mediates between at least one of the first relay 210 and the second relay 220 and the buffer unit 132, such as Figure 3 As shown in . Figure 3 An example is shown in which the second gate unit 133 is provided between the buffer unit 132 and the second relay 220 .

[0161] The second gate unit 133 may be designed to receive the third relay control signal RCS3 from the buffer unit 132 , receive the hold signal RS from the monitoring unit 120 , and output the second relay control signal RCS2 to the second relay 220 based on signal levels of the third relay control signal RCS3 and the hold signal RS.

[0162] As described in the previous embodiment, when the operating state of the processor 110 is the reset state, the hold signal RS may be output from the fourth buffer of the buffer unit 132 , and thus the third relay control signal RCS3 may be the hold signal RS output from the fourth buffer.

[0163] Therefore, since the gate unit receives the hold signal RS output from each of the buffer unit 132 and the monitoring unit 120, if the gate unit is implemented as an AND gate, the gate unit 133 is configured to output a high-level signal only when both received signals are high, thereby further improving the accuracy of the signal system.

[0164] The relay control device 100 according to the present disclosure can be applied to a BMS (Battery Management System). Specifically, the BMS according to the present disclosure can include the relay control device 100 described above. In this configuration, at least some of the components of the relay control device 100 can be implemented by supplementing or adding functionality to components included in a conventional BMS. For example, the processor 110, monitoring unit 120, and relay state determination unit 130 of the relay control device 100 can be implemented as components of the BMS.

[0165] Furthermore, the relay control device 100 according to the present disclosure may be provided in a battery pack. That is, the battery pack according to the present disclosure may include the relay control device 100 and at least one battery cell. Furthermore, the battery pack may further include electrical equipment (relays, fuses, etc.) and a housing.

[0166] Furthermore, the relay control device 100 according to the present disclosure can be provided to a vehicle. Thus, the relay control device 100 can control the relay so that the relay connecting the battery and the vehicle does not disconnect but remains closed even when the processor 110 is reset due to a system error while the vehicle is traveling.

[0167] The present disclosure has been described in detail. However, it should be understood that although the detailed description and specific examples indicate preferred embodiments of the present disclosure, they are given by way of illustration only, as various changes and modifications within the scope of the present disclosure will become apparent to those skilled in the art from this detailed description.

[0168] The accompanying drawings and the like used to explain the present disclosure and illustrate examples thereof may be shown in a somewhat exaggerated form in order to emphasize or highlight the technical content of the present disclosure. However, it should be understood that various modified examples are possible for those skilled in the art by considering the previously described contents and the matters shown in the accompanying drawings.

[0169] Furthermore, it goes without saying that expressions such as first, second, upper, lower, or top and bottom in the explanation of the present disclosure are merely tool-concept terms for distinguishing components (elements) relatively from each other, and are not terms for indicating a specific order, priority, etc., nor are they terms for physically distinguishing each component (element) on an absolute basis.

[0170] (reference numerals)

[0171] 100: Relay control device

[0172] 110: Processor

[0173] 120: Monitoring unit

[0174] 130: Relay status determination unit

[0175] 131: Trigger

[0176] 132: Buffer unit

[0177] 133: Second door unit

[0178] 134: First door unit

[0179] 200: Relay

[0180] 210: First relay

[0181] 220: Second relay

[0182] CS: basic control signal

[0183] CS1(2): First (second) basic control signal

[0184] DS: Decision control signal

[0185] DS1(2): First (second) decision control signal

[0186] RS: hold signal

[0187] RCS: Relay control signal

[0188] RCS1(2): First (second) relay control signal

[0189] Q1(2): First (second) output signal

Claims

1. A relay control device comprising: a processor configured to output a basic control signal for controlling an operation of the relay and a first decision control signal having a differential signal level according to an operation state of the processor; a monitoring unit configured to monitor an operating state of the processor and output a second decision control signal having a differential signal level according to the operating state of the processor and a holding signal for maintaining the operating state of the relay; as well as A relay state determining unit is configured to output one of the basic control signal and the holding signal as a relay control signal for controlling on / off of the relay based on the signal levels of the first decision control signal and the second decision control signal.

2. The relay control device according to claim 1, in, The relay state determination unit is configured to output one of the basic control signal and the holding signal as the relay control signal based on a signal level of a result signal of calculating the first decision control signal and the second decision control signal.

3. The relay control device according to claim 1, in, When the operating state of the processor is a reset state, the processor is configured to output a first switching control signal to the relay state determination unit, the first switching control signal being a first decision control signal having a signal level different from the first decision control signal output when the processor is in a normal state, and Wherein, when the operating state of the processor is the reset state, the monitoring unit is configured to output a second switching control signal to the relay state determination unit, and the second switching control signal is a second decision control signal having a signal level different from the second decision control signal output when the processor is in the normal state.

4. The relay control device according to claim 3, in, The monitoring unit is configured to output the second switching control signal only when both software monitoring using feedback information for the request and hardware monitoring using receipt of the trigger signal fail.

5. The relay control device according to claim 3, in, The relay state determination unit is configured to output the basic control signal as the relay control signal when neither the first switching control signal nor the second switching control signal is received, and to output the holding signal as the relay control signal when both the first switching control signal and the second switching control signal are received.

6. The relay control device according to claim 1, in, When the operation state of the processor is a reset state, the monitoring unit is configured to output the hold signal having a signal level corresponding to the basic control signal output by the processor in a normal state immediately before the reset state.

7. The relay control device according to claim 1, in, The monitoring unit is configured to output the hold signal at a second signal level when the reset state of the processor continues for a reference time, and output the hold signal at a first signal level after the reference time. 8 . A battery pack comprising the relay control device according to claim 1 . 9 . A vehicle comprising the relay control device according to claim 1 .

10. A relay control method, comprising: a basic signal receiving step for receiving a basic control signal for controlling the operation of the relay and a first decision control signal having a differential signal level according to an operation state of the processor; a control signal receiving step for receiving a second decision control signal having a differential signal level according to the operating state of the processor and a holding signal for maintaining the operating state of the relay; as well as A control signal outputting step of outputting one of the basic control signal and the holding signal as a relay control signal for controlling on / off of the relay based on the signal levels of the first decision control signal and the second decision control signal.

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