Multi-resonant oscillator / clock

Abstract

A clock device includes: an LC network including: a first inductive portion; a second inductive portion connected to the first inductive portion; a third inductive portion connected to the second inductive portion; a first capacitive portion connected to the first, second, and third inductive portions; and a second capacitive portion connected to the first inductive portion and the third inductive portion, where the LC network is configured to resonate at a first frequency and a second frequency substantially three times the first frequency simultaneously, and wherein a clock signal is provided between the first inductive portion and the third inductive portion by combining a first signal component and a second signal component, the second signal component being a third harmonic of the first signal component, and each inflection point of the first signal component is phase aligned with a corresponding inflection point of the second signal component.

Description

Technical Field

[0001] The present disclosure generally relates to oscillators and clocks on integrated circuit (IC) devices, such as complementary metal oxide semiconductor (CMOS) devices. Background Art

[0002] The clock signal generated by a conventional LC oscillator is generally a sine wave, ie, a single tone and a continuous waveform. For example, an IC device may include an LC tank coupled to a back-to-back CMOS inverter configuration to provide a sine wave clock signal. Summary of the Invention

[0003] In one aspect, some implementations provide a clock device for generating a clock signal, the clock device comprising: an LC network comprising: a first inductive portion comprising a first terminal and a second terminal; a second inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the second inductive portion is connected to the second terminal of the first inductive portion; a third inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the third inductive portion is connected to the second terminal of the second inductive portion; a first capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the first capacitive portion is connected to the second terminal of the first inductive portion and the first terminal of the second inductive portion, and wherein the second terminal of the first capacitive portion is connected to the second terminal of the second inductive portion and a first terminal of the third inductive portion; and a second capacitive portion including a first terminal and a second terminal, wherein the first terminal of the second capacitive portion is connected to the first terminal of the first inductive portion, and wherein the second terminal of the second capacitive portion is connected to the second terminal of the third inductive portion, wherein the LC network is configured to resonate simultaneously at a first resonant frequency and a second resonant frequency that is substantially three times the first resonant frequency, and wherein a clock signal is provided between the first terminal of the first inductive portion and the second terminal of the third inductive portion by a combination of a first resonant signal component and a second resonant signal component, the second resonant signal component being a third harmonic of the first resonant signal component, and each inflection point of the first resonant signal component is phase-aligned with a corresponding inflection point of the second resonant signal component.

[0004] Implementations may include one or more of the following features.

[0005] Each inflection point of the resonant signal at the first frequency may coincide with a corresponding inflection point of the resonant signal at the second frequency. The clock signal may have a waveform that is more trapezoidal than the resonant signal component at the first frequency and the resonant signal component at the second frequency. The first inductive portion may be characterized by an inductance Ls / 2. The third inductive portion may also be characterized by an inductance Ls / 2. The second inductive portion may be characterized by an inductance Lp. The first capacitive portion may be characterized by a capacitance Cp. The second capacitive portion may be characterized by a capacitance Cs. When the clock device is tuned within a certain frequency range, the ratio Cp / Cs may be substantially fixed. Cp and Cs may be variable so that the first frequency is adjustable within the frequency range while the second frequency remains three times the first frequency.

[0006] The first inductive component can be characterized by an inductance of Ls / 2. The third inductive component can also be characterized by an inductance of Ls / 2. The second inductive component can be characterized by an inductance of Lp. The first capacitive component can be characterized by a capacitance of Cp. The second capacitive component can be characterized by a capacitance of Cs. The first frequency can be characterized by:

[0007] .

[0008] The second frequency can be characterized by:

[0009] .

[0010] The clock device may further include a gain stage configured to amplify the resonant signal at the first frequency and the resonant signal at the second frequency when generating the clock signal. The gain stage may include a complementary metal oxide semiconductor (CMOS) amplifier. The gain stage may include a first pair of complementary transistors and a second pair of complementary transistors. The output nodes of the first pair of complementary transistors may be AC-coupled to the input gates of the second pair of complementary transistors, respectively. The output nodes of the second pair of complementary transistors may be AC-coupled to the input gates of the first pair of complementary transistors, respectively. The input gates of the first pair of complementary transistors may be arranged to receive corresponding bias voltages. The input gates of the second pair of complementary transistors may also be arranged to receive corresponding bias voltages.

[0011] A first terminal of the first inductive portion may be coupled to a first chip capacitor load. A second terminal of the third inductive portion may be coupled to a second chip capacitor load. The first chip capacitor load and the second chip capacitor load may be coupled to a semiconductor chip or a subcomponent thereof. The semiconductor chip may include a CMOS system-on-chip (SOC) device.

[0012] The clock device may include an inductive coil having four taps. The first inductive portion may include a first tap and a second tap of the inductive coil. The second inductive portion may include a second tap and a third tap of the inductive coil. The third inductive portion may include a third tap and a fourth tap of the inductive coil.

[0013] The first inductive portion may include a first set of winding loops surrounding a first region. The third inductive portion may include a third set of winding loops surrounding a third region. The second inductive portion may include a second set of winding loops surrounding a second region. The surface areas of the first region and the third region may be substantially the same. The electromagnetic effect of the first set of windings on the second set of windings and the electromagnetic effect of the third set of windings on the second set of windings may substantially cancel each other out. The mutual inductive coupling between the first set of winding loops and the second set of winding loops and the mutual inductive coupling between the second set of winding loops and the third set of winding loops may be substantially the same in magnitude but opposite in sign. The first set of winding loops may be wound in one of the following directions: clockwise or counterclockwise, and the third set of winding loops may be wound in the other of the following directions: clockwise or counterclockwise, relative to the flow of interconnecting current from the first set of winding loops through the second set of winding loops to the third set of winding loops. When a resonant signal component at a first frequency flows within the second group of winding loops, the resonant signal component at the first frequency may magnetically induce corresponding currents in the first group of winding loops and the third group of winding loops, the currents flowing in opposite directions and having substantially the same amplitude, relative to the flow of interconnected current from the first group of winding loops through the second group of winding loops to the third group of winding loops. When a resonant signal component at a second frequency flows within the first group of winding loops and the third group of winding loops, the resonant signal component flowing in the first group of winding loops and the resonant signal component flowing in the third group of winding loops may each magnetically induce, in the second group of winding loops, corresponding currents flowing in opposite directions and having substantially the same amplitude, in the third group of winding loops.

[0014] The first capacitive portion may include: at least one capacitor bank having two capacitors of substantially the same capacitance, the two capacitors being symmetrically arranged such that one terminal of each of the two capacitors is grounded, and the other terminal of each of the two capacitors is connected to the first terminal and the second terminal of the first capacitive portion, respectively, wherein the at least one capacitor bank includes at least one switchable capacitor. The first capacitive portion may further include: a voltage-controlled capacitor.

[0015] The second capacitive portion may include: at least one capacitor bank having two capacitors of substantially the same capacitance, the two capacitors being symmetrically arranged such that one terminal of each of the two capacitors is grounded, and the other terminal of each of the two capacitors is connected to the first terminal and the second terminal of the second capacitive portion, respectively, wherein the at least one capacitor bank includes at least one switchable capacitor. The second capacitive portion may further include: a voltage-controlled capacitor.

[0016] In another aspect, an implementation may provide a clock device for generating a clock signal, the clock device comprising: an LC network comprising: a first inductive portion comprising a first terminal and a second terminal; a second inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the second inductive portion is connected to the second terminal of the first inductive portion; a third inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the third inductive portion is connected to the second terminal of the second inductive portion; a first capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the first capacitive portion is connected to the second terminal of the first inductive portion and the first terminal of the second inductive portion, and wherein the second terminal of the first capacitive portion is connected to the second terminal of the second inductive portion a first terminal of the second capacitive portion and a first terminal of the third inductive portion; and a second capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the second capacitive portion is connected to the first terminal of the first inductive portion, and wherein the second terminal of the second capacitive portion is connected to the second terminal of the third inductive portion, wherein the first inductive portion is characterized by an inductance Ls / 2, wherein the second inductive portion is characterized by an inductance Lp, wherein the third inductive portion is characterized by an inductance Ls / 2, wherein the first capacitive portion is characterized by a capacitance Cp, wherein the second capacitive portion is characterized by a capacitance Cs, wherein the LC network is configured to resonate simultaneously at a first frequency and at a second frequency that is three times the first frequency, wherein the ratio Cp / Cs is substantially fixed when the clock device is tuned within a certain frequency range.

[0017] In yet another aspect, an implementation provides a clock device for generating a clock signal, the clock device comprising: an LC network comprising: a first inductive portion comprising a first terminal and a second terminal; a second inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the second inductive portion is connected to the second terminal of the first inductive portion; a third inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the third inductive portion is connected to the second terminal of the second inductive portion; a first capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the first capacitive portion is connected to the second terminal of the first inductive portion and the first terminal of the second inductive portion, and wherein the third inductive portion comprises ... a capacitive portion having a second terminal connected to the second terminal of the second inductive portion and the first terminal of the third inductive portion; and a second capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the second capacitive portion is connected to the first terminal of the first inductive portion, and wherein the second terminal of the second capacitive portion is connected to the second terminal of the third inductive portion, wherein the first inductive portion is characterized by an inductance Ls / 2, wherein the second inductive portion is characterized by an inductance Lp, wherein the third inductive portion is characterized by an inductance Ls / 2, wherein the first capacitive portion is characterized by a capacitance Cp, wherein the second capacitive portion is characterized by a capacitance Cs, wherein a first resonant frequency of the LC network is characterized by:

[0018] ,

[0019] The second resonant frequency of the LC network is characterized by:

[0020] ,and

[0021] The second resonant frequency is substantially three times the first resonant frequency.

[0022] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other aspects, features, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A An example of an equivalent circuit of a multi-resonance network according to some implementations of the present disclosure is illustrated.

[0024] Figure 1B Pictured Figure 1A Simplified approximate equivalent circuit of a multi-resonant network operating at the fundamental frequency.

[0025] Figure 1C Pictured Figure 1A Simplified approximate equivalent circuit of a multi-resonant network operating at the third harmonic frequency.

[0026] Figure 1D Pictured Figure 1A Example of the expected ideal waveform for a multi-resonant network.

[0027] Figure 2A Another example of an equivalent circuit of a multi-resonant network according to some implementations of the present disclosure is shown.

[0028] Figure 2B Shown Figure 2A Example of a gain stage of a multi-resonant network.

[0029] Figure 2C Shown Figure 2A Example of simulated AC impedance (in ohms) of a multi-resonant network as a function of frequency (in MHz).

[0030] Figure 2D Shown from Figure 2A Example of a simulated time-domain waveform obtained with a multiresonant network.

[0031] Figure 2E Shown from Figure 2A Additional examples of simulated time-domain waveforms obtained with a multi-resonant network.

[0032] Figure 2F and2G Shown from Figure 2A Example of a frequency domain spectrum obtained from a time domain simulation of a multiresonant network.

[0033] Figure 3A Yet another example of an equivalent circuit of a multi-resonance network according to some implementations of the present disclosure is shown.

[0034] Figure 3B 、 3C , 3D and 3E show the Figure 3A Examples of simulated waveforms and spectra obtained with a multiresonant network.

[0035] Figure 4 Yet another example of an equivalent circuit of a multi-resonance network according to some implementations of the present disclosure is shown.

[0036] Figure 5A and 5B An example of a physical inductor layout of a multi-resonant network according to some implementations of the present disclosure is shown.

[0037] Like reference numerals in the various drawings indicate like components. DETAILED DESCRIPTION

[0038] Clock signals provided by conventional LC resonant tank circuits are typically sinusoidal and limited in amplitude. However, when driving complementary metal oxide semiconductor (CMOS) flip-flops and clock loads in large CMOS system-on-chip (SoCs), the sinusoidal signal typically requires sharpening (i.e., modification with an increased slew rate for faster rising and falling edges), amplification, and re-buffering to provide an adequate drive-to-load ratio. Current practices typically incorporate multiple stages and groups of logic gates, inverters, level shifters, and other limiting amplifiers to convert the sinusoidal signal into a more trapezoidal waveform for logic operations. Each stage introduces a delay, including deterministic and random jitter due to power supply and device noise. Each stage may also require drive current and, therefore, introduce additional power losses. Distributed trees, such as multi-stage and branched H-trees, may involve repeaters, further exacerbating undesirable power consumption. Furthermore, when conventional LC resonant tank circuits are employed in phase-locked loop (PLL) oscillator stages, the limited amplitude and slew rate negatively impact their phase noise performance, in addition to the need for further amplification and buffering.

[0039] Implementations of the present disclosure can utilize a multi-tone LC network configuration on a clock device to provide a rail-to-rail (i.e., power supply voltage to ground voltage) drive signal with a substantially trapezoidal waveform to each endpoint (e.g., node or terminal) on a large CMOS SoC or its subcomponents. The implementation can reduce or eliminate clock delay / skew / jitter overhead and significantly reduce power loss. Both overhead and loss have plagued current practices for quite some time. The clock device can use power more efficiently, for example, by employing harmonic resonance directly on the capacitive clock load, thereby recycling charge between the capacitive load and the reactive elements in the multi-tone LC network configuration. The current originating from the gain stage is reduced to 1 / Q of its non-resonant counterpart, where Q is the ratio of energy stored to energy lost at a given power supply voltage, and is the ratio of the capacitive or inductive reactance at resonance to the loss resistance in the path of the LC network.

[0040] More specifically, through the proper configuration of the coupled LC elements of a multi-tone LC network, various clock devices can simultaneously resonate at the fundamental frequency (f0) and the third harmonic (i.e., 3f0), thereby concurrently generating the fundamental frequency (f0) and the third harmonic (e.g., 3f0). Furthermore, when the LC network is coupled to a gain stage, the fundamental frequency (f0) signal and the third harmonic signal are summed and phase-aligned because the 0° and 180° transition edges of the fundamental signal coincide with a subset of the 0° and 180° transition edges of the third harmonic signal. Consequently, the harmonic summation provides a time-domain waveform with a substantially trapezoidal shape. Generally speaking, the waveform can resemble a buffered CMOS gate output curve. Examples may include a plateau appearance with a rising phase that tracks, for example, an S-shaped function rather than a sine function. For example, when provided with a suitable CMOS-level gain stage (such as a back-to-back inverter or its gate-biased derivative), the combined signal is more suitable for directly driving CMOS-level downstream logic devices. Specifically, the result eliminates the need for additional components for generating a trapezoidal waveform. As a result, the generated signal can be used directly by downstream logic devices, i.e., without requiring additional slew rate modification via other components. Consequently, the described implementation can replace a large clock tree with one or more networks of directly driven multi-tone resonant capacitive loads. In some implementations, multiple distributed instances of the clock device can be connected via low-impedance conductive routing, eliminating the need for intermediate repeaters and amplifiers.

[0041] Figure 1AAn example of a simplified equivalent circuit 100 for a multi-resonant network according to some implementations of the present disclosure is shown. As explained in more detail below, the multi-resonant network oscillates simultaneously at the fundamental frequency f1 and the third harmonic f3, with the amplitude of the latter significantly scaled down relative to the amplitude of the former. The multi-resonant network can obtain a high slew rate full voltage range waveform at the input of the network. By adjusting the capacitor and inductor elements, the implementation can tune the multi-resonant network to achieve frequency and performance targets. In addition to the LC resonant tank circuit including inductive sections 101, 102, 104 and capacitive sections 103 and 105 (described below), the equivalent circuit also includes nodes oscp and oscn representing the input nodes of the amplifier side, and nodes intp and intn representing internal nodes.

[0042] As shown, the equivalent circuit 100 includes a first inductive portion 101, a second inductive portion 102, and a third inductive portion 104. The first inductive portion 101 and the third inductive portion 104 are both characterized by an inductance of Ls / 2. The second inductive portion 102 is characterized by an inductance of Lp. Each inductive portion can be an inductor. In some cases, the three inductive portions are implemented as, for example, a 4-tap inductive coil defined by a total of four nodes (i.e., oscp, oscn, intp, intn), as shown in FIG. Figure 1A For example, each inductive portion can also be implemented by winding one or more loops of an inductive loop coil, as described below in conjunction with Figure 5A Each loop of the inductive loop coil can be a complete loop, such as Figure 5A As shown, it can also be a partially complete loop, such as for example Figure 5B The arc shown.

[0043] The equivalent circuit 100 additionally includes a first capacitive portion 103 and a second capacitive portion 105. Implementations may include using the first capacitive portion 103 as a capacitor bank, such as two symmetrically arranged capacitors of identical capacitance, with one terminal of each capacitor connected to ground and the other terminal of each capacitor connected to one terminal of the first capacitive portion 103. In this arrangement, the capacitance of each of the two independent capacitors is twice the equivalent capacitance (e.g., Cs as shown). The second capacitive portion 105 may similarly be implemented as a capacitor bank, such as two symmetrically arranged capacitors of identical capacitance. Other examples may incorporate more than two symmetrically arranged capacitors.

[0044] The desired response of the multiresonant network can be expressed in the s-domain using the fundamental frequency F(s) and the third harmonic H(s) as follows:

[0045]

[0046] When operating in parallel resonance, observe the Z of this multi-resonant network. in The impedance should approach infinity twice: once at the desired fundamental frequency, and once at its third harmonic. in When the s-domain denominator of (s) is set to zero, the resulting function should conform to the form shown in Equation 1 above. The details of such a network are shown below.

[0047] about Figure 1A For a multi-resonance example, the circuit’s s-domain input impedance can be expressed as:

[0048]

[0049] In parallel resonance, Z in Close to infinity.

[0050]

[0051] Based on the above, the resonant frequency can be derived as a function of the component values. For example, f can be solved using a complex quadratic radical as shown below (note that s = j𝜔 = j2πf).

[0052]

[0053] In Equation 2 above, two solutions are generated from the above "±", representing each of the two poles. Without loss of generality, the two solutions, namely the resonant frequencies f1 and f2, can be expressed as:

[0054] ,and

[0055] .

[0056] As discussed above, the design goal is to place one pole pair at the fundamental frequency and another pole pair at the third harmonic. While the above solution captures a direct and comprehensive relationship, some implementations may use the following approximation to make initial component selections by examining the boundary conditions of the multiresonant network.

[0057] For ease of explanation, these implementations may define f3 as the third harmonic of f1, i.e.,

[0058]

[0059] In an ideal circuit, the resonant frequency f2 will be exactly equal to the third harmonic frequency f3, that is,

[0060]

[0061] However, as long as f2 ≈ f3, for example, f2 = f3 + / - 10%, the circuit will still operate satisfactorily. This is because the circuit has only one gain unit, applied simultaneously to both f1 and f3 coupled within the network. Since the AC gain of the single amplifier is applied to the knee point, any other oscillation mode will not survive, and each cycle will be forced to a 3:1 ratio: the output of the circuit must be the sum of f1 and f3. However, if the peaks of f1 and f2 do not differ by exactly 3 times, the balance will settle on the non-peak portion of the impedance function (which will be discussed below in conjunction with Figure 2C further discussion), thereby affecting the amplitude of the third harmonic frequency f3 in the output signal relative to the amplitude of the fundamental frequency f1.

[0062] At the fundamental frequency f1, the series Ls is effectively short-circuited, as Figure 1B As shown in the figure. Figure 1B In the figure,

[0063] .

[0064] At the third harmonic frequency f3, the parallel Cp is effectively short-circuited, as shown in Figure 1C As shown in the figure. Figure 1C In Figure 120,

[0065] .

[0066] Solving equations for f1 and f3 simultaneously yields,

[0067] ,

[0068] where k is a heuristic value comprising the ratio of the amplitude of the resonant signal component at the fundamental frequency to the amplitude of the resonant signal at the third harmonic frequency.

[0069] The above equations reveal that, when the inductance values of the two inductor components are given and fixed, it is expected that Cp / Cs will generally follow a fixed capacitance ratio governed by the above formula. For example, if a switched capacitor is used to change the frequency of a digitally controlled oscillator (DCO) in a phase-controlled loop (PLL) implementation, it is expected that the "switched-on" capacitor will follow this Cp / Cs (capacitance) ratio for various settings. As another example, if a voltage-controlled capacitor is used to change the frequency of a voltage-controlled oscillator (VCO) in a PLL, it is also expected that the voltage-controlled capacitor will follow this capacitance ratio for various settings. In these examples, capacitance Cp and capacitance Cs can be adjusted to tune the fundamental frequency f1 and the resonant frequency f2 so that the multi-resonant network can support a range of operating frequencies. Tuning involves, for example, cooperatively adjusting capacitance Cp and capacitance Cs to accommodate the frequency range and to compensate for process, voltage, and temperature variations across different chips and operating conditions. However, the capacitance ratio (i.e., Cp / Cs) remains substantially unchanged before, during, and after tuning. In other words, the capacitance ratio Cp / Cs is substantially fixed.

[0070] Figure 1D Figure 1 shows an example of ideal waveforms when sinusoids of frequencies f1 and f3 are added and subtracted at the same amplitude ratio of the sinusoid of frequency f1 to the sinusoid of frequency f3. Here, the sinusoid of frequency f1 has phase positions of 0° and 180° (indicated by the vertical dashed lines), corresponding to the inflection points or nodes of the sinusoid. Each of these phase positions of the f1 signal coincides with a position of the f3 signal having the same phase, as shown in Figure 1. Figure 1D As shown. In this disclosure, this coincident phase position between the inflection point of the f1 signal and the matching inflection point of the f3 signal is also referred to as phase alignment. As shown, the f3 signal has more inflection points than the f1 signal. Not all inflection points of the f3 signal are phase aligned with the f1 signal, as some inflection points of the f3 signal do not coincide with any inflection points of the f1 signal.

[0071] In FIG130, a trace 131 shows an example of a waveform of a resonant signal at a fundamental frequency (i.e., a sine wave at f1 in this example). A trace 132 shows an example of a waveform of a resonant signal at a third harmonic frequency (i.e., a sine wave at f3 in this example). A trace 133 shows an example of a waveform of a resonant signal at a third harmonic frequency (i.e., a sine wave at f3 in this example). Figure 1A The expected summing waveform (resulting from the fundamental frequency + (k*3rd harmonic)) at the input of the multi-resonant network (i.e., between oscp and oscn) is shown in FIG. Figure 1A The expected subtraction waveform (i.e., fundamental frequency - (k*third harmonic)) at the internal node of the multi-resonant network (i.e., between intp and intn).

[0072] In general, the resulting summed waveform can produce faster transition times, for example, the rise time of the resulting waveform is measured from 10% to 90% of the full amplitude relative to a sine wave. The rise time improvement relative to a sine wave can also be measured as a rise time from 20% to 80% of the full amplitude. This improvement allows the implementation to resonate large clock loads, thereby saving power. The improved rise time also has the practical advantage of reducing noise. The implementation can achieve a rise time of 10-90%, which is faster than the rise time of a sine wave (measured as 0.29 / f, where f is the frequency of the signal). In some cases, the rise time can reach, for example, 0.28 / f, or 0.27 / f or less. For example, the rise time can be in the range of 0.22 / f to 0.13 / f.

[0073] In one illustration, trace 133 shows a rise time of 0.167 / f. Figure 2D and 2E In the PLL VCO / DCO implementation schemes in the second to fifth regions of the figure, the 10%-90% rise time can range from about 0.17 / f to about 0.26 / f depending on the process, voltage, temperature, frequency, and electrical configuration. Figure 3B and 3C In the example of a resonant clock load in the upper region of the figure, the 10%-90% rise time can range from approximately 0.13 / f to approximately 0.22 / f, depending on process, voltage, and temperature. The desired rise time improvement for an application can depend on factors such as the RC time constant of the clock tree routing in a specific semiconductor process or the synchronous clock rate of the CMOS load of the multi-resonant network. On the other hand, the actual rise time improvement achieved by the multi-resonant network can depend on many factors, such as the quality factor (Q) of the network and its components, parasitic variations of components within the network path, the gain and linearity of the gain stages, and process / voltage / temperature variations.

[0074] Figure 2A According to some implementations of the present invention, Figure 1A More details are added. As depicted in Figure 200, the multi-resonant network includes inductor 201, inductor 202, and inductor 204. Inductors 201 and 204 are each configured to have an inductance of Ls / 2, while inductor 202 is configured to have an inductance of Lp. In some cases, the three inductors can be implemented as a 4-tap inductive coil. For example, each inductor can also be implemented by winding one or more loops of an inductive loop coil, as described below in conjunction with Figure 5A and 5B Further explanation.

[0075] The multi-resonant network additionally includes capacitors 205I and 205S and capacitors 203B and 203S. In various configurations, capacitors 205S and 203S have switchable capacitance and are therefore adjustable. The implementation may incorporate a capacitor bank for each exemplary capacitor. For example, each exemplary capacitor may be implemented as two or more symmetrically arranged ganged capacitors of the same or different capacitances, each having one terminal connected to ground. Figure 2A In this particular example, Cp / Cs ~ 1.67 and Lp / Ls ~ 1.79.

[0076] As shown in Figure 200, the multi-resonant network can be coupled to a differential nonlinear amplifier, such as gain stage 206, using coupling capacitors 207 and 208. Additionally or alternatively, a non-loop CMOS driver can also be coupled to the multi-resonant network. In any case, the figure provides an example of an oscillator with a square wave waveform, as opposed to a sine wave-like waveform when using a conventional single-pole resonant network. When combined with a low-impedance switch L and / or switch C network, such as when coupled to back-to-back CMOS inverters or the like, a wide-range PLL or multi-range high slew rate high-frequency clock driver can be formed. Using the illustrated multi-resonant network, some implementations can operate without using a long clock tree following the multi-resonant network because the waveform of the clock signal is already trapezoidal and can drive large capacitances, such as the gate load of a large driver stage.

[0077] Figure 2B Pictured Figure 2A The example of a differential gain stage of the gain stage 206 is shown. This gain stage example is configured using gate biased back-to-back inverters. The terminals oscp and oscn representing the differential outputs correspond to Figure 2A2. The same terminals are labeled around gain stage 206. As shown, transistors 211, 212, 213, and 214, along with coupling capacitors 215A, 215B, 215C, 214D, and parallel resistors 216A, 216B, 216C, and 216D, form a differential amplifier. Additionally, transistor pair 217 and 218 generate bias voltages Vbiasp and Vbiasn corresponding to bias currents ibiasp and ibiasn. As shown, the input gates of transistors 211 and 213 are AC-coupled to terminal oscp, which is arranged as an output node on transistors 212 and 214. Similarly, the input gates of transistors 212 and 214 are AC-coupled to terminal oscn, which is arranged as an output node on transistors 211 and 213. In this example of a self-compensating configuration, a crowbar current can track bias currents ibiasp and ibiasn across various process, voltage, and temperature variations. In this example, the shunt impedance and gain can be kept relatively high compared to other implementations that do not use gate biased inverters.

[0078] In various implementations, the multiresonant network can be connected directly to the CMOS gate. This allows the inductor switch to break the loop and enter power-down mode, leaving the node statically at a known CMOS level. Upon power-up, the switch simply reengages. Furthermore, given the initial CMOS voltage at the network's input, no special startup circuitry is required. Furthermore, known chaotic modes may not exist.

[0079] Figures 2C to 2G Shown Figure 2A Various examples of capacitor and inductor configurations for multi-resonant networks. Figure 2C The results of the simulated parallel resonant impedance (vertical axis in ohms) when continuously sweeping between about 11 GHz and about 33 GHz (horizontal axis) using a configurable C with Cp / Cs of about 5 / 3 and Lp / Ls of about 7 / 4 are shown; different curves represent different values of the Cp / Cs ratio. In the simulation, the back-to-back inverter oscillators of the gain stage are turned off (i.e., self-driven). As shown, the multi-resonant behavior is maintained (e.g., the fundamental frequency and the third harmonic are present simultaneously) when the capacitance parameters are changed. The top plot shows the AC impedance of f1 and f3 at the highest gain operating point given as a best-case angle, while the bottom plot shows the worst-case scenario during the simulation.

[0080] For example, Figure 2CThe diagram shows that the resonance peaks of f1 and f3 are not infinitely narrow impulse response functions. Instead, the resonance peaks are wide enough to cover a finite width. Therefore, a resonance frequency f2 (i.e., the right-hand peak in the diagram) that deviates three (3) times (e.g., 10% deviation) from the expected fundamental frequency f1 (i.e., the left-hand peak in the diagram) can still promote parallel resonance to improve the rise time of the resulting waveform. When the quality factor Q of the multi-resonant network is lower than Figure 2C As shown, the resonance peak may be broader.

[0081] The implementation involves only one gain cell for simultaneous operation of both the f1 and f3 resonant signals coupled within the network. Because the AC gain of a single amplifier is applied at the knee point, a 3:1 frequency ratio between a single frequency component within the f1 spectral width and the corresponding single frequency component within the f3 spectral width can be enforced within each cycle, as shown in Figure 2C In other words, as explained above, the Cp / Cs ratio need not be precisely fixed at an exact ratio, but can vary, but remain within a range of, for example, 10-20% above or below a given ratio. In other words, the Cp / Cs ratio only needs to be substantially fixed. As shown, Figure 2C The peak values of f1 and f2 may not differ exactly by a factor of 3, but the multi-resonant balance can be stabilized at Figure 2C Compared to a sine wave, this less than ideal situation still results in an improvement in rise time, such as Figure 2D Comparison of transient waveforms in the best case angle Figure 2E The worst-case corner transient waveforms (the top plot region representing v(oscp-oscn)) are shown in Figure 1. As discussed below, although both corners exhibit deviations from a perfect 3-ratio, as well as many other parameter differences included in the simulations, both plots still show rise times that are steeper than a sine wave. Implementations can generate waveforms that stay at the rail voltage for longer than a sine wave. In these implementations, the rail-to-rail stable voltage is comparable to that of a CMOS clock signal, rather than that of a sine wave, whose peak voltage is only a small fraction of the waveform. Therefore, the implementations can resonate large clock loads to save power. This capability also has the practical advantage of reducing noise.

[0082] Figure 2D The corresponding time results of the transient waveforms obtained from the simulation are shown, representing one extreme process, voltage and temperature angle. Various capacitor values were used, resulting in various fundamental frequencies and the corresponding third harmonics. In particular, on the amplifier side (e.g. Figure 2A The oscp and oscn nodes in the oscp and oscn nodes in the oscn node) obtained a square wave-like waveform. Figure 2AThe internal nodes (e.g., intp and intn nodes) of the multi-resonant network obtain a waveform similar to a triangle wave. In various implementations, the multi-resonant network includes input nodes (e.g., oscp and oscn) and internal nodes (e.g., intp and intn). The input nodes add the first harmonic and the third harmonic in phase (i.e., the rising edge of the fundamental frequency is aligned with a subset of the rising edge of the third harmonic, and the falling edge of the fundamental frequency is aligned with a subset of the falling edge of the third harmonic). Conversely, the internal nodes add the first harmonic and the third harmonic in anti-phase (i.e., the rising edge of the fundamental frequency is aligned with the falling edge of the third harmonic, and the falling edge of the fundamental frequency is aligned with the rising edge of the third harmonic).

[0083] Figure 2E The corresponding transient waveforms obtained from the simulation are shown, representing another extreme process, voltage, and temperature angle. Figure 2F Shown Figure 2D The result of the Fast Fourier Transform (FFT) of the transient waveform is Figure 2G Shown Figure 2E The curves 241 and 251 are taken from the amplifier side (ie, node oscp or oscn), while the curves 242 and 252 are taken from the internal side (ie, node intp or intn).

[0084] Figure 3A An example of a schematic diagram 300 for direct driving of a final clock load of a system-on-chip (SoC) configuration or a subcomponent thereof is shown. The SoC configuration or a component thereof may include thousands of synchronous gate (e.g., flip-flop) clock input pins and a grid connecting the input pins. The multi-resonant network includes: inductors 301, 302, and 304, and capacitors 305 and 303, which are arranged in the same manner as Figure 1A and 2A As described above, the three inductors can be implemented as 4-tap inductive coils. For example, each inductor can also be implemented by winding one or more loops of an inductive loop coil, as described below in conjunction with Figure 5A and Figure 5BFurther explained. The implementation can incorporate a capacitor bank for each exemplary capacitor, for example, implemented as two or more capacitors arranged symmetrically with respect to each terminal of capacitor 305 or 303. In this example, amplifiers 306A and 306B are configured in direct drive mode to drive the LC resonant tank circuit. As shown, amplifiers 306A and 306B can be driven by clock signals 309A and 309B, which are CMOS clock sources in a complementary format. Clock signals 309A and 309B can come from a phase-locked loop (PLL). As shown, load capacitors 307 and 308 represent a lumped clock load, which is balanced in this illustration. Compared to an implementation without the illustrated multi-resonant network, an implementation using the illustrated multi-resonant network can accommodate significantly increased lumped clock loads.

[0085] When the inputs of the multi-resonant network are connected in parallel with the inputs of other blocks, the described example can directly drive high-capacitance CMOS gate loads within the same voltage domain. Such a system exhibits very low phase noise and power consumption. This makes it possible to eliminate clock amplification trees, thereby improving deterministic jitter and reducing distribution skew while minimizing clock power transients (because large clock loads are part of the multi-resonant network, which recycles charge on each cycle rather than sourcing / sinking current through power / ground).

[0086] The example shown here involves a non-continuously configurable C and a discretely switched L, where Cp / Cs is approximately 1 and Lp / Ls is approximately 0.64. The simulation assumes component values of: Ls = 17.4pH, Cs = 300fF, Lp = 27.2pH, Cp = 300fF.

[0087] refer to Figures 3B to 3E The results are based on the summation of the fundamental frequency and third harmonic using time-domain network simulation to solve Equation 2. In practice, Ls and Lp are increased by approximately 16% to compensate for the effects of the active CMOS driver and the series damping components not included in the ideal s-domain analysis. This increase also sharpens the slew rate. As shown, the ratio remains unchanged. The waveforms obtained from the simulation include a power-off switch, which enables a CMOS-level power-off output (i.e., a broken LC loop) and allows zero-wait oscillation when the switch is closed. The waveforms are less ideal due to the potential for residual capacitance in the switch inductor at lower frequencies.

[0088] Figure 3B An example of a transient waveform obtained from a simulation is shown, representing an extreme process, voltage, and temperature angle, where the load on each pin is approximately 0.73pF. In particular, a square-wave-like waveform is obtained on the amplifier side (i.e., clkp or clkn). Figure 3AThe internal node (ie, intp or intn) of the multi-resonance network obtains a waveform similar to a triangle wave. Figure 3C An example of a transient waveform obtained from a simulation is shown, representing the opposite extremes of process, voltage, and temperature corners, where the load on each pin is also approximately 0.73pF. Figure 3B and 3C The fundamental frequency is 32 GHz and the third harmonic is 96 GHz.

[0089] Figure 3D and 3E The results are shown when the inductor switch is disabled, causing the resonant loop to be cut off. Figure 3F shows an example of the transient waveforms obtained from the simulation, representing a best-case example where the load on each pin is approximately 0.73pF. Figure 3G shows an example of the transient waveforms obtained from the worst-case example during the simulation. The upper waveform is obtained on the amplifier side (i.e., through the output of inverters 306A and 306B). The lower waveform is obtained from Figure 3A Since the main resonant loop is cut off, the sum of the fundamental frequency and the third harmonic no longer occurs. Figure 3D Or the difference between the square-wave-like waveform and the triangular waveform between the upper and lower regions of 3E. The overshoot and undershoot of the waveform are due to the disconnected inductor loop still coupling with its previously attached capacitor, causing parasitic LC oscillations.

[0090] Figure 4 FIG400 is a diagram illustrating another example of a multi-resonant network according to some implementations of the present disclosure. As illustrated, FIG400 is similar to FIG200 and also depicts a multi-resonant network comprising inductor 401, inductor 402, inductor 404, capacitors 405I and 405S, and capacitors 403B and 403S. In various configurations, capacitors 405S and 403S have switchable capacitance and are therefore adjustable. In this example, a phase-locked loop oscillator based on gain stage 406 directly drives the load, making load capacitors 407 and 408, which represent significant chip loads, part of the oscillator. As with FIG200, the variable capacitor frequency control of FIG400 can be combined with continuously variable voltage-controlled capacitors to implement a voltage-controlled oscillator element, or the capacitors can be switched with fine capacitance resolution as a digitally controlled oscillator element of a phase-locked loop. In this way, the phase-locked loop characteristics of FIG200 are combined with the direct drive characteristics of FIG300 for significant capacitive loads.

[0091] Figure 5AA diagram 500 depicting an example of a physical inductor layout for a multi-resonant network according to some implementations of the present disclosure is shown. As illustrated, the multi-resonant network is similar to those illustrated in Figures 200, 300, and 400 and also includes an inductor 501 (which may provide inductors 201, 301, 401), an inductor 502 (which may provide inductors 202, 302, 402), an inductor 504 (which may provide inductors 204, 304, 404), and load capacitors 507 (which may provide capacitors 207, 307, 407) and 508 (which may provide capacitors 208, 308, 408), as well as an internal node capacitor 511.

[0092] Although switchable capacitors are not shown, diagram 500 highlights the use of inductive coils for implementing the physical configuration of inductors 501, 502, and 504. Specifically, to maximize the quality factor Q at their respective resonant frequencies, inductors 501, 502, and 504 can be implemented using top metal layers in parallel to form interconnected single-turn loops, such as Figure 5B As depicted in FIG520, in particular, the absence of a large amount of overlap enables mutual inductance to be minimized. Specifically, the winding loops of inductor 501 (between nodes n4 and n3) and inductor 504 (between nodes n1 and n2) are oriented so that the magnetic fields radiate in opposite directions relative to the plane of the coils, thereby reducing third harmonic electromagnetic interference (EMI). It is worth noting that although the single-turn loops are shaped like arcs forming partially complete loops, the single-turn loop inductors 501, 502, and 504 are inductive. Additionally, a small but positive mutual inductance is generated between inductors 501 and 504, which is due to the fact that Figure 5A A stepped and non-mirrored connection configuration is illustrated with respect to inductor 502 .

[0093] Further references Figure 1A , when Lp (corresponding to inductor 502) resonates at the fundamental frequency, Lp and each of Ls / 2 (corresponding to inductors 501 and 504) are electromagnetically coupled only to a very small extent, but mainly in opposite directions. Lp therefore produces very little differential interference on Ls / 2. Similarly, further reference is made to Figure 1A When Ls / 2 (corresponding to inductors 501 and 504) resonates at the third harmonic frequency, as seen by the winding loop of inductor 502, the mutual magnetic and electric fields largely cancel each other. Simulation results thus demonstrate that the mutual inductive currents between the third harmonic Ls resonance and the fundamental frequency Lp resonance cancel each other, thereby preventing differential mutual interference. For example, the mutual inductive currents can substantially cancel each other, resulting in a cancellation exceeding 10 dB, or even 20 dB.

[0094] exist Figure 5BIn the depicted example, the mutual inductive coupling coefficients K between inductor 502 (having an inductance of Lp) and inductors 501 and 504 (each having an inductance of Ls / 2) are approximately +0.0152 and -0.0154, respectively. These values are indeed very small, but are primarily opposite to each other. In this example, the mutual inductive coupling coefficient K between inductors 501 and 504 remains very small, at +0.042. In addition to this example physical layout, those skilled in the art can readily devise a variety of alternative configurations and physical implementations.

[0095] A method for generating a substantially trapezoidal clock signal using a multi-resonant network has been described. Although numerous implementations have been described, it should be understood that various modifications may be made without departing from the spirit and scope of the present innovation. Furthermore, the logic flows depicted in the figures do not require the particular order shown or sequential order to achieve the desired results. Furthermore, additional steps may be provided or deleted from the described flows, and other elements may be added to or removed from the described systems. Therefore, other implementations are within the scope of the appended claims.

Claims

1. A clock device for generating a clock signal, the clock device comprising: An LC network, comprising: a first inductive portion comprising a first terminal and a second terminal; a second inductive portion, the second inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the second inductive portion is connected to the second terminal of the first inductive portion; a third inductive portion, the third inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the third inductive portion is connected to the second terminal of the second inductive portion; a first capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the first capacitive portion is connected to the second terminal of the first inductive portion and the first terminal of the second inductive portion, and wherein the second terminal of the first capacitive portion is connected to the second terminal of the second inductive portion and the first terminal of the third inductive portion; and a second capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the second capacitive portion is connected to the first terminal of the first inductive portion, and wherein the second terminal of the second capacitive portion is connected to the second terminal of the third inductive portion, wherein the LC network is configured to resonate simultaneously at a first resonant frequency and a second resonant frequency that is substantially three times the first resonant frequency, and The clock signal is provided between the first terminal of the first inductive part and the second terminal of the third inductive part by a combination of a first resonant signal component and a second resonant signal component, the second resonant signal component is a third harmonic of the first resonant signal component, and each inflection point of the first resonant signal component is phase-aligned with a corresponding inflection point of the second resonant signal component.

2. The clock device according to claim 1 , wherein each inflection point of the first resonance signal component coincides with a corresponding inflection point of the second resonance signal component, and The clock signal has a waveform that is more trapezoidal than the first resonance signal component and the second resonance signal component.

3. The clock device of claim 1 , wherein the first inductive portion is characterized by an inductance Ls / 2, wherein the second inductive part is characterized by an inductance Lp, wherein the third inductive part is also characterized by an inductance Ls / 2, wherein the first capacitive part is characterized by capacitance Cp, wherein the second capacitive part is characterized by capacitance Cs, When the clock device is tuned within a certain frequency range, the ratio Cp / Cs is substantially fixed.

4. The clock device of claim 3, wherein Cp and Cs are variable so that the first resonant signal component is tunable within the frequency range, while the second resonant signal component remains the third harmonic of the first resonant signal component.

5. The clock device of claim 1 , wherein the first inductive portion is characterized by an inductance Ls / 2, wherein the second inductive part is characterized by an inductance Lp, wherein the third inductive portion is characterized by an inductance Ls / 2, wherein the first capacitive part is characterized by capacitance Cp, wherein the second capacitive portion is characterized by capacitance Cs, and The first resonant frequency is characterized by: ,and The second resonant frequency is characterized by: 。 6. The clock device of claim 5, wherein f2 = f1 + / - 10%. 7 . The clock device of claim 1 , further comprising a gain stage configured to amplify the first resonant signal component and the second resonant signal component when generating the clock signal.

8. The clock device of claim 7, wherein the gain stage comprises a complementary metal oxide semiconductor (CMOS) amplifier.

9. The clock device of claim 7, wherein the gain stage comprises a first pair of complementary transistors and a second pair of complementary transistors, wherein the output nodes of the first pair of complementary transistors are respectively AC coupled to the input gates of the second pair of complementary transistors, wherein the output nodes of the second pair of complementary transistors are respectively AC coupled to the input gates of the first pair of complementary transistors, and wherein the input gates of the first pair of complementary transistors are arranged to receive respective bias voltages, and The input gates of the second pair of complementary transistors are also arranged to receive the corresponding bias voltage.

10. The clock device of claim 1 , wherein the first terminal of the first inductive portion is coupled to a first chip capacitor load, wherein the second terminal of the third inductive portion is coupled to a second chip capacitor load, and Wherein the first chip capacitor load and the second chip capacitor load are coupled to a semiconductor chip or a subcomponent thereof.

11. The clock device of claim 10, wherein the semiconductor chip comprises a CMOS system on chip (SOC) device.

12. The clock device according to claim 1, further comprising an inductive coil having four taps, The first inductive part includes a first tap and a second tap of the inductive coil, wherein the second inductive portion includes a second tap and a third tap of the inductive coil, and The third inductive part includes a third tap and a fourth tap of the inductive coil.

13. The clock device of claim 1 , wherein the first inductive portion comprises a first set of winding loops surrounding a first region, wherein the third inductive portion comprises a third set of winding loops surrounding a third region, wherein the second inductive portion comprises a second set of winding loops surrounding a second region, wherein the surface areas of the first region and the third region are substantially the same, and The electromagnetic effect of the first group of windings on the second group of windings and the electromagnetic effect of the third group of windings on the second group of windings substantially cancel each other out.

14. The clock device of claim 13, wherein the mutual inductive coupling between the first group of winding loops and the second group of winding loops and the mutual inductive coupling between the second group of winding loops and the third group of winding loops are substantially the same in magnitude but opposite in sign.

15. The clock device of claim 14 , wherein the first set of winding loops is wound in one of the following directions: clockwise or counterclockwise, and the third set of winding loops is wound in the other of the following directions: clockwise or counterclockwise, the directions being relative to interconnecting current flow from the first set of winding loops through the second set of winding loops to the third set of winding loops.

16. The clock device of claim 14 , wherein when the first resonant signal component flows within the second group of winding loops, the first resonant signal component magnetically induces corresponding currents in the first group of winding loops and the third group of winding loops that flow in opposite directions and have substantially the same amplitudes, the directions being relative to the interconnected current flow from the first group of winding loops through the second group of winding loops to the third group of winding loops.

17. The clock device of claim 14, wherein when the second resonant signal component flows in the first group of winding loops and the third group of winding loops, the second resonant signal component flowing in the first group of winding loops and the second resonant signal component flowing in the third group of winding loops each magnetically induce a corresponding current in the second group of winding loops that flows in opposite directions and has substantially the same amplitude in the third group of winding loops.

18. The clock device of claim 1 , wherein the first capacitive portion comprises: at least one capacitor bank having two capacitors of substantially the same capacitance, the two capacitors being symmetrically arranged such that one terminal of each of the two capacitors is connected to ground and the other terminal of each of the two capacitors is connected to the first terminal and the second terminal of the first capacitive portion, respectively; Wherein the at least one capacitor bank comprises at least one switchable capacitor.

19. The clock device of claim 18, wherein the first capacitive portion further comprises: Voltage controlled capacitor.

20. The clock device of claim 1, wherein the second capacitive portion comprises: at least one capacitor bank having two capacitors of substantially the same capacitance, the two capacitors being symmetrically arranged such that one terminal of each of the two capacitors is connected to ground and the other terminal of each of the two capacitors is connected to the first terminal and the second terminal of the second capacitive portion, respectively; Wherein the at least one capacitor bank comprises at least one switchable capacitor.

21. The clock device of claim 20, wherein the second capacitive portion further comprises: Voltage controlled capacitor.

22. A clock device for generating a clock signal, the clock device comprising: An LC network, comprising: a first inductive portion comprising a first terminal and a second terminal; a second inductive portion, the second inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the second inductive portion is connected to the second terminal of the first inductive portion; a third inductive portion, the third inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the third inductive portion is connected to the second terminal of the second inductive portion; a first capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the first capacitive portion is connected to the second terminal of the first inductive portion and the first terminal of the second inductive portion, and wherein the second terminal of the first capacitive portion is connected to the second terminal of the second inductive portion and the first terminal of the third inductive portion; and a second capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the second capacitive portion is connected to the first terminal of the first inductive portion, and wherein the second terminal of the second capacitive portion is connected to the second terminal of the third inductive portion, wherein the first inductive part is characterized by an inductance Ls / 2, wherein the second inductive part is characterized by an inductance Lp, wherein the third inductive portion is characterized by an inductance Ls / 2, wherein the first capacitive part is characterized by capacitance Cp, wherein the second capacitive part is characterized by capacitance Cs, wherein the LC network is configured to resonate simultaneously at a first frequency and a second frequency that is three times the first frequency, and When the clock device is tuned within a certain frequency range, the ratio Cp / Cs is substantially fixed.

23. A clock device for generating a clock signal, the clock device comprising: An LC network, comprising: a first inductive portion comprising a first terminal and a second terminal; a second inductive portion, the second inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the second inductive portion is connected to the second terminal of the first inductive portion; a third inductive portion, the third inductive portion comprising a first terminal and a second terminal, wherein the first terminal of the third inductive portion is connected to the second terminal of the second inductive portion; a first capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the first capacitive portion is connected to the second terminal of the first inductive portion and the first terminal of the second inductive portion, and wherein the second terminal of the first capacitive portion is connected to the second terminal of the second inductive portion and the first terminal of the third inductive portion; and a second capacitive portion comprising a first terminal and a second terminal, wherein the first terminal of the second capacitive portion is connected to the first terminal of the first inductive portion, and wherein the second terminal of the second capacitive portion is connected to the second terminal of the third inductive portion, wherein the first inductive part is characterized by an inductance Ls / 2, wherein the second inductive part is characterized by an inductance Lp, wherein the third inductive portion is characterized by an inductance Ls / 2, wherein the first capacitive part is characterized by capacitance Cp, wherein the second capacitive part is characterized by capacitance Cs, wherein the first resonant frequency of the LC network is characterized by: ， The second resonant frequency of the LC network is characterized by: ,and The second resonant frequency is substantially three times the first resonant frequency.

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