Imaging element and electronic device

Abstract

The present invention suppresses a change in charge injection associated with a switching operation during a sample and hold period. An imaging element according to the present technology includes a pixel array section and a sample-and-hold circuit provided corresponding to pixel rows of the pixel array section. The sample hold circuit includes: a first capacitive element and a second capacitive element; first and second sampling transistors connected in series to the first and second capacitive elements, respectively; first and second write transistors connected between the input terminal and the first and second sampling transistors to write a reset signal and a data signal input from the input terminal to the first and second capacitive elements; a first read transistor and a second read transistor that read a reset signal and a data signal written to the first capacitance element and the second capacitance element; and a reset transistor connected between the output terminal and a node at a predetermined reference potential.

Description

Technical Field

[0001] The present technology relates to an imaging element. Specifically, the present technology relates to an imaging element including a sample-and-hold circuit that samples and holds a pixel signal output from a pixel, and an electronic device including the imaging element. Background Art

[0002] Imaging elements such as complementary metal oxide semiconductor (CMOS) image sensors are equipped with an analog-to-digital conversion unit that digitizes analog pixel signals read from pixels. The analog-to-digital conversion unit installed on the imaging element has a so-called column-parallel analog-to-digital conversion unit configuration, which includes multiple analog-to-digital conversion circuits arranged corresponding to pixel columns.

[0003] In analog-to-digital conversion processing, by pipeline processing (pipelining) the signal reading operation from pixels and the analog-to-digital conversion operation, the large number of pixel signal reading operations including the analog-to-digital conversion process can be accelerated, thereby increasing the frame rate. In order to achieve pipeline processing of the signal reading operation and the analog-to-digital conversion operation, it is necessary to provide a sample-and-hold circuit before the analog-to-digital conversion circuit.

[0004] The pixel signal read from the pixel includes a reset signal (so-called P-phase signal) at a reset level and output from the pixel during resetting, and a data signal (so-called D-phase signal) at a signal level and output from the pixel during photoelectric conversion. As a sample-and-hold circuit for sampling and holding a pixel signal including a reset signal and a data signal, there is a sample-and-hold circuit that includes a path for sampling and holding the reset signal and a path for sampling and holding the data signal, respectively (for example, see Patent Document 1).

[0005] Reference List

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2009-253930 Summary of the Invention

[0008] Problems to be solved by the present invention

[0009] In the conventional technology described above, since the paths for sampling and holding the reset signal and the paths for sampling and holding the data signal are provided separately, variations in charge injection due to switching operations on each path cause variations in sampling error. These variations in sampling error appear as vertical streaks on the captured image, which degrades image quality.

[0010] The present technology has been made in view of such circumstances, and an object thereof is to suppress variations in charge injection due to switching operations at the time of sampling and holding in a sample-and-hold circuit.

[0011] Solution to the problem

[0012] The present technology has been made to solve the above-mentioned problems, and a first aspect of the present technology is an imaging element including: a pixel array unit in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels including a photoelectric conversion unit; and a sample-and-hold circuit provided corresponding to a pixel column of the pixel array unit and sampling and holding a pixel signal including a reset signal and a data signal output from the pixel through a signal line, wherein the sample-and-hold circuit includes: a first capacitance element; a first sampling transistor connected in series to the first capacitance element; a first write transistor connected between an input terminal configured to receive a reset signal and the first sampling transistor, and writing the reset signal input from the input terminal to the first sampling transistor through the first sampling transistor. A first capacitor element includes a first read transistor connected between the first sampling transistor and an output terminal, and the reset signal written into the first capacitor element is read by the first sampling transistor; a second capacitor element; a second sampling transistor connected in series to the second capacitor element; a second write transistor connected between an input terminal configured to receive a data signal and the second sampling transistor, and the data signal input from the input terminal is written into the second capacitor element by the second sampling transistor; a second read transistor connected between the second sampling transistor and the output terminal, and the data signal written into the second capacitor element is read by the second sampling transistor; and a reset transistor connected between the output terminal and a node of a predetermined reference potential. As a result, a variation in charge injection due to switching operation is suppressed during sampling and holding in the sample-and-hold circuit.

[0013] Furthermore, in the first aspect, the first sampling transistor and the second sampling transistor can each include a transistor having a relatively small size. As a result, there is provided an effect of being able to further suppress sampling errors.

[0014] In the first aspect, each of the first write transistor, the first read transistor, the second write transistor, the second read transistor, and the reset transistor can include a transistor having a relatively large size, thereby achieving high-speed operation.

[0015] Furthermore, in this first aspect, the imaging element may be configured such that the first write transistor and the first sampling transistor are brought into an on-state, a reset signal is written into the first capacitance element, the first sampling transistor is then brought into an off-state, the first read transistor and the reset transistor are brought into an on-state, and a signal read path is initialized, the first sampling transistor is then brought into an on-state, and the reset signal written into the first capacitance element is read through the signal read path, thereafter the second write transistor and the second sampling transistor are brought into an on-state, a data signal is written into the second capacitance element, the second sampling transistor is then brought into an off-state, the second read transistor and the reset transistor are brought into an on-state, the signal read path is initialized, the second sampling transistor is brought into an on-state, and the data signal written into the second capacitance element is read through the signal read path. As a result, a variation in charge injection due to switching operation during sampling and holding is suppressed.

[0016] Furthermore, in this first aspect, the imaging element can be configured such that, while the first sampling transistor and the second sampling transistor are always in the on state and the reset transistor is always in the off state, the first write transistor is turned on and a reset signal is written into the first capacitor, then the first read transistor is turned on and the reset signal written into the first capacitor is read, thereafter the second write transistor is turned on and a data signal is written into the second capacitor, then the second read transistor is turned on and the data signal written into the second capacitor is read. Thus, the time overhead between the write operation and the read operation of the reset signal and the data signal can be minimized, and the speed of the pixel signal read operation can be further improved.

[0017] Furthermore, in this first aspect, an amplifier provided between the signal line and the sample-hold circuit may be further included. As a result, an input conversion effect capable of reducing noise after the sample-hold circuit is provided.

[0018] Furthermore, in the first embodiment, the imaging element may have a low error driving mode and a high speed driving mode in a low error driving mode, the first writing transistor and the first sampling transistor are turned on and a reset signal is written to the first capacitor, the first sampling transistor is turned off, the first reading transistor and the reset transistor are turned on, and the signal reading path is initialized, the first sampling transistor is turned on, and the reset signal written in the first capacitor is read through the signal reading path, thereafter the second writing transistor and the second sampling transistor are turned on, and a data signal is written to the second capacitor, the second sampling transistor is turned off, and the second reading transistor and the reset transistor are turned off. The first sampling transistor is turned on and the signal reading path is initialized. Then, the second sampling transistor is turned on and the data signal written into the second capacitor is read through the signal reading path. In the high-speed driving mode, the first sampling transistor and the second sampling transistor are always turned on and the reset transistor is always turned off. The first write transistor is turned on and the reset signal is written into the first capacitor. Then, the first read transistor is turned on and the reset signal written into the first capacitor is read. Thereafter, the second write transistor is turned on and the data signal is written into the second capacitor. Then, the second read transistor is turned on and the data signal written into the second capacitor is read. As a result, even in a sample-and-hold circuit having the same circuit configuration, it is possible to select the emphasized characteristics or the operating speed by using the driving method of the sample-and-hold circuit.

[0019] Furthermore, in this first aspect, the imaging element can be configured such that the sample-and-hold circuit includes a power supply path switching unit that connects a power supply-side terminal of each of the first and second capacitive elements to electrically separate power supply paths; when writing signals to the first and second capacitive elements and when reading signals from the first and second capacitive elements, this circuit can reduce crosstalk that can cause fluctuations in signals read in parallel.

[0020] Furthermore, in this first aspect, the imaging element can be configured such that the sample-and-hold circuit has a wiring structure in which the wiring between the first capacitance element and the first sampling transistor and the wiring between the second capacitance element and the second sampling transistor are shielded by the wiring between the first capacitance element and the power supply path switching unit and the wiring between the second capacitance element and the power supply path switching unit. As a result, the imaging element can be enhanced in terms of resistance to noise and crosstalk.

[0021] Furthermore, in the first aspect, the imaging element can be configured such that, in the wiring structure, the wiring length of the wiring between the first capacitance element and the first sampling transistor is equal to the wiring length of the wiring between the second capacitance element and the second sampling transistor. As a result, the CDS processing performed in the analog-to-digital conversion unit in the subsequent stage can align and remove sampling errors and interference between the reset signal and the data signal.

[0022] Furthermore, a second aspect of the present technology is an electronic device including an imaging element, the imaging element including: a pixel array unit in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels including a photoelectric conversion unit; and a sample-and-hold circuit provided corresponding to a pixel column of the pixel array unit and sampling and holding a pixel signal including a reset signal and a data signal output from the pixel via a signal line, wherein the sample-and-hold circuit includes: a first capacitance element; a first sampling transistor connected in series to the first capacitance element; a first write transistor connected between an input terminal configured to receive a reset signal and the first sampling transistor, and writing the reset signal input from the input terminal to the first sampling transistor via the first sampling transistor. The present invention also includes a capacitor element; a first read transistor connected between the first sampling transistor and the output terminal, and reading a reset signal written into the first capacitor element via the first sampling transistor; a second capacitor element; a second sampling transistor connected in series to the second capacitor element; a second write transistor connected between an input terminal configured to receive a data signal and the second sampling transistor, and writing a data signal input from the input terminal into the second capacitor element via the second sampling transistor; a second read transistor connected between the second sampling transistor and the output terminal, and reading the data signal written into the second capacitor element via the second sampling transistor; and a reset transistor connected between the output terminal and a node of a predetermined reference potential. As a result, variations in charge injection caused by switching operations during sampling and holding are reduced, making it possible to suppress fixed pattern noise of the pixel column, resulting in an effect that a captured image with high image quality can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a system configuration diagram showing a configuration example of an imaging element according to an embodiment of the present technology.

[0024] Figure 2 : is a circuit diagram showing a circuit example of a pixel (pixel circuit) of an imaging element according to an embodiment of the present technology.

[0025] Figure 3 It is a perspective view for explaining an outline of a semiconductor chip structure of an imaging element according to an embodiment of the present technology.

[0026] Figure 4 : is a block diagram showing a basic configuration example of an analog-to-digital conversion unit of an imaging element according to an embodiment of the present technology.

[0027] Figure 5 is a diagram for explaining a sample-and-hold circuit according to Reference Example 1.

[0028] Figure 6 This is a diagram for explaining the mechanism of sampling error caused by changes in charge injection.

[0029] Figure 7 is a diagram for explaining a sample-and-hold circuit according to Reference Example 2.

[0030] Figure 8 is a timing chart for explaining a circuit operation example of the sample-and-hold circuit according to Reference Example 2.

[0031] Figure 9 is a circuit diagram showing a circuit configuration example of a sample-and-hold circuit according to an embodiment of the present technology.

[0032] Figure 10 1 is a timing chart showing circuit operation example 1 of the sample-and-hold circuit according to the embodiment of the present technology.

[0033] Figure 11 This is a diagram for explaining the consideration of sampling errors.

[0034] Figure 12 1 is a timing chart showing circuit operation example 2 of the sample-and-hold circuit according to the embodiment of the present technology.

[0035] Figure 13 : is a block diagram showing an arrangement example of a sample-and-hold circuit according to an embodiment of the present technology.

[0036] Figure 14 is a circuit diagram for explaining a driving mode of a sample-and-hold circuit according to an embodiment of the present technology.

[0037] Figure 15 It is a diagram for explaining the wiring structure of the sample-and-hold circuit according to the embodiment of the present technology.

[0038] Figure 16 is a block diagram illustrating a configuration example of an imaging device to which an embodiment of an electronic device of the present technology is applied.

[0039] Figure 17 It is a diagram showing an example of a field to which an embodiment of the present technology is applied.

[0040] Figure 18 It is a block diagram showing an embodiment of a schematic configuration of a vehicle control system.

[0041] Figure 19 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION

[0042] Modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described below. The description will be given in the following order.

[0043] 1. Imaging element of this technology

[0044] 1-1. Configuration Example of Imaging Element

[0045] 1-2. Pixel Circuit Example

[0046] 1-3. Semiconductor Chip Structure

[0047] 1-4. Basic Configuration Example of Analog-to-Digital Conversion Unit

[0048] 1-5. About pipeline processing

[0049] 1-6. Reference Example of Sample-and-Hold Circuit

[0050] 2. Sample-and-hold circuit according to an embodiment of the present technology

[0051] 2-1. Example 1 (Circuit Configuration Example of Sample-Hold Circuit)

[0052] 2-2. Example 2 (Circuit Operation Example 1 of Sample-Hold Circuit)

[0053] 2-3. Example 3 (Circuit Operation Example 2 of Sample-Hold Circuit)

[0054] 2-4. Example 4 (Example of Driving Mode of Imaging Element)

[0055] 2-5. Example 5 (Example of Arrangement of Sample-Hold Circuit)

[0056] 2-6. Example 6 (Example of Switching the Power Supply Path of the Low-Potential-Side Power Supply of the Capacitive Element)

[0057] 2-7. Example 7 (Example of Wiring Structure of Sample-Hold Circuit)

[0058] 3. Modifications

[0059] 4. Application Examples of Electronic Devices

[0060] 5. Examples of Use of Imaging Elements

[0061] 6. Available configurations for this technology

[0062] <Imaging element of the present technology>

[0063] One embodiment of the imaging element of the present technology is a CMOS image sensor, which is a type of XY address system imaging element. The CMOS image sensor is an imaging element manufactured by applying or partially using a CMOS process.

[0064] [Configuration Example of Imaging Element]

[0065] Figure 1 1 is a block diagram illustrating an example configuration of an imaging element according to an embodiment of the present technology. The imaging element 10 according to this embodiment has a configuration including a pixel array unit 11 and peripheral circuit units of the pixel array unit 11. The peripheral circuit units of the pixel array unit 11 include, for example, a vertical scanning unit 12, a load MOS unit 13, a sample-and-hold unit 14, an analog-to-digital conversion unit 15, a storage unit 16, a data processing unit 17, an output unit 18, a timing control unit 19, and the like.

[0066] The pixel array unit 11 has pixels (pixel circuits) 20 arranged two-dimensionally (i.e., in a matrix) in the row direction and the column direction. Each of the pixels 20 includes a photoelectric conversion unit (photoelectric conversion element). Here, the row direction refers to the direction in which the pixels 20 in the pixel row are arranged, and the column direction refers to the direction in which the pixels 20 in the pixel column are arranged. The pixels 20 perform photoelectric conversion to generate and accumulate photocharges corresponding to the amount of incident light. Figure 1 In the embodiment shown, the pixel array of the pixel array unit 11 is an array of m rows and n columns (m and n are integers), that is, "m" represents the number of rows, and "n" represents the number of columns.

[0067] In the pixel array unit 11 , a pixel control line 31 is wired for each pixel row for an array of m rows and n columns. A signal line 32 is wired for each pixel 20 .

[0068] When reading signals from the pixels 20, the pixel control line 31 transmits the drive signal output from the vertical scanning unit 12 in units of pixel rows. Figure 1 , the pixel control line 31 is shown as one wiring line, but the number is not limited to one. One end of the pixel control line 31 is connected to the output terminal corresponding to each row of the vertical scanning unit 12. The signal line 32 transmits the signal read from the pixel 20 to the sampling and holding unit 14.

[0069] Hereinafter, each component of the peripheral circuit unit of the pixel array unit 11 will be described, namely, the vertical scanning unit 12, the load MOS unit 13, the sampling and holding unit 14, the analog-to-digital conversion unit 15, the storage unit 16, the data processing unit 17, the output unit 18, and the timing control unit 19.

[0070] The vertical scanning unit 12 includes a shift register, an address decoder, and the like, and controls scanning of pixel rows and addresses of pixel rows based on a timing control signal supplied from the timing control unit 19 when selecting each pixel 20 of the pixel array unit 11. Although the specific configuration of the vertical scanning unit 12 is not shown, the vertical scanning unit 12 generally includes two scanning systems: a read scanning system and a sweep scanning system.

[0071] The read scanning system selectively scans the pixels 20 in the pixel array unit 11 in sequence row by row to read pixel signals from each pixel 20. The pixel signals read from the pixels 20 are analog signals. The sweep scanning system performs a sweep scan on a read row subjected to the read scanning of the read scanning system earlier than the read scanning by an amount of time corresponding to the shutter speed.

[0072] When the sweep scanning system performs a sweep scan, unnecessary charges are scanned from the photoelectric conversion units of the pixels 20 in the read row. As a result, the photoelectric conversion units are reset. Then, the unnecessary charges are cleared (reset) by the scanning system, thereby performing a so-called electronic shutter operation. Here, the electronic shutter operation refers to an operation that releases the photoelectric charges of the photoelectric conversion units and newly starts exposure (starts accumulation of photoelectric charges).

[0073] The signal read by the read scanning system during the read operation corresponds to the amount of light received after the immediately preceding read operation or electronic shutter operation. The time period from the read timing of the immediately preceding read operation or the scan timing of the electronic shutter operation to the read timing of the current read operation is the exposure time period for the photocharge in the pixel 20.

[0074] The load MOS unit 13 includes a plurality of current sources 33 (see Figure 2 ), each current source 33 includes a MOS transistor connected to each signal line 32 of each pixel column, and supplies a bias current to each pixel 20 of a pixel row selectively scanned by the vertical scanning unit 12 through each signal line 32.

[0075] The sample-hold unit 14 samples and holds a pixel signal supplied from the pixel 20 through the signal line 32. The present technology is applied to the sample-hold unit 14. Details of the sample-hold unit 14 to which the present technology is applied will be described later.

[0076] The analog-to-digital (A / D) conversion unit 15 includes a plurality of analog-to-digital conversion circuits provided corresponding to the signal lines 32, and converts the analog pixel signals output from the sample-and-hold unit 14 into digital signals for each pixel column. The analog-to-digital conversion circuits may be well-known analog-to-digital conversion circuits. Specifically, as the analog-to-digital conversion circuits, a single-slope analog-to-digital conversion circuit, a successive approximation analog-to-digital conversion circuit, or a ΔΣ analog-to-digital conversion circuit may be exemplified. However, the analog-to-digital conversion circuits are not limited to these types.

[0077] The storage unit 16 stores the analog-to-digital conversion result in the analog-to-digital conversion unit 15 under the processing of the data processing unit 17 .

[0078] The data processing unit 17 is a digital signal processing unit that processes the digital signal output from the analog-to-digital conversion unit 15 and performs processing of writing and reading the analog-to-digital conversion result to and from the storage unit 16 and performs various processing on the analog-to-digital conversion result.

[0079] The output unit 18 derives the signal processed by the data processing unit 17 as an imaging output.

[0080] The timing control unit 19 generates various timing signals, clock signals, control signals, etc. based on the synchronization signal supplied from the outside. Then, the timing control unit 19 performs drive control of the vertical scanning unit 12, the sampling and holding unit 14, the analog-to-digital conversion unit 15, the data processing unit 17, etc. based on the generated signals.

[0081] [Pixel Circuit Example]

[0082] Figure 2 1 is a circuit diagram showing an example of a circuit of a pixel (pixel circuit) 20 of the imaging element 10 according to an embodiment of the present technology. Each pixel 20 of the pixel array unit 11 includes a photoelectric conversion unit 21, a charge transfer unit 22, a charge-voltage conversion unit 23, a charge reset unit 24, a signal amplification unit 25, and a pixel selection unit 26. A predetermined voltage is supplied from the power supply (pixel power supply) of the pixel 20 to the charge reset unit 24 and the signal amplification unit 25.

[0083] Here, as the charge transfer unit 22, the charge resetting unit 24, the signal amplifying unit 25, and the pixel selecting unit 26, for example, N-channel MOS field effect transistors (hereinafter referred to as MOS transistors) can be used. However, the combination of the conductivity types of the four MOS transistors 22, 24, 25, and 26 illustrated here is merely an example, and the combination is not limited thereto.

[0084] For the pixels 20, as with the pixel control lines 31 described above, a plurality of pixel control lines are commonly wired to the pixels 20 in the same pixel row. The plurality of pixel control lines are connected in pixel row units to output terminals corresponding to each pixel row of the vertical scanning unit 12. The vertical scanning unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of pixel control lines.

[0085] It should be noted that the constant current source 33 is connected to one end of the signal line 32 wired for each pixel column of the pixel array unit 11 .

[0086] The photoelectric conversion unit 21 is a PN junction photodiode (PD). The photodiode has an anode electrode connected to a low-potential side power supply (for example, ground), and generates and accumulates charge according to the amount of incident light.

[0087] The charge transfer unit 22 transfers the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23 in accordance with the transfer signal TRG supplied from the vertical scanning unit 12. Specifically, the transfer signal TRG active at a high level is supplied from the vertical scanning unit 12 to the gate electrode of the transistor constituting the charge transfer unit 22. Then, the transistor constituting the charge transfer unit 22 enters a conductive state and transfers the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23.

[0088] The charge-voltage conversion unit 23 is a capacitor of a floating diffusion (FD) region formed between the drain region of the transistor constituting the charge transfer unit 22 and the source region of the transistor constituting the charge resetting unit 24. The charge-voltage conversion unit 23 converts the charge transferred from the photoelectric conversion unit 21 through the charge transfer unit 22 into a voltage.

[0089] The charge resetting unit 24 resets the charge accumulated in the charge-voltage conversion unit 23 according to the reset signal RST supplied from the vertical scanning unit 12. Specifically, the reset signal RST active at a high level is supplied from the vertical scanning unit 12 to the gate of the transistor constituting the charge resetting unit 24. Then, the transistor constituting the charge resetting unit 24 becomes conductive, and the charge accumulated in the charge-voltage conversion unit 23 is reset.

[0090] The signal amplification unit 25 amplifies the voltage converted by the charge-voltage conversion unit 23 and outputs a pixel signal at a level corresponding to the charge accumulated in the charge-voltage conversion unit 23. The gate electrode of the transistor constituting the signal amplification unit 25 is connected to the charge-voltage conversion unit 23, and the drain electrode is connected to the node of the power supply voltage VDD. Then, the transistor constituting the signal amplification unit 25 serves as an input unit of a readout circuit (i.e., a source follower circuit) that reads out the charge obtained by the photoelectric conversion in the photoelectric conversion unit 21. That is, in the transistor constituting the signal amplification unit 25, the source electrode is connected to the signal line 32 via the pixel selection unit 26, thereby constituting a source follower circuit with the constant current source 33 connected to one end of the signal line 32.

[0091] The pixel selection unit 26 selects any pixel 20 within the pixel array unit 11 under selective scanning by the vertical scanning unit 12. The transistor constituting the pixel selection unit 26 is connected between the source electrode of the transistor constituting the signal amplification unit 25 and the signal line 32, and a high-level active selection signal SEL is supplied from the vertical scanning unit 12 to its gate electrode. Then, when the selection signal SEL becomes high, the transistor constituting the pixel selection unit 26 enters a conductive state. As a result, the pixel 20 enters a selected state. When the pixel 20 enters the selected state, the signal output from the signal amplification unit 25 is read out to the load MOS unit 13 via the signal line 32.

[0092] The pixel 20 of the circuit configuration embodiment described above sequentially outputs a reset signal P (so-called P-phase signal) at a reset level when the charge-voltage conversion unit 23 is reset by the charge resetting unit 24, and a data signal D (so-called D-phase signal) at a signal level corresponding to the charge based on the photoelectric conversion in the photoelectric conversion unit 21. That is, the pixel signal output from the pixel 20 includes the reset signal P at the time of resetting and the data signal D at the time of photoelectric conversion in the photoelectric conversion unit 21.

[0093] [Semiconductor chip structure]

[0094] As the semiconductor chip structure of the imaging element 10 according to this embodiment having the above-described configuration, a planar semiconductor chip structure and a stacked semiconductor chip structure can be exemplified. Furthermore, regarding the pixel structure, when the substrate surface on the side where the wiring layer is formed is defined as the front surface (front face), a back-illuminated pixel structure that receives light emitted from the rear surface side opposite to the front surface can be employed, or a front-illuminated pixel structure that receives light emitted from the front surface side can be employed.

[0095] Hereinafter, an outline of a planar type semiconductor chip structure and a stacked type semiconductor chip structure will be described.

[0096] (Planar semiconductor chip structure)

[0097] exist Figure 3 In FIG. 1 , a is a perspective view schematically showing a flat chip structure of the imaging element 10. Figure 3As shown in FIG. 1 a , the planar semiconductor chip structure has a structure in which each component of the peripheral circuit unit of the pixel array unit 11 is formed on the same semiconductor substrate 41 as the pixel array unit 11 in which the pixels 20 are arranged in a matrix. Specifically, the vertical scanning unit 12, the load MOS unit 13, the sampling and holding unit 14, the analog-to-digital conversion unit 15, the storage unit 16, the data processing unit 17, the timing control unit 19, and the like are formed on the same semiconductor substrate 41 as the pixel array unit 11. For example, pads 42 for external connection and power supply are provided at the left and right end portions of the semiconductor substrate 41 in the first layer.

[0098] (Stacked semiconductor chip structure)

[0099] exist Figure 3 In FIG. 1 , b is an exploded perspective view schematically showing the stacked semiconductor chip structure of the imaging element 10. Figure 3 As shown in FIG. 2 b , the stacked type semiconductor chip structure has a structure in which at least two semiconductor substrates of a first-layer semiconductor substrate 43 and a second-layer semiconductor substrate 44 are stacked.

[0100] In this stacked semiconductor chip structure, the semiconductor substrate 43 of the first layer is a pixel chip in which the pixel array unit 11 is formed, in which pixels 20, each including a photoelectric conversion unit (e.g., a photodiode), are arranged two-dimensionally in a matrix. For example, pads 42 for external connection and power supply are provided at the left and right ends of the semiconductor substrate 43 in the first layer.

[0101] The semiconductor substrate 44 of the second layer is a circuit chip in which the peripheral circuit units of the pixel array unit 11, that is, the vertical scanning unit 12, the load MOS unit 13, the sampling and holding unit 14, the analog-to-digital conversion unit 15, the storage unit 16, the data processing unit 17, the timing control unit 19, etc. are formed. It should be noted that the arrangement of the vertical scanning unit 12, the load MOS unit 13, the sampling and holding unit 14, the analog-to-digital conversion unit 15, the storage unit 16, the data processing unit 17, the timing control unit 19, etc. is an embodiment and is not limited to this arrangement embodiment.

[0102] The pixel array unit 11 on the first semiconductor substrate 43 and the peripheral circuit unit on the second semiconductor substrate 44 are electrically connected via connections (not shown) including metal-metal junctions including Cu-Cu connections, through silicon vias (TSVs), micro pumps, and the like.

[0103] According to the stacked semiconductor chip structure described above, the process applicable to manufacturing the pixel array unit 11 can be applied to the first semiconductor substrate 43, and the process applicable to manufacturing the circuit portion can be applied to the second semiconductor substrate 44. Therefore, during the manufacturing of the imaging element 10, the process can be optimized. Specifically, advanced processes can be applied when manufacturing the circuit portion.

[0104] [Basic Configuration Example of Analog-to-Digital Converter]

[0105] Next, a basic configuration example of the analog-to-digital conversion unit 15 will be described. Figure 4 : is a block diagram showing a basic configuration example of the analog-to-digital conversion unit 15 of the imaging element 10 according to the embodiment of the present technology. Figure 4 Peripheral circuit units of the analog-to-digital conversion unit 15 are also shown.

[0106] The analog-to-digital conversion unit 15 acquires the analog pixel signal supplied from each pixel 20 of the pixel array unit 11 through the signal line 32 based on the timing control signal supplied from the timing control unit 19 , and sequentially converts the analog pixel signal into a digital pixel signal.

[0107] The analog-to-digital conversion unit 15 includes a plurality of analog-to-digital conversion circuits 50 provided corresponding to the respective pixels 20 of the pixel array unit 11. In the imaging element 10 according to the embodiment of the present technology, for example, a so-called single-slope analog-to-digital conversion circuit (which is an example of a reference signal comparison analog-to-digital conversion circuit) is used as the analog-to-digital conversion circuit 50.

[0108] In the analog-to-digital conversion unit 15 using a single-slope analog-to-digital conversion circuit, a reference signal of a ramp waveform that linearly changes (e.g., monotonically decreases) with a predetermined slope over time is used. That is, the ramp wave reference signal RAMP is used as a reference signal during analog-to-digital conversion. The ramp wave reference signal RAMP is generated in the reference signal generation unit 40 based on the timing control signal supplied from the timing control unit 19. The reference signal generation unit 40 can be configured using, for example, a digital-to-analog conversion circuit.

[0109] The analog-to-digital conversion circuit 50 includes a comparator 51 and a column counter 52 , and is provided for each pixel column of the pixel array unit 11 .

[0110] The comparator 51 uses the analog pixel signal Vsig supplied from each pixel 20 of the pixel array unit 11 via the signal line 32 as a comparison input, and uses the ramp wave reference signal RAMP generated by the reference signal generation unit 40 as a reference input for comparing the two signals. Then, for example, at the timing when the ramp wave reference signal RAMP exceeds the voltage value of the analog pixel signal Vsig, a signal (comparison result) Vco notifying that the reference signal RAMP exceeds the voltage value of the analog pixel signal Vsig is output. Thus, the comparator 51 outputs a pulse signal having a pulse width corresponding to the signal level of the analog pixel signal Vsig (specifically, corresponding to the amplitude of the signal level) as the comparison result Vco.

[0111] The clock signal CLK is supplied from the timing control unit 19 to the column counter 52 at the same timing as the supply start timing of the ramp wave reference signal RAMP. The column counter 52 performs a counting operation in synchronization with the clock signal CLK, thereby measuring the period of the pulse width of the output pulse of the comparator 51, that is, the period from the start of the comparison operation to the end of the comparison operation. The counting result (count value) of the column counter 52 is supplied to the data processing unit 17 as a digital value obtained by digitizing the analog pixel signal Vsig.

[0112] For example, an up / down counter can be used as the column counter 52. In the column counter 52 including the up / down counter, down counting (DOWN) or up counting (UP) is performed in synchronization with the clock signal CLK. Specifically, for example, for the reset signal P output from the pixel 20 and at the reset level when the charge-voltage conversion unit 23 is reset, and the data signal D output from the pixel 20 and at the signal level based on the photoelectric conversion, the reset signal P is counted down, while the data signal D is counted up.

[0113] The difference between the data signal D and the reset signal P can be obtained by the down-counting / up-counting operation. As a result, in addition to the analog-to-digital conversion process, the analog-to-digital conversion unit 15 also performs a correlated double sampling (CDS) process. Here, the "CDS process" is a process of removing pixel-specific fixed pattern noise (such as reset noise of the pixel 20 and threshold variation of the signal amplification unit 25) by obtaining the difference between the data signal D at a signal level based on photoelectric conversion and the reset signal P at a reset level when resetting the charge-voltage conversion unit 23.

[0114] As described above, the analog-to-digital conversion unit 15 including the single-slope analog-to-digital conversion circuit 50 compares the analog pixel signal Vsig output from the pixel 20 with the reference signal RAMP of the ramp wave generated by the reference signal generation unit 40. Then, a digital value can be obtained from time information starting with the time when the amplitude relationship between the analog pixel signal Vsig of the ramp wave and the reference signal RAMP changes (that is, the time when the output of the comparator 51 is inverted).

[0115] [About pipeline processing]

[0116] In the imaging element 10 according to the present embodiment described above (i.e., the imaging element 10 on which the column-parallel type analog-to-digital conversion unit 15 is mounted), pipeline processing of the signal reading operation from the pixel 20 and the analog-to-digital conversion operation can be achieved by providing the sampling and holding unit 14 at the preceding stage of the analog-to-digital conversion unit 15. Figure 4 As shown in , the sampling and holding unit 14 includes a plurality of sampling and holding circuits 70 arranged corresponding to respective pixel columns of the pixel array unit 11 .

[0117] By pipeline processing the signal reading operation and the analog-to-digital conversion operation (pipelining), the basic pixel signal reading operation including the analog-to-digital conversion process can be accelerated, making it possible to increase the frame rate. Conversely, without increasing the frame rate (i.e., when the frame rate is set to be equal to the normal frame rate), the blanking period during which signal reading and analog-to-digital conversion are not performed can be increased, thereby reducing the power consumption of the imaging element 10.

[0118] [Reference Example of Sample-and-Hold Circuit]

[0119] (Reference Example 1)

[0120] Here, a basic sample-and-hold circuit will be described as the sample-and-hold circuit according to Reference Embodiment 1. Figure 5 1 is a diagram for explaining a sample-and-hold circuit 70A according to Reference Example 1.

[0121] like Figure 5 As shown in a, the sample-and-hold circuit 70A according to Reference Example 1 has a circuit including a P-phase path 60 p and D phase path 60 d The circuit configuration of the P phase path is 60 p The D-phase path 60 is used to sample and hold the reset signal P (P-phase signal) at the reset level when the charge-voltage conversion unit 23 is reset. d It is used to sample and hold the data signal D (D-phase signal) at a signal level based on photoelectric conversion.

[0122] P-phase path 60p A sampling transistor 61 for sampling the reset signal P is included. p , maintained by the sampling transistor 61 p Capacitive element 62 of the sampled reset signal P p , and output transistor 63 p . Sampling transistor 61 p The reset signal P is sampled based on the control signal p_spl, and the capacitance element 62 is p Holds the reset signal P. Output transistor 63 p In response to the control signal p_out, the output is held in the capacitor element 62. p The reset signal P in.

[0123] D phase path 60 d A sampling transistor 61 for sampling the data signal D is included. d , maintained by the sampling transistor 61 d Capacitive element 62 of the sampled data signal D d , and output transistor 63 d . Sampling transistor 61 d The data signal D is sampled based on the control signal d_spl, and the capacitance element 62 is d Holds data signal D. Output transistor 63 d In response to the control signal d_out, the output is held in the capacitor element 62. d The data signal D in .

[0124] Figure 5 The timing diagram in b shows the timing relationship among the control signal p_spl, the control signal p_out, the control signal d_spl, the control signal d_out, the input signal IN (reset signal P / data signal D), and the output signal OUT.

[0125] As described above, the sample-and-hold circuit 70A according to Reference Embodiment 1 has the P-phase path 60 in which the reset signal P is separately provided. p and a D phase path 60 for sampling and holding the data signal D d Therefore, the sampling transistor 61 p and output transistor 63 p The channel charge may be due to the path 60 p and 60 d The threshold voltage V of each transistor in th The charge injection variation causes sampling errors (i.e., fixed pattern noise of pixel columns) and is visually recognized as vertical streaks on the captured image.

[0126] Will refer to Figure 6 Describe the mechanism by which variations in charge injection cause sampling errors as described above. Figure 6 In a, for the convenience of explanation, Figure 5 The P phase path of a 60 p is taken out and shown, but with the P phase path 60 p Similar things are also in the D phase path 60 d occurs in .

[0127] In the P phase path 60 p In the case where the capacitor element 62 p The capacitance value is C p And the output transistor 63 p The capacitance value of the parasitic capacitance on the output side is c x When C p >>c x Therefore, the impedance of node S (∝1 / C p ) is lower than the output node impedance (∝1 / c x ).

[0128] like Figure 6 As shown in b, the sampling transistor 61 p In the example, when the control signal p_spl changes from high level (Hi) to low level (Lo) (time t1), about half of the channel charge (q1+q2)q2 enters the middle impedance node S side, which causes a sampling error. p In FIG, when the control signal p_out is converted from a low level to a high level (time t2), most of the channel charge q3 is supplied from the impedance node S and some of the charges accumulated at the node S are consumed, which also causes a sampling error.

[0129] (Reference Example 2)

[0130] Next, a description is given of a sample-and-hold circuit intended to suppress variations in charge injection due to switching operations at the time of sampling and holding, as a sample-and-hold circuit according to Reference Example 2. Figure 7 This is a diagram for explaining a sample-and-hold circuit 70B according to Reference Example 2.

[0131] like Figure 7 As shown, the sample-and-hold circuit 70B according to the reference embodiment 2 includes an input terminal 71, a write circuit 72, a first capacitor 73, and a second capacitor 74. p , the second capacitor 73 d , a read circuit 74 and an output terminal 75 .

[0132] The input terminal 71 receives a reset signal P and a data signal D output from each pixel 20 of the pixel array unit 11. The reset signal P is a P-phase signal at a reset level when the charge-voltage conversion unit 23 is reset. The data signal D is a D-phase signal at a signal level based on photoelectric conversion in the photoelectric conversion unit 21.

[0133] The write circuit 72 samples and writes the reset signal P and the data signal D input from the input terminal 71. The first capacitor 73 p It is a P-phase capacitance element and holds the reset signal P written by the writing circuit 72. The second capacitance element 73 d The first capacitor 73 is a capacitor element of the D phase and holds the data signal D written by the write circuit 72. The read circuit 74 reads the data held in the first capacitor 73. p The reset signal P in the second capacitor element 73 is held d The output terminal 75 outputs the reset signal P and the data signal D read by the reading circuit 74 .

[0134] Circuit Configuration Example of Write Circuit

[0135] The writing circuit 72 includes a first capacitor 73 connected to the input terminal 71. p The first charging transistor 721 between p and connected between the input terminal 71 and the second capacitor element 73 d The second charging transistor 721 between d The writing circuit 72 further includes a sampling transistor 722 for sampling the reset signal P and the data signal D input from the input terminal 71, and a first capacitor 73 connected between the sampling transistor 722 and the first capacitor 73. p The first write transistor 723 between p , and connected between the sampling transistor 722 and the second capacitor 73 d The second write transistor 723 between d .

[0136] In the writing circuit 72 having the above circuit configuration, the first charging transistor 721 p , sampling transistor 722 , first writing transistor 723 p and the first capacitive element 73 p The P phase path for sampling and holding the reset signal P is formed. In addition, the second charging transistor 721 d , sampling transistor 722 , second writing transistor 723 d and the second capacitive element 73 dA D-phase path is configured for sampling and holding the data signal D. That is, in the write circuit 72 , the sampling transistor 722 is shared by the P-phase path and the D-phase path.

[0137] By entering the on state in response to the control signal p_charge, the first charging transistor 721 p The first capacitor 73 is reset based on the reset signal P input from the input terminal 71. p By responding to the control signal d_charge and entering the conductive state, the second charging transistor 721 d The second capacitive element 73 is connected to the second capacitive element 73 based on the data signal D input from the input terminal 71. d The sampling transistor 722 samples the reset signal P and the data signal D based on the control signal spl. By entering the conductive state in response to the control signal p_splen, the first write transistor 723 p The reset signal P sampled by the sampling transistor 722 is written into the first capacitor 73. p , and the reset signal P is maintained. By entering the on state in response to the control signal d_splen, the second write transistor 723 d The data signal D sampled by the sampling transistor 722 is written into the second capacitor 73. d , and the data signal D is maintained.

[0138] Circuit Operation Example of Write Circuit

[0139] Next, we will use Figure 8 1 and 2 are used to describe an embodiment of the circuit operation of the write circuit 72.

[0140] When the control signal p_charge is at time t when the reset signal P is input from the input terminal 71 11 When the first charging transistor 721 changes from a low level to a high level, p The first capacitor 73 is turned on based on the reset signal P input from the input terminal 71. p Charge.

[0141] Next, at time t 12 , the control signal p_charge changes from a high level to a low level, so that the first charging transistor 721 p At the same time, the control signal spl and the control signal p_splen are changed from low level to high level, so that the sampling transistor 722 and the first writing transistor 723 are turned off. p As a result, the reset signal P sampled by the sampling transistor 722 passes through the first write transistor 723. p is held in the first capacitor 73p middle.

[0142] Next, at time t 13 , the control signal spl changes from a high level to a low level, and the sampling transistor 722 enters a cut-off state, thereby determining that the first capacitive element 73 p The amount of charge retained in the. 13 To time t 15 , the first capacitor element 73 p In the hold state. 13 To time t 15 During the time period of p The potential level corresponding to the amount of charge in .

[0143] The operation similar to that of the P-phase path is performed for the D-phase path. That is, when the data signal D is input from the input terminal 71 at time t 14 When the control signal d_charge changes from low level to high level, the second charging transistor 721 d The second capacitor 73 is turned on based on the data signal D input from the input terminal 71. d Charge.

[0144] Then, at time t 16 , the control signal d_charge changes from a high level to a low level, so that the second charging transistor 721 d At the same time, the control signal spl and the control signal d_splen are changed from low level to high level, so that the sampling transistor 722 and the second writing transistor 723 are turned off. d Therefore, the data signal D sampled by the sampling transistor 722 is passed through the second writing transistor 723. d The second capacitor 73 d middle.

[0145] Next, at time t 17 , the control signal spl changes from high level to low level, and the sampling transistor 722 enters the cut-off state, thereby determining the second capacitor element 73 d The amount of charge retained in the. 17 To time t 18 , the second capacitor element 73 d In the hold state. 17 To time t 18 During the time period, the reading circuit 74 can read and hold the second capacitance element 73 in the subsequent stage. d The potential level corresponding to the amount of charge in.

[0146] As described above, in the write circuit 72, at time t 11 To time t 12 During the time period, under the control of the control signal p_charge, the first capacitor element 73 p is charged to the first charging transistor 721 p The signal level input from the input terminal 71. Therefore, at time t 12 To time t 13 In a short period of time, the sampling transistor 722 and the first writing transistor 723 p The path is switched to the path at high speed, and the first capacitance element 73 can be determined. p The sampling and holding voltage (the D-phase path is also the same as the P-phase path).

[0147] Circuit Configuration Example of Read Circuit

[0148] The read circuit 74 includes a first capacitor element 73 connected to the p and the first output circuit 740 between the output terminal 75 p , connected to the second capacitor element 73 d and the second output circuit 740 between the output terminal 75 d , and reset the first and second output circuits 740 p and 740 d Each output node N out The potential of the reset transistor 743. The first output circuit 740 p and the second output circuit 740 d Each output node N out Electrically connected to output terminal 75 .

[0149] First output circuit 740 p is a P-phase output path, and includes a first capacitance element 73 connected in series p With output node N out Between the front stage output transistor 741 p and the subsequent output transistor 742 p The second output circuit 740 d is a D-phase output path, and includes a second capacitance element 73 connected in series d With output node N out Between the front stage output transistor 741 d and the subsequent output transistor 742 d The reset transistor 743 is connected to a predetermined reference potential V ref The node is connected to the output node N of the output terminal 75. out between.

[0150] In the first output circuit 740 p In the front stage, the output transistor 741 p The subsequent output transistor 742 performs on / off operation according to the control signal p_out1. p The on / off operation is performed according to the control signal p_out2. d In the front stage, the output transistor 741 d The subsequent output transistor 742 performs an on / off operation in response to the control signal d_out1. d The reset transistor 743 performs an on / off operation in response to the control signal rst.

[0151] The reading circuit 74 controls the output terminal 75 to connect the capacitor C to the capacitor C in the subsequent stage. p The first capacitive element 73 p or with capacitance C d The second capacitive element 73 d The potential level corresponding to the amount of charge retained in the capacitor is output to the column parallel analog-to-digital conversion unit 15. x There is an output node N connected to the output terminal 75 out At the parasitic capacitance c x The first capacitive element 73 is read while retaining the potential history previously read. p or the second capacitor 73 d In the case of reading, a problem occurs in which a reading error occurs depending on the reading history.

[0152] Therefore, the read circuit 74 adopts a method in which a reset output node N is provided. out The potential of the reset transistor 743 is configured, and immediately after the first capacitance element 73 is executed p or the second capacitor 73 d Before reading, the output node N out The potential is reset to the predetermined reference potential V ref . This makes it possible to prevent the above-mentioned problems in advance.

[0153] Circuit Operation Example of Read Circuit

[0154] Next, we will refer to Figure 8 The timing diagram in b describes an embodiment of the circuit operation of the read circuit 74 .

[0155] At time t 21 To time t 22 During the time period including the capacitor value Cp The first capacitive element 73 p During this sampling period, the first output circuit 740 p The front-stage output transistor 741 p The control signal p_out1 is in a high level state, and the front-stage output transistor 741 p Enter the on state.

[0156] Next, at time t 22 To time t 26 During the time period corresponding to the first capacitance element 73 p Specifically, first, the control signal p_out1 is set at time t 22 The level changes from high to low, so that the front-stage output transistor 741 p Entering the cutoff state.

[0157] Next, at time t 23 , the control signal p_out2 and the control signal rst change from low level to high level, so that the subsequent output transistor 742 p The reset transistor 743 and the reset transistor 743 both enter the on state. Therefore, the output node N of the read circuit 74 out The potential is reset to a predetermined reference potential V ref Then, at time t 24 , the control signal rst is switched from low level to high level, and the reset transistor 743 enters the cut-off state, thereby outputting the node N out The reset operation is completed.

[0158] Next, at time t 25 , the control signal p_out1 changes from low level to high level, and the front-stage output transistor 741 p Entering the conductive state again, the first capacitance element 73 p The potential level of the charge amount in the front stage output transistor 741 p and the subsequent output transistor 742 p is read out to the output terminal 75. Then, at time t 26 , the control signal p_out2 changes from high level to low level, and the subsequent output transistor 742 p Entering the cut-off state, thereby completing the P-phase (reset signal P) reading operation.

[0159] The D-phase path performs an operation similar to that of the P-phase path. That is, at time t 22 To time t 26During the time period including the capacitor value C d The second capacitive element 73 d During this sampling period, the second output circuit 740 performs sampling of the D phase (data signal D) in the D phase path of the CMOS circuit. d The front-stage output transistor 741 d The control signal d_out1 is in a high level state, and the front stage output transistor 741 d Enter the on state.

[0160] Next, at time t 26 To time t 30 During the period of time, the operation corresponding to the operation held in the second capacitance element 73 is performed. d Specifically, first, at time t 26 , the control signal d_out1 changes from high level to low level, so that the front stage output transistor 741 d Entering the cutoff state.

[0161] Then, at time t 27 , the control signal d_out2 and the control signal rst are changed from low level to high level, so that the subsequent output transistor 742 d The reset transistor 743 and the reset transistor 743 both enter the on state. Therefore, the output node N of the read circuit 74 out The potential is reset to a predetermined reference potential V ref Then, at time t 28 , the control signal rst changes from low level to high level, and the reset transistor 743 enters the cut-off state, thereby completing the output node N out Reset.

[0162] Next, at time t 29 , the control signal d_out1 changes from low level to high level, and the front-stage output transistor 741 d Entering the conduction state again, the output transistor 741 of the previous stage d and the subsequent output transistor 742 d The second capacitor element 73 d The potential level corresponding to the amount of charge in is read out to the output terminal 75. Then, at time t 30 , the control signal d_out2 changes from high level to low level, and the subsequent output transistor 742 d Entering the cut-off state, thereby completing the D-phase (data signal D) reading operation.

[0163] In the sample-and-hold circuit 70B according to the above-described reference embodiment 2, for example, in the write circuit 72, a sampling error due to feedthrough and charge injection of the sampling transistor 722 shared by the P-phase and D-phase is detected in the first capacitance element 73. p and the second capacitive element 73 d Therefore, for example, by the CDS process performed in the column parallel analog-to-digital conversion unit 15, the first capacitance element 73 can be eliminated. p and the second capacitive element 73 d That is, the sample-and-hold circuit 70B according to Reference Embodiment 2 can solve the problem of the sample-and-hold circuit 70A according to Reference Embodiment 1, that is, the problem of sampling error caused by variation in charge injection.

[0164] However, the sample-hold circuit 70B according to Reference Embodiment 2 has a circuit configuration requiring five transistors for each of the write circuit 72 and the read circuit 74, that is, ten transistors in total, and the number of transistors constituting the sample-hold circuit 70B is very large. Moreover, since the sample-hold circuit 70B has a circuit configuration requiring five transistors for each of the write circuit 72 and the read circuit 74, that is, ten transistors in total, the number of transistors constituting the sample-hold circuit 70B is very large. Figure 8 There are many forward and backward constraints on the conversion timing of the control signals in the arrows (→) in a and b, so there is a problem of large timing overhead.

[0165] <Sample-and-Hold Circuit According to Embodiment of the Present Technology>

[0166] The sample-and-hold circuit according to the embodiment of the present technology has a simpler circuit configuration (simpler than the sample-and-hold circuit 70B according to Reference Example 2) to suppress sampling errors due to variations in charge injection in the sample-and-hold circuit 70A according to Reference Example 1.

[0167] [Example 1]

[0168] Example 1 is an example of a circuit configuration of a sample-and-hold circuit according to an embodiment of the present technology. Figure 9 is a circuit diagram showing a circuit configuration example of a sample-and-hold circuit according to an embodiment of the present technology.

[0169] like Figure 9 As shown, the sample-and-hold circuit 70 according to the embodiment of the present technology includes an input terminal 701 , a P-phase circuit 702 , a D-phase circuit 703 , a reset transistor 704 , and an output terminal 705 .

[0170] The pixel signal output from the pixel 20 through the signal line 32 is supplied to the input terminal 701. The pixel signal includes a reset signal P at a reset level when resetting the charge-voltage conversion unit 23 and a data signal D at a signal level based on photoelectric conversion. The input terminal 701 receives the reset signal P and the data signal D supplied from the signal line 32.

[0171] The P-phase circuit 702 includes a first capacitive element 711 p , the first sampling transistor 712 p , first write transistor 713 p and the first read transistor 714 p .

[0172] In the P-phase circuit 702, the first capacitor 711 p One end of the first sampling transistor 712 is connected to a power supply (eg, ground). p connected in series to the first capacitor element 711 p The first write transistor 713 p The first sampling transistor 712 is connected to the input terminal 701 p and enters a conductive state in response to a control signal p_writeen supplied to the gate electrode to transmit a reset signal P input from the input terminal 701 through the first sampling transistor 712. p Writing into the first capacitor element 711 p The first read transistor 714 p Connected to the first sampling transistor 712 p and the output terminal 705, and enters the on state in response to the control signal p_read supplied to the gate electrode to conduct the current through the first sampling transistor 712. p Read and write the first capacitor element 711 p The reset signal P in.

[0173] The D-phase circuit 703 includes a second capacitor 711 d , the second sampling transistor 712 d , second write transistor 713 d and the second read transistor 714 d .

[0174] In the D-phase circuit 703, the second capacitor 711 d One end of the second sampling transistor 712 is connected to a power supply (eg, ground). d and the second capacitor element 711 d connected in series. Second write transistor 713 d The input terminal 701 is connected to the second sampling transistor 712 dand enters the on state in response to the control signal d_writeen supplied to the gate electrode to conduct the current through the second sampling transistor 712 d The data signal D input from the input terminal 701 is written into the second capacitor 711. d The second read transistor 714 d Connected to the second sampling transistor 712 d and the output terminal 705, and enters the on state in response to the control signal d_read supplied to the gate electrode to conduct the current through the second sampling transistor 712. d Read and write the second capacitor element 711 d The data signal D in .

[0175] The reset transistor 704 is connected between the output terminal 705 and a predetermined reference potential V ref The output terminal 705 and the first read transistor 714 p and the second read transistor 714 d The path between is for the first capacitance element 711 p Read the reset signal P and the second capacitor element 711 d The signal reading path L reads the data signal D. The reset transistor 704 enters the conductive state in response to the control signal rst to reset the potential of the signal reading path L to a predetermined reference potential V ref .

[0176] The sample-and-hold circuit 70 having the above-described configuration according to the embodiment of the present technology uses, for example, an NMOS transistor as the first sampling transistor 712. p and the second sampling transistor 712 d , first write transistor 713 p and the second write transistor 713 d , first read transistor 714 p and the second read transistor 714 d , and reset transistor 704.

[0177] [Example 2]

[0178] Example 2 is an example (Part 1) of the circuit operation of the sample-and-hold circuit according to the embodiment of the present technology. Figure 10 1 is a timing chart showing circuit operation example 1 of the sample-and-hold circuit according to the embodiment of the present technology.

[0179] Figure 10The timing diagram shows the timing relationship between the control signal p_writeen, the control signal p_spl and the P-phase control signal p_read, the control signal d_writeen, the control signal d_spl and the D-phase control signal d_read and the control signal rst. These control signals are Figure 1 The timing control unit 19 generates as shown.

[0180] At time t 31 , the control signal p_writeen and the control signal p_spl are switched from low level to high level, so that the first write transistor 713 p and the first sampling transistor 712 p Enters the on state and executes the reset signal P to the first capacitor element 711 p write operation.

[0181] At time t 32 , the control signal p_spl changes from high level to low level, and the first sampling transistor 712 p Entering the cut-off state, thereby confirming that the first capacitor element 711 p Sampling of the reset signal P in .

[0182] Then, at time t 33 , the control signal p_writeen changes from high level to low level, the first write transistor 713 p At the same time, the control signal p_read is switched from low level to high level, and the first read transistor 714 p Enter the on state.

[0183] At the same time, at time t 33 , the control signal rst changes from a low level to a high level, and the reset transistor 704 enters a conductive state, so that the execution will include the first read transistor 714 p The potential of the signal reading path L is reset to a predetermined reference potential V ref By this reset operation, the history of previous read operations can be erased.

[0184] Next, at time t 34 , the control signal rst changes from high level to low level, and the reset transistor 704 enters the cut-off state. Thereafter, at time t 35 , the control signal p_spl changes from low level to high level, and the first sampling transistor 712 p As a result, the first read transistor 714 is executed. p Writing into the first capacitor 711 pIn parallel with the read operation of the reset signal P, an analog-to-digital conversion (ADC) process is performed.

[0185] At the same time, at time t 35 , the control signal d_writeen and the control signal d_spl are switched from low level to high level, so that the second write transistor 713 d and the second sampling transistor 712 d Enters the on state and executes the data signal D to the second capacitor element 711 d write operation.

[0186] At time t 36 , the control signal d_spl changes from high level to low level, and the second sampling transistor 712 d Entering the cut-off state, thereby confirming that the second capacitor element 711 d Sampling of the data signal D in .

[0187] Then, at time t 37 , the control signal d_writeen changes from high level to low level, and the second write transistor 713 d At the same time, the control signal d_read is switched from low level to high level, and the second read transistor 714 d Enter the on state.

[0188] At the same time, at time t 37 , the control signal rst changes from a low level to a high level, and the reset transistor 704 enters a conductive state, so that the execution will include the second read transistor 714 d The potential of the signal reading path L is reset to a predetermined reference potential V ref By this reset operation, the history of previous read operations can be erased.

[0189] Next, at time t 38 , the control signal rst changes from high level to low level, and the reset transistor 704 enters the cut-off state. Thereafter, at time t 39 , the control signal d_spl changes from a low level to a high level, and the second sampling transistor 712 d Enters the on state. Therefore, the second read transistor 714 is executed d Writing into the second capacitor 711 d The analog-to-digital conversion process is performed in parallel with the reading operation of the data signal D.

[0190] As described above, in the imaging element 10 including the sample-and-hold circuit 70 according to the embodiment of the present technology, in Circuit Operation Example 1, P-phase writing (sampling) and reading and D-phase writing (sampling) and reading are pipelined, and signal reading and analog-to-digital conversion from the pixel 20 are processed in parallel. Therefore, the pixel signal reading operation including the analog-to-digital conversion process can be substantially accelerated.

[0191] (Consideration of sampling error)

[0192] Here, we will refer to Figure 11 a and b in _ take into account the sampling error in the sample-and-hold circuit 70 according to the embodiment of the present technology. Figure 11 In a, for the convenience of description, it is taken out and shown Figure 9 The P-phase circuit 702 in a, but similar matters to those in the P-phase circuit 702 apply to the D-phase circuit 703.

[0193] exist Figure 10 In the timing diagram, when the first sampling transistor 712 p At time t 32 When entering the cut-off state, Figure 11 As shown in b, the first sampling transistor 712 p About half of the channel charge (q1+q2) is allocated to node A, and the remaining about half, q2, is allocated to node B. The previous charge q1 is erased in the path from node A to input terminal 701. The latter charge q2 becomes the charge of the sampling error.

[0194] like Figure 11 As shown in b, when at time t 35 The first sampling transistor 712 p When the first sampling transistor 712 is turned on, the supply from node B p The charge q2 is at time t 32 generated and only returns to the first sampling transistor 712 again p Therefore, the charge q1 affects the sampling error when the signal is read. Here, it is assumed that the first capacitor element 711 p If the capacitance value is C, the sampling error voltage V provided is V=q1 / C.

[0195] As described above, in the sample-and-hold circuit 70 according to the embodiment of the present technology, only the first sampling transistor 712 p and the second sampling transistor 712 d The charge q1 of about half of the channel charge (q1+q2) ultimately affects the sampling error.p and 712 d Transistors other than the CMOS do not affect the sampling error.

[0196] For the first write transistor 713 p and the second write transistor 713 d , by starting from time t 33 To time t 34 The reset operation at time t 33 The first write transistor 713 p and the second write transistor 713 d The charge injection that occurs at node A when entering the off state is erased. Therefore, the first write transistor 713 p and the second write transistor 713 d It does not affect the sampling error.

[0197] For the first read transistor 714 p and the second read transistor 714 d , in the first read transistor 714 p and the second read transistor 714 d Signal reading is performed after initialization in the on state. Therefore, the first read transistor 714 p and the second read transistor 714 d It does not affect the sampling error.

[0198] When the reset transistor 704 is at time t 34 When switching from the on state to the off state, charge injection occurs at the node A and the output terminal 705, but the charge injection can be removed by CDS processing performed in the subsequent stage in the analog-to-digital conversion unit 15. Therefore, the reset transistor 704 does not affect the sampling error.

[0199] As is apparent from the above considerations regarding sampling errors, the sample-and-hold circuit 70 according to the embodiment of the present technology can suppress sampling errors caused by variations in charge injection. Compared to the circuit configuration of the sample-and-hold circuit 70B according to Reference Example 2, which requires ten transistors, this circuit configuration is a simpler circuit configuration that can be configured with only seven transistors. In other words, the sample-and-hold circuit 70 according to the embodiment of the present technology can achieve the intended purpose with a simpler circuit configuration.

[0200] (About transistor configuration)

[0201] In the sample-and-hold circuit 70 according to the above-described embodiment, an example has been given in which an NMOS transistor is used as the first sampling transistor 712. p and the second sampling transistor 712 d , first write transistor 713p and the second write transistor 713 d , first read transistor 714 p and the second read transistor 714 d , and the configuration of the reset transistor 704, but the present disclosure is not limited to NMOS transistors. That is, PMOS transistors or CMOS transistors can be used.

[0202] When the potential of the input signal is low, it is preferred to use an NMOS transistor. Conversely, when the potential of the input signal is high, it is preferred to use a PMOS transistor. In the case where the input signal has a wide range from low to high, it is preferred to use a CMOS transistor. However, in the case of a CMOS transistor, since the number of elements constituting the transistor circuit is doubled, the change in charge injection is generally greater than that in the case of a single NMOS transistor or PMOS transistor.

[0203] In the sample-and-hold circuit 70 according to the embodiment of the present technology, only the first sampling transistor 712 p and the second sampling transistor 712 d By configuring the first and second sampling transistors 712 with transistors having relatively small sizes, the sampling error is affected. p and 712 d , the sampling error can be further suppressed. In addition, by p and the second sampling transistor 712 d The transistors other than the transistors are configured as transistors with relatively large sizes, which can achieve higher speed operation.

[0204] [Example 3]

[0205] Example 3 is an example (Part 2) of the circuit operation of the sample-and-hold circuit according to the embodiment of the present technology. Figure 12 1 is a timing chart showing circuit operation example 2 of the sample-and-hold circuit according to the embodiment of the present technology.

[0206] Figure 12 The timing diagram shows the timing relationship between the control signal p_writeen, the control signal p_spl, the P-phase control signal p_read, the control signal d_writeen, the control signal d_spl, the D-phase control signal d_read, and the control signal rst. In Circuit Operation Example 2, the control signal p_spl and the control signal d_spl are always fixed at a high level (Hi), and the control signal rst is always fixed at a low level (Lo).

[0207] At time t 41 When the control signal p_writeen changes from low level to high level, the first write transistor 713p Enters the on state, and through the first sampling transistor 712 which is always in the on state p The reset signal P is applied to the first capacitor element 711. p write operation.

[0208] Then, at time t 42 , the control signal p_writeen changes from high level to low level, the first write transistor 713 p Enters the cut-off state. Thereafter, at time t 43 , the control signal p_read is switched from a low level to a high level, and the first read transistor 714 p As a result, the first sampling transistor 712 is always in the on state. p , by the first read transistor 714 p Write to the first capacitor element 711 p In parallel with the read operation of the reset signal P, an analog-to-digital conversion process is performed.

[0209] At the same time, at time t 43 When the control signal d_writeen changes from low level to high level, the second write transistor 713 d Enters the on state, and through the second sampling transistor 712 which is always in the on state d The data signal D is sent to the second capacitor element 711. d write operation.

[0210] Then, at time t 44 , the control signal d_writeen changes from high level to low level, the second write transistor 713 d Enters the cut-off state. Thereafter, at time t 45 , the control signal d_read is switched from a low level to a high level, and the second read transistor 714 d Therefore, the second read transistor 714 is always in the on state. d Through the second sampling transistor 712 d Write to the second capacitor 711 d The analog-to-digital conversion process is performed in parallel with the reading operation of the data signal D.

[0211] As described above, in the imaging element 10 including the sampling and holding circuit 70 according to an embodiment of the present technology, in circuit operation embodiment 2, similar to the case of circuit operation embodiment 1, the P-phase writing and reading and the D-phase writing (sampling) and reading are pipelined, and the signal reading and analog-to-digital conversion from the pixel 20 are processed in parallel. Therefore, the pixel signal reading operation including the analog-to-digital conversion processing can be substantially accelerated. In addition, in circuit operation embodiment 2, since the control signal p_spl and the control signal d_spl are always fixed to the high level (Hi) and the control signal rst is always fixed to the low level (Lo), the time overhead between the writing operation and the reading operation of the reset signal P and the data signal D can be minimized, thereby further accelerating the pixel signal reading operation.

[0212] [Example 4]

[0213] Example 4 is an example of a driving mode of the imaging element 10 including the sample-and-hold circuit 70 according to the embodiment of the present technology.

[0214] The imaging element 10 including the sample-and-hold circuit 70 according to an embodiment of the present technology has two drive modes: a low-error drive mode and a high-speed drive mode. The low-error drive mode is a drive mode suitable for use in still image capture, etc. In the low-error drive mode, the sample-and-hold circuit 70 performs circuit operations based on the circuit operation embodiment 1 according to embodiment 2. The high-speed drive mode is a drive mode suitable for use in moving image capture, etc. In the high-speed drive mode, the sample-and-hold circuit 70 performs circuit operations based on the circuit operation embodiment 2 according to embodiment 3.

[0215] As described above, in the imaging element 10 having both the low-error driving mode and the high-speed driving mode, even in the sampling and holding circuit 70 having the same circuit configuration, the emphasis characteristics or the operation speed can be selected by using the driving method of the sampling and holding circuit 70.

[0216] [Example 5]

[0217] Example 5 is an example of the arrangement of the sample-and-hold circuit 70 according to an embodiment of the present technology. Figure 13 1 is a block diagram showing an arrangement example of the sample and hold circuit 70 according to an embodiment of the present technology. Here, arrangement example 1 and arrangement example 2 are shown as arrangement examples of the sample and hold circuit 70.

[0218] exist Figure 13, a shows an arrangement example 1 of the sample-and-hold circuit 70. Arrangement example 1 has a configuration in which the input terminal of the sample-and-hold circuit 70 is directly electrically connected to the signal line 32. That is, in arrangement example 1, the sample-and-hold circuit 70 directly samples the reset signal P and the data signal D output from the pixel 20 through the signal line 32.

[0219] exist Figure 13 , b shows an arrangement example 2 of the sample-and-hold circuit 70. Arrangement example 2 has a configuration in which the input terminal of the sample-and-hold circuit 70 is electrically connected to the signal line 32 via the amplifier 80. That is, in arrangement example 2, the amplifier 80 is provided between the signal line 32 and the sample-and-hold circuit 70, and the reset signal P and the data signal D supplied from the signal line 32 are once amplified by the amplifier 80 and then sampled by the sample-and-hold circuit 70. According to arrangement example 2, it is possible to reduce the noise of the input conversion after the sample-and-hold circuit 70.

[0220] [Example 6]

[0221] Example 6 is an example of switching the power supply path of the low potential side power supply of the capacitive element in the sample and hold circuit 70 according to the embodiment of the present technology. Figure 14 is a circuit diagram for explaining power supply switching of the sample-and-hold circuit 70 according to an embodiment of the present technology.

[0222] like Figure 14 As shown, the sampling and holding circuit 70 according to the sixth embodiment includes a power supply path switching unit 710 in a P-phase circuit 702. p and the power supply path switching unit 710 in the D-phase circuit 703 d .

[0223] In the P-phase circuit 702, the power supply path switching unit 710 p including a first capacitor element 711 connected to p The transistor 715 between the power supply side terminal (low potential side terminal) of the first power supply path and the second power supply path p and transistor 716 p The first power supply path and the second power supply path are electrically separated power supply paths. p When the control signal p_vss0en applied to the gate electrode is written to the signal on, the transistor 715 enters the on state. p The first capacitor element 711 p The power supply side terminal is electrically connected to the first power supply path. p When reading a signal, the transistor 716 enters a conducting state in response to a control signal p_vsslen applied to the gate electrode. pThe first capacitor element 711 p The power supply side terminal is electrically connected to the second power supply path.

[0224] In the D-phase circuit 703, the power supply path switching unit 710 d including a second capacitor element 711 connected d The transistor 715 between the power supply side terminal (low potential side terminal) of the first power supply path and the second power supply path d and transistor 716 d The first power supply path and the second power supply path are electrically separated power supply paths. d When the control signal d_vss0en applied to the gate electrode is written to the signal on, the transistor 715 enters the on state. d The second capacitor element 711 d The power supply side terminal is electrically connected to the first power supply path. d When the signal is read, the control signal d_vsslen applied to the gate electrode enters the on state, and the transistor 716 d The second capacitor element 711 d The power supply side terminal is electrically connected to the second power supply path.

[0225] In the sample-and-hold circuit 70 according to the embodiment of the present technology, when the above-described pipeline processing is performed, the first capacitive element 711 is written. p and the second capacitor 711 d A large current is generated during charging and discharging. The IR drop of the low-potential side power supply (eg, ground) caused by the write operation causes crosstalk that fluctuates the signals read in parallel.

[0226] On the other hand, in the sample-and-hold circuit 70 according to the fifth embodiment, the first capacitance element 711 p and the second capacitor 711 d At the time of signal writing and signal reading, the power supply path of the low potential side power supply is switched to the electrically separated first power supply path and second power supply path, so that crosstalk as described above can be reduced.

[0227] [Example 7]

[0228] Example 7 is an example of a wiring structure of a sample-and-hold circuit 70 according to an embodiment of the present technology. Figure 15 1 is a diagram for explaining the wiring structure of the sample-and-hold circuit 70 according to the embodiment of the present technology.

[0229] In the embodiment 6 Figure 14 In the sample-and-hold circuit 70 of the circuit configuration shown in FIG, the first capacitive element 711p With the first sampling transistor 712 p The wiring between is defined as B0, and the second capacitance element 711 d With the second sampling transistor 712 d The wiring between is defined as B1. In addition, the first capacitor element 711 p With transistor 715 p and 716 p The wiring between is defined as C0, and the second capacitance element 711 d With transistor 715 d and 716 d The wiring between them is defined as C1.

[0230] exist Figure 15 In the figure, a is a diagram showing a first capacitor element 711. p and the second capacitor 711 d And a conceptual diagram of an element layer 91 of various transistors and a wiring layer 92 including wirings B0, B1, C0 and C1. Figure 15 b is the first capacitance element 711 p It should be noted that in Figure 15 In the conceptual diagram of a, for the convenience of description, the element layer 91 and the wiring layer 92 are shown side by side, but in reality, Figure 15 As shown in FIG. 1 b , the element layer 91 and the wiring layer 92 are in a layered relationship.

[0231] As from Figure 15 As is apparent from FIG. 2 b, the wiring structure according to Example 7 has a wiring structure in which the wirings B0 and B1 are shielded by the wirings C0 and C1. In this way, by shielding the wirings B0 and B1 with the wirings C0 and C1, the noise and crosstalk resistance can be improved.

[0232] Furthermore, in the wiring structure according to Example 7, it is desirable that the wiring lengths of wirings B0 and B1 be as equal as possible. Here, "equal length" means not only that the lengths are strictly equal, but also that the lengths are substantially equal, and various variations caused by design or manufacturing are allowed. By setting the wiring lengths of wirings B0 and B1 to be as equal as possible, sampling errors and interference of the P-phase and D-phase can be aligned and removed through CDS processing performed in the analog-to-digital conversion unit 15 in the subsequent stage.

[0233] <Modification>

[0234] It should be noted that the above-described embodiments represent examples for embodying the present technology, and that the various contents in the embodiments correspond to the various contents specifying the present invention in the claims. Similarly, the matters specifying the present invention in the claims and the matters with the same names in the embodiments of the present technology each correspond to each other. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the scope of the present technology.

[0235] <Application Examples of Electronic Devices>

[0236] The imaging element according to the above-mentioned embodiment of the present technology can be applied to various electronic devices with imaging functions, such as, imaging devices such as digital still cameras or video cameras, mobile terminal devices with imaging functions (such as mobile phones), and copiers using imaging devices in image reading units.

[0237] [Embodiment of Imaging Device]

[0238] Figure 16 is a block diagram illustrating a configuration example of an imaging device to which an embodiment of an electronic device of the present technology is applied.

[0239] The imaging device 100 according to the present application embodiment is a device for imaging a subject, and includes an imaging optical system 101 including a lens group, etc., an imaging unit 102, a digital signal processor (DSP) circuit 103, a display unit 104, an operation unit 105, a storage unit 106, and a power supply unit 107. These are connected to each other via a bus 108. As the imaging device 100, for example, in addition to digital cameras such as digital still cameras, smartphones and personal computers having an imaging function, in-vehicle cameras, and the like are also assumed.

[0240] The imaging unit 102 generates pixel data through photoelectric conversion. The imaging element in the embodiment of the present technology can be used as the imaging unit 102. Light from a subject is condensed by the imaging optical system 101 arranged on the incident light side and guided to the light receiving surface of the imaging unit 102. The imaging unit 102 supplies the pixel data generated through photoelectric conversion to the DSP circuit 103 at the subsequent stage.

[0241] The DSP circuit 103 performs predetermined signal processing on the pixel data from the imaging unit 102. The display unit 104 displays the pixel data. As the display unit 104, for example, a liquid crystal panel or an organic electroluminescent (EL) panel is assumed. The operation unit 105 generates an operation signal based on a user operation. The storage unit 106 stores various types of data, such as pixel data. The power supply unit 107 supplies power to the imaging unit 102, the DSP circuit 103, the display unit 104, and the like.

[0242] In the imaging device 100 having the above configuration, the imaging element 10 including the sample-and-hold circuit 70 according to the embodiment of the present technology can be installed as the imaging unit 102. According to the imaging element 10, it is possible to suppress fixed pattern noise in pixel columns by reducing variations in charge injection caused by switching operations during sampling and holding. Consequently, vertical streaks caused by fixed pattern noise in pixel columns do not appear in captured images, resulting in a captured image with high image quality.

[0243] <Application Examples of Embodiments of the Present Technology>

[0244] The above-described embodiments of the present technology can be applied to various technologies as exemplified below.

[0245] Figure 17 Examples of fields to which embodiments of the present technology are applied are shown.

[0246] For example, the imaging device according to the embodiment of the present technology can be used as a device that captures images for viewing, such as a digital camera or a portable device having a camera function.

[0247] In addition, the imaging device can be used as a device for traffic purposes, such as an on-board sensor for capturing images of a car's surroundings, interior, etc., a surveillance camera for monitoring moving vehicles and roads, and a ranging sensor for measuring the distance between vehicles, etc. for safe driving (such as automatic stopping, identification of driver conditions, etc.).

[0248] In addition, the imaging device can be used as a device for home appliances such as televisions, refrigerators, and air conditioners to capture an image of a user's gesture and perform device operations according to the gesture.

[0249] Furthermore, the imaging device can be used as equipment for medical and healthcare use, such as an endoscope and an equipment that performs angiography by receiving infrared light.

[0250] Furthermore, the imaging device can be used as a device for security use, such as a security monitoring camera and a personal authentication camera.

[0251] Furthermore, the imaging device can be used as a device for beauty care, such as a skin measurement instrument for imaging the skin and a microscope for imaging the scalp.

[0252] In addition, the imaging device can be used as a device for sports, such as an action camera or a wearable camera for sports applications.

[0253] Furthermore, the imaging device may be used as a device for agriculture, such as a camera for monitoring the conditions of fields or crops.

[0254] <Application examples for mobile objects>

[0255] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any type of mobile object (such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, aircraft, drone, ship, or robot).

[0256] Figure 18 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0257] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 18 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated as functional components of the integrated control unit 12050.

[0258] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating the vehicle's drive force, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, a braking device for generating the vehicle's braking force, and the like.

[0259] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device as a substitute for key buttons or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0260] The vehicle exterior information detection unit 12030 detects information outside the vehicle, including information about the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. Furthermore, the vehicle exterior information detection unit 12030 can also detect objects such as people, vehicles, obstacles, signs, and text on the road, or detect their distance based on the received image.

[0261] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as information about the measured distance. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0262] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver is dozing off.

[0263] The microcomputer 12051 can calculate control target values for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, follow-up driving based on a following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from a lane, and the like.

[0264] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, which enables the vehicle to travel automatically without relying on the driver's operation, etc.

[0265] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for preventing glare by controlling the headlights to change from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0266] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Figure 18 In the embodiment of FIG, audio speakers 12061, a display portion 12062, and an instrument panel 12063 are illustrated as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0267] Figure 19 12031 is a view showing an embodiment of the installation position of the imaging unit 12031.

[0268] exist Figure 19 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 and 12105 .

[0269] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed, for example, at locations within the interior of vehicle 12100, such as the front nose, side-view mirrors, rear bumper, rear door, and the upper portion of the windshield. Imaging unit 12101 disposed within the vehicle's interior at the front nose and imaging unit 12105 disposed within the upper portion of the windshield primarily capture images of the front of vehicle 12100. Imaging units 12102 and 12103 disposed within the side-view mirrors primarily capture images of the sides of vehicle 12100. Imaging unit 12104 disposed within the rear bumper or rear door primarily captures images of the rear of vehicle 12100. Imaging unit 12105 disposed within the upper portion of the windshield primarily detects vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0270] Please note that Figure 19 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located on the rear bumper or rear door. For example, a bird's-eye view image of vehicle 12100 viewed from above can be obtained by superimposing image data captured by imaging units 12101 to 12104.

[0271] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0272] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100) based on the distance information obtained from imaging units 12101 to 12104. This can then extract objects that are on the path of vehicle 12100 and traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, microcomputer 12051 can pre-set a following distance to maintain a position ahead of the preceding vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), and the like. This enables coordinated control for autonomous driving, enabling the vehicle to travel independently of driver input.

[0273] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as those that are visually recognizable by the driver of vehicle 12100 and those that are difficult for the driver of vehicle 12100 to visually recognize. Microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, indicating a potential collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collisions.

[0274] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, identify pedestrians by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points representing the outline of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline for emphasis superimposed on the identified pedestrian. The audio / video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0275] An embodiment of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. For example, in the above-described configuration, the technology according to the present disclosure can be applied to the imaging unit 12031. Then, in the case where the imaging unit 12031 or the like includes a sampling and holding unit at the preceding stage of a column-parallel analog-to-digital conversion unit, the technology according to the present disclosure can be applied to each sampling and holding circuit constituting the sampling and holding unit. As a result, the fixed pattern noise of the pixel column can be suppressed by reducing the variation in charge injection due to the switching operation during sampling and holding. Therefore, vertical stripes caused by the fixed pattern noise of the pixel column do not appear on the captured image, and a captured image with high image quality can be obtained.

[0276] It should be noted that the effects described herein are merely illustrative and not restrictive, and other effects may also be present.

[0277] <Configurations that this technology can adopt>

[0278] It should be noted that the present technology can also have the following configurations.

[0279] (1) An imaging element comprising:

[0280] a pixel array unit in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels including a photoelectric conversion unit; and

[0281] The sampling and holding circuit is provided corresponding to the pixel column of the pixel array unit and samples and holds the pixel signal including the reset signal and the data signal output from the pixel through the signal line, wherein

[0282] The sample-and-hold circuit includes:

[0283] a first capacitive element;

[0284] a first sampling transistor connected in series to the first capacitive element;

[0285] a first writing transistor connected between an input terminal configured to receive a reset signal and the first sampling transistor, and writing the reset signal input from the input terminal into the first capacitance element through the first sampling transistor;

[0286] a first reading transistor connected between the first sampling transistor and the output terminal, and configured to read the reset signal written into the first capacitance element via the first sampling transistor;

[0287] a second capacitive element;

[0288] a second sampling transistor connected in series to a second capacitive element;

[0289] a second writing transistor connected between an input terminal configured to receive a data signal and the second sampling transistor, and writing the data signal input from the input terminal into the second capacitance element through the second sampling transistor;

[0290] a second reading transistor connected between the second sampling transistor and the output terminal and configured to read a data signal written in the second capacitance element via the second sampling transistor; and

[0291] The reset transistor is connected between the output terminal and a node of a predetermined reference potential.

[0292] (2) The imaging element according to (1), wherein

[0293] Each of the first sampling transistor and the second sampling transistor includes a transistor having a relatively small size.

[0294] (3) The imaging element according to (2), wherein

[0295] Each of the first write transistor, the first read transistor, the second write transistor, the second read transistor, and the reset transistor includes a transistor having a relatively large size.

[0296] (4) The imaging element according to any one of (1) to (3), wherein

[0297] The first write transistor and the first sampling transistor enter an on-state and a reset signal is written to the first capacitance element, then the first sampling transistor enters an off-state, then the first read transistor and the reset transistor enter an on-state, and the signal read path is initialized, then the first sampling transistor enters an on-state and the reset signal written to the first capacitance element is read through the signal read path, and

[0298] Thereafter, the second write transistor and the second sampling transistor enter an on state and the data signal is written to the second capacitance element, then the second sampling transistor enters an off state, then the second read transistor and the reset transistor enter an on state, and the signal read path is initialized, then the second sampling transistor enters an on state and the data signal written to the second capacitance element is read through the signal read path.

[0299] (5) The imaging element according to any one of (1) to (3), wherein

[0300] In a state where the first sampling transistor and the second sampling transistor are always in the on state and the reset transistor is always in the off state,

[0301] The first write transistor enters an on state and a reset signal is written to the first capacitance element, and then the first read transistor enters an on state and reads the reset signal written to the first capacitance element, and

[0302] Thereafter, the second write transistor enters an on state and the data signal is written to the second capacitance element, and then the second read transistor enters an on state and reads the data signal written to the second capacitance element.

[0303] (6) The imaging element according to any one of (1) to (5), further comprising:

[0304] The amplifier is arranged between the signal line and the sample-and-hold circuit.

[0305] (7) The imaging element according to any one of (1) to (3), wherein

[0306] Provides low error driving mode and high speed driving mode,

[0307] In low error drive mode,

[0308] The first write transistor and the first sampling transistor enter an on-state and a reset signal is written to the first capacitance element, then the first sampling transistor enters an off-state, then the first read transistor and the reset transistor enter an on-state and a signal read path is initialized, then the first sampling transistor enters an on-state and the reset signal written to the first capacitance element is read through the signal read path, and

[0309] Thereafter, the second write transistor and the second sampling transistor enter an on state and the data signal is written to the second capacitance element, then the second sampling transistor enters an off state, then the second read transistor and the reset transistor enter an on state and the signal read path is initialized, then the second sampling transistor enters an on state and the data signal written to the second capacitance element is read through the signal read path, and

[0310] In high-speed driving mode,

[0311] In a state where the first sampling transistor and the second sampling transistor are always in the on state and the reset transistor is always in the off state,

[0312] The first write transistor enters an on state and a reset signal is written to the first capacitance element, and then the first read transistor enters an on state and reads the reset signal written to the first capacitance element, and

[0313] Thereafter, the second write transistor enters an on state and the data signal is written to the second capacitance element, and then the second read transistor enters an on state and the data signal written to the second capacitance element is read.

[0314] (8) The imaging element according to any one of (1) to (3), wherein

[0315] The sample-and-hold circuit includes a power supply path switching unit that connects a terminal on a power supply side of each of the first capacitive element and the second capacitive element to electrically separated different power supply paths when writing a signal to the first capacitive element and the second capacitive element and when reading a signal from the first capacitive element and the second capacitive element.

[0316] (9) The imaging element according to (8), wherein

[0317] The sample-and-hold circuit has a wiring structure in which wiring between the first capacitance element and the first sampling transistor and wiring between the second capacitance element and the second sampling transistor are shielded by wiring between the first capacitance element and the power supply path switching unit and wiring between the second capacitance element and the power supply path switching unit.

[0318] (10) The imaging element according to (9), wherein

[0319] In the wiring structure, a wiring length of wiring between the first capacitance element and the first sampling transistor is equal to a wiring length of wiring between the second capacitance element and the second sampling transistor.

[0320] (11) An electronic device comprising an imaging element, the imaging element comprising:

[0321] a pixel array unit in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels including a photoelectric conversion unit; and

[0322] The sampling and holding circuit is provided corresponding to the pixel column of the pixel array unit and samples and holds the pixel signal including the reset signal and the data signal output from the pixel through the signal line, wherein

[0323] The sample-and-hold circuit includes:

[0324] a first capacitive element;

[0325] a first sampling transistor connected in series to the first capacitive element;

[0326] a first writing transistor connected between an input terminal configured to receive a reset signal and the first sampling transistor, and writing the reset signal input from the input terminal into the first capacitance element through the first sampling transistor;

[0327] a first reading transistor connected between the first sampling transistor and the output terminal, and configured to read the reset signal written into the first capacitance element via the first sampling transistor;

[0328] a second capacitive element;

[0329] a second sampling transistor connected in series to a second capacitive element;

[0330] a second writing transistor connected between an input terminal configured to receive a data signal and the second sampling transistor, and writing the data signal input from the input terminal into the second capacitance element through the second sampling transistor;

[0331] a second reading transistor connected between the second sampling transistor and the output terminal and configured to read a data signal written into the second capacitance element through the second sampling transistor; and

[0332] The reset transistor is connected between the output terminal and a node of a predetermined reference potential.

[0333] Reference Symbols List

[0334] 10 Imaging elements of this technology

[0335] 11 pixel array unit

[0336] 12 vertical scanning units

[0337] 13 load MOS units

[0338] 14 Sample and hold units

[0339] 15 analog-to-digital conversion unit

[0340] 16 storage units

[0341] 17 Data processing unit

[0342] 18 output units

[0343] 19 Timing control unit

[0344] 20 pixels (pixel circuit)

[0345] 21 Photodiode (photoelectric conversion unit)

[0346] 22 charge transfer units

[0347] 23 Charge-voltage conversion unit

[0348] 24 Charge reset unit

[0349] 25 Signal Amplification Unit

[0350] 26 pixel selection unit

[0351] 31 pixel control lines

[0352] 32 signal lines

[0353] 40 Reference signal generation unit

[0354] 50 single slope analog-to-digital conversion circuit

[0355] 70 Sample and hold circuit according to an embodiment of the present technology

[0356] 70A Sample-and-hold circuit according to Reference Example 1

[0357] 70B Sample-and-hold circuit according to reference embodiment 2

[0358] 80 amplifier

[0359] 91 Component Layer

[0360] 92 wiring layer

Claims

1. An imaging element, comprising: a pixel array unit in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels including a photoelectric conversion unit; and A sampling and holding circuit is provided corresponding to the pixel columns of the pixel array unit and samples and holds pixel signals including reset signals and data signals output from pixels through signal lines, wherein The sample-and-hold circuit comprises: a first capacitive element; a first sampling transistor connected in series to the first capacitive element; a first writing transistor connected between an input terminal configured to receive the reset signal and the first sampling transistor, and writing the reset signal input from the input terminal into the first capacitance element through the first sampling transistor; a first reading transistor connected between the first sampling transistor and an output terminal, and configured to read a reset signal written into the first capacitive element via the first sampling transistor; a second capacitive element; a second sampling transistor connected in series to the second capacitive element; a second writing transistor connected between an input terminal configured to receive the data signal and the second sampling transistor, and writing the data signal input from the input terminal into the second capacitive element through the second sampling transistor; a second reading transistor connected between the second sampling transistor and the output terminal, and reading a data signal written in the second capacitance element through the second sampling transistor; and A reset transistor is connected between the output terminal and a node of a predetermined reference potential.

2. The imaging element according to claim 1, wherein Each of the first sampling transistor and the second sampling transistor includes a transistor having a relatively small size.

3. The imaging element according to claim 2, wherein Each of the first write transistor, the first read transistor, the second write transistor, the second read transistor, and the reset transistor includes a transistor having a relatively large size.

4. The imaging element according to claim 1, wherein the first writing transistor and the first sampling transistor enter an on-state and the reset signal is written to the first capacitance element, then the first sampling transistor enters an off-state, then the first reading transistor and the reset transistor enter an on-state, and a signal reading path is initialized, then the first sampling transistor enters an on-state and the reset signal written to the first capacitance element is read through the signal reading path, and Thereafter, the second write transistor and the second sampling transistor enter an on state and a data signal is written to the second capacitance element, then the second sampling transistor enters an off state, then the second read transistor and the reset transistor enter an on state, and the signal read path is initialized, then the second sampling transistor enters an on state and the data signal written to the second capacitance element is read through the signal read path.

5. The imaging element according to claim 1, wherein In a state where the first sampling transistor and the second sampling transistor are always in the on state and the reset transistor is always in the off state, The first write transistor enters an on state and the reset signal is written to the first capacitance element, and then the first read transistor enters an on state and reads the reset signal written to the first capacitance element, and Thereafter, the second write transistor enters an on state, and the data signal is written to the second capacitance element, and then the second read transistor enters an on state and reads the data signal written to the second capacitance element.

6. The imaging element according to claim 1, further comprising: An amplifier is arranged between the signal line and the sample-and-hold circuit.

7. The imaging element according to claim 1, wherein Provides low error driving mode and high speed driving mode, In the low error drive mode, the first writing transistor and the first sampling transistor enter an on-state and the reset signal is written to the first capacitance element, then the first sampling transistor enters an off-state, then the first reading transistor and the reset transistor enter an on-state and a signal reading path is initialized, then the first sampling transistor enters an on-state and the reset signal written to the first capacitance element is read through the signal reading path, and Thereafter, the second write transistor and the second sampling transistor enter an on state and the data signal is written to the second capacitance element, then the second sampling transistor enters an off state, then the second read transistor and the reset transistor enter an on state and the signal read path is initialized, then the second sampling transistor enters an on state and the data signal written to the second capacitance element is read through the signal read path, and In the high-speed driving mode, In a state where the first sampling transistor and the second sampling transistor are always in the on state and the reset transistor is always in the off state, The first write transistor enters an on state and the reset signal is written to the first capacitance element, and then the first read transistor enters an on state and reads the reset signal written to the first capacitance element, and Thereafter, the second write transistor enters an on state and a data signal is written to the second capacitance element, and then the second read transistor enters an on state and reads the data signal written to the second capacitance element.

8. The imaging element according to claim 1, wherein The sample-and-hold circuit includes a power supply path switching unit that connects a terminal on a power supply side of each of the first capacitive element and the second capacitive element to electrically separate different power supply paths when writing a signal to the first capacitive element and the second capacitive element and when reading a signal from the first capacitive element and the second capacitive element.

9. The imaging element according to claim 8, wherein The sample-and-hold circuit has a wiring structure in which wiring between the first capacitance element and the first sampling transistor and wiring between the second capacitance element and the second sampling transistor are shielded by wiring between the first capacitance element and the power supply path switching unit and wiring between the second capacitance element and the power supply path switching unit.

10. The imaging element according to claim 9, wherein In the wiring structure, a wiring length of wiring between the first capacitance element and the first sampling transistor is equal to a wiring length of wiring between the second capacitance element and the second sampling transistor.

11. An electronic device comprising an imaging element, wherein the imaging element comprises: a pixel array unit in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels including a photoelectric conversion unit; and A sampling and holding circuit is provided corresponding to the pixel columns of the pixel array unit and samples and holds pixel signals including reset signals and data signals output from pixels through signal lines, wherein The sample-and-hold circuit comprises: a first capacitive element; a first sampling transistor connected in series to the first capacitive element; a first writing transistor connected between an input terminal configured to receive the reset signal and the first sampling transistor, and writing the reset signal input from the input terminal into the first capacitance element through the first sampling transistor; a first reading transistor connected between the first sampling transistor and an output terminal, and configured to read a reset signal written into the first capacitive element via the first sampling transistor; a second capacitive element; a second sampling transistor connected in series to the second capacitive element; a second writing transistor connected between an input terminal configured to receive the data signal and the second sampling transistor, and writing the data signal input from the input terminal into the second capacitive element through the second sampling transistor; a second reading transistor connected between the second sampling transistor and the output terminal, and reading a data signal written in the second capacitance element through the second sampling transistor; and A reset transistor is connected between the output terminal and a node of a predetermined reference potential.

Images