Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device (100) includes a semiconductor body (10) having a top side (11) and a bottom side (19). A first main electrode (2) is arranged on the top side and a second main electrode (3) is arranged on the bottom side. The semiconductor device includes a gate electrode (4) and at least two trenches, a first type trench (51) and a second type trench (52). The semiconductor body comprises a drift region (14) of a first conductivity type and at least three base regions (13a, 13b, 13c), each base region having a second conductivity type. The semiconductor body further comprises an implant region (12) of the first conductivity type. The first main electrode is in electrical contact with the implant region. The gate electrode extends into the first type of trench. The second type trench has no gate electrode. A conductive layer (8) is arranged on the top side and over the third base region and is electrically connected to the electrode. The conductive layer is positioned proximate the third base region such that it is capacitively coupled to the third base region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] There is a need for an improved semiconductor device, for example a semiconductor device with improved static and / or dynamic behavior. Furthermore, there is a need for a method for manufacturing such a semiconductor device. Summary of the Invention

[0003] Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the semiconductor device.

[0004] First, the semiconductor device will be described in detail.

[0005] According to an embodiment, a semiconductor device includes a semiconductor body extending vertically between a top side and a bottom side. A first main electrode is arranged on the top side, and a second main electrode is arranged on the bottom side. Furthermore, the semiconductor device includes a gate electrode and at least two trenches, namely, a first type trench and a second type trench, each extending from the top side into the semiconductor body. The semiconductor body includes: a drift region of a first conductivity type, vertically arranged between the top side and the bottom side; and at least three base regions, namely, a first, second, and third base region, each having a second conductivity type and each arranged vertically between the drift region and the top side. The semiconductor body further includes an implant region of the first conductivity type, the implant region being vertically separated from the drift region by the first base region and adjacent to the first base region. The first base region, the first type trench, the second base region, the second type trench, and the third base region are arranged one after the other in this order along a first lateral direction. The first main electrode is in electrical contact with the implant region. The gate electrode extends into a first type of trench, in which the gate electrode is separated from the semiconductor body by a gate insulating layer. The second type of trench does not have a gate electrode.

[0006] The arrangement with the second type trenches, the second base region and the third base region is particularly helpful in protecting the first type trenches, in particular the gate insulation layers therein, from avalanches, for example during switching events.

[0007] The semiconductor device described herein may be a power semiconductor device. For example, it is configured to carry a current of at least 10 A and / or handle a voltage of at least 1000 V or at least 3000 V. The semiconductor device may be a transistor device, in particular a gate-insulated transistor device (in particular an IGFET).

[0008] The semiconductor body may be based on silicon or silicon carbide. The thickness of the semiconductor body measured in the vertical direction is, for example, at least 100 μm or at least 200 μm and / or at most 500 μm. The top side and the bottom side are side faces of the semiconductor body and delimit the semiconductor body in the vertical direction.

[0009] The first and / or second main electrodes may include or consist of metal. Depending on the type of semiconductor device, the first electrode may also be referred to herein as an "emitter electrode" or a "source electrode," and the second main electrode may be referred to herein as a "collector electrode" or a "drain electrode," respectively.

[0010] The gate electrode may comprise metal and / or highly doped polysilicon. In particular, the gate electrode is an insulated gate electrode, ie, it is electrically insulated from the semiconductor body. This may be achieved, for example, with the aid of a gate insulating layer.

[0011] The trenches extend from the top side of the semiconductor body into the semiconductor body and terminate in the semiconductor body, for example, in the drift region. The trenches may have the same depth measured in the vertical direction. The depth of the trenches may be at least 1 μm or at least 5 μm and / or at most 20 μm or at most 10 μm. The trenches may each be elongated and may each extend in a lateral direction, wherein a lateral direction is defined herein as a direction perpendicular to the vertical direction. In particular, a lateral direction is a direction parallel to the main extension plane of the semiconductor body. For example, the trenches extend parallel to each other.

[0012] The first-type grooves and the second-type grooves may be spaced apart from each other along a first lateral direction. Each groove may extend along a second lateral direction perpendicular to the first lateral direction. The average distance between the first-type grooves and the second-type grooves is, for example, at least 100 nm, or at least 500 nm, and / or at most 2 μm. The distance between two grooves is defined herein as, for example, the spacing between the grooves, i.e., the distance between the centers of the grooves. For example, no additional grooves are arranged laterally between the first-type grooves and the second-type grooves.

[0013] The first type of trench is filled with a conductive material that is separated from the semiconductor body by a gate insulating layer. The conductive material is spatially and electrically separated from the semiconductor body by the gate insulating layer. The gate insulating layer can be an oxide, such as SiO2. The thickness of the gate insulating layer can be at least 10nm and / or at most 200nm. For example, the thickness of the gate insulating layer is between 50nm and 150nm (inclusive).

[0014] In particular, "electrically separated" in this context means that there is no electrical contact between two elements. Two electrically separated elements may, for example, be configured to be independently electrically biased or controlled. This means that they are configured to be at different electrical potentials during operation of the semiconductor device. In particular, two electrically separated elements may be electrically insulated from each other, i.e., no current can flow between them.

[0015] The conductive material in the first type of trench can be metal and / or highly doped polysilicon. The conductive material in the first type of trench is part of the gate electrode, i.e., electrically connected to the gate electrode. When two elements are electrically connected or in electrical contact, this means that the two elements cannot be independently electrically biased or independently controllable. Therefore, they are always at the same potential. The first type of trench is also referred to as an active trench in this article.

[0016] For example, the electrically conductive material in the first type trench reaches at least as deep into the semiconductor body as the first base region and / or the second base region.

[0017] The second type of trench does not have a gate electrode. In other words, the second type of trench is a gate-less trench. In other words, the second type of trench is electrically separated from the gate electrode.

[0018] The second type of trench may also be filled with a conductive material, which may be separated from the semiconductor body by an insulating layer. However, the conductive material is electrically separated from the gate electrode, i.e., not electrically connected to the gate electrode. The insulating layer may be the same as the gate insulating layer. Within the second type of trench, the conductive material may extend as deeply into the semiconductor body as the first and / or second base regions. The conductive material in the second type of trench may be metal and / or highly doped polysilicon.

[0019] For example, the conductive material in the second type trench is electrically connected to the first main electrode. In other words, the first main electrode may extend into the second type trench.

[0020] Instead of being filled with a conductive material, the second type trenches may be free of conductive material and may, for example, only be filled with an electrically isolating material.

[0021] The second type of trenches are also referred to herein as "passive trenches."

[0022] The drift region of the semiconductor body has a first conductivity type. The first conductivity type is, for example, n-type, i.e., the drift region is n-doped. The second conductivity type is opposite to the first conductivity type and can therefore be p-type. However, the opposite situation is also possible, where the first conductivity type is p-type and the second conductivity type is n-type.

[0023] The drift region extends, for example, continuously over all base regions, ie, in a top view onto the top side, the drift region overlaps with all three base regions.

[0024] The first type trench is arranged between the first base region and the second base region along a first lateral direction.For example, the first type trench adjoins the first base region on one side and / or adjoins the second base region on another side.

[0025] The second base region is arranged between the first type trench and the second type trench along the first lateral direction. The second base region may be adjacent to the second type trench. The second base region may extend continuously (eg, uninterruptedly) from the first type trench to the second type trench.

[0026] The second type trench is arranged between the second base region and the third base region along the first lateral direction.The second type trench may adjoin the third base region.

[0027] The third base region may extend continuously (eg, uninterruptedly) from the second type trench to another trench spaced apart from the second type trench in the first lateral direction. The other trench may be another second type trench, ie, electrically separated from the gate electrode or not filled with the gate electrode.

[0028] The structure comprising the first base region and the adjacent implantation structure, the first type trench, the second base region, the second type trench and the third base region may be repeated several times along the top side. A structure comprising at least a portion (half) of the first base region together with the adjacent implantation region, the first type trench, the second base region, the second type trench and a portion (half) of the third base region is also referred to as a "half cell" or a "transistor half cell". The semiconductor device may comprise several such half cells, which may be arranged one after another along the first lateral direction. Every two adjacent half cells may be mirror-symmetrical about a mirror plane. The mirror plane extends, for example, perpendicular to the first longitudinal direction. The mirror plane may intersect the first and / or third base region at half of their respective extension along the first lateral direction.

[0029] The semiconductor body includes an implant region of the first conductivity type. The implant region is vertically separated from the drift region by the first base region and is adjacent to the first base region. The implant region, for example, reaches the top side. The implant region may be embedded in the first base region. For example, the implant region may be adjacent to the first type trench at the same side as the first base region is adjacent to the first type trench. Each half cell may include exactly one such implant region. The implant region is also referred to as a source region.

[0030] The injection region is in electrical contact with the first main electrode, for example, it is adjacent to the first main electrode. During operation of the semiconductor device in a (static) transistor mode, first type charge carriers (for example, electrons) are injected from the first main electrode into the injection region. The semiconductor device is configured such that, by applying a certain potential to the gate electrode, the first base region adjacent to the first type trench is depleted, so that a path is formed for the first type charge carriers from the injection region towards the drift region, the path extending in a vertical direction along the first type trench.

[0031] The second base region may form a portion of the top side, for example the entire portion of the top side laterally between the first type trench and the second type trench. For example, any (implanted) region of the first conductivity type between the second base region and the top side and adjoining the second base region is not vertically arranged with the semiconductor body.

[0032] The third base region may also form a portion of the top side, for example the entire portion of the top side laterally situated between two trenches laterally delimiting the third base region. Any (implanted) regions of the first conductivity type between the third base region and the top side and adjoining the third base region may not be arranged vertically with the semiconductor body.

[0033] According to a further embodiment, the semiconductor body includes a conductive layer disposed on a top side of the semiconductor body and above the third base region. The conductive layer is electrically connected to an electrode of the semiconductor device that is different from the gate electrode. This means that the conductive layer is configured to be electrically biased / controlled independently of the gate electrode, i.e., it can be set to a potential that is different from the potential of the gate electrode.

[0034] The conductive layer on the top side and above the third base region may include or consist of metal and / or highly doped polysilicon. For example, the conductive layer is electrically connected to the first main electrode or to an electrode that is controllable / biasable independently of the first main electrode.

[0035] In a top view onto the top side, the conductive layer and the third base region at least partially overlap. That is, in a top view onto the top side, the conductive layer covers at least a portion of the third base region. The conductive layer can be a continuous layer or can be formed from several segments that are spaced apart from each other in at least one lateral direction. In particular, the conductive layer extends parallel to the top side of the semiconductor body and / or parallel to a main extension plane of the semiconductor body.

[0036] According to another embodiment, the conductive layer is positioned so close to the third base region that, by electrically biasing the conductive layer, such strong capacitive coupling between the third base region and the conductive layer can be achieved, whereby free charge carriers in the third base region are influenced. "Influenced" means, for example, that the free charge carriers are attracted or repelled by the conductive layer. In particular, depending on the conductivity type of the third base region, the free charge carriers are charge carriers of the second type. Thus, if the third base region is p-doped, the free charge carriers can be holes.

[0037] Such a conductive layer enables improved operation of the semiconductor device. For example, during static operation, free charge carriers in the third base region are repelled by the conductive layer in order to maintain a high electron-hole plasma in the semiconductor body or to displace them toward the gate electrode in the first type of trench. When the semiconductor device is switched, the second type of charge carriers are attracted by the conductive layer in order to draw the electron-hole plasma away from the first type of trench. This reduces the risk of damage to the gate insulation layer in the first type of trench due to avalanche, for example. For example, the density of the second type of free charge carriers in the third base region at the top side is at least 10% or at least 20% lower in static operation than in the absence of such a conductive layer.

[0038] The maximum distance between the third base region and the conductive layer to achieve such strong capacitive coupling depends on several factors, such as the potential applied to the conductive layer and the material vertically arranged between the conductive layer and the semiconductor body over the lateral extension of the conductive layer. For example, the maximum vertical distance between the conductive layer and the third base region is of the same order of magnitude as the thickness of the gate insulating layer.

[0039] According to another embodiment, the conductive layer is separated from the top side of the semiconductor body by an electrically isolating layer, which is arranged vertically between the top side and the conductive layer. The electrically isolating layer may comprise an oxide. For example, it may comprise the same material as the gate insulating layer. For example, the electrically isolating layer comprises SiO2.

[0040] For example, the conductive layer is separated from the top side only by the electrically isolating layer. That is, the vertical distance between the top side and the conductive layer is defined by the thickness of the electrically isolating layer. The electrically isolating layer may fill a majority of the space between the conductive layer and the top side of the semiconductor body. For example, at least 70%, at least 80%, or at least 90% of the volume between the conductive layer and the top side is filled by the electrically isolating layer.

[0041] According to further embodiments, the thickness of the electrically isolating layer is at most five times, or at most three times, or at most 1.5 times the thickness of the gate insulating layer.This is one way to achieve a strong capacitive coupling.

[0042] According to further embodiments, the vertical distance between the conductive layer and the third base region is at most 500 nm, or at most 300 nm, or at most 150 nm. Additionally or alternatively, the vertical distance between the conductive layer and the third base region may be at least 10 nm, or at least 50 nm. This minimum distance exists at least in certain areas of the conductive layer. This is one way to achieve strong capacitive coupling.

[0043] According to a further embodiment, the conductive layer and the third base region are electrically separated from one another. That is, the semiconductor device has no (direct) electrical connection between the conductive layer and the third base region. For example, the electrically isolating layer then extends continuously and uninterruptedly between the conductive layer and the top side of the semiconductor body and extends over the entire lateral extension of the conductive layer.

[0044] According to a further embodiment, an electrical connection is formed between the conductive layer and the third base region. For example, the conductive layer is in electrical contact with the third base region in one or more contact regions of the third base region. In these contact regions, the conductive layer may abut the third base region. When viewed in a top view onto the top side, the total area of the contact regions is, for example, at most 50%, at most 30%, or at most 10% of the area of the conductive layer. The remainder of the conductive layer (i.e., outside the contact regions) is separated from the semiconductor body, for example, by an electrically isolating layer.

[0045] According to another embodiment, in a top view onto the top side, the conductive layer covers a majority of the third base region. For example, in the plan view, the conductive layer covers at least 60%, at least 80%, or at least 90% of the third base region. Additionally or alternatively, in the top view, the conductive layer does not overlap with the second type trenches and / or does not overlap with any of the trenches that laterally bound the third base region. It is also possible that, in the top view, the conductive layer overlaps with the second type trenches or with any of the trenches that laterally bound the third base region, but does not extend laterally beyond the trench(es).

[0046] According to another embodiment, the conductive layer is arranged vertically between the top side of the semiconductor body and a portion of the emitter electrode. For example, in a top view onto the top side, the portion of the emitter electrode and the conductive layer overlap. For example, in this top view, the portion of the emitter electrode completely covers the conductive layer.

[0047] According to a further embodiment, a vertical distance between the conductive layer and the third base region is at most half, at most 1 / 5, or at most 1 / 10 of a vertical distance between the portion of the emitter electrode and the top side of the semiconductor body. In particular, the portion of the emitter electrode is so far away from the third base region that it is not capacitively coupled to the third base region.

[0048] For example, the vertical distance between the portion of the emitter electrode and the top side is at least 800 nm or at least 1 μm or at least 1.5 μm.

[0049] A further electrically isolating layer may be present, arranged vertically between the top side of the semiconductor body and the portion of the emitter electrode. The thickness of the further electrically isolating layer may define the distance between the portion of the emitter electrode and the top side. The further electrically isolating layer may comprise an oxide, such as SiO2. It is also referred to herein as a field insulation layer.

[0050] According to another embodiment, the semiconductor device can be operated in a first mode, in which free charge carriers (particularly charge carriers of the second type, such as holes) in the third base region are repelled by the conductive layer. For example, in the first mode, the conductive layer is at a positive potential.

[0051] According to another embodiment, the semiconductor device can be operated in a second mode, in which free charge carriers (particularly charge carriers of the second type, such as holes) in the third base region are attracted by the conductive layer. For example, in the second mode, the conductive layer is at a negative potential.

[0052] According to a further embodiment, the first mode is a transistor mode and / or the second mode is a diode mode. That is, in the first mode, the semiconductor device is operated as a transistor, and in the second mode, the semiconductor device is operated as a diode.

[0053] For example, in the first mode, the gate electrode and the first main electrode are at different potentials. In the transistor mode, the first main electrode can be at a positive potential relative to the second main electrode. In the diode mode, this can be reversed, i.e., the first main electrode is at a negative potential relative to the second main electrode.

[0054] According to a further embodiment, the third base region includes at least one contact region in which the third base region is electrically contacted with an electrode of the semiconductor device different from the gate electrode, eg it is controllable / biasable independently of the gate electrode.

[0055] During operation, charge carriers can be extracted from the semiconductor body via the contact region. Therefore, the contact region can also be referred to as an "extraction region". Such an extraction region can be advantageous during switching events (e.g., during the turn-off period of the transistor mode) because it helps to quickly reduce the plasma concentration in the semiconductor body. That is, the contact region constitutes a plasma control feature. On the other hand, if the semiconductor device is operated in diode mode, the electrical contact between the electrode and the semiconductor body in the contact region provides (multiple) (additional) charge carrier paths, thereby reducing the conduction losses in the diode mode. Since the contact region is in electrical contact with an electrode different from the gate electrode, the path for the charge carriers is independent of the gate electrode potential. The location of the contact region of the third base region (i.e., at a location separated from the first type of trench by the second type of trench) helps to protect the gate insulation layer in the first type of trench during switching events because the generation of avalanches in the region of the first type of trench is reduced.

[0056] For example, an electrode electrically connected to the third base region in the contact region is arranged on the top side. This electrode can be the first main electrode or another electrode controllable independently of the first main electrode.

[0057] Because the contact region belongs to the third base region, it is also referred to herein as the third contact region. The contact region may form part of the top side. The third base region may adjoin the electrode over the entire area of the contact region. When viewed in a top view onto the top side, the area of the contact region is, in particular, smaller than the area of the third base region. For example, in this top view, the area of the contact region is at most 50%, at most 10%, at most 5%, or at most 1% of the area of the third base region. In the case of multiple contact regions, all features disclosed for one contact region are also disclosed for the other contact regions.

[0058] According to further embodiments, the semiconductor device is an RC-IGBT (ie a reverse conducting IGBT) or a MISFET (in particular a MOSFET).

[0059] RC-IGBTs and MOSFETs are semiconductor devices that can be operated in diode mode. For such devices, the contact region in which the third base region is in electrical contact with the electrode is particularly beneficial, as explained above.

[0060] According to a further embodiment, the at least one contact region and the electrically conductive layer are electrically connected to the same electrode, eg to the first main electrode.

[0061] According to a further embodiment, the electrically conductive layer comprises at least two segments spaced apart from each other in the lateral direction.

[0062] According to another embodiment, the at least one contact region is arranged laterally between two sections of the conductive layer. For example, in a top view onto the top side, the at least two sections do not overlap with the contact region. When viewed in this top view, the contact portion can be arranged in the gap between the two sections.

[0063] According to another embodiment, the third base region includes a plurality of (third) contact regions. In each of these contact regions, the third base region is in electrical contact with the electrode. For example, the contact regions of the third base region are spaced apart from each other along at least one lateral direction (e.g., along a first lateral direction). All features disclosed with respect to one contact region of the third base region are also disclosed with respect to all other contact regions of the third base region.

[0064] The contact regions of the third base region may each be formed as a strip, for example, extending along the second lateral direction. Every two contact regions of the third base region may be spaced apart from each other. In areas outside the contact regions, there is no direct electrical contact between the electrode and the third base region. In particular, outside the contact regions, the electrode does not abut the third base region. For example, when viewed in a top view onto the top side, the multiple contact regions of the third base region are arranged in a rectangular pattern. For example, when viewed in this top view, at most 50% and / or at least 10% of the area of the third base region is formed by the contact regions.

[0065] According to a further embodiment, in a plan view onto the top side, the at least one contact region in the third base region and the electrically conductive layer overlap each other. For example, in the contact region, the third base region is electrically conductively connected to the electrically conductive layer.

[0066] Alternatively, a hole can be formed through the conductive layer, through which an electrode in contact with the third base region in the contact area is led. In the hole, the electrode can be spaced apart from the conductive layer, for example, by an electrically isolating layer.

[0067] According to a further embodiment, the third base region extends from the top side at least as deep into the semiconductor body as the second type trench and / or the first type trench. For example, the third base region extends deeper into the semiconductor body than the second type trench and / or the first type trench. It has been found that with such a design, the avalanche strength in the vicinity of the first type trench can be significantly reduced.

[0068] According to another embodiment, the first type trench and the second type trench have the same depth. Alternatively, the second type trench may extend deeper into the semiconductor than the first type trench. Results show that such deeper second type trenches further help keep avalanches away from the first type trenches.

[0069] According to a further embodiment, the third base region extends below the second type trenches towards the first type trenches.Thus, in a top view onto the top side, the second type trenches and the third base region may overlap each other.

[0070] According to a further embodiment, the second base region comprises at least one contact region, in which the second base region is electrically contacted with an electrode of the semiconductor device that is different from the gate electrode. This electrode may be the same electrode that is electrically contacted with the third base region in the corresponding (third) contact region. The contact region of the second base region (also referred to herein as the second contact region) may form part of the top side. When viewed in a top view onto the top side, the second contact region may have an area that is smaller than the area of the second base region. The same relative dimensions as disclosed in conjunction with the (third) contact region of the third base region also apply here.

[0071] By means of the contact region of the second base region, a further degree of freedom for optimizing the charge carrier extraction is achieved, for example during switch-off in the transistor mode and / or during the diode mode.

[0072] According to a further embodiment, the first base region comprises at least one contact region, in which the first base region is electrically contacted with an electrode of the semiconductor device that is different from the gate electrode. Furthermore, this electrode may be the same electrode that is electrically contacted with the third base region in a corresponding (third) contact region. The contact region of the first base region (also referred to herein as the first contact region) may adjoin the top side and / or the implanted region.

[0073] By means of the contact region of the first base region, a further degree of freedom for optimizing the charge carrier extraction is achieved, for example during switch-off in the transistor mode and / or during the diode mode.

[0074] Since the contact regions are in each case part of the respective base region, they have the second conductivity type.In each base region, the at least one contact region may be spaced apart from a trench laterally delimiting the respective base region.

[0075] Next, a method for manufacturing a semiconductor device is described in detail. For example, the method can be used to manufacture a semiconductor device as described in detail herein. Therefore, all features disclosed in conjunction with the semiconductor device are also disclosed with respect to the method, and vice versa.

[0076] According to an embodiment, a method for manufacturing a semiconductor device includes a step of providing a semiconductor body having a top side and a bottom side. Then, at least two trenches, namely a first type trench and a second type trench, are formed in the semiconductor body, wherein each of the trenches extends from the top side into the semiconductor body. Furthermore, a first main electrode is formed on the top side of the semiconductor body, and a second main electrode is formed on the bottom side of the semiconductor body. A gate electrode is formed such that the gate electrode extends into the first type trench, where the gate electrode is separated from the semiconductor body by a gate insulating layer. The second type trench remains free of a gate electrode. A semiconductor device is formed such that the semiconductor body includes: a drift region of a first conductivity type vertically arranged between the top side and the bottom side; and at least three base regions, namely, first, second, and third base regions, each having a second conductivity type and each arranged vertically between the drift region and the top side. The semiconductor body further includes an implant region of the first conductivity type, the implant region being vertically spaced apart from the drift region by the first base region and adjacent to the first base region. The first base region, the first type trench, the second base region, the second type trench and the third base region are arranged one after another in this order along the first lateral direction.

[0077] The first main electrode is in electrical contact with the implantation region.

[0078] The trench may be formed in the semiconductor body before forming the base region and the implant region. Alternatively, the base region may be at least partially formed before forming the trench.

[0079] According to another embodiment, a conductive layer is formed on the top side. The conductive layer is arranged above the third base region and is electrically connected to an electrode of the semiconductor device that is different from the gate electrode. The conductive layer is positioned close to the third base region so that by electrically biasing the conductive layer, such a strong capacitive coupling between the third base region and the conductive layer can be achieved, thereby influencing free charge carriers in the third base region.

[0080] Hereinafter, semiconductor devices and methods for manufacturing semiconductor devices will be explained in more detail with reference to the accompanying drawings based on exemplary embodiments. The accompanying drawings are included to provide further understanding. In the drawings, elements with the same structure and / or function may be referenced by the same reference numerals. It will be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. As long as elements or components in different figures correspond to each other in terms of their functions, their description will not be repeated for each of the following figures. For the sake of clarity, elements may not appear with corresponding reference numerals in all figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figures 1 to 8 as well as Figure 12 Different exemplary embodiments of a semiconductor device are shown in different views.

[0082] Figures 9 to 11 Different locations in an exemplary embodiment of a method for manufacturing a semiconductor device are shown. DETAILED DESCRIPTION

[0083] Figure 1 A first exemplary embodiment of a semiconductor device 100 is shown in cross-section. In this case, semiconductor device 100 is an RC-IGBT. It includes a semiconductor body 10 having a top side 11 and a bottom side 19, which are vertically opposite to each other. For example, semiconductor body 10 is based on Si or SiC.

[0084] At the bottom side 19, the semiconductor body 10 comprises alternatingly arranged first and second type regions 15, 16. The regions 15 and 16 are in electrical contact with a second main electrode 3, ie collector electrode 3, on the bottom side 19. The collector electrode 3 is formed of metal, for example.

[0085] The first type region 15 has a first conductivity type (hereinafter referred to as n-type), and the second type region 16 has a second conductivity type (hereinafter referred to as p-type). The drift region 14 is arranged between the top side 11 and the bottom side 19. The drift region 14 has the first conductivity type, i.e., n-type. The drift region 14 adjoins the first type region 15 and the second type region 16.

[0086] A plurality of trenches 51, 52 extend from the top into the semiconductor body 10 and into the drift region 14. Trenches 51 are first type trenches (also referred to herein as active trenches) and trenches 52 are second type trenches (also referred to herein as inactive trenches or dummy trenches).

[0087] The first-type trenches 51 are filled with a conductive material, which is electrically separated from the semiconductor body 10 by an electrically insulating layer 40 (referred to herein as a "gate insulating layer"). Therefore, there is no direct electrical contact between the semiconductor body 10 and the conductive material in the first-type trenches 51. The gate insulating layer 40 is formed, for example, of an oxide (e.g., SiO2). The conductive material in the first-type trenches 51 can be highly doped polysilicon. The conductive material in the first-type trenches 51 is part of the gate electrode 4 of the semiconductor device 100.

[0088] The second type trenches 52 are also filled with a conductive material, such as highly doped polysilicon, which is also electrically separated from the semiconductor body 10 by the same electrical insulation layer as the gate insulation layer 40. The conductive material in the second type trenches 52 is part of the first main electrode 2 (i.e., emitter electrode 2) arranged on the top side 12.

[0089] The semiconductor body 10 includes several base regions 13a, 13b, 13c, which are arranged vertically between the drift region 14 and the top side 11. The base regions 13a, 13b, 13c all have the second conductivity type, i.e., p-type, and all of them adjoin the drift region 14 and the top side 11. The first and second base regions 13a, 13b are shallower (have a smaller vertical extension) than the trenches 51, 52. The third base region 13c is deeper than the trenches 51, 52, i.e., extends further into the semiconductor body 10.

[0090] The first base region 13a adjoins and is in electrical contact with the emitter electrode 2 in a first contact region 6a (also referred to as an "Rb-prime region"). The third base region 13c adjoins and is in electrical contact with the emitter electrode 2 in a third contact region 6c. The function of these contact regions 6a, 6c will be explained further below.

[0091] As in Figure 1 As can be seen in FIG. 1 , the semiconductor device 100 is subdivided into a plurality of so-called half cells. Figure 2 One such half unit is shown in more detail in FIG. Figure 2 The structure between the vertical dashed lines in . Figure 1 In FIG, several such half cells are arranged one after another along a first lateral direction (extending from left to right). Two adjacent half cells are at a plane perpendicular to the first lateral direction and passing through the third base region 13c (see FIG. Figure 2 The right vertical dashed line in the figure) are mirror images relative to each other.

[0092] As in Figure 2 As can be seen in FIG, the half cell includes a portion (half) of the first base region 13 c, the first type trench 51, the second base region 13 b, the second type trench 52, and a portion (half) of the third base region 13 c, which are arranged one after another in this order along the first lateral direction. The half cell further includes an implantation region 12 (source region 12) of the first conductivity type (i.e., n-type) arranged vertically between the first base region 13 c and the top side 11. The implantation region 12 is adjacent to the first base region 13 c and the first type trench 51. The implantation region 12 is further adjacent to the emitter electrode 2 and is in electrical contact therewith.

[0093] The operation of the semiconductor device may be as follows:

[0094] In the so-called transistor mode, the emitter electrode 2 is set to ground, and the collector electrode 3 is set to a positive potential. The gate electrode 4 is set to a positive potential, causing the first base region 13a to be depleted at the boundary with the first-type trench 51. A conduction path is generated in the first base region 13c along the first-type trench 51. Electrons can then be injected from the emitter electrode 2 into the injection region 12, travel along the conduction path, and reach the drift region 14. On the bottom side 19, holes are injected from the collector electrode 3 via the second-type region 16 and also travel into the drift region 14, resulting in the generation of an electron-hole plasma.

[0095] When the transistor mode is switched off, electron-hole plasma can generate avalanches in the region of the first type trenches 51. Such avalanches can in turn damage the gate insulating layer 40, negatively impacting the long-term performance stability of the semiconductor device 10. It has been found that the second type of inactive trenches 52 and the third base region, which extends deeper into the semiconductor body than the trenches 51 and 52, help divert avalanches away from the active trenches.

[0096] This effect is additionally further increased by the fact that the third base region 13c is in electrical contact with the emitter electrode 2 in a third contact region 6c. Charge carriers (eg holes) can be dissipated via this third contact region 6c during switch-off.

[0097] Since semiconductor device 100 is an RC-IGBT, it can also operate in reverse mode (i.e., so-called diode mode). In diode mode, emitter electrode 2 is, for example, grounded, and collector electrode 2 is at a negative potential. Electrons are injected from collector electrode 3 into first type region 15 and must recombine with holes from emitter electrode 2.

[0098] Without the third contact region 6c in the third base region, the only path would be through the first base region 13c via the first contact region 6a. With a positive gate-emitter potential, the diode conduction loss (Vf) increases. This is because, with a positive gate-emitter potential, a channel is established between the n-type implant region 12 and the n-type drift region 14, creating an electron path. Consequently, since the electron path short-circuits the diode path, hole injection into the first base region 13a is reduced, resulting in a lower plasma concentration.

[0099] In order to keep the diode on-state losses low, the device 100 can be operated with a negative or shorted (Vg=0V) gate electrode. In this case, the electron path will not exist. However, this limits the usability of the device because the gate control driver and system need to be specially adapted (non-standard) or designed for the application to achieve the lowest possible losses.

[0100] In combination Figure 1 and Figure 2 In the exemplary embodiment shown, a charge carrier path for diode operation is formed through the third base region 13c via the contact region 6c in the third base region 13c. Holes can be injected through the third contact region 6c. This charge carrier path is independent of the gate electrode's potential, particularly because the second-type trench 52 adjacent to the third base region 13c is not at gate potential, but rather at emitter potential. Consequently, operation using conventional gate drive schemes is possible while maintaining low reverse recovery charge and Erec.

[0101] Figure 1 and Figure 2 The semiconductor device 100 further comprises an electrically conductive layer 8 on the top side 11 and above the third base region 13c. The electrically conductive layer 8 is spaced apart from the semiconductor body 10 by an electrically isolating layer 80, which in this example is the same as the gate insulating layer 40.

[0102] Conductive layer 8 is electrically connected to emitter electrode 2 and is close to third base region 13 c so as to be capacitively coupled to third base region 13 c. With the help of conductive layer 8, holes in third base region 13 c can be influenced, for example, by being attracted or repelled from conductive layer 8. For example, during the off state of transistor mode, holes are attracted by conductive layer 8. In diode mode, holes can be repelled by conductive layer 8.

[0103] The conductive layer 8 may be formed of highly doped polysilicon or metal. The distance between the conductive layer 8 and the third base region 13 c is, for example, at most 150 nm, which is determined by the thickness of the electrical isolation layer 80 .

[0104] Figure 3 Another exemplary embodiment of a semiconductor device 100 is shown, which is similar to Figure 1 , but now there is no third contact region 6c in the third base layer 13c. The conductive layer 8 is not directly electrically connected to the third base region 13c, but is electrically separated from it. The function of the conductive layer 8 is the same as Figure 1 and Figure 2 Same as in.

[0105] exist Figure 4 In the exemplary embodiment of FIG. 1 , gate electrode 4 and its connections to different regions of semiconductor device 100 are not shown in order to improve the clarity of the figure. Instead, a portion of emitter electrode 2 is shown extending throughout third base region 13 c. This portion of emitter electrode 2 is separated from top side 11 of semiconductor body 10 by a further electrically isolating layer 20 (also referred to herein as “field insulation layer 20”). Field insulation layer 20 may be formed of an oxide. The vertical distance between emitter electrode 2 and top side 11 is defined by the thickness of field insulation layer 20 and is much greater than the thickness of insulation layer 80 separating conductive layer 8 from top side 11.

[0106] As in Figure 4 It can be further seen in FIG that a portion of the conductive layer 8 extends to the third base region 13 c and adjoins the third base region 13 c in the contact region 6 c. Thus, an electrical contact between the third base region 13 c and the emitter electrode 2 is established via the conductive layer 8.

[0107] exist Figure 5In the exemplary embodiment of the present invention, the conductive layer 8 and the contact region 6 c in the third base region 13 c are electrically connected to an electrode 5 that is different from the emitter electrode 2 and from the gate electrode 4. The further electrode 5 is controllable / biasable independently of the gate electrode 4 and the emitter electrode 2. With such an electrode 5, different operating modes of the semiconductor device 100 can be further optimized. For example, in the static transistor mode, the electrode 5 can be set to a positive potential in order to repel holes from the conductive layer 8 and thereby shift the electron-hole plasma towards the active trench 51. During the off-state of the transistor mode, the further electrode 5 can be set to a negative potential in order to attract holes. In the (static) diode mode, the electrode 5 can be set to a positive potential again.

[0108] Figure 6 An exemplary embodiment of a semiconductor device 100 is shown in a top view onto the top side 11 of the semiconductor body 10. As can be seen, the conductive layer 8, indicated by dashed lines, includes a plurality of holes, wherein each of these holes overlaps with a contact region 6c of the third base region 13c. The contact region 6c is electrically connected to an electrode (e.g., the emitter electrode 2) through these holes in the conductive layer 8. The conductive layer 8 itself is formed continuously.

[0109] Figure 7 Another exemplary embodiment of a semiconductor device 100 is shown again in a top view onto the top side 11. In this case, the conductive layer 8 (again indicated by dashed lines) comprises two segments spaced apart from each other in a first lateral direction. The gap between the two segments overlaps with the contact region 6c of the third base region 13c.

[0110] Figure 8 A further exemplary embodiment of the semiconductor device 100 is now shown again in cross-section. In contrast to the previous exemplary embodiment, the third base region 13 c now comprises a plurality of contact regions 6 c spaced apart from one another in a first lateral direction. Each of these contact regions 6 c is in electrical contact with the emitter electrode 2 .

[0111] Furthermore, the second base regions 13 b each include a contact region 6 b (also referred to as second contact regions 6 b ), wherein the second base region 13 b is in electrical contact with the emitter electrode 2 in each of these contact regions 6 b .

[0112] By means of the contact regions 6 b in the second base region(s) 13 b , another degree of freedom for optimizing the operation of the semiconductor device 100 may be obtained.

[0113] Figure 9A first position is shown in an exemplary embodiment of a method for manufacturing a semiconductor device 100. In this position, a semiconductor body 10 having a top side 11 and a bottom side 19 is provided. The bottom side 19 is formed by alternating regions 15 of the first type and regions 16 of the second type. The top side 11 is formed by base regions 13 of the second conductivity type. A drift region 14 is arranged between the bottom side 19 and the base region 13, wherein the drift region 14 has the first conductivity type.

[0114] Figure 10 The position is shown after trenches 51, 52 have been formed in the semiconductor body 10. The trenches 51, 52 have been filled with a conductive material. The conductive material in the trenches 51, 52 is electrically separated from the semiconductor body 10 by an electrically isolating material 40 (gate insulating layer 40) arranged in the trenches 51, 52.

[0115] Furthermore, a first base region 13a, a second base region 13b and a third base region 13c have been formed, for example, by ion implantation. Furthermore, an implantation region 12 has been formed in the semiconductor body 10, for example, by means of ion implantation.

[0116] Figure 11 The position is shown where a conductive layer 8 has been formed on the top side 11 and above the third base region 13c. The conductive layer 8 is electrically separated from the third base region 13c by an electrical isolation layer 80 formed of the same material as the gate insulating layer 40.

[0117] Figure 12 The semiconductor device 100 is shown after the electrodes 2, 3, 4 have been applied to the semiconductor body 10. The electrically conductive layer 8 has been electrically connected to the emitter electrode 2.

[0118] As stated Figures 1 to 12 The embodiments shown in the accompanying drawings represent exemplary embodiments of the improved semiconductor device and the improved method for manufacturing the semiconductor device; therefore, they do not constitute a complete list of all embodiments of the improved semiconductor device according to the improved method. For example, the actual semiconductor device and method may differ from the embodiments shown in terms of arrangement, elements, and order of method steps.

[0119] Reference numerals

[0120] 2First main electrode / emitter electrode

[0121] 3 Second main electrode / collector electrode

[0122] 4 Gate electrode

[0123] 5 Additional electrodes

[0124] 6a First contact area

[0125] 6b Second contact area

[0126] 6c Third contact area

[0127] 8 Conductive layer

[0128] 10 Semiconductor body

[0129] 11 Top side

[0130] 12 Injection area

[0131] 13 Base region

[0132] 13a First base region

[0133] 13b Second base region

[0134] 13c Third base region

[0135] 14 Drift Zone

[0136] 15 Category I Area

[0137] 16 Category II Area

[0138] 19 bottom side

[0139] 20 electrical isolation layer / field insulation layer

[0140] 40 electrical isolation layer / gate insulation layer

[0141] 51 Type 1 groove

[0142] 52 Type II groove

[0143] 80 Electrical isolation layer

[0144] 100 Semiconductor Devices / RC-IGBT

Claims

1. A semiconductor device (100), comprising: a semiconductor body (10) extending in a vertical direction between a top side (11) and a bottom side (19), - a first main electrode (2) on the top side (11) and a second main electrode (3) on the bottom side (19), - a gate electrode (4), - at least two trenches, namely a first type trench (51) and a second type trench (52), each trench extending from the top side (11) into the semiconductor body (10), wherein - the semiconductor body (10) comprises: - a drift region (14) of a first conductivity type, arranged vertically between the top side (11) and the bottom side (19), - at least three base regions, namely a first base region (13a), a second base region (13b) and a third base region (13c), each base region having the second conductivity type and each base region being arranged vertically between the drift region (14) and the top side (11), an implantation region (12) of the first conductivity type, the implantation region being vertically spaced apart from the drift region (14) by the first base region (13a) and adjoining the first base region (13a), wherein - the first base region (13a), the first type trench (51), the second base region (13b), the second type trench (52) and the third base region (13c) are arranged one after another in this order along a first lateral direction, - the first main electrode (2) is in electrical contact with the injection region (12), - the gate electrode (4) extends into the first type of trench (51), in which the gate electrode is separated from the semiconductor body (10) by a gate insulating layer (40), - the second type of trench (52) is devoid of the gate electrode (4), a conductive layer (8) arranged on the top side (11) and above the third base region (13c) and electrically connected to an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4), - the conductive layer (8) is positioned close to the third base region (13c) so that a strong capacitive coupling between the third base region (13c) and the conductive layer (8) can be achieved by electrically biasing the conductive layer (8), whereby free charge carriers in the third base region (13c) are influenced, - the electrically conductive layer (8) is spaced apart from the top side (11) by an electrically isolating layer (80), the electrically isolating layer being arranged vertically between the top side (11) and the electrically conductive layer (8), - the thickness of the electrical isolation layer (80) is at most five times the thickness of the gate insulating layer (40).

2. The semiconductor device (100) according to claim 1, wherein - The electrode (5) electrically connected to the conductive layer (8) is controllable independently of the first main electrode (2).

3. The semiconductor device (100) according to claim 1 or 2, wherein: - The vertical distance between the conductive layer (8) and the third base region (13c) is at most 500 nm.

4. The semiconductor device (100) according to any one of the preceding claims, wherein - the conductive layer (8) and the third base region (13c) are electrically separated from each other.

5. The semiconductor device (100) according to any one of claims 1 to 3, wherein: - forming an electrical connection between the conductive layer (8) and the third base region (13c).

6. The semiconductor device (100) according to any one of the preceding claims, wherein - in a plan view onto the top side (11), the conductive layer (8) covers a large portion of the third base region (13c).

7. The semiconductor device (100) according to any one of the preceding claims, wherein - the conductive layer (8) is arranged vertically between a top side (11) of the semiconductor body (10) and a portion of the emitter electrode (2), - the vertical distance between the conductive layer (8) and the third base region (13c) is at most half the vertical distance between the portion of the emitter electrode (2) and the top side (11) of the semiconductor body (10).

8. The semiconductor device (100) according to any one of the preceding claims, wherein - the semiconductor device (100) is operable in a first mode in which free charge carriers in the third base region (13c) are repelled by the conductive layer (8), and / or - the semiconductor device (100) is operable in a second mode in which free charge carriers in the third base region (13c) are attracted by the conductive layer (8).

9. The semiconductor device (100) according to any one of the preceding claims, wherein - The semiconductor device (100) is an RC-IGBT or a MISFET.

10. The semiconductor device (100) according to claim 8 and 9, wherein - the first mode is a transistor mode, and / or - The second mode is a diode mode.

11. The semiconductor device (100) according to any one of the preceding claims, wherein The third base region (13c) comprises at least one contact region (6c), in which the third base region (13c) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4).

12. The semiconductor device (100) according to claim 11, wherein - the at least one contact region (6c) and the conductive layer (8) are electrically connected to the same electrode (2, 5).

13. The semiconductor device (100) according to claim 11 or 12, in, - the conductive layer (8) comprises at least two segments spaced apart from each other in the lateral direction, The at least one contact region (6c) is arranged laterally between two sections of the electrically conductive layer (8).

14. The semiconductor device (100) according to any one of claims 11 to 13, wherein: - the third base region (13c) comprises a plurality of contact regions (6c), wherein in each of these contact regions (6c), the third base region (13c) is in electrical contact with the electrode (2, 5), - the contact regions (6c) in the third base region (13c) are spaced apart from one another in at least one lateral direction.

15. A method for manufacturing a semiconductor device (100), the method comprising: - providing a semiconductor body (10) having a top side (11) and a bottom side (19), - forming at least two trenches, namely a first type trench (51) and a second type trench (52), each trench extending from said top side (11) into the semiconductor body (10), - forming a first main electrode (2) on the top side (11) and a second main electrode (3) on the bottom side (19), - forming a gate electrode (4) such that the gate electrode (4) extends into the first type of trench (51), in which the gate electrode is separated from the semiconductor body by a gate insulating layer (40), wherein - said second type of trenches (52) remain free of said gate electrodes (4), - forming a conductive layer (8) on the top side (11), wherein The semiconductor device (100) is formed such that the semiconductor body (10) comprises: - a drift region (14) of a first conductivity type, arranged vertically between the top side (11) and the bottom side (19), - at least three base regions, namely a first base region (13a), a second base region (13b) and a third base region (13c), each base region having the second conductivity type and each base region being arranged vertically between the drift region (14) and the top side (11), an implantation region (12) of the first conductivity type, said implantation region being vertically spaced apart from said drift region (14) by said first base region (13a) and adjoining said first base region (13a), - the first base region (13a), the first type trench (51), the second base region (13b), the second type trench (52) and the third base region (13c) are arranged one after another in this order along a first lateral direction, - the first main electrode (2) is in electrical contact with the injection region (12), - the conductive layer (8) is arranged above the third base region (13c) and is electrically connected to an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4), - the conductive layer (8) is positioned close to the third base region (13c) so that a strong capacitive coupling between the third base region (13c) and the conductive layer (8) can be achieved by electrically biasing the conductive layer (8), whereby free charge carriers in the third base region (13c) are influenced, - the electrically conductive layer (8) is spaced apart from the top side (11) by an electrically isolating layer (80), the electrically isolating layer being arranged vertically between the top side (11) and the electrically conductive layer (8), - the thickness of the electrical isolation layer (80) is at most five times the thickness of the gate insulating layer (40).

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