Storage system for ARINC664 terminal configuration table

Abstract

The invention discloses a storage system for an ARINC664 terminal configuration table. The storage system comprises a key module, a PCIe (Peripheral Component Interconnect Express) interface module, an FPGA (Field Programmable Gate Array) subsystem, an upper computer module and a Flash module. According to the method, configuration table storage is carried out on the ARINC664 terminal adopting the AFDX avionics network, and the method can be applied to initial information configuration of various types of terminal systems in the avionics field, including multiple scenes such as an aircraft communication and navigation system, a flight control system and an onboard entertainment and information system. According to the invention, a power-on self-loading configuration table storage scheme is provided for a terminal system, the step of issuing configuration information by an upper computer after each power-on is omitted, and the configuration table can be repeatedly used after one-time writing. The method has high flexibility and high reliability, supports two-layer CRC check detection of configuration information, and improves the security of an avionics system.

Description

Technical Field

[0001] The present invention relates to the field of avionics technology, and more particularly to a terminal device configuration table storage solution based on the AFDX network protocol and the ARINC 664 standard. The solution is applicable to terminal device configuration table storage in multiple scenarios within the avionics field, including aircraft communication and navigation systems, flight control systems, and in-flight entertainment and information systems. Background Art

[0002] As avionics systems continue to grow in complexity, requirements for data transmission speed, reliability, and security are also increasing. This led to the emergence of AFDX (Aviation Full-Duplex Switched Ethernet), an evolution of Ethernet technology, which was standardized as ARINC 664 Part 7. AFDX provides a full-duplex switched Ethernet solution capable of supporting high-bandwidth data transmission while ensuring deterministic and secure data transmission through the concept of virtual links (VLs). However, despite AFDX's excellent data transmission performance, the large number of virtual links and ports required for configuration poses challenges for terminal device configuration management. Traditional methods typically rely on the host computer to send configuration information to terminal devices at each system startup. This approach is not only inefficient but also increases system startup time and operational complexity. Furthermore, frequent configuration delivery can introduce errors, compromising system stability and safety. Therefore, for avionics systems with high security and compatibility requirements, a more efficient, reliable, and flexible configuration table storage solution is crucial. Summary of the Invention

[0003] The purpose of the present invention is to provide a storage system for ARINC664 terminal configuration tables, which realizes hardware-level configuration table storage, efficient management and fast loading through circuit design. The button allows the user to directly select the configuration table group to be loaded after power-on; or receive the loading instructions or new configuration information issued by the host computer through the PCIe interface; and the FPGA programmable gate array subsystem, as the core processing unit, is not only responsible for reading and writing the Flash chip, but also realizes two-layer CRC verification of the configuration table, thereby ensuring the accuracy and integrity of the data. The present invention realizes a configuration table storage solution with diverse loading paths, which has high flexibility and compatibility, and also significantly enhances the security and reliability of the system, greatly simplifying the maintenance process of the terminal equipment.

[0004] The specific technical solution for achieving the purpose of the present invention is: A storage system for ARINC664 terminal configuration tables includes a key module, a PCIe interface module, an FPGA programmable gate array subsystem, a host computer module, and a Flash module. The key module is connected to the FPGA programmable gate array subsystem and is used to select a terminal type and self-load configuration table group information by pressing a key after power is turned on. The PCIe interface module is connected to the FPGA programmable gate array subsystem and the host computer module and serves as a local interface for high-speed data transmission. The FPGA programmable gate array subsystem is connected to the key module, the PCIe interface module, and the Flash module. A driver for reading and writing the Flash module reads the configuration table from the Flash module, writes the configuration table sent by the host computer module through the PCIe interface module into the Flash module, temporarily stores the configuration table within the FPGA programmable gate array subsystem and performs a CRC check on the configuration table; the host computer module is connected to the PCIe interface module and is used to send instructions for writing a configuration table group into the Flash module or loading a configuration table group; the Flash module is connected to the FPGA programmable gate array subsystem and is used to store multiple groups of configuration tables, each terminal type corresponds to a group of configuration tables, and each group contains several configuration tables.

[0005] The FPGA programmable gate array subsystem includes a configuration table selection module, a high-speed data communication module, a Flash driver module, a Flash configuration table storage and reading module, and a Flash configuration table temporary storage module; the configuration table selection module is connected to the key module, the high-speed data communication module, and the Flash configuration table storage and reading module, and is used to process the selection or operation instructions obtained from the key module or the host computer module; the high-speed data communication module is connected to the PCIe interface module, the configuration table selection module, and the Flash configuration table storage and reading module, and is used to process the operation instructions sent by the host computer module through the PCIe interface module; the Flash driver The module is connected to the Flash module and the Flash configuration table storage and reading module, and is used to drive the Flash chip to complete the specified read and write operations; the Flash configuration table storage and reading module is connected to the configuration table selection module, the high-speed data communication module, the Flash driver module and the Flash configuration table temporary storage module, and is used to control and manage the process of reading and writing the Flash configuration table, including writing the received configuration table group into the Flash module and reading the configuration table group from the Flash module; the Flash configuration table temporary storage module is connected to the Flash configuration table storage and reading module, and is used to temporarily store the configuration table being read and written, and perform periodic CRC check.

[0006] The beneficial effects of the present invention are: aThe system proposed in the present invention supports write-once-and-use-many, which simplifies the maintenance process of the terminal equipment and saves the time and workload of repeated configuration after each power-on.

[0007] b. The system proposed in the present invention can store multiple groups of configuration tables to adapt to terminal devices of different types and uses, and has good flexibility and compatibility.

[0008] The system proposed in this invention allows users to quickly select and load the required configuration table group by pressing a button or by specifying a specific location discrete value sent by the host computer when the terminal device is powered on. If the user does not make a selection within a certain period of time, the configuration table group loaded during the previous power-on is automatically loaded. This eliminates the need for manual intervention or reliance on real-time configuration from the host computer, significantly shortening system startup time and improving work efficiency.

[0009] dThe system proposed in this invention uses a two-layer CRC check mechanism to check the configuration information. The check is performed when the configuration table is read from Flash and periodically after loading is completed. This ensures the accuracy and integrity of the data, improves the security of the system, and reduces the risk of failure due to configuration errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural block diagram of the present invention; Figure 2 It is a schematic diagram of the working state of the present invention; Figure 3 This is a flow chart of the present invention when powering on and reading the configuration table; Figure 4 This is a flow chart of the present invention when writing a new configuration table group into Flash. DETAILED DESCRIPTION

[0011] The present invention is described in detail below with reference to the accompanying drawings and embodiments. Example

[0012] See Figure 1The present invention includes a key module 1, a PCIe interface module 2, an FPGA programmable gate array subsystem 3, a host computer module 4 and a Flash module 5; the key module 1 is connected to the FPGA programmable gate array subsystem 3, and uses a nine-key matrix as shortcut keys corresponding to the nine most commonly used terminal device types, which is used to quickly select the terminal type after power-on to load its corresponding configuration table group information; the PCIe interface module 2 is connected to the FPGA programmable gate array subsystem 3 and the host computer module 4, and uses a dual-channel PCIe 3.0 slot, used to connect the FPGA programmable gate array subsystem 3 and the host computer module 4 to achieve high-speed data transmission; the FPGA programmable gate array subsystem 3 is connected to the key module 1, the PCIe interface module 2 and the Flash module 5 to realize the drive for reading and writing the Flash module 5, read the configuration table from the Flash module 5, use the RAM resources of the FPGA programmable gate array subsystem 3 to store the configuration table and perform CRC check on the configuration table, or write the configuration table issued by the host computer module 4 through the PCIe interface module 2 into the Flash module 5; the host computer module 4 is connected to the PCIe interface module 2, and is used to issue the configuration table group that needs to be written to the Flash module 5 or the instruction to load the configuration table, use the WinDriver driver development tool to develop the PCIe bus driver, transmit the configuration information through the PCIe3.0 bus and read the position discrete quantity of the configuration table; the Flash module 5 is connected to the FPGA programmable gate array subsystem 3, and uses the NORFlash model MT25QU01GBBB8ESF-0SIT The memory chip is used to store configuration table groups. The size of each configuration table group is different, but each group (including data and check bits) requires a maximum capacity of 256KB. This type of memory chip has 2048 64KB sectors, so 4 sectors can be used to store a group of configuration tables. In addition, an additional sector is required to store the number of configuration table groups currently stored in Flash module 5, and one sector is used to store the position discrete quantity, address offset, and end address of each group of configuration tables. Therefore, a maximum of 511 groups of configuration tables can be stored, corresponding to 511 different types of terminal devices.

[0013] See Figure 1The FPGA programmable gate array subsystem 3 includes a configuration table selection module 31, a high-speed data communication module 32, a Flash driver module 33, a Flash configuration table storage and reading module 34, and a Flash configuration table temporary storage module 35. The FPGA programmable gate array chip used is XCVU125-2FLVA2104; the configuration table selection module 31 is connected to the key module 1, the high-speed data communication module 32, and the Flash configuration table storage and reading module 34 to implement the read or write operation processing for the configuration table, and hand over the result to the Flash configuration table storage and reading module 34 for the next step of processing. The specific operation instructions include 1 1) Selecting a configuration table group to be loaded from the Flash module 5 based on input from the key module 1; 2) Selecting a configuration table group to be loaded from the Flash module 5 based on the position discrete value received by the high-speed data communication module 32; 3) Writing a new configuration table group to the Flash module 5 based on the configuration information received by the high-speed data communication module 32; 4) Automatically loading the configuration table group loaded during the previous power-on if any of the instructions in 1) and 2) are not received within 20 seconds of power-on. The high-speed data communication module 32 is connected to the PCIe interface module 2, the configuration table selection module 31, and the Flash configuration table storage and reading module 34, and utilizes PCIe 3.0 bus communication, for receiving the operation instructions sent by the host computer module 4 through the PCIe interface module 2 and handing them over to the configuration table selection module 31 for processing, or receiving new configuration information that needs to be written, and sending this information to the Flash configuration table storage and reading module 34 for writing into the Flash module 5; the Flash driver module 33 is connected to the Flash module 5 and the Flash configuration table storage and reading module 34, and when writing data, the configuration information given by the Flash configuration table storage and reading module 34 is written into the Flash module 5 through a write operation, and when reading data, the configuration information is read from the Flash module 5 through a read operation according to the address given by the Flash configuration table storage and reading module 34; the Flash configuration table storage and reading module 34 is connected to the configuration table selection module 31, the high-speed data communication module 32, the Flash driver module 33, and the Flash configuration table temporary storage module 35, and is used to control and manage the reading and writing of the configuration table of the Flash module 5. The process involves calling the Flash driver module 33 to read the configuration table based on the result provided by the configuration table selection module 31. The read configuration information is then stored in the Flash configuration table temporary storage module 35. If the CRC check is correct after the entire configuration table is read, the reading is complete. When writing the configuration table, the new configuration data received from the high-speed data communication module 32 is first stored in the Flash configuration table temporary storage module 35. The new configuration table group is then written by calling the Flash driver module 33. The Flash configuration table temporary storage module 35 is connected to the Flash configuration table storage and reading module 34, utilizing the RAM resources of the FPGA programmable gate array subsystem 3 to temporarily store the configuration table being read or written. A periodic CRC check is then performed on the temporarily stored configuration table group at a 50ms cycle. If an error is detected, the error is reported to the high-speed data communication module 32 via the Flash configuration table storage and reading module 34, and finally sent to the host computer module 4 for processing.

[0014] See Figure 2 During operation, the present invention connects the Flash configuration table storage and reading module 34 to the ARINC664 terminal. After each power-on, the Flash configuration table storage and reading module 34 successfully reads the configuration table group from the Flash module 5, sends the configuration information to the ARINC664 terminal, and configures the registers inside the ARINC664 terminal, thereby completing the function of self-loading the configuration table upon power-on.

[0015] See Figure 3During the process of reading the configuration table upon power-on, the system first determines the configuration table group to be read through the configuration table selection module 31. The first of the three read instructions input to the configuration table selection module 31 becomes the target of this read. These three read instructions are: 1) select the configuration table group loaded from the Flash module 5 based on the input of the key module 1; 2) select the configuration table group loaded from the Flash module 5 based on the position discrete quantity received by the high-speed data communication module 32; and 3) if any of the instructions 1) and 2) are not received within 20 seconds of power-on, the configuration table group loaded during the previous power-on is automatically loaded. After obtaining the configuration table group to be read, the Flash configuration table storage and reading module 34 calls the Flash driver module 33 to search the configuration table group stored in the Flash module 5. After finding the corresponding group, each configuration table in the group is read sequentially. After each configuration table is read, a CRC check is performed on it. If the check fails, it is immediately reported and the reading stops. If the check passes, the configuration table is stored in the Flash configuration table temporary storage module 35 and the next configuration table is read until all configuration tables in the group are read. After the configuration is completed, the configuration table group stored in the Flash configuration table temporary storage module 35 needs to be CRC checked every 50ms. If an error occurs, it is immediately reported to the host computer module 4 for processing.

[0016] See Figure 4 When writing a new configuration table group to the Flash module 5, the system first stores all the new configuration table information received by the high-speed data communication module 32 in the Flash configuration table temporary storage module 35 via the Flash configuration table storage and reading module 34. The Flash driver module 33 then updates the configuration table index stored in the Flash module 5. Each configuration table is then written to the Flash module 5 in sequence. After each table is written, the Flash configuration table storage and reading module 34 generates a corresponding CRC check bit and writes it to the Flash module 5. Once the entire set of new configuration tables has been written, the last address of the configuration table group is written to the configuration table index in the Flash module 5, and the writing process ends.

Claims

1. A storage system for ARINC664 terminal configuration table, characterized in that: The system comprises a key module (1), a PCIe interface module (2), an FPGA programmable gate array subsystem (3), a host computer module (4) and a Flash module (5). The key module (1) is connected to the FPGA programmable gate array subsystem (3) and is used to select a terminal type and self-loaded configuration table group information through a key after power-on; the PCIe interface module (2) is connected to the FPGA programmable gate array subsystem (3) and the host computer module (4) and serves as a local interface for realizing high-speed data transmission; the FPGA programmable gate array subsystem (3) is connected to the key module (1), the PCIe interface module (2) and the Flash module (5) and is used to control the Flash The h module (5) is driven to read and write, reads the configuration table from the Flash module (5), writes the configuration table sent by the host computer module (4) through the PCIe interface module (2) into the Flash module (5), temporarily stores the configuration table inside the FPGA programmable gate array subsystem (3) and performs CRC check on the configuration table; the host computer module (4) is connected to the PCIe interface module (2) and is used to send instructions for writing a configuration table group into the Flash module (5) or loading a configuration table group; the Flash module (5) is connected to the FPGA programmable gate array subsystem (3) and is used to store multiple groups of configuration tables, each terminal type corresponds to a group of configuration tables, and each group contains a number of configuration tables.

2. A storage system for ARINC664 terminal configuration table according to claim 1, characterized in that: The FPGA programmable gate array subsystem (3) includes a configuration table selection module (31), a high-speed data communication module (32), a Flash driver module (33), a Flash configuration table storage and reading module (34), and a Flash configuration table temporary storage module (35); the configuration table selection module (31) is connected to the key module (1), the high-speed data communication module (32), and the Flash configuration table storage and reading module (34), and is used to process the selection or operation instructions obtained from the key module (1) or the host computer module (4); the high-speed data communication module (32) is connected to the PCIe interface module (2), the configuration table selection module (31), and the Flash configuration table storage and reading module (34), and is used to process the selection or operation instructions obtained from the key module (1) or the host computer module (4). The Flash driver module (33) is connected to the Flash module (5) and the Flash configuration table storage and reading module (34) to drive the Flash chip to complete the specified read and write operations; the Flash configuration table storage and reading module (34) is connected to the configuration table selection module (31), the high-speed data communication module (32), the Flash driver module (33) and the Flash configuration table temporary storage module (35) to control and manage the process of reading and writing the Flash configuration table, including writing the received configuration table group into the Flash module (5) and reading the configuration table group from the Flash module (5); The Flash configuration table temporary storage module (35) is connected to the Flash configuration table storage and reading module (34) and is used for temporarily storing the configuration table being read and written and performing periodic CRC check.

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