Chip output data acquisition method and device, electronic equipment and storage medium

Abstract

The invention provides a chip output data collection method and device, electronic equipment and a storage medium, and relates to the technical field of chip test.The method comprises the steps that output signals of multiple chips are collected at the same time within a preset time period according to a preset sampling frequency, and multiple sets of binary data streams are obtained; for the target group of binary data streams, a target bit stream corresponding to the target group of binary data streams is determined according to a predetermined algorithm, the target group of binary data streams are any group of binary data streams, and the target bit stream comprises bit data corresponding to the output signal of the target chip; each piece of bit data in the target bit stream corresponds to one square wave signal in the output signals of the target chip; and converting the target bit stream into target byte data through an inverse transformation algorithm, wherein the target byte data is used for representing byte data corresponding to the output signal of the target chip. By implementing the technical scheme provided by the invention, the effect of improving the chip testing efficiency is achieved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a method, device, electronic device and storage medium for collecting chip output data. Background Art

[0002] During the mass production of integrated circuits, chip testing efficiency directly impacts overall production performance. In scenarios where multiple chips need to be tested simultaneously, if the starting time points of the outputs from multiple chips are unstable, there's no way to read the chip output data simultaneously at a specific time point. Testing methods in related technologies typically employ serial reading, which serializes the output data from each chip one by one. While this ensures data accuracy, efficiency is significantly reduced when faced with a large number of chips outputting data concurrently, impacting production line throughput. This serial reading approach in related technologies results in excessively long test times, reducing the overall efficiency of large-scale chip testing. In particular, in the case of multiple chips outputting data in parallel, real-time or near-real-time data capture cannot be achieved, limiting the flexibility and responsiveness of the production line. Summary of the Invention

[0003] In order to solve the above technical problems, the present application provides a method, device, electronic device and storage medium for collecting chip output data.

[0004] In the first aspect, the present application provides a method for collecting chip output data, including: simultaneously collecting the output signals of multiple chips at a preset sampling frequency within a preset time period to obtain multiple groups of binary data streams; for a target group of binary data streams, determining a target bit stream corresponding to the target group of binary data streams according to a predetermined algorithm, wherein the target group of binary data streams is any one of the multiple groups of binary data streams, the target bit stream includes bit data corresponding to the output signal of the target chip, each bit data in the target bit stream corresponds to a square wave signal in the output signal of the target chip, and the multiple chips include the target chip; converting the target bit stream into target byte data through an inverse transformation algorithm, wherein the target byte data is used to represent the byte data corresponding to the output signal of the target chip.

[0005] By adopting the above technical solution, the output signals of multiple chips are simultaneously collected at a preset sampling frequency within a preset time period, which can avoid the inefficiency caused by the serial reading method, realize parallel data collection, and significantly shorten the test time; for the target group binary data stream, the target bit stream is determined according to a predetermined algorithm, and the bit data corresponding to the output signal of the target chip can be accurately extracted to ensure the accuracy of the data; the target bit stream is converted into target byte data through an inverse transformation algorithm, realizing efficient conversion from original collected data to readable byte data, which is convenient for subsequent analysis and processing. Even if the output signals of multiple chips are not synchronized, this technical solution can collect and process the output signals of multiple chips at the same time, thereby effectively improving the efficiency of chip testing.

[0006] Optionally, for the target group binary data stream, the target bit stream corresponding to the target group binary data stream is determined according to a predetermined algorithm, including: preprocessing the target group binary data stream to obtain a processed binary data stream, wherein the preprocessing is used to represent extracting a valid data area from the target group binary data stream; using a statistical analysis algorithm to compare the number of data points in the processed binary data stream where the sampled data corresponding to each square wave signal is 0 and 1, so as to determine the bit data corresponding to each square wave signal and obtain the target bit stream.

[0007] By adopting the above technical solution, the bit data corresponding to the square wave signal can be effectively extracted from the target group binary data stream. Specifically, by preprocessing the target group binary data stream, the valid data area can be accurately located, reducing the interference of invalid data, thereby improving the accuracy of data processing; using a statistical analysis algorithm to compare the number of data points of 0 and 1 in all the sampled data of each square wave signal, the bit data corresponding to each square wave signal can be reliably determined, ensuring the accuracy of bit stream generation. This solution significantly improves the efficiency and accuracy of chip output data acquisition, especially in the case of parallel output of multiple chips, and can achieve real-time or quasi-real-time data capture, effectively solving the problem of low efficiency of serial reading mentioned in related technologies.

[0008] Optionally, a statistical analysis algorithm is used to compare the number of data points in the processed binary data stream whose sampling data corresponding to each square wave signal is 0 and 1 to determine the bit data corresponding to each square wave signal, including: the target square wave signal is any square wave signal in the output signal of the target chip, and the number of data points in which the sampling data corresponding to the target square wave signal is 0 and 1 is counted to obtain a statistical result; and the bit data corresponding to the target square wave signal is determined to be 0 or 1 based on the statistical result.

[0009] By employing this technical solution, the bit data corresponding to each square wave signal in the processed binary data stream can be accurately determined. Specifically, by counting the number of data points where the sampled data corresponding to the target square wave signal is 0 and 1, the high and low level states of each square wave signal can be effectively distinguished, thereby ensuring the accuracy of the bit data determination. This method not only improves the reliability of data analysis, but also reduces the probability of misjudgment when multiple chips are outputting in parallel, thereby improving overall test efficiency.

[0010] Optionally, determining whether the bit data corresponding to the target square wave signal is 0 or 1 is based on the statistical results, including: when the statistical results indicate that the number of data points with sampled data of 0 is greater than the number of data points with sampled data of 1, determining that the bit data corresponding to the target square wave signal is 0; when the statistical results indicate that the number of data points with sampled data of 0 is less than the number of data points with sampled data of 1, determining that the bit data corresponding to the target square wave signal is 1.

[0011] By adopting the above technical solution, if the statistical results show that the number of data points of the sampled data is 0 is greater than the number of data points of 1, then the bit data corresponding to the target square wave signal is determined to be 0; if the statistical results show that the number of data points of the sampled data is 0 is less than the number of data points of 1, then the bit data corresponding to the target square wave signal is determined to be 1; by counting the number of data points of 0 and 1 in the sampled data and determining the value of the bit data based on the comparison result, the accuracy of data analysis is improved, and the influence of signal noise or interference on data judgment is effectively avoided; this method can adapt to the characteristics of output signals of different chips, ensure that data can still be stably captured and analyzed in complex environments, and improve the reliability of the overall test system.

[0012] Optionally, the target bit stream is converted into target byte data through an inverse transformation algorithm, including: converting binary data in the target bit stream into hexadecimal data according to a fixed mapping rule to obtain the target byte data.

[0013] By adopting the above technical solution, binary data can be converted into hexadecimal data based on the collected target bit stream using fixed mapping rules, thereby efficiently generating the target byte data. This approach simplifies the data conversion process, ensures the accuracy and consistency of data representation, and improves data processing efficiency, facilitating subsequent analysis and application. Specifically, the effect of converting according to fixed mapping rules is to clarify the uniformity of the data format, reduce errors caused by inconsistent data formats, and improve the reliability of the entire system.

[0014] Optionally, the preset time period is a time period starting from a time point within the test waiting cycle, the duration corresponding to the preset time period is greater than or equal to the preset duration, the preset duration D = (N+2) × T, and the preset sampling frequency is greater than or equal to K times 1 / T, where N represents the bit data length represented by the output signals of multiple chips, T represents the period of each square wave signal in the output signal, and K represents the number of sampling points for each square wave signal.

[0015] By adopting the above technical solution, by setting a preset time period and a preset sampling frequency, the simultaneous acquisition of output signals of multiple chips is ensured, the inefficiency of the traditional serial reading method is avoided, and the overall efficiency of large-scale chip testing is improved; the duration of the preset time period is designed to be greater than or equal to the preset duration D = (N + 2) × T, which ensures that the acquisition process can cover the complete output signal cycle, thereby improving the integrity and accuracy of data acquisition; the preset sampling frequency is greater than or equal to K times 1 / T, which ensures sufficient sampling of each square wave signal, improves the accuracy of data acquisition, and further guarantees the reliability of subsequent data processing.

[0016] Optionally, the above method further includes: monitoring the output signals of multiple chips in real time during the acquisition process; and dynamically adjusting the preset sampling frequency and preset duration according to the monitoring results.

[0017] By adopting the above technical solution, the output signals of multiple chips can be monitored in real time during the chip output signal acquisition process, and the preset sampling frequency and preset duration can be dynamically adjusted based on the monitoring results. This technical means can effectively deal with unstable chip output signals and ensure the adaptability and accuracy of the acquisition process. Specifically, real-time monitoring of the output signals of multiple chips can promptly detect signal changes and avoid data acquisition errors or omissions caused by signal fluctuations; dynamically adjusting the preset sampling frequency can optimize sampling accuracy based on the frequency of signal changes and reduce unnecessary sampling points, thereby improving acquisition efficiency and reducing system load; dynamically adjusting the preset duration can flexibly set the acquisition window based on the signal duration, ensuring that acquisition is completed within the signal stability period, further improving data reliability and integrity.

[0018] Optionally, the preset sampling frequency and preset duration are dynamically adjusted according to the monitoring results, including: automatically adjusting the preset sampling frequency according to the changing frequency of the output signals of multiple chips; automatically adjusting the preset duration according to the duration of the output signals of multiple chips.

[0019] By adopting the above technical solution, when the chip output signal changes, the sampling frequency and the duration of the acquisition period can be dynamically adjusted according to the frequency and duration of the signal change. This enables the acquisition method to adapt to the characteristics of different chip output signals and avoid the problem of inaccurate or inefficient data acquisition caused by fixed parameters. Specifically, the preset sampling frequency is automatically adjusted according to the frequency of change of the chip output signal, ensuring that the sampling frequency is increased to capture more details when the signal changes faster, and the sampling frequency is reduced to reduce redundant data when the signal changes slowly, thereby improving the accuracy and efficiency of data acquisition; and the preset duration is automatically adjusted according to the duration of the chip output signal, so that the acquisition period can cover the complete signal cycle, avoiding signal truncation due to too short an acquisition period or waste of resources due to too long an acquisition period, further optimizing the time management of the test process.

[0020] In the second aspect of the present application, a device for collecting chip output data is also provided, including: an acquisition module, used to simultaneously collect the output signals of multiple chips according to a preset sampling frequency within a preset time period to obtain multiple groups of binary data streams; a processing module, used to determine the target bit stream corresponding to the target group binary data stream according to a predetermined algorithm, wherein the target group binary data stream is any group of binary data streams among the multiple groups of binary data streams, the target bit stream includes bit data corresponding to the output signal of the target chip, each bit data in the target bit stream corresponds to a square wave signal in the output signal of the target chip, and the multiple chips include the target chip; a conversion module, used to convert the target bit stream into target byte data through an inverse transformation algorithm, wherein the target byte data is used to represent the byte data corresponding to the output signal of the target chip.

[0021] In a third aspect of the present application, an electronic device is provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor implements any one of the above method steps when executing the program.

[0022] In a fourth aspect of the present application, a computer-readable storage medium is further provided. The computer-readable storage medium stores instructions. When the instructions are executed, any one of the above method steps is performed.

[0023] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. It can avoid the inefficiency problem caused by the serial reading method and significantly shorten the test time; it can simultaneously collect and process the output signals of multiple chips, effectively improving the chip test efficiency; 2. By counting the number of data points where the sampled data corresponding to the target square wave signal is 0 and 1, the high and low level states of each square wave signal can be effectively distinguished, thereby ensuring the accuracy of bit data determination. This not only improves the reliability of data analysis, but also reduces the probability of misjudgment in the case of parallel output of multiple chips, thereby improving overall test efficiency. 3. By setting the preset time period and preset sampling frequency, the simultaneous acquisition of multiple chip output signals is ensured, avoiding the inefficiency of the traditional serial reading method and improving the overall efficiency of large-scale chip testing; the duration of the preset time period is designed to be greater than or equal to the preset duration D = (N+2) × T, ensuring that the acquisition process can cover the complete output signal cycle, thereby improving the integrity and accuracy of data acquisition; the preset sampling frequency is greater than or equal to K times 1 / T, ensuring sufficient sampling of each square wave signal, improving the accuracy of data acquisition, and further ensuring the reliability of subsequent data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a flow chart of a method for collecting chip output data provided by an embodiment of the present application; Figure 2 This is an example of a chip output signal waveform provided in an embodiment of the present application. Figure 1 ; Figure 3 This is an example of a chip output signal waveform provided in an embodiment of the present application. Figure 2 ; Figure 4 This is an example diagram of a sampling starting point provided in an embodiment of the present application; Figure 5 This is a schematic diagram of a chip output data collection process provided in an embodiment of the present application; Figure 6 This is a structural block diagram of a device for collecting chip output data provided in an embodiment of the present application; Figure 7 This is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application.

[0025] Description of reference numerals: 700 - electronic device; 701 - processor; 702 - communication bus; 703 - user interface; 704 - network interface; 705 - memory. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0027] In the description of the embodiments of this application, words such as "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "for example" or "for instance" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "for example" or "for instance" is intended to present the relevant concepts in a concrete manner.

[0028] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprise," "have" and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0029] The following is combined with Figure 1-Figure 7 The embodiments of the present application are described.

[0030] This application provides a method for collecting chip output data, referring to Figure 1 , Figure 1 : is a flow chart of a chip output data collection method provided in an embodiment of the present application, the method comprising: Step S101, sampling output signals of multiple chips simultaneously at a preset sampling frequency within a preset time period to obtain multiple sets of binary data streams; Step S102: determining a target bit stream corresponding to a target group binary data stream according to a predetermined algorithm, wherein the target group binary data stream is any one of a plurality of binary data streams, the target bit stream includes bit data corresponding to an output signal of a target chip, each bit data in the target bit stream corresponds to a square wave signal in the output signal of the target chip, and the plurality of chips include the target chip; Step S103: converting the target bit stream into target byte data through an inverse transformation algorithm, wherein the target byte data is used to represent the byte data corresponding to the output signal of the target chip.

[0031] Through the above steps, the output signals of multiple chips are simultaneously collected at a preset sampling frequency within a preset time period, which can avoid the inefficiency caused by the serial reading method, realize parallel data collection, and significantly shorten the test time; for the target group binary data stream, the target bit stream is determined according to a predetermined algorithm, and the bit data corresponding to the output signal of the target chip can be accurately extracted to ensure the accuracy of the data; the target bit stream is converted into target byte data through an inverse transformation algorithm, realizing efficient conversion from original collected data to readable byte data, which is convenient for subsequent analysis and processing. Even if the output signals of multiple chips are not synchronized, this embodiment can also collect and process the output signals of multiple chips at the same time, thereby effectively improving the chip testing efficiency.

[0032] For the application scenario of testing multiple chips at the same time, this embodiment first collects the output signals of multiple chips at the same time according to the preset sampling frequency within a preset time period, so that multiple groups of binary data streams can be obtained, ensuring that the output information of each chip in the same time period can be fully collected, providing a data basis for subsequent processing; then, for any group of binary data streams, such as the target group binary data stream, a predetermined algorithm is used to determine its corresponding target bit stream. Since each bit data corresponds to a square wave signal in the output signal of the target chip, this algorithm can accurately extract the bit data related to the output signal of the target chip from the collected binary data stream, thereby realizing the precise positioning and extraction of the output data of each chip; finally, the target bit stream is converted into target byte data through the inverse transformation algorithm, and the bit data is converted into more practical byte data, so as to facilitate the subsequent understanding and processing of the chip output data. The above-mentioned preset time period can be a time period starting from a time point within the test waiting cycle. Generally, during the test, there is a test waiting cycle between inputting the test signal to the chip and outputting the signal from the chip. For example, the test waiting cycle is 500us (or other time). The duration of the preset time period is greater than or equal to the preset time length. In practical applications, the output signal is composed of multiple square wave signals, each square wave signal corresponds to a bit number, and the preset time length can be the number of bits corresponding to the output signal of each chip multiplied by the period corresponding to each square wave signal. For example, the preset time length = N×T, N is the number of bit data bits corresponding to the output signal, and T is the period of each square wave signal. Preferably, in order to ensure the integrity of the collected signal, several more periods can be collected, for example, the preset time length = (N+2)×T, where 2 is merely an example. The preset sampling frequency (or sampling rate) can be determined based on the number of sampling points within each square wave signal. For example, if K points are planned to be sampled for each square wave signal, then the preset sampling frequency is greater than or equal to K / T. This embodiment is suitable for situations where the output signals of multiple chips are asynchronous, which is not possible in the related art. In the related art, such situations can only be addressed by serial reading, which significantly reduces efficiency when dealing with a large number of chips with concurrent output. The method of this embodiment, by simultaneously collecting the output signals of multiple chips within a preset time period, avoids the time-consuming process of serial reading each chip one by one, significantly improving data collection efficiency. This is particularly applicable to scenarios with multiple chips with parallel output, effectively resolving the issue of excessive test time caused by serial reading. This improved collection efficiency shortens the time required to test large quantities of chips, thereby improving overall production efficiency and increasing production line throughput. The ability to capture data in real time or near real time allows the production line to quickly adjust and respond based on the timely data acquired, enhancing its flexibility and responsiveness, and helping to better adapt to varying production needs and changes.

[0033] In an optional embodiment, for a target group binary data stream, a target bit stream corresponding to the target group binary data stream is determined according to a predetermined algorithm, including: preprocessing the target group binary data stream to obtain a processed binary data stream, wherein the preprocessing is used to represent extracting a valid data area from the target group binary data stream; using a statistical analysis algorithm to compare the number of data points in the processed binary data stream where the sampled data corresponding to each square wave signal is 0 and 1, so as to determine the bit data corresponding to each square wave signal and obtain the target bit stream.

[0034] In the above embodiment, the bit data corresponding to the square wave signal can be effectively extracted from the target group binary data stream. Specifically, by preprocessing the target group binary data stream, the valid data area can be accurately located, the interference of invalid data can be reduced, and the accuracy of data processing can be improved; using a statistical analysis algorithm to compare the number of data points of 0 and 1 in all sampled data of each square wave signal, the bit data corresponding to each square wave signal can be reliably determined, ensuring the accuracy of bit stream generation. This method significantly improves the efficiency and accuracy of chip output data acquisition, especially in the case of multi-chip parallel output, and can achieve real-time or quasi-real-time data capture, effectively solving the problem of low efficiency of serial reading mentioned in the related art.

[0035] During the chip output signal acquisition process, noise or invalid data may exist, affecting the accuracy and reliability of the data. This embodiment preprocesses the target group binary data stream in order to accurately extract the data portion containing valid information from the collected original data. This can remove possible irrelevant data or noise interference, laying the foundation for subsequent accurate analysis and processing of data. A statistical analysis algorithm is used to compare the number of data points of 0 and 1 in the sampled data corresponding to each square wave signal in the processed binary data stream. Since the square wave signal in the chip output signal corresponds to the bit data, this statistical analysis method can be used to determine the bit data corresponding to each square wave signal based on the comparison of the number of data points of 0 and 1, and then obtain the target bit stream, thereby realizing the conversion from the original binary data stream to meaningful bit stream data. Specifically, the statistical analysis algorithm described above compares the number of data points in the processed binary data stream where the sampled data corresponding to each square wave signal is 0 or 1. Since the square wave signal in the chip output signal corresponds to a series of binary sampled data during acquisition, by counting the number of 0s and 1s, the bit data corresponding to the square wave signal can be determined according to the majority principle or other predetermined rules. These determined bit data are then combined to obtain the target bit stream. In this embodiment, preprocessing removes invalid data and noise, ensuring that the extracted bit data is more accurate and reliable. Using the statistical analysis algorithm, the bit data corresponding to each square wave signal can be quickly and accurately extracted from the binary data stream, improving data processing efficiency.

[0036] In an optional embodiment, a statistical analysis algorithm is used to compare the number of data points in the processed binary data stream where the sampled data corresponding to each square wave signal is 0 and 1 to determine the bit data corresponding to each square wave signal, including: the target square wave signal is any square wave signal in the output signal of the target chip, and the number of data points where the sampled data corresponding to the target square wave signal is 0 and 1 is counted to obtain a statistical result; and based on the statistical result, it is determined that the bit data corresponding to the target square wave signal is 0 or 1.

[0037] In the above embodiment, the bit data corresponding to each square wave signal can be accurately determined in the processed binary data stream. Specifically, by counting the number of data points where the sampled data corresponding to the target square wave signal is 0 and 1, the high and low level states of each square wave signal can be effectively distinguished, thereby ensuring the accuracy of the bit data determination. This method not only improves the reliability of data analysis, but also reduces the probability of misjudgment when multiple chips are output in parallel, thereby improving overall test efficiency.

[0038] For any square wave signal (target square wave signal) in the target chip's output signal, the number of data points corresponding to the sampled data that are 0 and 1 is counted to obtain a statistical result. During the chip output signal acquisition process, each square wave signal is sampled as a series of binary data (0 or 1) over a period of time. By counting the number of 0s and 1s in these data, the characteristics of the square wave signal during the sampling period can be understood. Based on the statistical results, the bit data corresponding to the target square wave signal is determined to be 0 or 1. Typically, a rule can be set: for example, when the number of 1s in the statistical result exceeds the number of 0s, the bit data corresponding to the square wave signal is determined to be 1; otherwise, it is determined to be 0. In this way, an accurate correspondence is established between the sampled data and the bit data corresponding to the chip output signal. For example, if 20 points are collected during a square wave signal cycle, of which 6 points have sampled data of 0 and 14 points have sampled data of 1, the bit data corresponding to the square wave signal is considered to be 1, indicating a high level. This embodiment can accurately reflect the information represented by each square wave signal in the chip output signal by accurately counting the number of 0s and 1s in the sampled data corresponding to the target square wave signal and determining the bit data based on the statistical results, thereby improving the accuracy of data conversion; accurately determining the bit data helps to obtain more reliable target byte data, thereby improving the reliability of the data collected during the entire chip testing process and providing a solid foundation for subsequent analysis and judgment; the clear statistical analysis algorithm enables different personnel to obtain consistent results when performing the same test, thereby enhancing the repeatability and consistency of the test method, and facilitating the promotion and application of chip testing technology.

[0039] In an optional embodiment, determining whether the bit data corresponding to the target square wave signal is 0 or 1 is based on statistical results, including: when the statistical results indicate that the number of data points with sampled data of 0 is greater than the number of data points with sampled data of 1, determining that the bit data corresponding to the target square wave signal is 0; when the statistical results indicate that the number of data points with sampled data of 0 is less than the number of data points with sampled data of 1, determining that the bit data corresponding to the target square wave signal is 1.

[0040] In the above embodiment, if the statistical result shows that the number of data points of the sampled data is 0 is greater than the number of data points of 1, then the bit data corresponding to the target square wave signal is determined to be 0; if the statistical result shows that the number of data points of the sampled data is 0 is less than the number of data points of 1, then the bit data corresponding to the target square wave signal is determined to be 1; by counting the number of data points of 0 and 1 in the sampled data and determining the value of the bit data based on the comparison result, the accuracy of data analysis is improved, and the influence of signal noise or interference on data judgment is effectively avoided; this method can adapt to the characteristics of output signals of different chips, ensure that data can still be stably captured and analyzed in complex environments, and improve the reliability of the overall test system.

[0041] In chip signal transmission, the high and low levels of a square wave signal typically correspond to logical 0 and 1. After counting the sampled data, if the number of data points with 0 values is greater than the number of data points with 1 values, based on the principle of high probability, it can be inferred that the square wave signal primarily exhibited a low-level state during transmission, and the corresponding bit data is determined to be 0. Conversely, if the number of data points with 1 values is greater than the number of data points with 0 values, it indicates that the square wave signal primarily exhibited a high-level state, and the corresponding bit data is determined to be 1. After counting the number of data points with 0 and 1 values corresponding to the target square wave signal, the two numbers are compared. If the number of data points with 0 values is greater than the number of data points with 1 values, it indicates that during the sampling period, the square wave signal was more likely to exhibit the state represented by 0, and therefore the bit data corresponding to the target square wave signal is determined to be 0. Conversely, if the number of data points with 0 values is less than the number of data points with 1 values, it indicates that during the sampling period, the square wave signal was more likely to exhibit the state represented by 1, and therefore the bit data corresponding to the target square wave signal is determined to be 1. The majority principle is a simple and effective determination method that can accurately reflect the main state of the square wave signal during the sampling period, thereby improving the accuracy of determining the bit data, so that the final target byte data can more truly reflect the output information of the chip; accurately and consistently determining the bit data helps the smooth progress of the entire chip output data acquisition method, reduces problems such as repeated testing caused by inaccurate or inconsistent bit data determination, optimizes the chip testing process, and improves test efficiency.

[0042] In an optional embodiment, the target bit stream is converted into target byte data by using an inverse transformation algorithm, including: converting binary data in the target bit stream into hexadecimal data according to a fixed mapping rule to obtain the target byte data.

[0043] In the above embodiment, based on the collected target bit stream, fixed mapping rules can be used to convert binary data into hexadecimal data, thereby efficiently generating target byte data. This approach simplifies the data conversion process, ensures the accuracy and consistency of data representation, improves data processing efficiency, and facilitates subsequent analysis and application. Specifically, the effect of converting according to fixed mapping rules is to clarify the uniformity of the data format, reduce errors caused by inconsistent data formats, and improve the reliability of the entire system.

[0044] In chip data processing, a bit stream is a binary data sequence consisting of 0s and 1s, while byte data is typically presented in hexadecimal format, which is more convenient for data storage, transmission, and subsequent analysis. Using fixed mapping rules, the binary data in the target bit stream is systematically converted into hexadecimal data, thereby obtaining the target byte data. For example, four consecutive binary bits can be mapped to one hexadecimal bit (0000 corresponds to 0, 0001 corresponds to 1, ..., 1111 corresponds to F). By mapping and combining them segment by segment, the conversion from binary bit stream to hexadecimal byte data is completed, achieving a transition from the underlying binary format to the more easily processable hexadecimal format. Fixed mapping rules are relatively simple and straightforward, requiring no complex calculations. They can quickly complete the conversion from binary bit stream to hexadecimal byte data. During chip testing, large amounts of data can be quickly processed, reducing data waiting time, significantly improving the overall efficiency of chip testing, accelerating production line operation, and increasing production capacity.

[0045] In an optional embodiment, the preset time period is a time period starting from a time point within the test waiting cycle, the duration corresponding to the preset time period is greater than or equal to the preset duration, the preset duration D = (N+2) × T, and the preset sampling frequency is greater than or equal to K times 1 / T, where N represents the bit data length represented by the output signals of multiple chips, T represents the period of each square wave signal in the output signal, and K represents the number of sampling points for each square wave signal.

[0046] In the above embodiment, by setting a preset time period and a preset sampling frequency, the simultaneous acquisition of output signals of multiple chips is ensured, the inefficiency of the traditional serial reading method is avoided, and the overall efficiency of large-scale chip testing is improved; the duration of the preset time period is designed to be greater than or equal to the preset duration D = (N+2) × T, which ensures that the acquisition process can cover the complete output signal cycle, thereby improving the integrity and accuracy of data acquisition; the preset sampling frequency is greater than or equal to K times 1 / T, which ensures sufficient sampling of each square wave signal, improves the accuracy of data acquisition, and further guarantees the reliability of subsequent data processing.

[0047] The preset time period begins at a point within the test wait cycle and lasts longer than or equal to the preset duration, D = (N + 2) × T, where N represents the bit length of the output signals of the multiple chips, and T represents the period of each square wave signal in the output signal. This setting ensures that the bit data represented by the chip output signals can be fully acquired within the preset period. To account for possible transitions at the beginning and end of the signal, an additional duration of 2T is added to ensure the integrity of the acquired data. The preset sampling frequency is greater than or equal to K times 1 / T, where K represents the number of sampling points for each square wave signal. Since each square wave signal has a period of T, at least K samples are required within each period to ensure accurate acquisition of the square wave signal's characteristics. Therefore, the sampling frequency must meet this condition to ensure that the acquired data truly reflects the changes in the chip output signal. This embodiment ensures that the chip output signal can be completely and accurately collected through reasonable preset time period and preset sampling frequency settings, improves the accuracy of the collected binary data stream, and provides a reliable basis for subsequent bit stream determination and byte data conversion; accurate data collection reduces the complexity and error of subsequent data processing, making the entire chip output data collection method more efficient and stable, and optimizing the data processing flow of chip testing; by clarifying the relationship between the preset time period and preset sampling frequency and the chip output signal parameters (bit data length, square wave signal period, number of sampling points), the test method can adapt to the test requirements of chips with different characteristics, thereby enhancing the versatility and applicability of the test method.

[0048] In an optional embodiment, the above method further includes: monitoring the output signals of multiple chips in real time during the acquisition process; and dynamically adjusting the preset sampling frequency and preset duration according to the monitoring results.

[0049] In the above embodiment, the output signals of multiple chips can be monitored in real time during the chip output signal acquisition process, and the preset sampling frequency and preset duration can be dynamically adjusted based on the monitoring results. This technical means can effectively deal with the situation where the chip output signal is unstable and ensure the adaptability and accuracy of the acquisition process. Specifically, real-time monitoring of the output signals of multiple chips can promptly detect signal changes and avoid data acquisition errors or omissions caused by signal fluctuations; dynamic adjustment of the preset sampling frequency can optimize sampling accuracy based on the frequency of signal changes and reduce unnecessary sampling points, thereby improving acquisition efficiency and reducing system load; dynamic adjustment of the preset duration can flexibly set the acquisition window based on the signal duration, ensuring that acquisition is completed within the signal stability period, further improving data reliability and integrity.

[0050] This embodiment monitors the output signals of multiple chips in real time during the acquisition process, enabling real-time acquisition of chip output signal status information, including signal stability, frequency variations, amplitude fluctuations, and so on. This monitoring data reflects the actual characteristics of the chip output signals, providing a basis for subsequent adjustments. The preset sampling frequency and duration are dynamically adjusted based on the monitoring results. If monitoring reveals a change in the frequency of the chip output signal, the original preset sampling frequency may not meet the requirements for accurate acquisition. In this case, the sampling frequency needs to be adjusted to ensure that each square wave signal is sampled a sufficient number of times. Similarly, if the signal's bit data length or period changes, the preset duration also needs to be adjusted accordingly to ensure that valid data is fully acquired.

[0051] In an optional embodiment, the preset sampling frequency and the preset duration are dynamically adjusted according to the monitoring results, including: automatically adjusting the preset sampling frequency according to the changing frequency of the output signals of multiple chips; automatically adjusting the preset duration according to the duration of the output signals of multiple chips.

[0052] In the above embodiment, when the chip output signal changes, the sampling frequency and the duration of the acquisition period can be dynamically adjusted according to the frequency and duration of the signal change. This enables the acquisition method to adapt to the characteristics of different chip output signals and avoid the problem of inaccurate or inefficient data acquisition caused by fixed parameters. Specifically, the preset sampling frequency is automatically adjusted according to the frequency of change of the chip output signal, ensuring that the sampling frequency is increased to capture more details when the signal changes faster, and the sampling frequency is reduced to reduce redundant data when the signal changes slowly, thereby improving the accuracy and efficiency of data acquisition; and the preset duration is automatically adjusted according to the duration of the chip output signal, so that the acquisition period can cover the complete signal cycle, avoiding signal truncation due to too short an acquisition period or waste of resources due to too long an acquisition period, further optimizing the time management of the test process.

[0053] Based on real-time monitoring of multiple chip output signals, the preset sampling frequency and preset duration are dynamically adjusted based on the signal's frequency of change and duration. By monitoring the output signal's frequency of change, the dynamic characteristics of the signal can be understood. When the signal changes frequently, the preset sampling frequency is increased to ensure that every detail of the signal change is captured; conversely, when the signal changes more slowly, the sampling frequency is appropriately reduced to avoid collecting excessive redundant data. Adjusting the preset duration based on the output signal's duration ensures that the acquisition process fully covers the signal's valid period, avoiding data loss due to a duration that is too short or resource waste due to a duration that is too long. By automatically adjusting the preset sampling frequency based on the output signal's frequency of change, this embodiment enables the sampling process to accurately adapt to the signal's dynamic characteristics. Whether the signal is changing rapidly or slowly, it can be acquired at an appropriate sampling frequency, effectively improving the quality and effectiveness of the acquired data and providing a reliable data foundation for accurate chip performance analysis. Automatically adjusting the preset duration based on the output signal's duration ensures the rational use of acquisition resources and avoids resource waste or incomplete data caused by unreasonable acquisition durations. While ensuring the collection of complete and valid data, unnecessary data collection and processing are reduced, the operating efficiency of the entire chip testing system is improved, and costs are reduced.

[0054] Obviously, the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below with reference to specific embodiments.

[0055] For the scenario of testing multiple chips simultaneously, the conventional approach is to perform serial reading because the output times of most chips may not be consistent. However, serial reading greatly prolongs the time required, wasting mass production efficiency. In the scenario of parallel output of multiple chips, the traditional serial reading method is inefficient due to the output time difference, which seriously affects the rapidity of chip testing and the efficiency of large-scale production.

[0056] The embodiment of the present application provides a high-speed acquisition method for chip output data. The solution of the present application is to read the entire waveform output by the chip in a short time interval sampling manner. Probably hundreds of data will be read (a continuous 000000111111100000011111). In this data, 1 represents a high level and 0 represents a low level. This is equivalent to converting the sequence and duration of high and low levels in the chip output waveform into the sequence and number of data points of continuous 0 and 1. Then, statistical operations are performed on the waveform output by the chip corresponding to this string of data to calculate whether each bit of the output data is 0 or 1. Finally, these data points are restored to the bytes output by the chip through decoding operations.

[0057] In order to solve the problem of low serial reading efficiency caused by asynchronous output time when multiple chips are outputting in parallel, the following solution is proposed: Using a high-frequency sampling method within a short period of time, the waveform data output by all chips is captured at once, regardless of whether there are differences in their output time points. This includes the following steps: S1: Set the high-frequency sampling rate to continuously collect the chip output signal within a predetermined time period, and convert the collected signal stream into a binary data stream, where 1 represents a high level and 0 represents a low level, forming a continuous sequence of 0s and 1s.

[0058] S2: Preprocess the obtained binary data stream, extract the valid data area, and eliminate the invalid part.

[0059] S3: Using a statistical analysis algorithm, the number of data points of 0 and 1 in each bit of data is compared to determine the bit of data.

[0060] S4: Based on the recognition results, the original chip output byte data is reconstructed through the inverse transformation algorithm.

[0061] Figure 2 This is an example of the waveform of the chip output signal Figure 1 , contains multiple square wave signals, each square wave signal represents a bit number, such as 0 or 1, such as Figure 2 The waveforms corresponding to the continuous black, gray and thick black lines are bit1, bit1 and bit0 respectively; Figure 3 This is the actual waveform. Figure 2 and Figure 3 It can be seen that a bit of 0 (bit0) indicates that the low level accounts for a large proportion in a square wave period, and a bit of 1 (bit1) indicates that the high level accounts for a large proportion in a square wave period.

[0062] Specific examples: Assume that the number of chips to be tested is 8, the sampling rate is tens to hundreds of kHz, and the expected acquisition time is 3.5ms.

[0063] First, all chip output signals are densely sampled at this rate within 3.5ms to obtain 8 segments of binary data streams with more than 100 sample points. For example, if the number of sampling points for each square wave signal is 20, at least 160 sample points are sampled.

[0064] Next, the continuous 1s and 0s in each data stream are counted and compared in turn to parse out the actual binary sequence output by each chip.

[0065] Finally, the binary expression is restored to a hexadecimal number through decoding, which is a set of byte information that accurately reflects the output characteristics of each chip.

[0066] like Figure 4 As shown, the leftmost square wave signal represents the signal in the test waiting period, which is generally a high level. The predetermined time period in the embodiment of the present application starts from a time point in the test waiting period, such as Figure 4 The sampling starting point in the test sampling period indicates the beginning of the first bit of data. Figure 4 The output waveform starting point in the output waveform is shown in Figure 2. In actual applications, each bit of data starts at a low level and ends at a high level. The ratio of high and low levels is used to represent 0 or 1. When performing multi-point acquisition on a square wave signal, multiple data points 0 may be collected during the low level period of a square wave signal. Similarly, multiple data points 1 may be collected during the high level period of a square wave signal.

[0067] Figure 5 This is a schematic diagram of a chip output data collection process provided by an embodiment of the present application, specifically including: After sampling, a waveform is converted into a binary data stream, such as Figure 5 "1110000000000111111000000111111111000000000011..."; Then extract the valid part and define the range of each bit. For example, the first few consecutive 1s in the above series of binary data streams represent the signal of the test waiting cycle, which is an invalid signal. The valid part starts from the first 0 at the end, and the range of each bit starts from 0 and ends at 1, which means that the next 0 represents the next bit of data. The number of 0s and 1s in each bit is used to determine whether the bit is 0 or 1, such as Figure 5 In the example, we get bit0=0, bit1=1, bit2=0, ...; Then, we get the binary representation of the output bytes, such as Figure 5 10011010 in Finally, the decoded code is restored to a hexadecimal number, such as 0X9A.

[0068] The embodiments of the present application have at least the following technical effects: after the sampling time is adjusted in a targeted manner, the parallel data reading of multiple chips can be carried out stably with an accuracy rate of up to 100%; because of the use of short time interval sampling technology and parallel computing architecture, the efficiency and accuracy of multi-chip testing are greatly improved, and the test time is greatly shortened compared to the traditional serial method, achieving a time saving of more than 95%; these technical means work together to make the chip testing process more efficient and stable, which not only improves the performance of the test link in large-scale production, but also provides more accurate basic data support for subsequent quality management and performance analysis.

[0069] This application also provides a device for collecting chip output data, such as Figure 6 As shown, Figure 6 This is a structural block diagram of a chip output data acquisition device provided in an embodiment of the present application, the device comprising: The acquisition module 601 is used to simultaneously acquire the output signals of multiple chips at a preset sampling frequency within a preset period of time to obtain multiple sets of binary data streams; a processing module 602 configured to determine, for a target group binary data stream, a target bit stream corresponding to the target group binary data stream according to a predetermined algorithm, wherein the target group binary data stream is any one of a plurality of binary data streams, the target bit stream includes bit data corresponding to an output signal of a target chip, each bit data in the target bit stream corresponds to a square wave signal in the output signal of the target chip, and the plurality of chips include the target chip; The conversion module 603 is used to convert the target bit stream into target byte data through an inverse transformation algorithm, wherein the target byte data is used to represent the byte data corresponding to the output signal of the target chip.

[0070] In an optional embodiment, the above-mentioned processing module 602 includes: a preprocessing unit, which is used to preprocess the target group binary data stream to obtain a processed binary data stream, wherein the preprocessing is used to represent the extraction of a valid data area from the target group binary data stream; a determination unit, which is used to use a statistical analysis algorithm to compare the number of data points in the processed binary data stream where the sampling data corresponding to each square wave signal is 0 and 1, so as to determine the bit data corresponding to each square wave signal and obtain the target bit stream.

[0071] In an optional embodiment, the above-mentioned determination unit includes: a statistical subunit, which counts the number of data points whose sampling data corresponding to the target square wave signal is 0 and 1 to obtain a statistical result, and the target square wave signal is any square wave signal in the output signal of the target chip; a determination subunit, which is used to determine whether the bit data corresponding to the target square wave signal is 0 or 1 based on the statistical result.

[0072] In an optional embodiment, the above-mentioned determination subunit is used to determine whether the bit data corresponding to the target square wave signal is 0 or 1 in the following manner: when the statistical result indicates that the number of data points with sampled data of 0 is greater than the number of data points with sampled data of 1, the bit data corresponding to the target square wave signal is determined to be 0; when the statistical result indicates that the number of data points with sampled data of 0 is less than the number of data points with sampled data of 1, the bit data corresponding to the target square wave signal is determined to be 1.

[0073] In an optional embodiment, the conversion module 603 includes: a conversion unit, configured to convert binary data in the target bit stream into hexadecimal data according to a fixed mapping rule to obtain target byte data.

[0074] In an optional embodiment, the above-mentioned preset time period is a time period starting from a time point within the test waiting cycle, the duration corresponding to the preset time period is greater than or equal to the preset duration, the preset duration D = (N+2) × T, and the preset sampling frequency is greater than or equal to K times 1 / T, where N represents the bit data length represented by the output signals of multiple chips, T represents the period of each square wave signal in the output signal, and K represents the number of sampling points for each square wave signal.

[0075] In an optional embodiment, the above-mentioned device further includes: a monitoring module for monitoring the output signals of multiple chips in real time during the acquisition process; and an adjustment module for dynamically adjusting the preset sampling frequency and preset duration according to the monitoring results.

[0076] In an optional embodiment, the above-mentioned adjustment module includes: a first adjustment unit, used to automatically adjust the preset sampling frequency according to the changing frequency of the output signals of multiple chips; a second adjustment unit, used to automatically adjust the preset duration according to the duration of the output signals of multiple chips.

[0077] It should be noted that the above embodiments provide devices that implement their functions using only the division of the above functional modules as examples. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0078] The present application also provides a computer-readable storage medium, which stores instructions. When the instructions are executed, any one of the above-mentioned method steps is executed.

[0079] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0080] This application also discloses an electronic device. Figure 7 As shown, Figure 7Schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application. The electronic device 700 may include: at least one processor 701, at least one communication bus 702, a user interface 703, at least one network interface 704, and a memory 705.

[0081] The communication bus 702 is used to implement the connection and communication between these components.

[0082] The user interface 703 may include a display screen (Display) and a camera (Camera). Optionally, the user interface 703 may also include a standard wired interface and a wireless interface.

[0083] The network interface 704 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0084] The processor 701 may include one or more processing cores. Using various interfaces and circuits, the processor 701 connects various components within the electronic device (such as a server). By running or executing instructions, programs, code sets, or instruction sets stored in the memory 705 and accessing data stored in the memory 705, the processor 701 performs various server functions and processes data. Optionally, the processor 701 may be implemented using at least one of the following hardware forms: a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 701 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing content displayed on the display; and the modem handles wireless communications. It is understood that the modem may also be implemented as a separate chip, rather than integrated into the processor 701.

[0085] Among them, the memory 705 may include a random access memory (RAM) or a read-only memory (Read-Only Memory). Optionally, the memory 705 includes a non-transitory computer-readable storage medium. The memory 705 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 705 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 705 may also optionally be at least one storage device located away from the aforementioned processor 701. Refer to Figure 7 , the memory 705 as a computer storage medium may include an operating system, a network communication module, a user interface module and an application program of a chip output data collection method.

[0086] exist Figure 7 In the electronic device 700 shown, the user interface 703 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 701 can be used to call an application program of a chip output data acquisition method stored in the memory 705. When executed by one or more processors 701, the electronic device 700 executes one or more of the methods described in the above embodiments. It should be noted that for the aforementioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should know that this application is not limited to the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required for this application.

[0087] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0088] The foregoing is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of the present disclosure. In other words, any equivalent variations and modifications made in accordance with the teachings of the present disclosure are still within the scope of the present disclosure. Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the disclosure herein.

[0089] This application is intended to cover any modifications, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not described in the present disclosure.

Claims

1. A method for collecting chip output data, characterized in that: include: The output signals of multiple chips are collected simultaneously at a preset sampling frequency within a preset time period to obtain multiple sets of binary data streams; For a target group binary data stream, determining a target bit stream corresponding to the target group binary data stream according to a predetermined algorithm, wherein the target group binary data stream is any one of the multiple groups of binary data streams, the target bit stream includes bit data corresponding to an output signal of a target chip, each bit data in the target bit stream corresponds to a square wave signal in the output signal of the target chip, and the multiple chips include the target chip; The target bit stream is converted into target byte data through an inverse transformation algorithm, wherein the target byte data is used to represent byte data corresponding to the output signal of the target chip.

2. The method according to claim 1, characterized in that For a target group binary data stream, determining a target bit stream corresponding to the target group binary data stream according to a predetermined algorithm includes: Preprocessing the target group binary data stream to obtain a processed binary data stream, wherein the preprocessing is used to extract a valid data area from the target group binary data stream; A statistical analysis algorithm is used to compare the number of data points in the processed binary data stream whose sampled data corresponding to each square wave signal is 0 and 1, so as to determine the bit data corresponding to each square wave signal and obtain the target bit stream.

3. The method according to claim 2, characterized in that Using a statistical analysis algorithm, comparing the number of data points in the processed binary data stream where the sampled data corresponding to each square wave signal is 0 and the number of data points where the sampled data is 1, to determine the bit data corresponding to each square wave signal, including: The target square wave signal is any square wave signal among the output signals of the target chip, and the number of data points corresponding to the target square wave signal whose sampled data are 0 and 1 is counted to obtain a statistical result; Determine whether the bit data corresponding to the target square wave signal is 0 or 1 according to the statistical result.

4. The method according to claim 3, characterized in that Determining, according to the statistical result, whether the bit data corresponding to the target square wave signal is 0 or 1 includes: When the statistical result indicates that the number of data points where the sampled data is 0 is greater than the number of data points where the sampled data is 1, determining that the bit data corresponding to the target square wave signal is 0; When the statistical result indicates that the number of data points where the sampled data is 0 is less than the number of data points where the sampled data is 1, it is determined that the bit data corresponding to the target square wave signal is 1.

5. The method according to claim 1, wherein Converting the target bit stream into target byte data by an inverse transformation algorithm includes: The binary data in the target bit stream is converted into hexadecimal data according to a fixed mapping rule to obtain the target byte data.

6. The method according to claim 1, characterized in that The preset time period is a time period starting from a time point within the test waiting cycle, the duration corresponding to the preset time period is greater than or equal to the preset duration, the preset duration D=(N+2)×T, and the preset sampling frequency is greater than or equal to K times 1 / T, where N represents the bit data length represented by the output signals of the multiple chips, T represents the period of each square wave signal in the output signal, and K represents the number of sampling points for each square wave signal.

7. The method according to claim 6, characterized in that The method further comprises: monitoring the output signals of the plurality of chips in real time during the acquisition process; The preset sampling frequency and the preset duration are dynamically adjusted according to the monitoring results.

8. A device for collecting chip output data, characterized in that: include: An acquisition module is used to simultaneously acquire the output signals of multiple chips at a preset sampling frequency within a preset period of time to obtain multiple sets of binary data streams; a processing module, configured to determine, for a target group binary data stream, a target bit stream corresponding to the target group binary data stream according to a predetermined algorithm, wherein the target group binary data stream is any one of the multiple groups of binary data streams, the target bit stream includes bit data corresponding to an output signal of a target chip, each bit data in the target bit stream corresponds to a square wave signal in the output signal of the target chip, and the multiple chips include the target chip; A conversion module is used to convert the target bit stream into target byte data through an inverse transformation algorithm, wherein the target byte data is used to represent the byte data corresponding to the output signal of the target chip.

9. An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, and when the instructions are executed, the method according to any one of claims 1 to 7 is performed.

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