Coding graph neural network method and device, computer storage medium and terminal

Abstract

A method and device for encoding a graph neural network, a computer storage medium and a terminal, according to the embodiment of the disclosure, a node feature vector of a CNN of graph data is encoded into an initial node feature vector of a GNN network, an initial lightweight graph neural network (GNN) network is obtained, and the complexity and resource occupation of graph data calculation are effectively reduced; the method comprises the following steps of: mapping an initial aggregation operation of a lightweight GNN network to a processing unit array of an FPGA (Field Programmable Gate Array) by adopting a hierarchical feature aggregation mode to obtain a lightweight GNN model; the contribution value of the feature vector in the column direction is assigned to the corresponding PE, deployment of the lightweight GNN model on the FPGA is achieved, resource limitation and performance requirements of the FPGA can be adapted, parallel computing and hardware acceleration capabilities of the FPGA are utilized, parallel computing efficiency of graph data is improved, the requirement for real-time performance is met, energy consumption of the system is reduced, and the method has the advantages of being high in practicability and easy to popularize. And the processing efficiency of the graph data is improved.

Description

Technical Field

[0001] This article relates to field programmable gate array technology, and more particularly to a method, device, computer storage medium, and terminal for encoding graph neural networks. Background Art

[0002] Field Programmable Gate Arrays (FPGAs) are a highly integrated class of programmable logic devices and a hardware development platform based on hardware description languages. Compared to application-specific integrated circuits (ASICs), they offer advantages such as high flexibility, fast data processing speed, short design cycles, and low costs. In parallel processing, FPGAs operate differently from ARM processors, offering an absolute advantage in parallel processing. Unlike the time-sliced operation of real-time operating systems, FPGAs can achieve true real-time performance, making them ideal for applications such as environmental perception and motor control. In digital image processing, although the algorithms are relatively simple, they involve large amounts of data and require repeated use. Therefore, image processing, especially convolution operations, is often the most time-consuming step in the system, significantly impacting overall system speed. FPGAs bring new approaches and insights to digital image signal processing algorithms and system architectures, offering greater possibilities for high-precision control of device behavior. Because all elements in an image can be subjected to the same operations, inherent parallelism exists, making them ideal for hardware algorithm implementation mapped to the FPGA architecture, significantly accelerating image processing speed. In recent years, FPGA has developed rapidly, and computer vision applications such as real-time processing have broad prospects. In particular, in terms of improving computing speed, porting intelligent algorithms to hardware platforms for acceleration has become a hot research direction in the current field and has become mature. Environmental perception and motor control require improved real-time performance, but the drive output method is very simple. Digital image processing has a large amount of data for underlying image processing, requiring high processing speed but relatively simple calculation results.

[0003] Regarding the graph neural network programming model, the challenge of graph neural network processing lies in its combination of the irregularity of traditional graph computing and the regularity of neural network computing. The computation process of graph neural network (GNN) can be divided into two stages: aggregation and combination. Figure 1As shown, the aggregation phase leverages the connectivity of the graph structure to collect information about adjacent vertices. Due to the sparsity of the graph data structure, memory access during the aggregation phase is random. In the combination phase, aggregated vertex features are transformed by the neural network layers to obtain updated vertex features. Therefore, computation and memory access are regular, similar to traditional neural networks. This shows that the GNN computational paradigm exhibits mixed characteristics, which poses significant challenges to its efficient operation on hardware platforms.

[0004] In related technologies, the implementation and optimization of multi-robot intelligent inspection systems face multiple challenges. First, multi-robot systems need to process large amounts of multimodal data (such as location information, task status, and environmental characteristics) in real time, but traditional methods perform poorly in dynamic modeling and computational efficiency, making it difficult to meet real-time requirements. Second, the GNNs in multi-robot systems are inherently computationally complex, including message passing and feature aggregation operations, which place high demands on computing resources. Due to their limited logic units and storage resources, directly deploying complex GNN models on FPGAs will create performance bottlenecks. Third, the communication topology in multi-robot collaborative environments is dynamic, and GNN methods are mostly designed for static graphs and lack flexible support for dynamic topologies, resulting in insufficient adaptability for task allocation and path planning. In addition, traditional GNN acceleration mostly relies on GPUs. Although they have powerful performance, they consume significantly more power and cannot meet the low-power requirements of multi-robot systems. FPGA implementations, while low-power, struggle to achieve high real-time performance. At the deployment level, the training and optimization processes of GNN algorithms are complex, and porting them to FPGA platforms faces high barriers such as model quantization and interface design, further increasing the difficulty of engineering implementation.

[0005] In summary, how to improve the coding design quality of FPGA-based GNN has become an issue to be solved. Summary of the Invention

[0006] This embodiment of the present application provides a method for encoding a graph neural network, including: Encode the node feature vector of the convolutional neural network (CNN) into the initial node feature vector of the graph neural network (GNN) network to obtain an initial lightweight GNN network, wherein the node feature vector of the CNN includes the node feature vector of the CNN of the graph data; Using a hierarchical feature aggregation approach, the aggregation operations of the initial lightweight GNN network are mapped to the FPGA's processing unit (PE) array, and the feature representation of the target node is updated layer by layer to obtain the GNN model. By loading the feature vector, the contribution value of the feature vector in the column direction is generated, and the generated contribution value is assigned to the corresponding PE to complete the deployment of the GNN model on the FPGA.

[0007] On the other hand, an embodiment of the present application also provides a computer storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of encoding graph neural network is implemented.

[0008] On the other hand, an embodiment of the present application further provides a terminal, comprising: a memory and a processor, wherein the memory stores a computer program; wherein: The processor is configured to execute the computer program in the memory; When the computer program is executed by the processor, the method for encoding a graph neural network as described above is implemented.

[0009] On the other hand, the embodiment of the present application further provides a device for encoding a graph neural network, comprising: an encoding unit, a hierarchical aggregation unit, and a deployment unit; wherein, The encoding unit is set to: encode the node feature vector of the convolutional neural network CNN into the initial node feature vector of the graph neural network GNN network to obtain an initial lightweight GNN network, wherein the node feature vector of the CNN includes the node feature vector of the CNN of the graph data; The hierarchical aggregation unit is set as follows: using a hierarchical feature aggregation method, the aggregation operation of the initial lightweight GNN network is mapped to the FPGA processing unit PE array, and the feature representation of the target node is updated layer by layer to obtain the GNN model; The deployment unit is set as follows: by loading the feature vector, the contribution value of the feature vector in the column direction is generated, and the generated contribution value is assigned to the corresponding PE to complete the deployment of the GNN model on the FPGA.

[0010] The disclosed embodiment encodes the node feature vectors of the CNN of graph data into the initial node feature vectors of the GNN network to obtain an initial lightweight graph neural network (GNN) network, effectively reducing the complexity and resource occupancy of graph data calculations; adopts a hierarchical feature aggregation method to map the aggregation operations of the initial lightweight GNN network to the processing unit array of the FPGA to obtain a lightweight GNN model; assigns the contribution value of the column-wise feature vector to the corresponding PE, realizes the deployment of the lightweight GNN model on the FPGA, can adapt to the resource limitations and performance requirements of the FPGA, and utilizes the parallel computing and hardware acceleration capabilities of the FPGA to improve the parallel computing efficiency of the graph data, which not only meets the real-time requirements, but also reduces the energy consumption of the system and improves the processing efficiency of the graph data.

[0011] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0013] Figure 1 Schematic diagram of hybrid computing of neural networks in related technical figures; Figure 2 A flowchart of a method for encoding a graph neural network according to an embodiment of the present disclosure; Figure 3 A structural block diagram of an apparatus for encoding a graph neural network according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0015] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0016] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0017] Figure 2 A flowchart of a method for encoding a graph neural network according to an embodiment of the present disclosure, such as Figure 2 Shown, including: Step 201: Encode the node feature vectors of the convolutional neural network (CNN) into the initial node feature vectors of the graph neural network (GNN) network to obtain an initial lightweight GNN network, wherein the node feature vectors of the CNN include the node feature vectors of the CNN of the graph data; Step 202: Using a hierarchical feature aggregation approach, the aggregation operations of the initial lightweight GNN network are mapped to the processing element (PE) array of the FPGA, and the feature representation of the target node is updated layer by layer to obtain a GNN model; Step 203: Generate the contribution value of the column-wise feature vector by loading the feature vector, and assign the generated contribution value to the corresponding PE to complete the deployment of the GNN model on the FPGA.

[0018] The disclosed embodiment encodes the node feature vectors of the CNN of graph data into the initial node feature vectors of the GNN network to obtain an initial lightweight graph neural network (GNN) network, effectively reducing the complexity and resource occupancy of graph data calculations; adopts a hierarchical feature aggregation method to map the aggregation operations of the initial lightweight GNN network to the processing unit array of the FPGA to obtain a lightweight GNN model; assigns the contribution value of the column-wise feature vector to the corresponding PE, realizes the deployment of the lightweight GNN model on the FPGA, can adapt to the resource limitations and performance requirements of the FPGA, and utilizes the parallel computing and hardware acceleration capabilities of the FPGA to improve the parallel computing efficiency of the graph data, which not only meets the real-time requirements, but also reduces the energy consumption of the system and improves the processing efficiency of the graph data.

[0019] In an exemplary embodiment, CNN typically processes image or grid data, while GNN processes graph-structured data. Adapting the spatial features extracted by CNN to the graph nodes of GNN requires dimensionality reduction mapping. The disclosed embodiment encodes the node feature vectors of the CNN network into the initial node feature vectors of the GNN network to obtain an initial lightweight graph neural network (GNN) network, including: Use CNN to encode the original graph data and obtain a CNN node feature vector ,in, Represents feature dimension; In order to enable the graph neural network to capture more complex information between nodes, it is necessary to further process the node feature vectors extracted by CNN. The outer product matrix multiplication module is introduced to reduce the dimension of the node feature vectors of the high-dimensional CNN according to a pre-set weight matrix. (in ) is mapped to a low-dimensional space; the calculation formula is: Through the above-mentioned dimensionality reduction mapping operation, the feature dimension is reduced while also providing a basis for subsequent outer product processing.

[0020] For outer product processing, by calculating Get one The matrix can effectively capture the second-order interaction between features; however, the outer product processing usually causes the gradient explosion problem, so The matrix is further activated element-by-element nonlinearly using the ReLU activation function and then flattened into a one-dimensional vector as the initial lightweight GNN feature of each node to obtain the initial lightweight GNN network.

[0021] The disclosed embodiment obtains the initial lightweight graph neural network (GNN) network through the above-mentioned processing, which not only retains the rich second-order interaction information between node features, but also retains the efficiency and stability of subsequent graph neural network aggregation operations.

[0022] In an exemplary embodiment, before encoding the node feature vector of the convolutional neural network (CNN) into the initial node feature vector of the graph neural network (GNN), the embodiment of the present disclosure further includes: Graph data is collected from a multi-robot collaborative environment, the collected graph data is encoded, and the node feature vectors of the CNN network are obtained.

[0023] In an exemplary embodiment, the present disclosure uses a hierarchical feature aggregation approach to map the aggregation operations of a graph neural network to a processing unit array (PE array), including: A shared bus is used in the row direction to load the side information of the GNN network in parallel, and an independent bus is used in the column direction to distribute the initial node feature vectors of the GNN network to achieve dual parallel operations at the feature level and vertex level.

[0024] Memory bandwidth is a common bottleneck problem in hardware design. Since GNN requires large-scale data transmission during data aggregation and feature transformation, the data flow design must be optimized to alleviate bandwidth pressure. The disclosed embodiment adopts a multi-channel data bus design, using a shared bus to load edge information in parallel in the row direction, and using an independent bus to distribute node features in the column direction. This not only disperses the data transmission load, but also enables data reuse. The disclosed embodiment maps the aggregation operation to the PE array, guides the parallel aggregation of the adjacency relationship of features through the adjacency matrix, and designs a hardware structure that supports parallel processing to ensure that each layer can effectively load edge information and distribute node features; the row bus transmits the edge information associated with the target vertex, and the column bus distributes the features of neighboring nodes, maximizing the utilization of hardware resources; hardware mapping is achieved through the aggregation operation, and the initial node feature vector of the GNN network is distributed to each column of PE through an independent bus in the column direction, and each column independently processes different feature dimensions of the target vertex.

[0025] In an exemplary embodiment, the method of the present disclosure further includes: In the PE array, edge information loading, calculation of the initial node feature vector of the GNN network, and accumulation of the calculation results are performed in a pipeline form.

[0026] Data dependency conflicts are a key challenge in parallel computing. Since there are a large number of operations that depend on the results of previous calculations in the GNN calculation process, an effective synchronization mechanism and conflict resolution strategy must be designed to ensure that different PEs do not have competition conflicts when sharing data. The disclosed embodiment performs edge information loading, calculation of the initial node feature vector of the GNN network, and accumulation of calculation results in a pipeline form, which optimizes data flow and calculation scheduling, improves the utilization efficiency of memory bandwidth, and ensures that the PE array will not be affected by poor data transmission during parallel computing. It enables the entire PE array to run in an efficient and continuous manner, improving the system's parallel computing capabilities and real-time response performance. The disclosed embodiment is based on the above-mentioned fine-grained scheduling strategy and segmented pipeline design to ensure that necessary cache writes are completed before data is updated or transmitted, effectively solving data dependency problems and ensuring the continuity and efficiency of the entire computing process.

[0027] In an exemplary embodiment, the method of the present disclosure further includes: Divide the FPGA into multiple levels of cache and build a shared feature cache module based on the divided multi-level cache. The constructed feature cache module stores the node features of the GNN model, the weight matrix used in the process of encoding the node feature vector of the CNN network into the initial node feature vector of the GNN network, and the intermediate calculation results; Among them, the feature cache module adopts data pre-fetching mechanism to load data.

[0028] The disclosed embodiments can utilize BRAM to construct the divided multi-level cache into a shared feature cache module; the node features of the GNN model are stored in the feature cache module, which effectively reduces the number of external memory accesses and improves the data access speed; ensures that the PE array can quickly obtain data when needed, reducing the overall data acquisition and processing delay; data prefetching improves the utilization efficiency of memory bandwidth and ensures that the PE array will not be affected by poor data transmission during parallel computing.

[0029] In an exemplary embodiment, when a hierarchical feature aggregation approach is adopted to map the aggregation operation of a graph neural network to a processing unit array (PE array), the method of the embodiment of the present disclosure further includes: During the pruning process of hierarchical feature aggregation, edge data are organized through sparse storage.

[0030] The disclosed embodiments optimize the sparsity of aggregation calculations during the pruning process, improving the hardware data stream transmission efficiency during the aggregation phase. The disclosed embodiments may include sparse storage methods such as certificate request file (CSR) format, which is not limited by the disclosed embodiments.

[0031] In an exemplary embodiment, the method of the present disclosure further includes: The node feature vectors of the CNN network are encoded into the weight matrix of the initial node feature vector of the GNN network, and low-dimensional wide quantization processing is performed to convert the weight matrix from floating-point form to integer form.

[0032] The feature vector dimension of CNN is inconsistent with the feature dimension of GNN node. The embodiment of the present disclosure projects and aligns them through the weight matrix, performs low-bit-width quantization through the weight matrix, converts the floating-point weights into integer form, and reduces the computational complexity of matrix multiplication.

[0033] The embodiment of the present disclosure generates the contribution value of the feature vector in the column direction by loading the feature vector, and assigns the generated contribution value to the corresponding PE to complete the deployment of the GNN model on the FPGA; the embodiment of the present disclosure can use the outer product method to generate the contribution values of multiple feature vectors in the column direction by loading the input feature vector once, and after distributing the generated contribution values to the corresponding PE, the local calculation results can be directly accumulated in the PE array; after the obtained GNN model is deployed on the FPGA platform, the parallel computing and hardware acceleration capabilities of the FPGA are utilized to significantly improve the computing efficiency.

[0034] An embodiment of the present disclosure also provides a computer storage medium, in which a computer program is stored. When the computer program is executed by a processor, the above-mentioned method of encoding graph neural network is implemented.

[0035] The embodiment of the present disclosure further provides a terminal, comprising: a memory and a processor, wherein a computer program is stored in the memory; The processor is configured to execute the computer program in the memory; When the computer program is executed by a processor, the method of encoding a graph neural network as described above is implemented.

[0036] Figure 3 This is a structural block diagram of a device for encoding a graph neural network according to an embodiment of the present disclosure, such as Figure 3 As shown, it includes: a coding unit, a hierarchical aggregation unit and a deployment unit; wherein, The encoding unit is set to: encode the node feature vector of the convolutional neural network CNN into the initial node feature vector of the graph neural network GNN network to obtain an initial lightweight GNN network, wherein the node feature vector of the CNN includes the node feature vector of the CNN of the graph data; The hierarchical aggregation unit is set as follows: using a hierarchical feature aggregation method, the aggregation operation of the initial lightweight GNN network is mapped to the FPGA processing unit PE array, and the feature representation of the target node is updated layer by layer to obtain the GNN model; The deployment unit is set as follows: by loading the feature vector, the contribution value of the feature vector in the column direction is generated, and the generated contribution value is assigned to the corresponding PE to complete the deployment of the GNN model on the FPGA.

[0037] In an exemplary embodiment, the apparatus of the embodiment of the present disclosure further includes an acquisition processing unit configured to: Graph data is collected from a multi-robot collaborative environment, the collected graph data is encoded, and the node feature vectors of the CNN network are obtained.

[0038] In an exemplary embodiment, the hierarchical aggregation unit of the present disclosure is configured as follows: A shared bus is used in the row direction to load the side information of the GNN network in parallel, and an independent bus is used in the column direction to distribute the initial node feature vectors of the GNN network to achieve dual parallel operations at the feature level and vertex level.

[0039] In an exemplary embodiment, the hierarchical aggregation unit of the embodiment of the present disclosure is further configured to: In the PE array, edge information loading, calculation of the initial node feature vector of the GNN network, and accumulation of the calculation results are performed in a pipeline form.

[0040] In an exemplary embodiment, the hierarchical aggregation unit of the embodiment of the present disclosure is further configured to: Divide the FPGA into multiple levels of cache and build a shared feature cache module based on the divided multi-level cache. The constructed feature cache module stores the node features of the GNN model, the weight matrix used in the process of encoding the node feature vector of the CNN network into the initial node feature vector of the GNN network, and the intermediate calculation results; Among them, the feature cache module adopts data pre-fetching mechanism to load data.

[0041] In an exemplary embodiment, the hierarchical aggregation unit of the embodiment of the present disclosure is further configured to: When the aggregation operation of the graph neural network is mapped to the processing unit array PE array using a hierarchical feature aggregation method, the edge data is organized through sparse storage during the pruning process of the hierarchical feature aggregation.

[0042] In an exemplary embodiment, the encoding unit of the embodiment of the present disclosure is further configured to: The node feature vectors of the CNN network are encoded into the weight matrix of the initial node feature vector of the GNN network, and low-dimensional wide quantization processing is performed to convert the weight matrix from floating-point form to integer form.

[0043] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the methods, systems, and devices disclosed above may be implemented as software, firmware, hardware, or any combination thereof. In hardware implementations, the division between functional modules / units described above does not necessarily correspond to the division between physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is well known to those skilled in the art, the term "computer storage media" encompasses volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A method for encoding a graph neural network, characterized in that include: Encode the node feature vector of the convolutional neural network (CNN) into the initial node feature vector of the graph neural network (GNN) network to obtain an initial lightweight GNN network, wherein the node feature vector of the CNN includes the node feature vector of the CNN of the graph data; Using a hierarchical feature aggregation approach, the aggregation operations of the initial lightweight GNN network are mapped to the FPGA's processing unit (PE) array, and the feature representation of the target node is updated layer by layer to obtain the GNN model. By loading the feature vector, the contribution value of the feature vector in the column direction is generated, and the generated contribution value is assigned to the corresponding PE to complete the deployment of the GNN model on the FPGA.

2. The method according to claim 1, characterized in that Before encoding the node feature vector of the convolutional neural network (CNN) into the initial node feature vector of the graph neural network (GNN), the method further includes: The graph data is collected from a multi-robot collaborative environment, the collected graph data is encoded, and a node feature vector of the CNN network is obtained.

3. The method according to claim 1, characterized in that The hierarchical feature aggregation method is used to map the aggregation operation of the graph neural network to the processing unit array PE array, including: A shared bus is used in the row direction to load the edge information of the GNN network in parallel, and an independent bus is used in the column direction to distribute the initial node feature vectors of the GNN network to achieve dual parallel operations at the feature level and vertex level.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: In the PE array, side information loading, calculation of the initial node feature vector of the GNN network, and accumulation of the calculation results are performed in a pipeline form.

5. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Dividing a multi-level cache within the FPGA, and constructing a shared feature cache module based on the divided multi-level cache, storing the node features of the GNN model, the weight matrix used in the process of encoding the node feature vector of the CNN network into the initial node feature vector of the GNN network, and intermediate calculation results through the constructed feature cache module; Wherein, the feature cache module adopts a data pre-fetching mechanism to load data.

6. The method according to any one of claims 1 to 3, characterized in that When the hierarchical feature aggregation method is adopted to map the aggregation operation of the graph neural network to the processing unit array PE array, the method further includes: In the pruning process of the hierarchical feature aggregation, the edge data of the GNN model is organized through sparse storage.

7. The method according to any one of claims 1 to 3, characterized in that The method further comprises: The node feature vectors used for the CNN network are encoded as a weight matrix of the initial node feature vectors of the GNN network, and low-dimensional wide quantization processing is performed to convert the weight matrix from a floating-point form to an integer form.

8. A computer storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method for encoding a graph neural network as described in any one of claims 1 to 7.

9. A terminal comprising: A memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute the computer program in the memory; When the computer program is executed by the processor, the method for encoding a graph neural network according to any one of claims 1 to 7 is implemented.

10. A device for encoding a graph neural network, comprising: Coding unit, hierarchical aggregation unit and deployment unit; wherein, The encoding unit is set to: encode the node feature vector of the convolutional neural network CNN into the initial node feature vector of the graph neural network GNN network to obtain an initial lightweight GNN network, wherein the node feature vector of the CNN includes the node feature vector of the CNN of the graph data; The hierarchical aggregation unit is set as follows: using a hierarchical feature aggregation method, the aggregation operation of the initial lightweight GNN network is mapped to the FPGA processing unit PE array, and the feature representation of the target node is updated layer by layer to obtain the GNN model; The deployment unit is set as follows: by loading the feature vector, the contribution value of the feature vector in the column direction is generated, and the generated contribution value is assigned to the corresponding PE to complete the deployment of the GNN model on the FPGA.

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